A differential signal extraction method based on parallel ladder differentiator

Abstract

This invention discloses a method for extracting differential signals based on a parallel staircase differentiator, comprising the following steps: S1, inputting the input signal into the parallel staircase differentiator sQ. b (s) Operation module; S2, sQ b (s) The arithmetic module performs operations on the input signal to obtain the first-level signal; S3, iterative calculation is performed, and the first-level signal is passed through the P of the parallel ladder differential n-1 times. b (s) The operation module performs the operation and then inputs it to the adder operation module of the parallel ladder-type differentiator, which adds it to the original (n-1)th level signal to obtain the nth level signal; S4, output the nth level signal, which is the differential signal of the extracted input signal; The parallel ladder-type differentiator of the present invention adopts a parallel ladder structure and uses the method of series partial summation to improve the differential tracking effect. There is no stability problem, and the initial differential peak phenomenon of digital tracking differentiators is avoided. At the same time, the differentiator is implemented using conventional analog circuits, which has higher real-time performance and lower cost than digital tracking differentiators.

Description

Technical Field

[0001] This invention relates to the technical field of signal differential extraction, and in particular to a differential signal extraction method based on a parallel ladder differentialr. Background Technology

[0002] In system modeling, prediction, and control, obtaining the derivative of a signal is a crucial signal processing step. Existing methods for determining the derivative of a signal by the ratio of its increment to the time required for that increment are highly susceptible to noise in the acquired signal. Because the time required to obtain the derivative increment is relatively small, while the change in increment caused by noise can be quite large, the differentiator becomes a noise amplifier, and the useful derivative signal may be completely submerged in the noise.

[0003] Existing analog differentiators are constructed using a differentiating circuit and a low-pass filter. This presents a trade-off between differentiating tracking capability and noise immunity, making it difficult to find a suitable balance in circuit parameters and selecting appropriate values. While digital differentiators are widely used, analog differentiators, implemented with analog circuits, remain indispensable in ultra-high-speed control applications due to their low cost and high processing speed. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by providing a method for extracting differential signals based on a parallel ladder-type differentiator. The parallel ladder-type differentiator is implemented using ordinary resistor, capacitor, and amplifier circuits. It improves the differential tracking effect by using a series partial summation method, without stability issues, and avoids the initial differential peak phenomenon of digital tracking differentiators.

[0005] The objective of this invention is achieved through the following technical solution: a method for extracting differential signals based on a parallel stair-step differentiator, wherein the parallel stair-step differentiator employs a low-bandwidth low-pass filter as the basic filter, and the differential signal extraction method includes the following steps:

[0006] S1, Input the input signal Y1 to the parallel ladder differentiator sQ b (s) computation module;

[0007] S2, sQ b (s) The operation module performs operations on the input signal Y1 to obtain the first-level signal;

[0008] S3. Perform iterative calculations, passing the first-level signal through n-1 parallel ladder-type differentiators P. b The operation of the (s) operation module is then input to the adder operation module of the parallel ladder differential, and added to the original (n-1)th level signal to obtain the nth level signal, where n≥2;

[0009] S4. Output the nth level signal, which is the differential signal Z2 of the extracted input signal Y1.

[0010] Furthermore, the low-pass filter is a linear second-order filter, and its formula is as follows:

[0011]

[0012] Where, ω b For the basic linear low-pass filter Q b bandwidth, ξ b For a decaying system, take ξ b Let s be 1, and s be the Laplace operator; define the geometric series as...

[0013]

[0014] The common ratio is

[0015] P b (s)=ρ b (1-Q b (s)) (3)

[0016] Where 0 < ρ b <1 represents the robustness coefficient. The partial sum of the geometric series is...

[0017]

[0018] By selecting ρ b Expressions (3) and (4) guarantee that 0 < |P| b (jω)|<1,(2) represents the sum of the geometric series.

[0019]

[0020] Substituting (1) and (3) into (5) gives

[0021]

[0022] in Therefore, the bandwidth of F(s) is greater than that of Q. b Increase, while the attenuation system decreases, partly and F N (s) bandwidth and attenuation system in Q b Between F(s), a parallel ladder-type differentiator is implemented through the partial sum of a geometric series. The Laplace transform of the input signal is Y1(s), and its differential signal is Z2(s).

[0023] Z2(s)=sF N (s)Y1(s) (7)

[0024] Take ξ b=1,ρ b ρ is the robustness coefficient. b Smaller is more robust, but performance suffers; ρ b The larger the value, the worse the robustness, but the stronger the following performance. To ensure sufficient robustness, let ρ... b The range of values ​​is

[0025] Furthermore, the sQ b (s) The operational module includes a first operational amplifier U1A, a second operational amplifier U1B, a third operational amplifier U1C, and a first resistor R. 11 Second resistor R 12 Third resistor R 13 Fourth resistor R 14 Fifth resistor R 15 First capacitor C 11 Second capacitor C 12 The first resistor R 11 One end and the input terminal V 11 Connection, the first resistor R 11 The other end is connected to the first capacitor C. 11 One end of the capacitor is connected to the non-inverting input of the first operational amplifier U1A, and the first capacitor C is connected to the non-inverting input of the first operational amplifier U1A. 11 The other end is grounded. The inverting input of the first operational amplifier U1A is connected to the output of the first operational amplifier U1A. The output of the first operational amplifier U1A is connected through the second capacitor C. 12 With the second resistor R 12 One end of the second resistor is connected to the inverting input of the second operational amplifier U1B, and the other end of the second resistor is connected to the inverting input of the second operational amplifier U1B. The non-inverting input of the second operational amplifier U1B is connected to ground and to the non-inverting input of the third operational amplifier U1C. The output of the second operational amplifier U1B is connected to the third resistor R. 13 The output of the second operational amplifier U1B is connected to the inverting input terminal of the second operational amplifier U1B, and the output terminal of the second operational amplifier U1B is connected to the fourth resistor R. 14 It is connected to the inverting input of the third operational amplifier U1C, which is connected to the fifth resistor R. 15 Connected to the output terminal of the third operational amplifier U1C, the output terminal of the third operational amplifier U1C is connected to the output terminal V. 12 connect.

[0026] Furthermore, the sQ b The formula for the (s) operation module is as follows:

[0027]

[0028] Where R is taken12 C 12 =1,R 11 C 11 =R 13 C 12 =1 / ω b R 14 =R 15 .

[0029] Furthermore, the P b (s) The operational module includes the fourth operational amplifier U2A, the fifth operational amplifier U2B, the sixth operational amplifier U2C, the seventh operational amplifier U2D, and the sixth resistor R. 21 The seventh resistor R 22 The eighth resistor R 23 Ninth resistor R 24 The tenth resistor R 25 Eleventh resistor R 26 The twelfth resistor R 27 Third capacitor C 21 and the fourth capacitor C 22 One end of the sixth resistor R21 is connected to the input terminal V21, and the sixth resistor R 21 The other end is connected to the third capacitor C. 21 One end of the capacitor is connected to the non-inverting input of the fourth operational amplifier U2A, and the third capacitor C... 21 The other end is grounded. The inverting input of the fourth operational amplifier U2A is connected to the output of the fourth operational amplifier U2A. The output of the fourth operational amplifier U2A is connected to the seventh resistor R. 22 One end is connected to the seventh resistor R. 22 The other end is connected to the fourth capacitor C. 22 One end of the capacitor is connected to the non-inverting input of the fifth operational amplifier U2B, and the fourth capacitor C... 22 The other end is grounded, and the inverting input terminal of the fifth operational amplifier U2B is connected to the output terminal of the fifth operational amplifier U2B. The output terminal of the fifth operational amplifier U2B is connected to the ninth resistor R. 24 One end is connected to the ninth resistor R. 24 The other end is connected to the inverting input of the sixth operational amplifier U2C, which is connected to the tenth resistor R. 25 Connected to the output terminal of the sixth operational amplifier U2C, the non-inverting input terminal of the sixth operational amplifier U2C is grounded, and the output terminal of the sixth operational amplifier U2C is connected to the output terminal V. 22 The inverting input terminal of the seventh operational amplifier U2D is connected to the input terminal V through the eleventh resistor R26. 21The connection is as follows: the non-inverting input terminal of the seventh operational amplifier U2D is grounded, and the output terminal of the seventh operational amplifier U2D is connected through the twelfth resistor R. 27 The output of the seventh operational amplifier U2D is connected to the inverting input terminal of the seventh operational amplifier U2D, and the output terminal of the seventh operational amplifier U2D is connected to the eighth resistor R. 23 Connect to the inverting input of the sixth operational amplifier U2C.

[0030] Furthermore, the P b The formula for the (s) operation module is as follows:

[0031] Let R 23 =R 24 =R 25 ,have

[0032]

[0033] Take R 21 C 21 =R 22 C 22 =1 / ω b , ρ b =R 27 / R 26 .

[0034] Furthermore, the adder operation module includes an eighth operational amplifier U3A, a ninth operational amplifier U3B, and a thirteenth resistor R. 31 Fourteenth resistor R 32 The fifteenth resistor R 33 The sixteenth resistor R 34 and the seventeenth resistor R 35 The thirteenth resistor R 31 One end is connected to the first input terminal V 31 Connection, the thirteenth resistor R 31 The other end is connected to the fifteenth resistor R. 33 One end of the resistor is connected to the inverting input of the eighth operational amplifier U3A, and the fourteenth resistor R is connected to the inverting input of the eighth operational amplifier U3A. 32 One end and the second input terminal V 32 Connection, the fourteenth resistor R 32 The other end is connected to the inverting input of the eighth operational amplifier U3A, the non-inverting input of the eighth operational amplifier U3A is grounded, and the output of the eighth operational amplifier U3A is connected to the fifteenth resistor R. 33 The other end is connected, and the output terminal of the eighth operational amplifier U3A is connected through the sixteenth resistor R. 34 The inverting input of the ninth operational amplifier U3B is connected to the seventeenth resistor R. 35Connected to the output terminal of the ninth operational amplifier U3B, the output terminal of the ninth operational amplifier U3B is connected to the output terminal V. 33 The connection is made so that the non-inverting input terminal of the ninth operational amplifier U3B is grounded.

[0035] Furthermore, let R 31 =R 32 =R 33 and R 34 =R 35 The formula for the adder operation module is as follows:

[0036] V 33 (s)=V 31 (s)+V 32 (s) (10).

[0037] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0038] 1. The parallel stepped differentiator uses a low-bandwidth low-pass filter as the basic filter, which is different from the existing analog differentiator which uses a wide-bandwidth low-pass filter. The parallel stepped differentiator improves the noise immunity of the differentiator and solves the contradiction between the differentiating following ability and the noise immunity of the conventional analog differentiator.

[0039] 2. The parallel stepped differentiator adopts a parallel stepped structure and uses a series partial summation method to improve the differential following effect. It has no stability problem and avoids the initial differential peak phenomenon of the digital tracking differentiator.

[0040] 3. It can be implemented using conventional analog circuits, offering higher real-time performance and lower cost compared to digital tracking differentiators. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a parallel ladder-type differentiator.

[0042] Figure 2 For sQ b (s) Schematic diagram of the operation module.

[0043] Figure 3 For P b (s) Schematic diagram of the operation module.

[0044] Figure 4 This is a schematic diagram of the adder operation module. Detailed Implementation

[0045] The present invention will be further described below with reference to specific embodiments.

[0046] See Figure 1As shown, this embodiment provides a differential signal extraction method based on a parallel ladder differentiator. The parallel ladder differentiator uses a low-bandwidth low-pass filter as the basic filter. The differential signal extraction method includes the following steps:

[0047] S1, Input the input signal Y1 to the parallel ladder differentiator sQ b (s) computation module;

[0048] S2, sQ b (s) The operation module performs operations on the input signal Y1 to obtain the first-level signal;

[0049] S3. Perform iterative calculations, passing the first-level signal through n-1 parallel ladder-type differentiators P. b The operation of the (s) operation module is then input to the adder operation module of the parallel ladder differential, and added to the original (n-1)th level signal to obtain the nth level signal, where n≥2;

[0050] S4. Output the nth level signal, which is the differential signal Z2 of the extracted input signal Y1.

[0051] The low-pass filter is a linear second-order filter, but a nonlinear filter can also be used. This embodiment uses a linear filter as an example, and its formula is as follows:

[0052]

[0053] Where, ω b For the basic linear low-pass filter Q b bandwidth, ξ b For a decaying system, take ξ b Let s be 1, and s be the Laplace operator; define the geometric series as...

[0054]

[0055] The common ratio is

[0056] P b (s)=ρ b (1-Q b (s)) (3)

[0057] Where 0 < ρ b <1 represents the robustness coefficient. The partial sum of the geometric series is...

[0058]

[0059] By selecting ρ b Expressions (3) and (4) guarantee that 0 < P. b (jω)<1, (2) represents the sum of the geometric series.

[0060]

[0061] Substituting (1) and (3) into (5) gives

[0062]

[0063] in Therefore, the bandwidth of F(s) is greater than that of Q. b Increase, while the attenuation system decreases, partly and F N (s) bandwidth and attenuation system in Q b Between F(s), a parallel ladder-type differentiator is implemented through the partial sum of a geometric series. The Laplace transform of the input signal is Y1(s), and its differential signal is Z2(s).

[0064] Z2(s)=sF N (s)Y1(s) (7)

[0065] Take ξ b =1,ρ b ρ is the robustness coefficient. b Smaller is more robust, but performance suffers; ρ b The larger the value, the worse the robustness, but the stronger the following performance. To ensure sufficient robustness, let ρ... b The range of values ​​is

[0066] See Figure 2 As shown, this is sQ b (s) Schematic diagram of the operation module, wherein sQ b (s) The operational module includes a first operational amplifier U1A, a second operational amplifier U1B, a third operational amplifier U1C, and a first resistor R. 11 Second resistor R 12 Third resistor R 13 Fourth resistor R 14 Fifth resistor R 15 First capacitor C 11 Second capacitor C 12 The first resistor R 11 One end and the input terminal V 11 Connection, the first resistor R 11 The other end is connected to the first capacitor C. 11 One end of the capacitor is connected to the non-inverting input of the first operational amplifier U1A, and the first capacitor C is connected to the non-inverting input of the first operational amplifier U1A. 11 The other end is grounded. The inverting input of the first operational amplifier U1A is connected to the output of the first operational amplifier U1A. The output of the first operational amplifier U1A is connected through the second capacitor C. 12 With the second resistor R 12One end of the second resistor is connected to the inverting input of the second operational amplifier U1B, and the other end of the second resistor is connected to the inverting input of the second operational amplifier U1B. The non-inverting input of the second operational amplifier U1B is connected to ground and to the non-inverting input of the third operational amplifier U1C. The output of the second operational amplifier U1B is connected to the third resistor R. 13 The output of the second operational amplifier U1B is connected to the inverting input terminal of the second operational amplifier U1B, and the output terminal of the second operational amplifier U1B is connected to the fourth resistor R. 14 It is connected to the inverting input of the third operational amplifier U1C, which is connected to the fifth resistor R. 15 Connected to the output terminal of the third operational amplifier U1C, the output terminal of the third operational amplifier U1C is connected to the output terminal V. 12 connect.

[0067] The sQ b The formula for the (s) operation module is as follows:

[0068]

[0069] Where R is taken 12 C 12 =1,R 11 C 11 =R 13 C 12 =1 / ω b R 14 =R 15 .

[0070] See Figure 3 As shown, P b (s) Schematic diagram of the operation module, wherein P b (s) The operational module includes the fourth operational amplifier U2A, the fifth operational amplifier U2B, the sixth operational amplifier U2C, the seventh operational amplifier U2D, and the sixth resistor R. 21 The seventh resistor R 22 The eighth resistor R 23 Ninth resistor R 24 The tenth resistor R 25 Eleventh resistor R 26 The twelfth resistor R 27 Third capacitor C 21 and the fourth capacitor C 22 One end of the sixth resistor R21 is connected to the input terminal V21, and the sixth resistor R 21 The other end is connected to the third capacitor C. 21 One end of the capacitor is connected to the non-inverting input of the fourth operational amplifier U2A, and the third capacitor C... 21The other end is grounded. The inverting input of the fourth operational amplifier U2A is connected to the output of the fourth operational amplifier U2A. The output of the fourth operational amplifier U2A is connected to the seventh resistor R. 22 One end is connected to the seventh resistor R. 22 The other end is connected to the fourth capacitor C. 22 One end of the capacitor is connected to the non-inverting input of the fifth operational amplifier U2B, and the fourth capacitor C... 22 The other end is grounded, and the inverting input terminal of the fifth operational amplifier U2B is connected to the output terminal of the fifth operational amplifier U2B. The output terminal of the fifth operational amplifier U2B is connected to the ninth resistor R. 24 One end is connected to the ninth resistor R. 24 The other end is connected to the inverting input of the sixth operational amplifier U2C, which is connected to the tenth resistor R. 25 Connected to the output terminal of the sixth operational amplifier U2C, the non-inverting input terminal of the sixth operational amplifier U2C is grounded, and the output terminal of the sixth operational amplifier U2C is connected to the output terminal V. 22 The inverting input terminal of the seventh operational amplifier U2D is connected to the input terminal V through the eleventh resistor R26. 21 The connection is as follows: the non-inverting input terminal of the seventh operational amplifier U2D is grounded, and the output terminal of the seventh operational amplifier U2D is connected through the twelfth resistor R. 27 The output of the seventh operational amplifier U2D is connected to the inverting input terminal of the seventh operational amplifier U2D, and the output terminal of the seventh operational amplifier U2D is connected to the eighth resistor R. 23 Connect to the inverting input of the sixth operational amplifier U2C.

[0071] The P b The formula for the (s) operation module is as follows:

[0072] Let R 23 =R 24 =R 25 ,have

[0073]

[0074] Take R 21 C 21 =R 22 C 22 =1 / ω b , ρ b =R 27 / R 26 .

[0075] See Figure 4The diagram shown is a schematic of the adder operation module. The adder operation module includes an eighth operational amplifier U3A, a ninth operational amplifier U3B, and a thirteenth resistor R. 31 Fourteenth resistor R 32 The fifteenth resistor R 33 The sixteenth resistor R 34 and the seventeenth resistor R 35 The thirteenth resistor R 31 One end is connected to the first input terminal V 31 Connection, the thirteenth resistor R 31 The other end is connected to the fifteenth resistor R. 33 One end of the resistor is connected to the inverting input of the eighth operational amplifier U3A, and the fourteenth resistor R is connected to the inverting input of the eighth operational amplifier U3A. 32 One end and the second input terminal V 32 Connection, the fourteenth resistor R 32 The other end is connected to the inverting input of the eighth operational amplifier U3A, the non-inverting input of the eighth operational amplifier U3A is grounded, and the output of the eighth operational amplifier U3A is connected to the fifteenth resistor R. 33 The other end is connected, and the output terminal of the eighth operational amplifier U3A is connected through the sixteenth resistor R. 34 The inverting input of the ninth operational amplifier U3B is connected to the seventeenth resistor R. 35 Connected to the output terminal of the ninth operational amplifier U3B, the output terminal of the ninth operational amplifier U3B is connected to the output terminal V. 33 The connection is made so that the non-inverting input terminal of the ninth operational amplifier U3B is grounded.

[0076] Let R 31 =R 32 =R 33 and R 34 =R 35 The formula for the adder operation module is as follows:

[0077] V 33 (s)=V 31 (s)+V 32 (s) (10).

[0078] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Therefore, any changes made in accordance with the shape and principle of the present invention should be covered within the protection scope of the present invention.

Claims

1. A method for extracting differential signals based on a parallel ladder differentiator, characterized in that: The parallel ladder-type differentiator uses a low-bandwidth low-pass filter as the basic filter, and the differential signal extraction method includes the following steps: S1, Input signal Input to a parallel staircase differentiator Computation module; S2, The arithmetic module processes the input signal The first-level signal is obtained through calculation; S3. Perform iterative calculations, passing the first-level signal through n-1 parallel ladder-type differentiators. The arithmetic module's input is then fed into the adder module of the parallel ladder differential, where it is added to the original (n-1)th level signal to obtain the nth level signal. ; S4. Output the nth level signal, which is the extracted input signal. Differential signal ; The The operational module includes a first operational amplifier U1A, a second operational amplifier U1B, a third operational amplifier U1C, and a first resistor R. 11 Second resistor R 12 Third resistor R 13 Fourth resistor R 14 Fifth resistor R 15 First capacitor C 11 Second capacitor C 12 The first resistor R 11 One end and the input terminal V 11 Connection, the first resistor R 11 The other end is connected to the first capacitor C. 11 One end of the capacitor is connected to the non-inverting input of the first operational amplifier U1A, and the first capacitor C is connected to the non-inverting input of the first operational amplifier U1A. 11 The other end is grounded. The inverting input of the first operational amplifier U1A is connected to the output of the first operational amplifier U1A. The output of the first operational amplifier U1A is connected through the second capacitor C. 12 With the second resistor R 12 One end of the second resistor is connected to the inverting input of the second operational amplifier U1B, and the other end of the second resistor is connected to the inverting input of the second operational amplifier U1B. The non-inverting input of the second operational amplifier U1B is connected to ground and to the non-inverting input of the third operational amplifier U1C. The output of the second operational amplifier U1B is connected to the third resistor R. 13 The output of the second operational amplifier U1B is connected to the inverting input terminal of the second operational amplifier U1B, and the output terminal of the second operational amplifier U1B is connected to the fourth resistor R. 14 It is connected to the inverting input of the third operational amplifier U1C, which is connected to the fifth resistor R. 15 Connected to the output terminal of the third operational amplifier U1C, the output terminal of the third operational amplifier U1C is connected to the output terminal V. 12 connect; The The operational module includes the fourth operational amplifier U2A, the fifth operational amplifier U2B, the sixth operational amplifier U2C, the seventh operational amplifier U2D, and the sixth resistor R. 21 The seventh resistor R 22 The eighth resistor R 23 Ninth resistor R 24 The tenth resistor R 25 Eleventh resistor R 26 12th resistor R 27 Third capacitor C 21 and the fourth capacitor C 22 One end of the sixth resistor R21 is connected to the input terminal V21, and the sixth resistor R 21 The other end is connected to the third capacitor C. 21 One end of the capacitor is connected to the non-inverting input of the fourth operational amplifier U2A, and the third capacitor C... 21 The other end is grounded. The inverting input of the fourth operational amplifier U2A is connected to the output of the fourth operational amplifier U2A. The output of the fourth operational amplifier U2A is connected to the seventh resistor R. 22 One end is connected to the seventh resistor R. 22 The other end is connected to the fourth capacitor C. 22 One end of the capacitor is connected to the non-inverting input of the fifth operational amplifier U2B, and the fourth capacitor C... 22 The other end is grounded, and the inverting input terminal of the fifth operational amplifier U2B is connected to the output terminal of the fifth operational amplifier U2B. The output terminal of the fifth operational amplifier U2B is connected to the ninth resistor R. 24 One end is connected to the ninth resistor R. 24 The other end is connected to the inverting input of the sixth operational amplifier U2C, which is connected to the tenth resistor R. 25 Connected to the output terminal of the sixth operational amplifier U2C, the non-inverting input terminal of the sixth operational amplifier U2C is grounded, and the output terminal of the sixth operational amplifier U2C is connected to the output terminal V. 22 The inverting input terminal of the seventh operational amplifier U2D is connected to the input terminal V through the eleventh resistor R26. 21 The connection is as follows: the non-inverting input terminal of the seventh operational amplifier U2D is grounded, and the output terminal of the seventh operational amplifier U2D is connected through the twelfth resistor R. 27 The output of the seventh operational amplifier U2D is connected to the inverting input terminal of the seventh operational amplifier U2D, and the output terminal of the seventh operational amplifier U2D is connected to the eighth resistor R. 23 Connect to the inverting input of the sixth operational amplifier U2C.

2. The method for extracting differential signals based on a parallel ladder differentiator according to claim 1, characterized in that, The low-pass filter is a linear second-order filter, and its formula is as follows: (1) in, For basic linear low-pass filters bandwidth, For an attenuation system, take Let s be 1, and s be the Laplace operator; define the geometric series as... (2) The common ratio is (3) in The robustness coefficient is ; the partial sum of the geometric series is (4) By selection Expressions (3) and (3) can guarantee The sum of the geometric series represented by formula (2) is (5) Substituting (1) and (3) into (5) gives (6) in , ,therefore bandwidth ratio Increase, while the attenuation system decreases, partly and The bandwidth and attenuation system in and Between these, a parallel ladder-type differentiator is implemented using partial sums of a geometric series, and the Laplace transform of the input signal is: Its differential signal is for (7) Pick =1, The robustness coefficient is... Smaller is more robust, but performance suffers from reduced following speed; The larger the value, the worse the robustness, but the stronger the following performance. To ensure sufficient robustness, let... The range of values ​​is .

3. The method for extracting differential signals based on a parallel ladder differentiator according to claim 1, characterized in that, The The formulas for the calculation module are as follows: (8) Among them, take =1, .

4. The method for extracting differential signals based on a parallel ladder differentiator according to claim 1, characterized in that, The The formulas for the calculation module are as follows: make ,have (9) Pick , .

5. The method for extracting differential signals based on a parallel ladder differentiator according to claim 1, characterized in that, The adder operation module includes an eighth operational amplifier U3A, a ninth operational amplifier U3B, and a thirteenth resistor R. 31 Fourteenth resistor R 32 The fifteenth resistor R 33 The sixteenth resistor R 34 and the seventeenth resistor R 35 The thirteenth resistor R 31 One end is connected to the first input terminal V 31 Connection, the thirteenth resistor R 31 The other end is connected to the fifteenth resistor R. 33 One end of the resistor is connected to the inverting input of the eighth operational amplifier U3A, and the fourteenth resistor R is connected to the inverting input of the eighth operational amplifier U3A. 32 One end and the second input terminal V 32 Connection, the fourteenth resistor R 32 The other end is connected to the inverting input of the eighth operational amplifier U3A, the non-inverting input of the eighth operational amplifier U3A is grounded, and the output of the eighth operational amplifier U3A is connected to the fifteenth resistor R. 33 The other end is connected, and the output terminal of the eighth operational amplifier U3A is connected through the sixteenth resistor R. 34 The inverting input of the ninth operational amplifier U3B is connected to the seventeenth resistor R. 35 Connected to the output terminal of the ninth operational amplifier U3B, the output terminal of the ninth operational amplifier U3B is connected to the output terminal V. 33 The connection is made so that the non-inverting input terminal of the ninth operational amplifier U3B is grounded.

6. The differential signal extraction method based on a parallel ladder differentiator according to claim 5, characterized in that: make and The formula for the adder operation module is as follows: (10)。

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