A back contact heterojunction solar cell and a method for manufacturing the same

Abstract

The present invention discloses a back-contact heterojunction solar cell and a manufacturing method thereof, and relates to the technical field of solar cells, so as to simultaneously reduce the contact barrier between the P-type region and the first electrode, and the contact barrier between the N-type region and the second electrode in the back-contact heterojunction solar cell to a smaller target range, thereby improving its photoelectric conversion efficiency. The back-contact heterojunction solar cell comprises: a silicon heterojunction substrate, a first transparent conductive layer, and a second transparent conductive layer. The silicon heterojunction substrate has a first surface and a second surface opposite to each other. Along a direction parallel to the second surface, the second surface has a P-type region and an N-type region alternately arranged at intervals. The first transparent conductive layer is at least formed on the P-type region. The second transparent conductive layer is at least formed on the N-type region. The portion of the second transparent conductive layer located on the N-type region is insulated from the portion of the first transparent conductive layer located on the P-type region. The work function of the second transparent conductive layer is less than the work function of the first transparent conductive layer.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back-contact heterojunction solar cell and a manufacturing method thereof. Background Art

[0002] Back-contact heterojunction solar cells are a type of cell structure that has no metal electrode shading on the front, has a high open-circuit voltage, high conversion efficiency, low temperature coefficient, and no photoinduced degradation. They have received extensive attention from the photovoltaic academic and industrial communities and have become a popular development direction for high-efficiency solar cell technology.

[0003] However, the first transparent conductive layer and the second transparent conductive layer with opposite polarities included in the existing back-contact heterojunction solar cell have at least part of the same material, which causes one of the first transparent conductive layer and the second transparent conductive layer to fail to meet the energy level matching requirement, thereby affecting the further improvement of the performance of the back-contact heterojunction solar cell. Summary of the invention

[0004] The object of the present invention is to provide a back-contact heterojunction solar cell and a method for manufacturing the same, which are used to simultaneously reduce the contact barrier between the P-type region and the first electrode, and the contact barrier between the N-type region and the second electrode in the back-contact heterojunction solar cell to a smaller target range, thereby improving the photoelectric conversion efficiency of the back-contact heterojunction solar cell.

[0005] In a first aspect, the present invention provides a back-contact heterojunction solar cell, which includes: a silicon heterojunction substrate, a first transparent conductive layer, and a second transparent conductive layer. The silicon heterojunction substrate has a first surface and a second surface opposite to each other. Along a direction parallel to the second surface, the second surface has P-type regions and N-type regions alternately arranged at intervals. The first transparent conductive layer is formed at least on the P-type region. The second transparent conductive layer is formed at least on the N-type region. The portion of the second transparent conductive layer located on the N-type region is insulated from the portion of the first transparent conductive layer located on the P-type region. The work function of the second transparent conductive layer is less than the work function of the first transparent conductive layer.

[0006] In the case of adopting the above technical solution, the back-contact heterojunction solar cell provided by the present invention includes a first transparent conductive layer formed at least on the P-type region of the silicon heterojunction substrate. The second transparent conductive layer is formed at least on the N-type region of the silicon heterojunction substrate. In addition, because the conductivity types of the N-type region and the P-type region are opposite, when the portion of the second transparent conductive layer located on the N-type region and the portion of the first transparent conductive layer located on the P-type region are insulated from each other, leakage between the first transparent conductive layer and the second transparent conductive layer can be prevented. In addition, the first transparent conductive layer is arranged between the P-type region and the first electrode for collecting holes. The second transparent conductive layer is arranged between the N-type region and the second electrode for collecting electrons. In this case, because the work function of the N-type region of the silicon heterojunction substrate is smaller than the work function of the P-type region, when the work function of the second transparent conductive layer is smaller than the work function of the first transparent conductive layer, the work functions of the second transparent conductive layer and the first transparent conductive layer can be determined according to the smaller work function corresponding to the N-type region and the larger work function corresponding to the P-type region, respectively. This helps to reduce the contact barrier between the P-type region and the first electrode and the contact barrier between the N-type region and the second electrode in the back-contact heterojunction solar cell to a smaller target range at the same time, solving the problem in the prior art that only one of the two contact barriers can be reduced to the target range while the other cannot meet the preset requirements, thereby improving the photoelectric conversion efficiency of the back-contact heterojunction solar cell.

[0007] As a possible implementation, the material of the first transparent conductive layer is completely different from that of the second transparent conductive layer. In this case, the materials of the first transparent conductive layer and the second transparent conductive layer can be adjusted separately to prevent at least part of the material of one of the first transparent conductive layer and the second transparent conductive layer from being the same as the material of the other, thereby preventing the first transparent conductive layer from reducing the contact barrier between the P-type region and the first electrode and the second transparent conductive layer from reducing the contact barrier between the N-type region and the second electrode.

[0008] As a possible implementation, the silicon heterojunction substrate includes: a silicon substrate, a first semiconductor stack and a second semiconductor stack. The first semiconductor stack is at least formed on a portion of the silicon substrate corresponding to a P-type region. In a direction away from the silicon substrate, the first semiconductor stack includes a first intrinsic silicon layer and a P-type doped silicon layer located on the first intrinsic silicon layer. The second semiconductor stack is at least formed on a portion of the silicon substrate corresponding to an N-type region. In a direction away from the silicon substrate, the second semiconductor stack includes a second intrinsic silicon layer and an N-type doped silicon layer located on the second intrinsic silicon layer.

[0009] As a possible implementation, the portion of the silicon substrate corresponding to the N-type region has a groove, and the second semiconductor stack at least covers the sidewall and bottom of the groove.

[0010] In the case of adopting the above technical solution, compared with the prior art in which the maximum surface heights of the N-type region and the P-type region of the silicon substrate are equal, the portion of the silicon substrate corresponding to the N-type region in the back contact heterojunction solar cell provided by the present invention has a groove, and at this time the total surface area of ​​the silicon substrate corresponding to the N-type region is the sum of the groove bottom area and the side wall area of ​​the groove, so that the surface area of ​​the silicon substrate corresponding to the N-type region is larger. Based on this, the portion of the second semiconductor stack formed on the N-type region can not only cover the groove bottom of the groove, but also cover the side wall of the groove, so that the contact area between the second intrinsic silicon layer included in the second semiconductor stack and the N-type region can be increased, and then the passivation effect of the second intrinsic silicon layer on the N-type region can be improved. At the same time, the surface area of ​​the N-type doped silicon layer included in the second semiconductor stack can also be increased, that is, the conductive area of ​​the N-type region of the silicon heterojunction substrate is increased, which is conducive to increasing the short-circuit current of the back contact heterojunction solar cell, and further improving the photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0011] As another possible implementation, the portion of the silicon substrate corresponding to the P-type region has a groove. And the first semiconductor stack at least covers the sidewall and bottom of the groove. The beneficial effects in this case can be analyzed with reference to the beneficial effects of the portion of the silicon substrate corresponding to the N-type region having a groove as described above, which will not be repeated here.

[0012] As a possible implementation manner, the bottom surface of the groove is a velvet surface.

[0013] In the case of adopting the above technical solution, the part of the silicon substrate corresponding to the N-type region having a groove is used as an example for explanation. When the size of the groove bottom surface of the groove is the same, because the velvet surface has an undulating surface morphology, compared with the groove bottom surface of the groove being a flat polished surface, when the groove bottom surface of the groove is a velvet surface, the surface area of ​​the groove bottom surface of the groove is larger, thereby further increasing the gap between the second intrinsic silicon layer and the N-type region, and further improving the passivation effect of the second intrinsic silicon layer on the N-type region. At the same time, the conductive area of ​​the N-type region of the silicon heterojunction substrate can be further increased, which is more conducive to improving the photoelectric conversion efficiency of the back contact heterojunction solar cell. When the part of the silicon substrate corresponding to the P-type region has a groove and the groove bottom surface of the groove is a velvet surface, the beneficial effects can refer to the above beneficial effect analysis, which will not be repeated here.

[0014] As a possible implementation, the depth of the groove is 1 μm to 10 μm. At this time, the depth of the groove is moderate, which can prevent the surface area of ​​the first semiconductor stack or the second semiconductor stack formed on the groove from increasing to a low degree due to the small depth of the groove, which is not conducive to the beneficial effects of improving the passivation effect of the corresponding intrinsic silicon layer as mentioned above. At the same time, it can also prevent the problem of insufficient light absorption depth, easy breakage and hidden cracks due to the large thickness of the silicon substrate corresponding to the N-type region or the P-type region due to the large depth of the groove, thereby improving the yield and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0015] As a possible implementation, the second surface further has an isolation region between each P-type region and the N-type region, and the surface of the isolation region is a polished surface. In addition, an insulating material is provided between the portion of the first transparent conductive layer located on the P-type region and the portion of the second transparent conductive layer located on the N-type region. The insulating material is located on the isolation region.

[0016] In the case of adopting the above technical solution, the insulating material located on the isolation area can isolate the portion of the first transparent conductive layer located on the P-type area from the portion of the second transparent conductive layer located on the N-type area. Based on this, in the actual manufacturing process, when the surface of the isolation area is a polished surface, the surface of the isolation area is relatively flat, which is conducive to making the portion of the first transparent conductive layer and the second transparent conductive layer formed on the isolation area also have a relatively flat morphology, and is convenient for completely removing the portion of the first transparent conductive material layer and the second transparent conductive material layer filled in the area of ​​the pre-formed insulating material before forming the insulating material on the isolation area, reducing the difficulty of removal, and preventing impurities from remaining, ensuring that the portion of the first transparent conductive layer located on the P-type area and the portion of the second transparent conductive layer located on the N-type area are insulated from each other, thereby improving the electrical stability of the back-contact heterojunction solar cell.

[0017] As a possible implementation, the first semiconductor stack is also formed on a portion of the silicon substrate corresponding to the isolation region. The second semiconductor stack is also formed on a portion of the first semiconductor stack corresponding to the isolation region, and the portion of the second semiconductor stack corresponding to the isolation region is in direct contact with the portion of the first semiconductor stack corresponding to the isolation region.

[0018] When the above technical solution is adopted, compared with the prior art in which the insulating layer at least acts as a mask is provided on the portion of the first semiconductor stack corresponding to the isolation region, the portion of the second semiconductor stack corresponding to the isolation region in the back-contact heterojunction solar cell provided by the present invention is in direct contact with the portion of the first semiconductor stack corresponding to the isolation region. Based on this, in the actual application process, a selective etching solution with a higher etching rate for the N-type doped silicon layer and a lower etching rate for the P-type doped silicon layer can be used to achieve selective etching of the portion of the stacked material layer formed on the first semiconductor stack for manufacturing the second semiconductor stack, thereby saving the process of forming the above insulating layer on the portion of the first semiconductor stack corresponding to the isolation region, simplifying the manufacturing process of the back-contact heterojunction solar cell, and reducing the manufacturing cost of the back-contact heterojunction solar cell.

[0019] As a possible implementation, the thickness of the second intrinsic silicon layer is 1 nm to 20 nm. In this case, the thickness of the second intrinsic silicon layer is moderate, which can prevent leakage between the N-type doped silicon layer and the P-type doped silicon layer due to the small thickness of the second intrinsic silicon layer. At the same time, it can also prevent the difficulty of electrons passing through the part of the second intrinsic silicon layer located on the N-type region through the tunneling effect due to the large thickness of the second intrinsic silicon layer, ensuring that the second intrinsic silicon layer has a tunneling resistance of a suitable size, and ensuring that the back-contact heterojunction solar cell has excellent electrical properties.

[0020] In a second aspect, the present invention provides a method for manufacturing a back-contact heterojunction solar cell, the method for manufacturing a back-contact heterojunction solar cell comprising:

[0021] A silicon heterojunction substrate is formed. The silicon heterojunction substrate has a first surface and a second surface opposite to each other. Along a direction parallel to the second surface, the second surface has P-type regions and N-type regions alternately arranged.

[0022] A first transparent conductive layer is formed at least on the P-type region, and a second transparent conductive layer is formed at least on the N-type region. The portion of the second transparent conductive layer located on the N-type region is insulated from the portion of the first transparent conductive layer located on the P-type region. The work function of the second transparent conductive layer is smaller than the work function of the first transparent conductive layer.

[0023] As a possible implementation manner, the step of forming the first transparent conductive layer at least on the P-type region and forming the second transparent conductive layer at least on the N-type region includes:

[0024] A second transparent conductive material layer is formed to cover at least the P-type region and the N-type region.

[0025] At least a portion of the second transparent conductive material layer located on the P-type region is removed, so that the remaining portion of the second transparent conductive material layer forms a second transparent conductive layer.

[0026] A first transparent conductive material layer is formed to cover at least the P-type region and the second transparent conductive layer.

[0027] An insulating groove is formed that penetrates at least the first transparent conductive material layer and the second transparent conductive layer simultaneously, so that a portion of the first transparent conductive material layer located on the P-type region and a portion of the second transparent conductive layer located on the N-type region are insulated from each other.

[0028] The portion of the first transparent conductive material layer located on the second transparent conductive layer is removed, so that the remaining portion of the first transparent conductive material layer forms the first transparent conductive layer.

[0029] When the above technical solution is adopted, the second transparent conductive material layer used to manufacture the second transparent conductive layer and the first transparent conductive material layer used to manufacture the first transparent conductive layer are formed step by step in different operation steps, so that the factors affecting the work function of the first transparent conductive material layer and the second transparent conductive material layer (for example, material) can be separately regulated according to the smaller work function corresponding to the N-type region and the larger work function corresponding to the P-type region, thereby reducing the difficulty of manufacturing the first transparent conductive layer and the second transparent conductive layer that meet the corresponding work function requirements.

[0030] As a possible implementation, the above-mentioned removing at least the portion of the second transparent conductive material layer located on the P-type region includes: forming a mask layer at least on the portion of the second transparent conductive material layer corresponding to the N-type region. Under the masking effect of the mask layer, at least the portion of the second transparent conductive material layer located on the P-type region is removed.

[0031] Forming the first transparent conductive material layer at least covering the P-type region and the second transparent conductive layer includes: forming the first transparent conductive material layer at least covering the P-type region and the mask layer.

[0032] After removing the portion of the first transparent conductive material layer located on the mask layer, the method for manufacturing a back-contact heterojunction solar cell further includes: removing the mask layer.

[0033] In the case of adopting the above technical solution, before at least removing the portion of the second transparent conductive material layer located on the P-type region, a mask layer is formed on the portion of the second transparent conductive material layer corresponding to the second transparent conductive layer. The mask layer can ensure that the surface of the second transparent conductive layer away from the silicon heterojunction substrate is not affected by the patterning process during the patterning process of the second transparent conductive material layer, thereby improving the film formation quality of the second transparent conductive layer and further improving the yield of the back contact heterojunction solar cell.

[0034] As a possible implementation, the mask layer is an ink mask layer or a photoresist mask layer. In this case, removing the portion of the first transparent conductive material layer located on the mask layer includes: removing the portion of the first transparent conductive material layer located on the mask layer by a stripping process. And / or, removing the mask layer includes: removing the mask layer by a wet etching process.

[0035] In the case of adopting the above technical solution, the stripping process is a pattern transfer process technology that does not require an etching process. Compared with the etching process, the stripping process is easier to implement and has a simpler operation process. In this case, since the adhesion between the ink mask layer and the photoresist mask layer and the first transparent conductive material layer is relatively poor, the above stripping process can be used to remove the portion of the first transparent conductive layer located on the mask layer, thereby reducing the difficulty of patterning the first transparent conductive material layer and simplifying the patterning process of the first transparent conductive material layer.

[0036] In addition, as mentioned above, when the mask layer is an ink mask layer or a photoresist mask layer, the adhesion between the mask layer and the first transparent conductive material layer made of a conductive material is relatively poor. Therefore, when the mask layer is removed by a wet etching process, the portion of the first transparent conductive material layer located on the surface of the mask layer will also float. The adhesion between the portion of the first transparent conductive material layer that is not formed on the mask layer and the silicon heterojunction substrate is relatively strong, so that the portion is retained after the wet etching process, and the patterning of the first transparent conductive material layer is achieved. In other words, when the mask layer is removed by a wet etching process, the patterning of the first transparent conductive material layer is also achieved, thereby improving the manufacturing efficiency of the back contact heterojunction solar cell.

[0037] As a possible implementation manner, the above-mentioned forming of a silicon heterojunction substrate includes: providing a silicon substrate.

[0038] A first semiconductor stack is formed at least on a portion of the silicon substrate corresponding to the P-type region. Along a direction away from the silicon substrate, the first semiconductor stack includes a first intrinsic silicon layer and a P-type doped silicon layer located on the first intrinsic silicon layer.

[0039] Under the masking action of the same mask layer, a second semiconductor stack is formed at least on the portion of the silicon substrate corresponding to the N-type region. The mask layer is formed at least on the portion of the second transparent conductive material layer located on the N-type region. Along the direction away from the silicon substrate, the second semiconductor stack includes a second intrinsic silicon layer and an N-type doped silicon layer located on the second intrinsic silicon layer. The silicon heterojunction substrate includes a silicon substrate, a first semiconductor stack and a second semiconductor stack.

[0040] In the case of adopting the above technical solution, after forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, under the masking action of the same mask layer, the second semiconductor stack is formed at least on the portion of the silicon substrate corresponding to the N-type region. The mask layer is the mask layer used when removing at least the portion of the second transparent conductive material layer located on the P-type region as mentioned above. In this case, during the etching process, the mask layer can not only protect the portion of the second transparent conductive material layer located thereunder, but also protect the stacking material layer used to manufacture the second semiconductor stack. There is no need to form two mask layers in different operation steps in order to realize patterning of the second transparent conductive material layer and the stacking material layer, thereby simplifying the manufacturing process of the back contact heterojunction solar cell.

[0041] As a possible implementation method, after forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, and before forming the second transparent conductive material layer covering at least the P-type region and the N-type region, the method for manufacturing a back-contact heterojunction solar cell includes: forming a stacked material layer directly covering the first semiconductor stack and the portion of the silicon substrate corresponding to the N-type region.

[0042] The method for manufacturing a back-contact heterojunction solar cell includes: under the masking action of the mask layer, after at least the portion of the second transparent conductive material layer located on the P-type region is removed, and before forming a first transparent conductive material layer covering at least the P-type region and the mask layer, the method includes: under the masking action of the same mask layer, using a selective etching solution to remove at least the portion of the stacked material layer located above the P-type region, so that the remaining portion of the stacked material layer forms a second semiconductor stack.

[0043] As a possible implementation manner, the selective etching solution includes at least one of a KOH solution and a NaOH solution, and a reaction inhibitor.

[0044] In the case of adopting the above technical solution, since the majority of carriers in the N-type doped silicon layer included in the second semiconductor stack are electrons, and the majority of carriers in the P-type doped silicon layer included in the first semiconductor stack are holes. In addition, the stacked material layer is a material layer used to manufacture the second semiconductor stack. Based on this, since the above-mentioned selective etching solution includes at least one of a KOH solution and a NaOH solution, the selective etching solution is an alkaline solution. When alkaline etching is performed by the selective etching solution, at least one of the KOH solution and the NaOH solution will first oxidize the portion of the stacked material layer exposed outside the mask layer to form an oxide film, and then the stacked material layer is etched by removing the oxide film. In the above-mentioned oxidation process, the oxidized substance loses electrons. In this case, since the majority of carriers in the N-type doped silicon layer are electrons, the electron concentration therein is much greater than the electron concentration in the P-type doped silicon layer, and therefore the selective etching of at least one of the KOH solution and the NaOH solution has a much greater oxidation rate on the stacked material layer than on the first semiconductor stack, and further, in the entire selective etching process, the etching rate and etching amount of the selective etching solution on the stacked material layer are respectively much greater than the etching rate and etching amount of the first semiconductor stack, so that even if the insulating layer acting as a mask is not formed on the first semiconductor stack, the first semiconductor stack will not be etched to a large extent, simplifying the manufacturing process of the back-contact heterojunction solar cell and ensuring the yield of the back-contact heterojunction solar cell. In addition, in the above etching process, the reaction inhibitor can simultaneously reduce the etching rate of the selective etching solution on the stacked material layer and the first semiconductor stack, so as to further ensure that after removing the portion of the stacked material layer located on the P-type region, the first semiconductor layer will not be affected by the selective etching solution, and the impact is small.

[0045] As a possible implementation method, after forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, and before forming the second semiconductor stack at least on the portion of the silicon substrate corresponding to the N-type region under the masking action of the same mask layer, the method for manufacturing a back-contact heterojunction solar cell also includes: opening a groove on the portion of the silicon substrate corresponding to the N-type region.

[0046] As a possible implementation, when the surface of the P-type region is a polished surface and the bottom surface of the groove is a velvet surface, the deposition time corresponding to the second intrinsic silicon layer is 1.2 to 2 times the deposition time corresponding to the first intrinsic silicon layer.

[0047] When the above technical solution is adopted, the suede surface has an undulating surface morphology, while the polished surface has a flat surface morphology, so the specific surface area of ​​the suede surface is greater than the specific surface area corresponding to the polished surface. Moreover, within a certain period of time, the deposition thickness of the intrinsic silicon material on the surface with a larger specific surface area is less than the deposition thickness of the intrinsic silicon material on the surface with a smaller specific surface area. In this case, when the surface of the P-type region is a polished surface and the bottom surface of the groove is a velvet surface, since the first intrinsic silicon layer is at least formed on the P-type region and the second intrinsic silicon layer covers at least the bottom surface and side walls of the groove, and the deposition thickness of the intrinsic silicon material is proportional to the deposition time, when the deposition time corresponding to the second intrinsic silicon layer is 1.2 to 2 times that of the first intrinsic silicon layer, the problem of difficulty in isolating the P-type doped silicon layer and the N-type doped silicon layer located in the isolation region through the second intrinsic silicon layer due to the small deposition thickness of the second intrinsic silicon layer can be prevented. At the same time, the problem of the large tunneling resistance of the portion of the second intrinsic silicon layer located in the N-type region affecting the electron extraction due to the large deposition thickness of the second intrinsic silicon layer can be prevented, thereby ensuring that the manufactured back-contact heterojunction solar cell has stable electrical properties.

[0048] As another possible implementation, after providing the silicon substrate, before forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, the method for manufacturing a back-contact heterojunction solar cell further includes: opening a groove on the portion of the silicon substrate corresponding to the P-type region.

[0049] In a third aspect, the present invention further provides another back-contact heterojunction solar cell, which includes: a silicon substrate, a first semiconductor stack and a second semiconductor stack.

[0050] The silicon substrate has a first surface and a second surface opposite to each other. Along a direction parallel to the second surface, the second surface has a first region and a second region arranged alternately and spaced apart. The second region has a groove that is concave inward relative to the surface of the first region. The first semiconductor stack is formed at least on the first region. Along a direction away from the silicon substrate, the first semiconductor stack includes a first intrinsic silicon layer and a first doped silicon layer located on the first intrinsic silicon layer. The second semiconductor stack covers at least the sidewalls and the bottom of the groove. Along a direction away from the silicon substrate, the second semiconductor stack includes a second intrinsic silicon layer and a second doped silicon layer located on the second intrinsic silicon layer. The conductivity type of the second doped silicon layer is opposite to the conductivity type of the first doped amorphous layer.

[0051] In a fourth aspect, the present invention further provides another back-contact heterojunction solar cell, which includes: a silicon substrate, a first semiconductor stack and a second semiconductor stack.

[0052] The silicon substrate has a first surface and a second surface relative to each other. Along a direction parallel to the second surface, the second surface has a first region and a second region alternately arranged at intervals, and an isolation region between each first region and the second region. A first semiconductor stack is formed on the first region and the isolation region. Along a direction away from the silicon substrate, the first semiconductor stack includes a first intrinsic silicon layer and a P-type doped silicon layer located on the first intrinsic silicon layer. A second semiconductor stack is formed on the second region and a portion of the first semiconductor stack located on the isolation region. The portion of the second semiconductor stack located on the isolation region is in direct contact with the portion of the first semiconductor stack located on the isolation region. Along a direction away from the silicon substrate, the second semiconductor stack includes a second intrinsic silicon layer and an N-type doped silicon layer located on the second intrinsic silicon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0054] Figure 1 A schematic longitudinal cross-sectional view of the structure of a silicon substrate provided by an embodiment of the present invention;

[0055] Figure 2 It is a schematic longitudinal cross-sectional view of a structure after a first intrinsic silicon material layer, a P-type doped silicon material layer and a texturing mask layer are sequentially formed on a surface of the silicon substrate corresponding to the second surface in an embodiment of the present invention;

[0056] Figure 3 It is a schematic longitudinal cross-sectional view of the structure after the texturing mask layer, the P-type doped silicon material layer and the first intrinsic silicon material layer are patterned in an embodiment of the present invention;

[0057] Figure 4 It is a schematic longitudinal cross-sectional view of a structure after a surface of a silicon substrate corresponding to the first surface and a portion of the silicon substrate corresponding to the N-type region are textured and grooves are formed in an embodiment of the present invention;

[0058] Figure 5 1 is a schematic longitudinal cross-sectional view of the structure after a third intrinsic silicon layer, a conductive doped silicon layer and an anti-reflection layer are formed on a surface of the silicon substrate corresponding to the first surface, and a second intrinsic silicon material layer, an N-type doped silicon material layer and a second transparent conductive material layer are sequentially formed to cover at least the first semiconductor stack and the N-type region.

[0059] Figure 6 is a schematic longitudinal cross-sectional view of a structure after a mask layer is formed on the second transparent conductive material layer in an embodiment of the present invention;

[0060] Figure 7It is a schematic longitudinal cross-sectional view of the structure after the second semiconductor stack and the second transparent conductive layer are formed in the embodiment of the present invention;

[0061] Figure 8 A schematic longitudinal cross-sectional view of the structure of a silicon heterojunction substrate according to an embodiment of the present invention;

[0062] Fig. 9 It is a schematic longitudinal cross-sectional view of the structure after forming a first transparent conductive material layer at least covering the P-type region and the mask layer in an embodiment of the present invention;

[0063] Fig.10 It is a longitudinal cross-sectional schematic diagram of a first structure after the insulating groove is formed in an embodiment of the present invention;

[0064] Fig.11 It is a longitudinal cross-sectional schematic diagram of a second structure after the insulating groove is formed in the embodiment of the present invention;

[0065] Fig.12 It is a longitudinal cross-sectional schematic diagram of a third structure after the insulating groove is formed in the embodiment of the present invention;

[0066] Fig.13 A schematic longitudinal cross-sectional view of a first structure of a back-contact heterojunction solar cell provided by an embodiment of the present invention;

[0067] Fig.14 A schematic longitudinal cross-sectional view of a second structure of a back-contact heterojunction solar cell provided by an embodiment of the present invention;

[0068] Fig.15 A schematic longitudinal cross-sectional view of a third structure of a back-contact heterojunction solar cell provided by an embodiment of the present invention;

[0069] Fig.16 A flow chart of a method for manufacturing a back-contact heterojunction solar cell provided in an embodiment of the present invention.

[0070] Figure numerals: 11 is a silicon heterojunction substrate, 12 is a first surface, 13 is a second surface, 14 is a P-type region, 15 is an N-type region, 16 is a first transparent conductive layer, 17 is a second transparent conductive layer, 18 is a silicon substrate, 19 is a first semiconductor stack, 20 is a first intrinsic silicon layer, 21 is a P-type doped silicon layer, 22 is a second semiconductor stack, 23 is a second intrinsic silicon layer, 24 is an N-type doped silicon layer, 25 is a groove, 26 is an isolation region, 27 is Insulating groove, 28 is the third intrinsic silicon layer, 29 is the conductive doped silicon layer, 30 is the anti-reflection layer, 31 is the first electrode, 32 is the second electrode, 33 is the first intrinsic silicon material layer, 34 is the P-type doped silicon material layer, 35 is the second intrinsic silicon material layer, 36 is the N-type doped silicon material layer, 37 is the second transparent conductive material layer, 38 is the mask layer, 39 is the first transparent conductive material layer, 40 is the first region, 41 is the second region, and 42 is the third region. DETAILED DESCRIPTION

[0071] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0072] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may further design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0073] In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0074] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0075] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0076] Back-contact heterojunction solar cells are a type of cell structure that has no metal electrode shading on the front, high open-circuit voltage, high conversion efficiency, low temperature coefficient, and no photoinduced degradation. They have received extensive attention from the photovoltaic academic and industrial circles and have become a popular development direction for high-efficiency solar cell technology.

[0077] In the working state of the existing back-contact heterojunction solar cell, the crystalline silicon substrate included therein generates electron-hole pairs after absorbing photons. Among them, the holes pass through the first intrinsic passivation layer and the P-type doped layer to enter the first transparent conductive layer, and are collected by the first metal electrode formed on the first transparent conductive layer. The electrons pass through the second intrinsic passivation layer and the N-type doped layer to enter the second transparent conductive layer, and are collected by the second metal electrode formed on the second transparent conductive layer, thereby forming a photocurrent. Specifically, the interface between the above-mentioned P-type doped layer and the first metal electrode is a typical metal-semiconductor contact interface. A first transparent conductive layer is provided between the P-type doped layer and the first metal electrode to reduce the contact barrier between the P-type doped layer and the first metal electrode, which is conducive to the transmission of holes from the P-type doped layer to the first metal electrode through the first transparent conductive layer. Similarly, the second transparent conductive layer is used to reduce the contact barrier between the N-type doped layer and the second metal electrode, which is conducive to the transmission of electrons from the N-type doped layer to the second metal electrode through the second transparent conductive layer, thereby facilitating the improvement of the photoelectric conversion efficiency of the back-contact heterojunction solar cell.

[0078] However, the first transparent conductive layer and the second transparent conductive layer of opposite polarity included in the existing back contact heterojunction solar cell are formed simultaneously in the same operation step, so that the materials of the two are exactly the same. Alternatively, part of the material of one of the first transparent conductive layer and the second transparent conductive layer is formed in the same operation step as the other, resulting in the first transparent conductive layer and the second transparent conductive layer having part of the same material. For example: along the direction away from the crystalline silicon substrate, the first transparent conductive layer includes a first transparent conductive film and a second transparent conductive film located on the first transparent conductive film. Among them, only after the first transparent conductive film is formed on the P-type doped layer, the second transparent conductive film and the second transparent conductive layer are formed simultaneously in the same operation step. At this time, the material of the second transparent conductive film included in the first transparent conductive layer is exactly the same as the material of the second transparent conductive layer. It can be understood that the work function of the parts of the first transparent conductive layer and the second transparent conductive layer with the same material is the same. In addition, because the work function of the P-type doped layer is greater than the work function of the N-type doped layer, in order to simultaneously achieve the purpose of reducing the contact barrier of opposite conductivity types, it is necessary to adjust the work function of the first transparent conductive layer and the second transparent conductive layer according to the conductivity type. Based on this, in the case where at least part of the materials of the first transparent conductive layer and the second transparent conductive layer included in the existing back-contact heterojunction solar cell are the same, the part of the same material in the two only meets the work function matching requirements of one of the P-type doped layer and the N-type doped layer, resulting in one of the first transparent conductive layer and the second transparent conductive layer being unable to meet the energy level matching requirements, thereby affecting the further improvement of the performance of the back-contact heterojunction solar cell. For example: the work function of the above-mentioned second transparent conductive film only meets the work function matching requirements of the N-type doped layer, and it does not meet the work function matching requirements of the P-type doped layer. However, the first transparent conductive layer formed on the P-type doped layer includes the above-mentioned second transparent conductive film, which results in the first transparent conductive layer being unable to meet the energy level matching requirements, thereby making the contact barrier between the P-type doped layer and the first metal electrode larger, which is not conducive to the transmission of holes.

[0079] In order to solve the above technical problems, Fig.15 As shown, an embodiment of the present invention provides a back-contact heterojunction solar cell. The back-contact heterojunction solar cell includes: a silicon heterojunction substrate 11, a first transparent conductive layer 16, and a second transparent conductive layer 17. The silicon heterojunction substrate 11 has a first surface 12 and a second surface opposite to each other. Along a direction parallel to the second surface, the second surface has P-type regions and N-type regions alternately arranged at intervals. The first transparent conductive layer 16 is at least formed on the P-type region. The second transparent conductive layer 17 is at least formed on the N-type region. The portion of the second transparent conductive layer 17 located on the N-type region is insulated from the portion of the first transparent conductive layer 16 located on the P-type region. The work function of the second transparent conductive layer 17 is less than the work function of the first transparent conductive layer 16.

[0080] Specifically, the specific structure of the silicon heterojunction substrate can be set according to the actual application scenario. Figure 8 As shown, the silicon heterojunction substrate 11 may include: a silicon substrate 18, a first semiconductor stack 19 and a second semiconductor stack 22. The first semiconductor stack 19 is formed at least on a portion of the silicon substrate 18 corresponding to the P-type region 14. Along the direction away from the silicon substrate 18, the first semiconductor stack 19 includes a first intrinsic silicon layer 20 and a P-type doped silicon layer 21 located on the first intrinsic silicon layer 20. The second semiconductor stack 22 is formed at least on a portion of the silicon substrate 18 corresponding to the N-type region 15. Along the direction away from the silicon substrate 18, the second semiconductor stack 22 includes a second intrinsic silicon layer 23 and an N-type doped silicon layer 24 located on the second intrinsic silicon layer 23.

[0081] Among them, from the aspect of conductivity type, the above silicon substrate can be an N-type silicon substrate or a P-type silicon substrate. In addition, because the first surface of the silicon heterojunction substrate corresponds to the light-receiving surface of the back-contact heterojunction solar cell, and the second surface of the silicon heterojunction substrate corresponds to the backlight surface of the back-contact heterojunction solar cell. Based on this, from the aspect of structure, the side of the silicon substrate corresponding to the first surface of the silicon heterojunction substrate can be a polished surface. Or, as Fig.15 As shown, the side of the silicon substrate 18 corresponding to the first side 12 may also be a velvet surface with a velvet structure. In this case, because the velvet structure has a light trapping effect, when the side of the silicon substrate 18 corresponding to the first side 12 has a velvet structure, more light can be refracted into the silicon substrate 18, thereby improving the photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0082] The surface morphology of the silicon substrate and the surface corresponding to the second surface of the silicon heterojunction base can be set according to actual needs, as long as it can be applied to the back-contact heterojunction solar cell provided in the embodiment of the present invention.

[0083] For the first semiconductor stack and the second semiconductor stack, the formation range of the first semiconductor stack and the second semiconductor stack on the side of the silicon substrate corresponding to the second side can be set according to actual needs. Figure 8 As shown, for the convenience of subsequent description, the side of the silicon substrate 18 corresponding to the second side 13 can be divided into first regions 40 and second regions 41 that are alternately distributed along the direction parallel to the second side 13, and a third region 42 between each first region 40 and the second region 41. In this case, the first semiconductor stack 19 can be formed only on the first region 40 of the silicon substrate 18. At this time, the region corresponding to the P-type doped silicon layer 21 included in the first semiconductor stack 19 is the P-type region 14 of the silicon heterojunction substrate 11. Or, as Fig.14 and Fig.15As shown, the first semiconductor stack 19 can also be formed on the first region and the third region. At this time, the region corresponding to the portion of the P-type doped silicon layer 21 located on the first region is the P-type region of the silicon heterojunction substrate 11 .

[0084] As for the second semiconductor stack, the second semiconductor stack can be formed only on the second region of the silicon substrate. In this case, the region corresponding to the N-type doped silicon layer included in the second semiconductor stack is the N-type region of the silicon heterojunction substrate. Or, Fig.14 and Fig.15 As shown, the second semiconductor stack 22 can also be formed on the second region and the third region. At this time, the region corresponding to the portion of the N-type doped silicon layer 24 located on the second region is the N-type region of the silicon heterojunction substrate 11 .

[0085] Among them, Figure 8 As shown, when at least one of the first semiconductor stack 19 and the second semiconductor stack 22 is also formed on the third region 42 of the silicon substrate 18, the second surface 13 of the silicon heterojunction substrate 11 also includes an isolation region 26 between each P-type region 14 and the N-type region 15. The isolation region 26 is a region corresponding to the portion of the first semiconductor stack 19 and the second semiconductor stack 22 formed on the third region 42 of the silicon substrate 18. Specifically, when the first semiconductor stack 19 and the second semiconductor stack 22 are also formed on the third region 42, the portion of the first semiconductor stack located on the third region may be formed on the portion of the second semiconductor stack located on the third region. Or, as Figure 8 As shown, the portion of the second semiconductor stack 22 located on the third region 42 may also be formed on the portion of the first semiconductor stack 19 located on the third region 42. Fig.15As shown, when the first semiconductor stack 19 is also formed on the portion of the silicon substrate 18 corresponding to the isolation region 26, the second semiconductor stack 22 can also be formed on the portion of the first semiconductor stack 19 corresponding to the isolation region 26, and the portion of the second semiconductor stack 22 corresponding to the isolation region 26 can be in direct contact with the portion of the first semiconductor stack 19 corresponding to the isolation region 26. At this time, compared with the prior art in which the portion of the first semiconductor stack 19 corresponding to the isolation region 26 has an insulating layer that at least acts as a mask, the portion of the second semiconductor stack 22 corresponding to the isolation region 26 in the back-contact heterojunction solar cell provided by the embodiment of the present invention is in direct contact with the portion of the first semiconductor stack 19 corresponding to the isolation region 26. Based on this, in actual application, a selective etching solution with a higher etching rate for the N-type doped silicon layer 24 and a lower etching rate for the P-type doped silicon layer 21 can be used to achieve selective etching of the portion of the stacked material layer for manufacturing the second semiconductor stack 22 formed on the first semiconductor stack 19, thereby saving the process of forming the above-mentioned insulating layer on the portion of the first semiconductor stack 19 corresponding to the isolation area 26, simplifying the manufacturing process of the back-contact heterojunction solar cell, and reducing the manufacturing cost of the back-contact heterojunction solar cell.

[0086] In addition, the first intrinsic silicon layer included in the first semiconductor stack and the second intrinsic silicon layer included in the second semiconductor stack may be made of amorphous silicon or microcrystalline silicon. The thickness of the first intrinsic silicon layer and the second intrinsic silicon layer may be set according to actual application scenarios.

[0087] Furthermore, the above-mentioned P-type doped silicon layer may be an amorphous silicon layer or a microcrystalline silicon layer doped with P-type impurities such as boron. The N-type doped silicon layer may be an amorphous silicon layer or a microcrystalline silicon layer doped with N-type impurities such as phosphorus. Among them, the doping concentration of impurities of corresponding doping types in the P-type doped silicon layer and the N-type doped silicon layer, and the thickness of the P-type doped silicon layer and the N-type doped silicon layer can be set according to the actual application scenario.

[0088] For the first transparent conductive layer and the second transparent conductive layer, the material and thickness of the first transparent conductive layer and the second transparent conductive layer can be set according to actual needs, as long as the work function of the second transparent conductive layer can be smaller than the work function of the first transparent conductive layer. Specifically, the work functions of the first transparent conductive layer and the second transparent conductive layer can be determined according to the work functions of the P-type region and the N-type region of the silicon heterojunction substrate, respectively, and are not specifically limited here.

[0089] In addition, the formation range of the first transparent conductive layer and the second transparent conductive layer on the second surface of the silicon heterojunction substrate can be set according to actual needs. Fig.15As shown, the first transparent conductive layer 16 can be formed only on the P-type region. Alternatively, in the case where the second surface of the silicon heterojunction substrate also has an isolation region, the first transparent conductive layer can also be formed on the isolation region. As for the second transparent conductive layer, it can be formed only on the N-type region. Alternatively, as Fig.15 As shown, in the case where the second surface of the silicon heterojunction substrate 11 further has an isolation region, the second transparent conductive layer 17 may also be formed on the isolation region.

[0090] Furthermore, in actual application, the portion of the first transparent conductive layer located on the P-type region and the portion of the second transparent conductive layer located on the N-type region can be insulated from each other by providing an insulating groove. The insulating groove can be filled with insulating materials such as air. The specific position of the insulating groove can be set according to the actual application scenario and is not specifically limited here.

[0091] In some cases, such as Figures 13 to 15 As shown, the back-contact heterojunction solar cell provided by the embodiment of the present invention further includes a first electrode 31 formed on the first transparent conductive layer 16, and a second electrode 32 formed on the second transparent conductive layer 17. The first electrode 31 and the second electrode 32 may be made of conductive materials such as silver, aluminum, copper, and nickel.

[0092] When the above technical solution is adopted, Fig.15As shown, the back-contact heterojunction solar cell provided by the embodiment of the present invention includes a first transparent conductive layer 16 formed at least on the P-type region of the silicon heterojunction substrate 11. The second transparent conductive layer 17 is formed at least on the N-type region of the silicon heterojunction substrate 11. In addition, because the conductivity types of the N-type region and the P-type region are opposite, when the portion of the second transparent conductive layer 17 located on the N-type region and the portion of the first transparent conductive layer 16 located on the P-type region are insulated from each other, leakage between the first transparent conductive layer 16 and the second transparent conductive layer 17 can be prevented. In addition, the first transparent conductive layer 16 is arranged between the P-type region and the first electrode 31 for collecting holes. The second transparent conductive layer 17 is arranged between the N-type region and the second electrode 32 for collecting electrons. In this case, because the work function of the N-type region of the silicon heterojunction substrate 11 is smaller than the work function of the P-type region, when the work function of the second transparent conductive layer 17 is smaller than the work function of the first transparent conductive layer 16, the work functions of the second transparent conductive layer 17 and the first transparent conductive layer 16 can be determined according to the smaller work function corresponding to the N-type region and the larger work function corresponding to the P-type region, respectively. This helps to reduce the contact barrier between the P-type region 14 and the first electrode 31 and the contact barrier between the N-type region 15 and the second electrode 32 in the back-contact heterojunction solar cell to a smaller target range at the same time, solving the problem in the prior art that only one of the two contact barriers can be reduced to the target range while the other cannot meet the preset requirements, thereby improving the photoelectric conversion efficiency of the back-contact heterojunction solar cell.

[0093] As a possible implementation, the material of the first transparent conductive layer is completely different from that of the second transparent conductive layer. In this case, the materials of the first transparent conductive layer and the second transparent conductive layer can be adjusted separately to prevent at least part of the material of one of the first transparent conductive layer and the second transparent conductive layer from being the same as the material of the other, thereby preventing the first transparent conductive layer from reducing the contact barrier between the P-type region and the first electrode and the second transparent conductive layer from reducing the contact barrier between the N-type region and the second electrode.

[0094] Specifically, the first transparent conductive layer and the second transparent conductive layer are made of completely different materials, which may mean that the elements contained in the material of the first transparent conductive layer are completely different or not completely the same as the elements contained in the material of the second transparent conductive layer. For example, the materials of the first transparent conductive layer and the second transparent conductive layer may be any two different ones of fluorine-doped tin oxide, aluminum-doped zinc oxide, tin-doped indium oxide, tungsten-doped indium oxide, molybdenum-doped indium oxide, cerium-doped indium oxide, and indium hydroxide.

[0095] Alternatively, it may also mean that the elements contained in the material of the first transparent conductive layer are the same as the elements contained in the material of the second transparent conductive layer, and the ratio of at least one element in the first transparent conductive layer is different from the ratio of the corresponding element in the second transparent conductive layer. For example, when the materials of the first transparent conductive layer and the second transparent conductive layer are both tin-doped indium oxide, the tin doping content in the first transparent conductive layer is different from the tin doping content in the second transparent conductive layer.

[0096] In actual application, in addition to separately regulating the materials of the first transparent conductive layer and the second transparent conductive layer to achieve a work function of the first transparent conductive layer greater than the work function of the second transparent conductive layer, factors that affect the work function, such as the thickness of the first transparent conductive layer and the second transparent conductive layer, and the type and amount of fluorine atoms or chlorine atoms adsorbed on the surface, can also be separately regulated.

[0097] For example, fluorine atoms may be adsorbed on the surface of the first transparent conductive layer, and the same number of chlorine atoms may be adsorbed on the surface of the second transparent conductive layer, so that the work function of the first transparent conductive layer is greater than the work function of the second transparent conductive layer. Alternatively, fluorine atoms may be adsorbed on the surfaces of both the first transparent conductive layer and the second transparent conductive layer, and the number of fluorine atoms adsorbed on the surface of the first transparent conductive layer is greater than the number of fluorine atoms adsorbed on the surface of the second transparent conductive layer, so that the work function of the first transparent conductive layer is greater than the work function of the second transparent conductive layer.

[0098] As a possible implementation, Figure 4 As shown, the portion of the silicon substrate 18 corresponding to the N-type region has a groove 25. And the second semiconductor stack at least covers the sidewall and bottom of the groove 25. In the above case, compared with the prior art in which the maximum surface heights of the N-type region and the P-type region of the silicon substrate 18 are equal, the portion of the silicon substrate 18 corresponding to the N-type region in the back-contact heterojunction solar cell provided by the embodiment of the present invention has a groove 25. At this time, the total surface area of ​​the silicon substrate 18 corresponding to the N-type region is the sum of the bottom area and the sidewall area of ​​the groove 25, so that the surface area of ​​the silicon substrate 18 corresponding to the N-type region is larger. Based on this, the portion of the second semiconductor stack formed on the N-type region can not only cover the bottom of the groove 25, but also cover the sidewall of the groove 25, so that the contact area between the second intrinsic silicon layer included in the second semiconductor stack and the N-type region can be increased, and then the passivation effect of the second intrinsic silicon layer on the N-type region can be improved. At the same time, the surface area of ​​the N-type doped silicon layer included in the second semiconductor stack can also be increased, that is, the conductive area of ​​the N-type region of the silicon heterojunction substrate 11 is increased, which is beneficial to increase the short-circuit current of the back-contact heterojunction solar cell and further improve the photoelectric conversion efficiency of the back-contact heterojunction solar cell.

[0099] Alternatively, as another possible implementation, the portion of the silicon substrate corresponding to the P-type region has a groove. And the first semiconductor stack at least covers the sidewall and bottom of the groove. The beneficial effects in this case can be analyzed with reference to the beneficial effects of the portion of the silicon substrate corresponding to the N-type region having a groove as described above, which will not be repeated here.

[0100] Specifically, the morphology of the above-mentioned groove can be set according to actual needs. Take the case where the portion of the silicon substrate corresponding to the N-type region has a groove as an example. In terms of the surface morphology of the bottom surface of the groove, the bottom surface of the groove can be a polished surface or a velvet surface. Fig.15 As shown, when the bottom surface of the groove is a velvet surface, when the size of the bottom surface of the groove is the same, because the velvet surface has an undulating surface morphology, compared with the flat polished surface of the bottom surface of the groove, when the bottom surface of the groove is a velvet surface, the bottom surface of the groove has a larger surface area, thereby further increasing the contact area between the second intrinsic silicon layer 23 and the N-type region, and further improving the passivation effect of the second intrinsic silicon layer 23 on the N-type region. At the same time, the conductive area of ​​the N-type region of the silicon heterojunction substrate 11 can be further increased, which is more conducive to improving the photoelectric conversion efficiency of the back contact heterojunction solar cell. When the portion of the silicon substrate corresponding to the P-type region has a groove and the bottom surface of the groove is a velvet surface, the beneficial effects can refer to the above beneficial effect analysis, which will not be repeated here.

[0101] In terms of the specifications of the groove, the width of the groove can be smaller than the width of the P-type region or the N-type region. Figure 4 As shown, the width of the groove 25 can also be equal to the width of the P-type region or the N-type region. Among them, taking the part of the silicon substrate 18 corresponding to the N-type region having the groove 25 as an example for explanation, when the width of the groove 25 can be equal to the width of the N-type region, the formation range of the groove 25 is the largest. At this time, the surface area of ​​the groove bottom and the side wall of the groove 25 are both the largest. Based on this, because the second semiconductor stack at least covers the groove bottom and the side wall of the groove 25, when the surface area of ​​the side wall of the groove 25 is increased, the surface area of ​​the second semiconductor stack will also be further increased. In addition, when the groove bottom surface of the groove 25 is a velvet surface, the increase in the surface area of ​​the groove bottom of the groove 25 will also further increase the surface area of ​​the second semiconductor stack. Among them, the effect of increasing the surface area of ​​the second semiconductor stack can be referred to the previous text, and will not be repeated here.

[0102] In addition, the depth of the above groove can be set according to actual needs and is not specifically limited here. Figure 4 As shown, the depth L of the groove 25 may be 1 μm to 10 μm. For example, the depth L of the groove 25 may be 1 μm, 3 μm, 5 μm, 7 μm or 10 μm. Figure 4As shown, when the bottom surface of the groove 25 is a velvet surface, the depth L of the groove 25 is equal to the distance between the top of the velvet structure and the notch of the groove 25.

[0103] When the above technical solution is adopted, Figure 4 As shown, a suitable depth L of the groove 25 can be selected as needed to prevent the surface area of ​​the first semiconductor stack or the second semiconductor stack formed on the groove 25 from increasing to a low degree due to the small depth L of the groove 25, which is not conducive to the beneficial effects of improving the passivation effect of the corresponding intrinsic silicon layer as mentioned above. At the same time, it can also prevent the problem of insufficient light absorption depth, easy breakage and hidden cracks due to the large thickness of the silicon substrate 18 corresponding to the N-type region or the P-type region due to the large depth L of the groove 25, thereby improving the yield and photoelectric conversion efficiency of the back contact heterojunction solar cell.

[0104] As a possible implementation, the thickness of the second intrinsic silicon layer may be 1 nm to 20 nm. For example, the thickness of the second intrinsic silicon layer may be 1 nm, 2 nm, 3 nm, 5 nm, 8 nm, 10 nm, 12 nm, 15 nm, 18 nm or 20 nm. When the above technical solution is adopted, the thickness of the second intrinsic silicon layer is moderate. When the portion of the second semiconductor stack corresponding to the isolation region is in direct contact with the portion of the first semiconductor stack corresponding to the isolation region, leakage between the N-type doped silicon layer and the P-type doped silicon layer due to the small thickness of the second intrinsic silicon layer can be prevented. At the same time, it can also prevent the difficulty of electrons passing through the portion of the second intrinsic silicon layer located on the N-type region through the tunneling effect due to the large thickness of the second intrinsic silicon layer, thereby ensuring that the second intrinsic silicon layer has a tunneling resistance of a suitable size and ensuring that the back-contact heterojunction solar cell has excellent electrical properties.

[0105] Of course, the thickness of the second intrinsic silicon layer may also be set to other appropriate values ​​according to actual application scenarios, which is not specifically limited here.

[0106] As a possible implementation, Fig.15 As shown, the second surface also has an isolation region between each P-type region and the N-type region, and the surface of the isolation region is a polished surface. In addition, there is an insulating material between the portion of the first transparent conductive layer 16 located on the P-type region and the portion of the second transparent conductive layer 17 located on the N-type region. The insulating material is located on the isolation region 26.

[0107] Specifically, the insulating material fills the insulating groove. Based on this, in terms of the depth of the insulating groove, Fig.15 As shown, the insulating groove 27 may be formed only between the portion of the first transparent conductive layer 16 located on the P-type region and the portion of the second transparent conductive layer 17 located on the N-type region. Fig.14As shown, when the first semiconductor stack 19 and the second semiconductor stack 22 are both formed in the third region of the silicon substrate 18, the insulating groove 27 also penetrates the upper one of the first semiconductor stack 19 and the second semiconductor stack 22. Alternatively, as Fig.13 As shown, when the first semiconductor stack 19 and the second semiconductor stack 22 are both formed in the third region of the silicon substrate 18 , the insulating trench 27 also penetrates the first semiconductor stack 19 and the second semiconductor stack 22 at the same time.

[0108] In terms of the width of the above-mentioned insulating groove, the width of the insulating groove can be less than or equal to the width of the isolation region, as long as the portion of the first transparent conductive layer located on the P-type region can be isolated from the portion of the second transparent conductive layer located on the N-type region by filling the insulating material in the insulating groove.

[0109] In the case of adopting the above technical solution, the insulating material located on the isolation area can isolate the portion of the first transparent conductive layer located on the P-type area from the portion of the second transparent conductive layer located on the N-type area. Based on this, in the actual manufacturing process, when the surface of the isolation area is a polished surface, the surface of the isolation area is relatively flat, which is conducive to making the portion of the first transparent conductive layer and the second transparent conductive layer formed on the isolation area also have a relatively flat morphology, and is convenient for completely removing the portion of the first transparent conductive material layer and the second transparent conductive material layer filled in the area of ​​the pre-formed insulating material before forming the insulating material on the isolation area, reducing the difficulty of removal, and preventing impurities from remaining, ensuring that the portion of the first transparent conductive layer located on the P-type area and the portion of the second transparent conductive layer located on the N-type area are insulated from each other, thereby improving the electrical stability of the back-contact heterojunction solar cell.

[0110] In some cases, such as Fig.15 As shown, the silicon heterojunction substrate 11 may further include a third intrinsic silicon layer 28, a conductive doped silicon layer 29 and an anti-reflection layer 30. Along the direction away from the silicon substrate 18, the third intrinsic silicon layer 28, the conductive doped silicon layer 29 and the anti-reflection layer 30 are sequentially stacked on the side of the silicon substrate 18 corresponding to the first surface 12. Among them, the third intrinsic silicon layer 28 can passivate the side of the silicon substrate 18 corresponding to the first surface 12. In addition, the conductive doped silicon layer 29 has the same conductivity type as the silicon substrate 18, and is a front surface field disposed on the side of the silicon substrate 18 corresponding to the first surface 12. Therefore, the field passivation effect can be used to reduce the minority carrier concentration on the surface of the silicon substrate 18, thereby reducing the surface recombination rate, and at the same time, the series resistance can be reduced, and the carrier transmission capacity can be improved.

[0111] As for the above-mentioned anti-reflection layer, the anti-reflection layer can reduce the reflected light on the side of the silicon substrate corresponding to the light-receiving surface, so that more light can be transmitted into the silicon substrate, further improving the photoelectric conversion efficiency of the back-contact heterojunction solar cell.

[0112] The material of the third intrinsic silicon layer and the conductive doped silicon layer may be amorphous silicon or microcrystalline silicon. The material of the anti-reflection layer may be silicon oxide, silicon nitride or aluminum oxide. The thickness of the third intrinsic silicon layer, the conductive doped silicon layer and the anti-reflection layer may be set according to actual needs and is not specifically limited here.

[0113] like Fig.16 As shown, an embodiment of the present invention provides a method for manufacturing a back-contact heterojunction solar cell. Figures 1 to 15 The manufacturing process is described by referring to the cross-sectional view of the operation shown in FIG. 1 . Specifically, the manufacturing method of the back contact heterojunction solar cell includes the following steps:

[0114] First, if Figure 8 As shown, a silicon heterojunction substrate 11 is formed. The silicon heterojunction substrate 11 has a first surface 12 and a second surface 13 opposite to each other. Along a direction parallel to the second surface 13, the second surface 13 has P-type regions 14 and N-type regions 15 arranged alternately. The specific structure of the silicon heterojunction substrate 11, as well as the materials of each structure and other information can be referred to in the previous text, and will not be repeated here.

[0115] Exemplarily, in the case where the silicon heterojunction substrate includes a silicon substrate, a first semiconductor stack and a second semiconductor stack, the above-mentioned formation of the silicon heterojunction substrate may include the following steps: Figure 1 As shown, a silicon substrate 18 is provided. Figure 3 As shown, a first semiconductor stack 19 is formed at least on a portion of the silicon substrate 18 corresponding to the P-type region. Along a direction away from the silicon substrate 18, the first semiconductor stack 19 includes a first intrinsic silicon layer 20 and a P-type doped silicon layer 21 located on the first intrinsic silicon layer 20. Figure 7 As shown, a second semiconductor stack 22 is formed at least on a portion of the silicon substrate 18 corresponding to the N-type region. In a direction away from the silicon substrate 18 , the second semiconductor stack 22 includes a second intrinsic silicon layer 23 and an N-type doped silicon layer 24 on the second intrinsic silicon layer 23 .

[0116] In actual application, Figure 2 As shown, after providing the silicon substrate 18, a first intrinsic silicon material layer 33 and a P-type doped silicon material layer 34 covering the side of the silicon substrate 18 corresponding to the second side can be sequentially formed by using low pressure chemical vapor deposition or plasma chemical vapor deposition. Figure 3As shown, laser etching, dry etching or wet etching can be used to pattern the first intrinsic silicon material layer and the P-type doped silicon material layer, at least retaining the first intrinsic silicon material layer and the P-type doped silicon material layer located on the P-type region corresponding to the silicon substrate 18, to form the first intrinsic silicon layer 20 and the P-type doped silicon layer 21. Figure 5 As shown, the above-mentioned deposition process is then used to form a second intrinsic silicon material layer 35 and an N-type doped silicon material layer 36 that at least cover the first semiconductor stack 19 and the portion of the silicon substrate 18 corresponding to the N-type region. Laser etching, dry etching, or wet etching processes can be used to pattern the second intrinsic silicon material layer and the N-type doped silicon material layer, at least retaining the second intrinsic silicon material layer and the N-type doped silicon material layer located on the N-type region of the silicon substrate 18, to form a second intrinsic silicon layer 23 and an N-type doped silicon layer 24, and obtain a silicon heterojunction substrate 11.

[0117] It should be noted that, as mentioned above, when the silicon substrate has a groove corresponding to the P-type region or the N-type region, it is necessary to form the groove on the corresponding region of the silicon substrate before forming the corresponding first semiconductor stack or second semiconductor stack.

[0118] For example, when the portion of the silicon substrate corresponding to the N-type region has a groove, after the first semiconductor stack is formed at least on the portion of the silicon substrate corresponding to the P-type region, and before the second semiconductor stack is formed at least on the portion of the silicon substrate corresponding to the N-type region, the method for manufacturing a back-contact heterojunction solar cell further includes the following steps: Figure 4 As shown, a groove 25 is formed in the portion of the silicon substrate 18 corresponding to the N-type region.

[0119] For another example: in the case where the portion of the silicon substrate corresponding to the P-type region has a groove, after providing the silicon substrate as mentioned above, before forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, the method for manufacturing a back-contact heterojunction solar cell also includes the step of: opening a groove on the portion of the silicon substrate corresponding to the P-type region.

[0120] Specifically, as described above, the bottom surface of the groove can be a polished surface or a velvet surface. When the bottom surface of the groove is a velvet surface and the light-receiving surface of the silicon substrate is also a velvet surface, Figure 4 As shown, under the masking action of the corresponding textured mask layer, the light-receiving surface of the silicon substrate 18 and the backlight surface of the silicon substrate 18 can be simultaneously subjected to wet chemical treatment, and the time of the wet chemical treatment can be appropriately extended so that a textured surface is formed on the light-receiving surface of the silicon substrate 18, and a groove 25 with a textured bottom surface is formed in the portion of the silicon substrate 18 corresponding to the N-type region or the P-type region, thereby improving the manufacturing efficiency of the back-contact heterojunction solar cell.

[0121] In addition, the velvet surface has an undulating surface morphology, while the polished surface has a flat surface morphology, so the specific surface area of ​​the velvet structure is greater than the specific surface area of ​​the polished surface, and the deposition thickness of the intrinsic silicon material on the surface with a smaller specific surface area is greater than the deposition thickness of the intrinsic silicon material on the surface with a larger specific surface area. Based on this, since the deposition thickness of the intrinsic silicon material is proportional to the deposition time, when the bottom surface of the groove is a velvet surface, and the surface of the silicon substrate without a groove is a polished surface, the deposition time corresponding to the formation of the corresponding first intrinsic silicon layer or the second intrinsic silicon layer on the groove can be appropriately extended to ensure that the deposition thickness of the corresponding first intrinsic silicon layer or the second intrinsic silicon layer on the velvet surface is approximately the same as the deposition thickness on the polished surface. Among them, the length of the extension of the deposition time can be determined according to the actual application scenario, and is not specifically limited here.

[0122] For example: Figure 5 As shown, when the surface of the P-type region is a polished surface and the bottom surface of the groove is a velvet surface, the deposition time corresponding to the second intrinsic silicon layer can be 1.2 to 2 times of the deposition time corresponding to the first intrinsic silicon layer 20. For example, the deposition time corresponding to the second intrinsic silicon layer can be 1.2 times, 1.3 times, 1.4 times, 1.5 times, 1.6 times, 1.7 times, 1.8 times, 1.9 times or 2 times of the deposition time corresponding to the first intrinsic silicon layer 20. In this case, when the deposition time corresponding to the second intrinsic silicon layer is 1.2 to 2 times of the deposition time corresponding to the first intrinsic silicon layer 20, the problem of difficulty in isolating the P-type doped silicon layer 21 and the N-type doped silicon layer located on the isolation region through the second intrinsic silicon layer due to the small deposition thickness of the second intrinsic silicon layer can be prevented, and the problem of the tunneling resistance of the part of the second intrinsic silicon layer located on the N-type region being large and affecting the electron extraction due to the large deposition thickness of the second intrinsic silicon layer can be prevented, thereby ensuring that the manufactured back-contact heterojunction solar cell has stable electrical properties.

[0123] For another example, when the surface of the N-type region is a polished surface and the bottom surface of the groove is a velvet surface, the deposition time corresponding to the first intrinsic silicon layer can be 1.2 to 2 times the deposition time corresponding to the second intrinsic silicon layer. The beneficial effects in this case can be analyzed with reference to the beneficial effects of the examples described above, and will not be repeated here.

[0124] It should also be noted that the above description is based on the example of forming the first semiconductor stack first to illustrate the process of forming a silicon heterojunction substrate. In actual application, the first semiconductor stack may also be formed after the second semiconductor stack is formed.

[0125] In addition, when the second semiconductor stack is formed after the first semiconductor stack is formed, an insulating layer for protection may be formed on the first semiconductor stack after the first semiconductor stack is formed. Then, the second intrinsic silicon material layer and the N-type doped silicon material layer are formed at least on the insulating layer and the portion of the silicon substrate corresponding to the N-type region. Alternatively, Figure 5 As shown, after forming the first semiconductor stack 19, the above process can be used to form a stack material layer directly covering the first semiconductor stack 19 and the portion of the silicon substrate 18 corresponding to the N-type region. The stack material layer is used to manufacture the second semiconductor stack 22, which includes a second intrinsic silicon material layer 35 and an N-type doped silicon material layer 36. Then, as Figure 7 As shown, under the masking effect of the mask layer 38 , a selective etching solution can be used to remove at least a portion of the stacked material layer located above the P-type region, so that the remaining portion of the stacked material layer forms the second semiconductor stack 22 .

[0126] The selective etching solution may be any etching solution having a higher etching rate for the stacked material layer than for the first semiconductor stacked layer, as long as it can be applied to the back-contact heterojunction solar cell provided in the embodiment of the present invention.

[0127] Exemplarily, the selective etching solution includes at least one of a KOH solution and a NaOH solution, and a reaction inhibitor. Specifically, the selective etching solution may be a mixture of a KOH solution and a reaction inhibitor. Alternatively, the selective etching solution may be a mixture of a NaOH solution and a reaction inhibitor. Alternatively, the selective etching solution may also be a mixture of a KOH solution, a NaOH solution and a reaction inhibitor. In addition, the above-mentioned reaction inhibitor may be an inorganic reaction inhibitor or an organic reaction inhibitor.

[0128] Among them, the type of reaction inhibitor and the ratio of KOH solution, NaOH solution and reaction inhibitor in the selective etching solution can be set according to actual needs, as long as it can be applied to the manufacturing method of the back-contact heterojunction solar cell provided in the embodiment of the present invention.

[0129] For example, the reaction inhibitor may be hydrogen peroxide or a surfactant. When the reaction inhibitor is hydrogen peroxide, the mass concentration of the reaction inhibitor is 0.01%wt to 1%wt. When the reaction inhibitor is a surfactant, the concentration of the reaction inhibitor is 1%ppm to 20%ppm.

[0130] For example, the mass concentration of KOH solution or NaOH solution is 0.1%wt to 10%wt.

[0131] In this case, since the majority carriers in the N-type doped silicon layer included in the second semiconductor stack are electrons, and the majority carriers in the P-type doped silicon layer included in the first semiconductor stack are holes. In addition, the stacked material layer is a material layer used to manufacture the second semiconductor stack. Based on this, since the above-mentioned selective etching solution includes at least one of a KOH solution and a NaOH solution, the selective etching solution is an alkaline solution. When alkaline etching is performed by the selective etching solution, at least one of the KOH solution and the NaOH solution will first oxidize the portion of the stacked material layer exposed outside the mask layer to form an oxide film, and then the stacked material layer is etched by removing the oxide film. In the above-mentioned oxidation process, the oxidized substance loses electrons. In this case, since the majority of carriers in the N-type doped silicon layer are electrons, the electron concentration therein is much greater than the electron concentration in the P-type doped silicon layer, and therefore the selective etching of at least one of the KOH solution and the NaOH solution has a much greater oxidation rate on the stacked material layer than on the first semiconductor stack, and further, in the entire selective etching process, the etching rate and etching amount of the selective etching solution on the stacked material layer are respectively much greater than the etching rate and etching amount of the first semiconductor stack, so that even if the insulating layer acting as a mask is not formed on the first semiconductor stack, the first semiconductor stack will not be etched to a large extent, simplifying the manufacturing process of the back-contact heterojunction solar cell and ensuring the yield of the back-contact heterojunction solar cell. In addition, in the above etching process, the reaction inhibitor can simultaneously reduce the etching rate of the selective etching solution on the stacked material layer and the first semiconductor stack, so as to further ensure that after removing the portion of the stacked material layer located on the P-type region, the first semiconductor layer will not be affected by the selective etching solution, and the impact is small.

[0132] In some cases, as described above, when the silicon heterojunction substrate further includes a third intrinsic silicon layer, a conductive doped silicon layer and an anti-reflection layer, if the conductive doped silicon layer and the P-type doped silicon layer included in the first semiconductor stack have the same conductivity type, the third intrinsic silicon layer and the conductive doped silicon layer can be formed at the same time as the first intrinsic silicon material layer and the P-type doped silicon material layer are formed. Figure 5 As shown, if the conductive doped silicon layer 29 and the N-type doped silicon layer included in the second semiconductor stack have the same conductivity type, the third intrinsic silicon layer 28 and the conductive doped silicon layer 29 can be formed while forming the second intrinsic silicon material layer 35 and the N-type doped silicon material layer 36. Then, the anti-reflection layer 30 is formed by a deposition process. Alternatively, other formation orders of the third intrinsic silicon layer, the conductive doped silicon layer and the anti-reflection layer can also be determined according to actual application scenarios, which are not specifically limited here.

[0133] like Fig.15As shown, a first transparent conductive layer 16 is formed at least on the P-type region, and a second transparent conductive layer 17 is formed at least on the N-type region. The portion of the second transparent conductive layer 17 located on the N-type region is insulated from the portion of the first transparent conductive layer 16 located on the P-type region. The work function of the second transparent conductive layer 17 is smaller than the work function of the first transparent conductive layer 16.

[0134] Specifically, the formation range and material of the first transparent conductive layer and the second transparent conductive layer can be referred to in the above text, which will not be described in detail here.

[0135] Exemplarily, the above-mentioned forming of the first transparent conductive layer at least on the P-type region and the forming of the second transparent conductive layer at least on the N-type region may include the following steps: Figure 5 As shown in FIG. 1 , a second transparent conductive material layer 37 is formed to cover at least the P-type region and the N-type region. Figure 7 As shown, at least the portion of the second transparent conductive material layer located on the P-type region is removed, so that the remaining portion of the second transparent conductive material layer forms the second transparent conductive layer 17. Fig. 9 As shown, a first transparent conductive material layer 39 is formed to cover at least the P-type region and the second transparent conductive layer 17. Figures 10 to 12 As shown, an insulating groove 27 is formed that at least penetrates the first transparent conductive material layer 39 and the second transparent conductive layer 17 at the same time, so that the portion of the first transparent conductive material layer 39 located on the P-type region 14 and the portion of the second transparent conductive layer 17 located on the N-type region are insulated from each other. Finally, the portion of the first transparent conductive material layer located on the second transparent conductive layer 17 is removed, so that the remaining portion of the first transparent conductive material layer forms the first transparent conductive layer 16.

[0136] In the actual manufacturing process, the second transparent conductive material layer can be formed by chemical vapor deposition and other processes. Laser etching, dry etching or wet etching and other processes can be used to remove at least the portion of the second transparent conductive material layer located on the P-type region to obtain the second transparent conductive layer. Then, a deposition process can be used to form a first transparent conductive material layer that at least covers the P-type region and the second transparent conductive layer. Then, laser etching and other processes can be used to selectively etch at least the portion of the first transparent conductive material layer and / or the second transparent conductive layer located on the isolation region to form the above-mentioned insulating groove. Information such as the depth of the insulating groove can be referred to in the previous text and will not be repeated here. Finally, etching and other processes can be used to remove the portion of the first transparent conductive material layer located on the second transparent conductive layer to obtain the first transparent conductive layer.

[0137] Among them, Figure 6As shown, after forming the second transparent conductive material layer 37, a mask layer 38 can be formed on at least the portion of the second transparent conductive material layer 37 located on the N-type region. Specifically, the material of the mask layer 38 can be a mask material such as silicon oxide, silicon nitride, ink or photoresist. The formation process of the mask layer 38 can be determined according to the material of the mask layer 38. For example: when the material of the mask layer is silicon oxide or silicon nitride, the mask layer can be formed by a deposition and etching process. For another example: when the material of the mask layer is ink, the mask layer can be formed by a process such as screen printing. For another example: when the material of the mask layer is photoresist, the mask layer can be formed by a photolithography process. As shown in FIG. Figure 7 As shown, then, under the masking action of the mask layer 38, at least the portion of the second transparent conductive material layer located on the P-type region can be removed to ensure that the surface of the second transparent conductive layer 17 away from the silicon heterojunction substrate 11 is not affected by the patterning treatment, thereby improving the film formation quality of the second transparent conductive layer 17 and further improving the yield of the back-contact heterojunction solar cell.

[0138] It should be noted that, when at least the portion of the second transparent conductive material layer located on the P-type region is removed under the masking action of the mask layer, since the second transparent conductive layer to be formed by the second transparent conductive material layer is located on the second semiconductor stack, the formation range of the second transparent conductive layer on the silicon heterojunction substrate coincides with the boundary of the formation range of the second semiconductor stack on the silicon substrate. Based on this, the second transparent conductive material layer used to manufacture the second transparent conductive layer and the stacked material layer used to manufacture the second semiconductor stack can be patterned under the masking action of the same mask layer. In other words, Figure 7 As shown, during the above-mentioned patterning process, the mask layer 38 can not only protect the portion of the second transparent conductive material layer located thereunder, but also protect the stacked material layer for manufacturing the second semiconductor stack 22. There is no need to form two mask layers in different operation steps in order to pattern the second transparent conductive material layer and the stacked material layer, thereby simplifying the manufacturing process of the back-contact heterojunction solar cell.

[0139] In addition, when at least the portion of the second transparent conductive material layer located on the P-type region is removed under the masking effect of the mask layer, as Figure 7 As shown in FIG. 1 , after the second transparent conductive material layer is patterned, the mask layer 38 is still located on the obtained second transparent conductive layer 17. In this case, the mask layer can be removed before forming the first transparent conductive material layer. Alternatively, as shown in FIG. Fig. 9As shown, the mask layer 38 can also be retained before forming the first transparent conductive material layer 39. At this time, the above-mentioned formation of the first transparent conductive material layer 39 covering at least the P-type region and the second transparent conductive layer 17 is: forming the first transparent conductive material layer 39 covering at least the P-type region and the mask layer 38. And, after removing the portion of the first transparent conductive material layer located on the mask layer, it is necessary to remove the mask layer. Among them, the removal order of the above-mentioned mask layers can be set according to actual needs, and is not specifically limited here.

[0140] Exemplarily, when the mask layer is an ink mask layer or a photoresist mask layer, the mask layer can be removed after the insulating groove is formed. Based on this, the above-mentioned removal of the portion of the first transparent conductive material layer located on the mask layer can include the step of: removing the portion of the first transparent conductive material layer located on the mask layer by a stripping process. In addition, the mask layer can be removed by a wet etching process.

[0141] In the case of adopting the above technical solution, the stripping process is a pattern transfer process technology that does not require an etching process. Compared with the etching process, the stripping process is easier to implement and the operation process is simpler. In this case, because the ink mask layer and the photoresist mask layer have relatively poor adhesion to the first transparent conductive material layer, the above stripping process can be used to remove the portion of the first transparent conductive layer located on the mask layer, which reduces the difficulty of patterning the first transparent conductive material layer and simplifies the patterning process of the first transparent conductive material layer. In addition, as mentioned above, in the case where the mask layer is an ink mask layer or a photoresist mask layer, the adhesion between the mask layer and the first transparent conductive material layer made of a conductive material is relatively poor, so when the wet etching process is used to remove the mask layer, the portion of the first transparent conductive material layer located on the surface of the mask layer will also float. The portion of the first transparent conductive material layer that is not formed on the mask layer has relatively strong adhesion to the silicon heterojunction substrate, so that the portion is retained after the wet etching process, and the patterning process of the first transparent conductive material layer is realized. In other words, when the mask layer is removed by a wet etching process, the patterning of the first transparent conductive material layer is also achieved, thereby improving the manufacturing efficiency of the back-contact heterojunction solar cell.

[0142] It can be seen from the manufacturing process of the first transparent conductive layer and the second transparent conductive layer that the second transparent conductive material layer used to manufacture the second transparent conductive layer and the first transparent conductive material layer used to manufacture the first transparent conductive layer are formed step by step in different operation steps, so that the factors affecting the work function of the first transparent conductive material layer and the second transparent conductive material layer (for example, material) can be separately regulated according to the smaller work function corresponding to the N-type region and the larger work function corresponding to the P-type region, thereby reducing the manufacturing difficulty of forming the first transparent conductive layer and the second transparent conductive layer that meet the corresponding work function requirements.

[0143] Finally, if Figures 13 to 15 As shown, after forming the first transparent conductive layer 16 and the second transparent conductive layer 17, a first electrode 31 can be formed on the first transparent conductive layer 16 by screen printing or the like, and a second electrode 32 can be formed on the second transparent conductive layer 17. The materials of the first electrode 31 and the second electrode 32 can be referred to above and will not be described again here.

[0144] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0145] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, a person skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A back contact heterojunction solar cell, characterized in that: include: A silicon heterojunction substrate having a first surface and a second surface opposite to each other; Along a direction parallel to the second surface, the second surface has P-type regions and N-type regions alternately arranged; A first transparent conductive layer, formed at least on the P-type region; and a second transparent conductive layer, formed at least on the N-type region; A portion of the second transparent conductive layer located on the N-type region and a portion of the first transparent conductive layer located on the P-type region are insulated from each other; The work function of the second transparent conductive layer is smaller than the work function of the first transparent conductive layer; The silicon heterojunction substrate comprises: a silicon substrate, a first semiconductor stack and a second semiconductor stack; the first semiconductor stack is at least formed on a portion of the silicon substrate corresponding to the P-type region; the first semiconductor stack comprises a P-type doped silicon layer; the second semiconductor stack is at least formed on a portion of the silicon substrate corresponding to the N-type region; the second semiconductor stack comprises an N-type doped silicon layer; the work function of the P-type doped silicon layer is greater than the work function of the N-type doped silicon layer.

2. The back contact heterojunction solar cell according to claim 1, characterized in that: The material of the first transparent conductive layer is completely different from that of the second transparent conductive layer.

3. The back contact heterojunction solar cell according to claim 1, characterized in that: The first semiconductor stack further includes a first intrinsic silicon layer; along a direction away from the silicon substrate, the P-type doped silicon layer is located on the first intrinsic silicon layer; The second semiconductor stack further includes a second intrinsic silicon layer; along a direction away from the silicon substrate, the N-type doped silicon layer is located on the second intrinsic silicon layer.

4. The back contact heterojunction solar cell according to claim 3, characterized in that: The silicon substrate has a groove at a portion corresponding to the N-type region; the second semiconductor stack at least covers the sidewall and bottom of the groove; Alternatively, a portion of the silicon substrate corresponding to the P-type region has a groove; and the first semiconductor stack at least covers the sidewall and bottom of the groove.

5. The back contact heterojunction solar cell according to claim 4, characterized in that: The bottom surface of the groove is velvet; and / or, The depth of the groove is 1 μm to 10 μm.

6. The back-contact heterojunction solar cell according to any one of claims 3 to 5, characterized in that: The second surface also has an isolation region between each of the P-type regions and the N-type region, and the surface of the isolation region is a polished surface; An insulating material is provided between a portion of the first transparent conductive layer located on the P-type region and a portion of the second transparent conductive layer located on the N-type region; The insulating material is located on the isolation region.

7. The back-contact heterojunction solar cell according to claim 6, characterized in that: The first semiconductor stack is also formed on a portion of the silicon substrate corresponding to the isolation region; The second semiconductor stack is also formed on a portion of the first semiconductor stack corresponding to the isolation region, and the portion of the second semiconductor stack corresponding to the isolation region is in direct contact with the portion of the first semiconductor stack corresponding to the isolation region.

8. The back-contact heterojunction solar cell according to any one of claims 3 to 5, characterized in that: The second intrinsic silicon layer has a thickness of 1 nm to 20 nm.

9. A method for manufacturing a back-contact heterojunction solar cell, characterized in that: include: forming a silicon heterojunction substrate; The silicon heterojunction substrate has a first surface and a second surface opposite to each other; Along a direction parallel to the second surface, the second surface has P-type regions and N-type regions alternately arranged; The silicon heterojunction substrate comprises: a silicon substrate, a first semiconductor stack and a second semiconductor stack; the first semiconductor stack is formed at least on a portion of the silicon substrate corresponding to the P-type region; the first semiconductor stack comprises a P-type doped silicon layer; the second semiconductor stack is formed at least on a portion of the silicon substrate corresponding to the N-type region; the second semiconductor stack comprises an N-type doped silicon layer; the work function of the P-type doped silicon layer is greater than the work function of the N-type doped silicon layer; A first transparent conductive layer is formed at least on the P-type region, and a second transparent conductive layer is formed at least on the N-type region; a portion of the second transparent conductive layer located on the N-type region and a portion of the first transparent conductive layer located on the P-type region are insulated from each other; a work function of the second transparent conductive layer is smaller than a work function of the first transparent conductive layer.

10. The method for manufacturing a back-contact heterojunction solar cell according to claim 9, characterized in that: The forming of the first transparent conductive layer at least on the P-type region and the forming of the second transparent conductive layer at least on the N-type region comprises: forming a second transparent conductive material layer covering at least the P-type region and the N-type region; removing at least a portion of the second transparent conductive material layer located on the P-type region, so that the remaining portion of the second transparent conductive material layer forms the second transparent conductive layer; forming a first transparent conductive material layer covering at least the P-type region and the second transparent conductive layer; forming an insulating groove that at least penetrates the first transparent conductive material layer and the second transparent conductive layer simultaneously, so that a portion of the first transparent conductive material layer located on the P-type region and a portion of the second transparent conductive layer located on the N-type region are insulated from each other; The portion of the first transparent conductive material layer located on the second transparent conductive layer is removed, so that the remaining portion of the first transparent conductive material layer forms the first transparent conductive layer.

11. The method for manufacturing a back-contact heterojunction solar cell according to claim 10, characterized in that: The removing at least the portion of the second transparent conductive material layer located on the P-type region comprises: forming a mask layer at least on the portion of the second transparent conductive material layer corresponding to the N-type region; and removing at least the portion of the second transparent conductive material layer located on the P-type region under the masking effect of the mask layer; The forming of the first transparent conductive material layer at least covering the P-type region and the second transparent conductive layer comprises: forming the first transparent conductive material layer at least covering the P-type region and the mask layer; After removing the portion of the first transparent conductive material layer located on the mask layer, the method for manufacturing a back-contact heterojunction solar cell further includes: removing the mask layer.

12. The method for manufacturing a back-contact heterojunction solar cell according to claim 11, characterized in that: The mask layer is an ink mask layer or a photoresist mask layer; The removing of the portion of the first transparent conductive material layer located on the mask layer includes: removing the portion of the first transparent conductive material layer located on the mask layer by a stripping process; and / or, the removing of the mask layer includes: removing the mask layer by a wet etching process.

13. The method for manufacturing a back-contact heterojunction solar cell according to claim 11 or 12, characterized in that: The forming of the silicon heterojunction substrate comprises: Providing the silicon substrate; The first semiconductor stack is formed at least on a portion of the silicon substrate corresponding to the P-type region; along a direction away from the silicon substrate, the first semiconductor stack includes a first intrinsic silicon layer and the P-type doped silicon layer located on the first intrinsic silicon layer; Under the masking action of the same mask layer, the second semiconductor stack is formed at least on the portion of the silicon substrate corresponding to the N-type region; the mask layer is formed at least on the portion of the second transparent conductive material layer located on the N-type region; along the direction away from the silicon substrate, the second semiconductor stack includes a second intrinsic silicon layer and the N-type doped silicon layer located on the second intrinsic silicon layer.

14. The method for manufacturing a back-contact heterojunction solar cell according to claim 13, characterized in that: After forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, and before forming the second transparent conductive material layer covering at least the P-type region and the N-type region, the method for manufacturing a back-contact heterojunction solar cell includes: forming a stacked material layer directly covering the first semiconductor stack and the portion of the silicon substrate corresponding to the N-type region; After at least the portion of the second transparent conductive material layer located on the P-type region is removed under the masking action of the mask layer, and before the first transparent conductive material layer covering at least the P-type region and the mask layer is formed, the method for manufacturing a back-contact heterojunction solar cell includes: under the masking action of the same mask layer, using a selective etching solution to remove at least the portion of the stacked material layer located above the P-type region, so that the remaining portion of the stacked material layer forms the second semiconductor stack.

15. The method for manufacturing a back-contact heterojunction solar cell according to claim 14, characterized in that: The selective etching solution includes at least one of a KOH solution and a NaOH solution, and a reaction inhibitor.

16. The method for manufacturing a back-contact heterojunction solar cell according to claim 13, characterized in that: After forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, and before forming the second semiconductor stack at least on the portion of the silicon substrate corresponding to the N-type region under the masking action of the same mask layer, the method for manufacturing a back-contact heterojunction solar cell further includes: A groove is formed on a portion of the silicon substrate corresponding to the N-type region.

17. The method for manufacturing a back-contact heterojunction solar cell according to claim 16, characterized in that: When the surface of the P-type region is a polished surface and the bottom surface of the groove is a velvet surface, The deposition time corresponding to the second intrinsic silicon layer is 1.2 to 2 times of the deposition time corresponding to the first intrinsic silicon layer.

18. The method for manufacturing a back-contact heterojunction solar cell according to claim 13, characterized in that: After providing the silicon substrate, before forming the first semiconductor stack at least on the portion of the silicon substrate corresponding to the P-type region, the method for manufacturing a back-contact heterojunction solar cell further includes: opening a groove on the portion of the silicon substrate corresponding to the P-type region.

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