A high-gain operational amplifier circuit based on negative resistance technology

Abstract

The present invention discloses a high-gain operational amplifier circuit based on negative resistance technology, comprising an auxiliary operational amplifier A, multiple P-type MOS transistors, multiple N-type MOS transistors, a current source IB1, and a current source IB2. The multiple P-type MOS transistors are respectively designated as PMOS transistor P1, PMOS transistor P2, and PMOS transistor P3; and the multiple N-type MOS transistors are respectively designated as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, and NMOS transistor N4. The input end of the current source IB1 and the input end of the current source IB2 are both connected to a power supply voltage. The source of the PMOS transistor P1 and the source of the PMOS transistor P2 are connected and then connected together to the output end of the current source IB1. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N3.

Description

Technical Field

[0001] The present invention relates to the field of gain operational amplifier circuits, and more particularly to a high-gain operational amplifier circuit based on negative resistance technology. Background Art

[0002] In CMOS processes at 40nm and below, the supply voltage of core devices has dropped to 0.9V or even lower, yet the noise level of semiconductor devices has increased rather than decreased. Furthermore, in advanced CMOS processes, the output impedance of MOS transistors has severely degraded, and their intrinsic gain has decreased. As core components of analog circuits, op amps have high requirements for gain and output voltage swing, posing significant design challenges in advanced CMOS processes with low supply voltages.

[0003] An op amp is a single-pole system with high DC voltage gain. The intrinsic gain of MOS devices in traditional CMOS processes is only around 40dB, and even drops to around 20dB in advanced CMOS processes. Therefore, op amps typically employ a two-stage amplification structure, with the second stage typically employing a simple common-source bias to maximize the output voltage swing. Miller compensation is also used to achieve a dominant pole and push the output pole to the high frequency range.

[0004] At a power supply voltage of 0.9V, the average drain-source voltage drop of the MOS tube in the common-source and common-gate structure is only more than 200mV. The bias current and threshold voltage will change with temperature, process angle, etc. The voltage drop of the folding point current source may be as low as around 150mV. At this time, the output impedance of the current source will further deteriorate, which will lead to a decrease in the voltage gain of the op amp.

[0005] The disadvantages of the existing technology are as follows:

[0006] At low power supply voltages, bias circuit design is extremely challenging, and improper biasing can easily lead to a significant reduction in gain.

[0007] Even if the bias is normal, the open-loop gain of the folded cascode structure op amp at a voltage of 0.9V is often only 50-60dB.

[0008] The present invention solves the above problems, has a simple bias circuit, and achieves a DC gain of more than 70dB. At the same time, the output voltage swing is also very wide. Summary of the Invention

[0009] In order to solve at least one of the above technical problems, the present invention proposes a high-gain operational amplifier circuit based on negative resistance technology.

[0010] A first aspect of the present invention provides a high-gain operational amplifier circuit based on negative resistance technology, comprising: an adaptive control module, a plurality of P-type MOS transistors and a plurality of N-type MOS transistors, a current source IB1 and a current source IB2;

[0011] The plurality of P-type MOS transistors are respectively recorded as PMOS transistor P1, PMOS transistor P2, and PMOS transistor P3; the plurality of N-type MOS transistors are respectively recorded as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, and NMOS transistor N4;

[0012] The input end of the current source IB1 and the input end of the current source IB2 are both connected to the power supply voltage. The source of the PMOS transistor P1 and the source of the PMOS transistor P2 are connected and connected to the output end of the current source IB1. The drain of the PMOS transistor P1 is connected to the adaptive control module.

[0013] The drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N2, the source of the NMOS transistor N2 is connected to the source of the NMOS transistor N4, and the two are grounded together. The gate of the NMOS transistor N4 is connected to the drain of the NMOS transistor N2, and the drain of the NMOS transistor N4 is connected to the output end of the current source IB2.

[0014] The gate of the PMOS tube P1 is connected to the voltage input terminal V inn , the gate of PMOS tube P2 is connected to the voltage input terminal V inp , the gate of PMOS tube P3 is grounded.

[0015] In a preferred embodiment of the present invention, NMOS tubes N1, N3 and auxiliary operational amplifier A constitute an adaptive control module (whose gain is set to A ACF ), so that the equivalent output impedance of the NMOS tube N2 is increased by times the intrinsic gain of the MOS tube.

[0016] Through small signal model analysis, the equivalent output impedance of the N2 tube in the first stage of the op amp is

[0017] R out =1 / (g dsN2 +g mN2 A ACF )

[0018] where g dsN2 is the output admittance of the N2 tube, g mN2 is the transconductance of N2 tube, and the gain of the adaptive control module is

[0019]

[0020] Good circuit matching can ensure g mN1 =g mN2 , g dsN1 =g dsN2 Under the premise of , substituting the above formula into the equivalent output impedance expression, we can get:

[0021]

[0022] That is, the equivalent output impedance of NMOS tube N2 is increased (1+g mN2 / g dsP1 ) times.

[0023] The adaptive control module includes an auxiliary operational amplifier A, an NMOS transistor N1 and an NMOS transistor N3;

[0024] The output end of the auxiliary operational amplifier A is connected to the gate of the NMOS transistor N3, the drain of the NMOS transistor N3 is connected to the drain of the PMOS transistor P1, the source of the NMOS transistor N3 is connected to the drain of the NMOS transistor N1, the gate of the NMOS transistor N1 is connected to the gate of the NMOS transistor N2, and together are connected to the drain of the PMOS transistor P1.

[0025] The source of the NMOS transistor N1 is grounded, the non-inverting input of the auxiliary operational amplifier A is connected to the drain of the PMOS transistor P3 , and the inverting input of the auxiliary operational amplifier A is connected to the drain of the NMOS transistor N1 .

[0026] In a preferred embodiment of the present invention, the operational amplifier A includes a current source IB3 and current sources IB4, IB5, and IB6, an NMOS transistor N5, and an NMOS transistor N6;

[0027] The input end of the current source IB3 is connected to the input end of the current source IB4, the output end of the current source IB3 is connected to the drain of the NMOS transistor N5, the source of the NMOS transistor N5 is connected to the input end of the current source IB5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6 and together connected to the drain of the NMOS transistor N6, the drain of the NMOS transistor N6 is connected to the output end of the current source IB4, the source of the NMOS transistor N6 is connected to the input end of the current source IB6, the output end of the current source IB5 and the output end of the current source IB6 are both grounded, and a voltage output end Vout is provided between the current source IB3 and the drain of the NMOS transistor N5.

[0028] In a preferred embodiment of the present invention, a resistor R1 and a capacitor C1 are further included, one end of the resistor R1 is connected to the gate of the NMOS transistor N4, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the drain of the NMOS transistor N4.

[0029] The above technical solution of the present invention has the following advantages over the prior art:

[0030] This application can obtain a DC gain of more than 70dB at a power supply voltage of 0.9V. The transconductance of the second-stage common-source amplifier is large, and deep Miller compensation is not required, which is conducive to reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific embodiments or the description of the prior art. Obviously, some of the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 is a main circuit diagram of an operational amplifier in an embodiment of the present invention;

[0033] Figure 2 is a circuit diagram of an operational amplifier A according to an embodiment of the present invention;

[0034] Figure 3 1 is the amplitude-frequency and phase-frequency response curve of the embodiment of the present invention; DETAILED DESCRIPTION

[0035] In order to more clearly understand the above-mentioned objects, features and advantages of the present invention, the present invention is further described in detail below in conjunction with specific embodiments. It should be noted that, in the absence of conflict, the embodiments of the present application and the features therein can be combined with each other.

[0036] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Therefore, the scope of protection of the present invention is not limited to the specific embodiments disclosed below.

[0037] Example 1

[0038] See also Figure 1-3 As shown, the present invention proposes a high-gain op amp circuit based on negative resistance technology, comprising: an adaptive control module, multiple P-type MOS transistors, multiple N-type MOS transistors, and current sources IB1 and IB2. Negative resistance has the opposite characteristics of normal resistance, with current decreasing as voltage increases. In analog integrated circuits, when the gate and drain of a MOS transistor are in phase opposition, its output impedance exhibits negative resistance. Ignoring the channel length modulation effect, its magnitude is -1 / gm. Negative resistance technology is commonly used in high-gain op amp designs.

[0039] The plurality of P-type MOS transistors are respectively recorded as PMOS transistor P1, PMOS transistor P2, and PMOS transistor P3; the plurality of N-type MOS transistors are respectively recorded as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, and NMOS transistor N4;

[0040] The input terminals of current source IB1 and current source IB2 are both connected to the power supply voltage. The source terminals of PMOS transistor P1 and PMOS transistor P2 are connected and connected to the output terminal of current source IB1. The drain terminal of PMOS transistor P1 is connected to the adaptive control module.

[0041] The drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N2, the source of the NMOS transistor N2 is connected to the source of the NMOS transistor N4, and the two are grounded together. The gate of the NMOS transistor N4 is connected to the drain of the NMOS transistor N2, and the drain of the NMOS transistor N4 is connected to the output end of the current source IB2.

[0042] The gate of the PMOS tube P1 is connected to the voltage input terminal V inn , the gate of PMOS tube P2 is connected to the voltage input terminal V inp , the gate of PMOS tube P3 is grounded;

[0043] The high-gain operational amplifier circuit further includes a resistor R1 and a capacitor C1. One end of the resistor R1 is connected to the gate of the NMOS transistor N4. The other end of the resistor R1 is connected to one end of the capacitor C1. The other end of the capacitor C1 is connected to the drain of the NMOS transistor N4.

[0044] Furthermore, the adaptive control module includes an auxiliary operational amplifier A, an NMOS transistor N1 and an NMOS transistor N3;

[0045] The output of the auxiliary operational amplifier A is connected to the gate of the NMOS tube N3, the drain of the NMOS tube N3 is connected to the drain of the PMOS tube P1, the source of the NMOS tube N3 is connected to the drain of the NMOS tube N1, the gate of the NMOS tube N1 is connected to the gate of the NMOS tube N2, and together connected to the drain of the PMOS tube P1.

[0046] The source of the NMOS tube N1 is grounded, the non-inverting input terminal of the auxiliary operational amplifier A is connected to the drain of the PMOS tube P3, and the inverting input terminal of the auxiliary operational amplifier A is connected to the drain of the NMOS tube N1.

[0047] Operational amplifier A includes current source IB3, current sources IB4, IB5, IB6, NMOS transistor N5, and NMOS transistor N6;

[0048] The input end of current source IB3 is connected to the input end of current source IB4, the output end of current source IB3 is connected to the drain of NMOS transistor N5, the source of NMOS transistor N5 is connected to the input end of current source IB5, the gate of NMOS transistor N5 is connected to the gate of NMOS transistor N6 and together connected to the drain of NMOS transistor N6, the drain of NMOS transistor N6 is connected to the output end of current source IB4, and the source of NMOS transistor N6 is connected to the input end of current source IB6.

[0049] Furthermore, the output end of the current source IB5 and the output end of the current source IB6 are both grounded, and a voltage output end Vout is provided between the current source IB3 and the drain of the NMOS transistor N5 .

[0050] Furthermore, in order to achieve high output impedance, the first stage of the operational amplifier of this invention adds an adaptive control module (ACF) based on the five-transistor OTA. The ACF module consists of a single-stage operational amplifier A, transistors N1 and N3, where the single-stage operational amplifier A adopts a common gate amplifier structure ( Figure 2 ), used to force the potentials of points X and Y to be equal.

[0051] Furthermore, an operational transconductance amplifier (OTA) is an amplifier that converts an input differential voltage into an output current. In CMOS technology, due to the limited output impedance, it is sometimes not specifically distinguished from other types and is collectively referred to as an "operational amplifier" or simply "op amp".

[0052] Assume the ACF module gain is A V , through small signal model analysis, the output impedance of the first stage of the op amp is

[0053] R out =1 / (g dsN2 +g mN2 A V )

[0054] where g dsN2 is the output admittance of the N2 tube, g mN2 is the transconductance of the N2 tube.

[0055] Designed to make A V →-g dsN2 / g mN2 , then the output impedance of the first stage of the op amp approaches ∞, thus achieving high gain. Of course, if A V Forward approximation to -r ds2 / g m2 , the output impedance is negative ∞, which means that negative feedback becomes positive feedback, resulting in instability. The characteristics of the present invention are:

[0056]

[0057] When a good match between N1 and N2 can be guaranteed, that is, in g mN1 =g mN2 , g dsN1 =g dsN2 Under the premise of being guaranteed, A V Just slightly smaller than -g in magnitude dsN2 / g mN2 , which can ensure that positive feedback is not triggered.V Substituting into the output impedance expression, we can get:

[0058]

[0059] It can be seen that the output impedance of the N2 tube is improved (1+g mN2 / g dsP1 ) times.

[0060] At the same time, what is seen from point Y upwards is a common source and common gate structure, which also has a considerable output impedance. Therefore, the output impedance of the first stage of the operational amplifier of the present invention is very high, ensuring the high gain of the operational amplifier. Figure 3 The solid line is the amplitude-frequency response curve, and the dotted line is the phase-frequency response curve ( Figure 3 ).

[0061] In addition, the gate-grounded P3 transistor is also helpful in ensuring that the drain voltages of the input pair of transistors are approximately equal, thereby reducing the non-ideal effects of the input differential pair.

[0062] The second stage of the operational amplifier of the present invention uses common source amplification, wherein the N4 tube uses a native-NMOS tube, which has a low threshold voltage characteristic, and the gate-source voltage can be controlled between 150-200mV. Resistor R1 and capacitor C1 form Miller compensation to ensure the stability of the operational amplifier. The present application can obtain a DC gain of more than 70dB at a power supply voltage of 0.9V ( Figure 3 ), the transconductance of the second-stage common-source amplifier is large, and deep Miller compensation is not required, which is beneficial to reducing power consumption.

[0063] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0064] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present invention. Various modifications to the above embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0065] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A high-gain operational amplifier circuit based on negative resistance technology, comprising: Auxiliary operational amplifier A, multiple P-type MOS transistors and multiple N-type MOS transistors, current source IB1 and current source IB2; characterized in that, The plurality of P-type MOS transistors are respectively recorded as PMOS transistor P1, PMOS transistor P2, and PMOS transistor P3; the plurality of N-type MOS transistors are respectively recorded as NMOS transistor N1, NMOS transistor N2, NMOS transistor N3, and NMOS transistor N4; The source end of the current source IB1 and the source end of the current source IB2 are both connected to the power supply voltage. The source of the PMOS transistor P1 and the source of the PMOS transistor P2 are connected and connected together to the output end of the current source IB1. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N3 and to the gates of the NMOS transistors N1 and N2. The drain of the PMOS transistor P2 is connected to the source of the PMOS transistor P3, the drain of the PMOS transistor P3 is connected to the drain of the NMOS transistor N2 and the non-inverting input terminal of the auxiliary operational amplifier A, the sources of the NMOS transistors N1 and N2 are connected to the source of the NMOS transistor N4 and are grounded together, the gate of the NMOS transistor N4 is connected to the drain of the NMOS transistor N2, and the drain of the NMOS transistor N4 is connected to the output terminal of the current source IB2; The gate of the NMOS transistor N3 is connected to the output terminal of the auxiliary operational amplifier A, and the source of the NMOS transistor N3 is connected to the drain of the NMOS transistor N1, and together connected to the inverting input terminal of the auxiliary operational amplifier A; The gate of the PMOS tube P1 is connected to the voltage input terminal V inn , the gate of PMOS tube P2 is connected to the voltage input terminal V inp , the gate of PMOS tube P3 is grounded.

2. The high-gain operational amplifier circuit based on negative resistance technology according to claim 1, characterized in that: NMOS tubes N1, N3 and auxiliary operational amplifier A form an adaptive control module, whose gain is set to A ACF ; Through small signal model analysis, the equivalent output impedance of the N2 tube in the first stage of the op amp is R out =1 / (g dsN2 +g mN2 A ACF ) where g dsN2 is the output admittance of the N2 tube, g mN2 is the transconductance of N2 tube, and the gain of the adaptive control module is Where V Z represents the small signal voltage at node Z, V X represents the small signal voltage at node X, g dsN1 represents the small signal output admittance of N1 tube, g dsP1 represents the small signal output admittance of P1 tube, g mN1 Represents the small signal transconductance of N1 tube; Good circuit matching can ensure g mN1 =g mN2 , g dsN1 =g dsN2 Under the premise of , substituting the above formula into the equivalent output impedance expression, we can get: That is, the equivalent output impedance of NMOS tube N2 is increased (1+g mN2 / g dsP1 ) times.

3. The high-gain operational amplifier circuit based on negative resistance technology according to claim 2, characterized in that: The auxiliary operational amplifier A includes current sources IB3, IB4, IB5, and IB6, and NMOS transistors N5 and NMOS transistors N6. The input end of the current source IB3 is connected to the input end of the current source IB4, the output end of the current source IB3 is connected to the drain of the NMOS transistor N5, the source of the NMOS transistor N5 is connected to the input end of the current source IB5, the gate of the NMOS transistor N5 is connected to the gate of the NMOS transistor N6 and connected together to the drain of the NMOS transistor N6, the drain of the NMOS transistor N6 is connected to the output end of the current source IB4, and the source of the NMOS transistor N6 is connected to the input end of the current source IB6; The output end of the current source IB5 and the output end of the current source IB6 are both grounded; A voltage output terminal V is provided between the current source IB3 and the drain of the NMOS tube N5. out .

4. The high-gain operational amplifier circuit based on negative resistance technology according to claim 1, characterized in that: It also includes a resistor R1 and a capacitor C1, one end of the resistor R1 is connected to the gate of the NMOS transistor N4, the other end of the resistor R1 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the drain of the NMOS transistor N4, serving as the output end of the operational amplifier circuit.

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