Method and device for generating decompression circuit

Abstract

A method and device for generating a decompression circuit relate to the field of IC chip testing. The method for generating the decompression circuit includes: determining the position coordinates of a driving XOR gate and the coupling relationship between the driving XOR gate and the input end of the scan chain according to the position coordinates of the input end of the scan chain (S601); determining the position coordinates of an intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate according to the position coordinates of the input end of the scan chain (S602); and determining the position coordinates of a CA register and the coupling relationship between the CA register and the intermediate XOR gate according to the position coordinates of the intermediate XOR gate (S603).

Description

Technical Field

[0001] The present application relates to the field of integrated circuit (IC) chip testing, and in particular to a method and device for generating a decompression circuit. Background Art

[0002] As IC chip technology advances, IC chips become larger and larger, and quality and stability requirements become increasingly stringent. Consequently, the number of test patterns is increasing. To save test time and costs, on-chip test pattern compression has become an indispensable technology.

[0003] When testing an IC chip, one method is to electrically connect the input and output pins of the IC chip to automatic test equipment (ATE). The ATE inputs test stimuli to the input pins of the IC chip, measures the test results output by the IC chip, and compares them with the expected test results to determine whether the IC chip has design defects.

[0004] The IC chip includes a decompression circuit, a circuit to be tested, and a compression circuit. The decompression circuit expands the test stimulus into a large number of scan chain test signals, which are input to the circuit to be tested on the IC chip. The circuit to be tested then inputs a large number of test results into the compression circuit, which compresses the test results and outputs them through a small number of output pins of the IC chip.

[0005] The decompression circuit can include multiple cellular automata (CA) circuits and phase shifters. The phase shifters include multiple XOR gates. The CA register inputs a test stimulus and outputs it to the XOR gates of the phase shifters. The XOR gates perform XOR operations and then fan out the scan chain. The layout of the XOR gates of the phase shifters affects the wiring complexity. Summary of the Invention

[0006] The embodiments of the present application provide a method and apparatus for generating a decompression circuit, which are used to optimize the layout of the decompression circuit and reduce the complexity of wiring.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a method for generating a decompression circuit is provided. The decompression circuit includes multiple cellular automaton (CA) registers and a phase shifter. The phase shifter includes an intermediate XOR gate and a driving XOR gate. One input of the intermediate XOR gate is coupled to the output of a CA register, the output of the intermediate XOR gate is coupled to an input of the driving XOR gate, and the output of the driving XOR gate is coupled to the input of a scan chain. The method includes: determining the position coordinates of the driving XOR gate and the coupling relationship between the driving XOR gate and the input of the scan chain based on the position coordinates of the input of the scan chain; determining the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate based on the position coordinates of the input of the scan chain; and determining the position coordinates of the CA register and the coupling relationship between the CA register and the intermediate XOR gate based on the position coordinates of the intermediate XOR gate.

[0009] The method for generating a decompression circuit provided in an embodiment of the present application optimizes the layout of the decompression circuit and reduces the complexity of wiring by hierarchically designing the position coordinates and mutual coupling relationships of the CA register, the driving XOR gate of the phase shifter, and the intermediate XOR gate in the decompression circuit.

[0010] In one possible implementation, the coordinates of the driven XOR gates are within a first range of the coordinates of the scan chain inputs; the output of each driven XOR gate is coupled to the input of a scan chain. This implementation describes how to determine the coordinates of the driven XOR gates and the coupling relationship between the driven XOR gates and the scan chain inputs.

[0011] In one possible implementation, the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate are determined based on the position coordinates of the scan chain inputs. This method includes fixing the position coordinates of a first charge and iteratively updating the position coordinates of a second charge to achieve electrostatic equilibrium, thereby determining the position coordinates of the intermediate XOR gate. The first charge corresponds to the scan chain input, and the second charge corresponds to the intermediate XOR gate. The first and second charges are of different types. The charge of the first charge is equal to the number of CA registers driven by each scan chain, and the charge of the second charge is equal to the number of scan chains driven by the intermediate XOR gate. The input of the driving XOR gate is coupled to the output of at least one of the nearest intermediate XOR gates. By refining the decompression circuit wiring problem into the layout of the intermediate XOR gates and CA registers, and treating the intermediate XOR gates and scan chain inputs as physical particles with different positive and negative charges, the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate are determined based on the principle that like charges repel and unlike charges attract. This minimizes the overall wiring and avoids congestion.

[0012] In one possible implementation, determining the position coordinates of the CA register and the coupling relationship between the CA register and the intermediate XOR gate based on the position coordinates of the intermediate XOR gate includes: fixing the position coordinates of a third charge, iteratively updating the position coordinates of a fourth charge, and achieving electrostatic equilibrium between the third and fourth charges to determine the position coordinates of the CA register. The third charge corresponds to the intermediate XOR gate, and the fourth charge corresponds to the CA register; the third and fourth charges are of different types; the charge magnitude of the third charge is equal to the number of scan chains driven by the intermediate XOR gate, and the charge magnitude of the fourth charge is equal to the number of scan chains driven by the CA register. The input of the intermediate XOR gate is coupled to the output of at least one of the nearest CA registers. By refining the decompression circuit's wiring problem as the layout of the intermediate XOR gate and the CA register, and equating the intermediate XOR gate and the CA register to physical particles with different positive and negative charges, and based on the principle that like charges repel and unlike charges attract, the position coordinates of the CA register and the coupling relationship between the CA register and the intermediate XOR gate are determined. This minimizes overall wiring and avoids congestion.

[0013] In the second aspect, a method for generating a decompression circuit is provided, comprising: obtaining the number of cellular automaton CA registers and the number of scan chains, executing the method for generating a decompression circuit as in the first aspect and any embodiment thereof, and generating a decompression circuit.

[0014] In a third aspect, a device for generating a decompression circuit is provided, comprising a processor and a memory, wherein: computer instructions are stored in the memory, and the processor executes the computer instructions to implement the method for generating a decompression circuit described in the first aspect and any embodiment thereof and the second aspect.

[0015] In a fourth aspect, a device for generating a decompression circuit is provided, comprising a processing module, the processing module being configured to implement the method for generating a decompression circuit according to the first aspect and any embodiment thereof and the second aspect.

[0016] In a fifth aspect, a computer-readable storage medium is provided. The computer-readable storage medium is non-volatile and stores computer-readable instructions. When the computer-readable instructions are executed on a computer, the computer executes the method of the first aspect and any of its embodiments.

[0017] In a sixth aspect, a computer program product is provided, which includes computer-readable instructions. When the computer-readable instructions are run on a computer, the computer executes the method of the first aspect and any of its embodiments.

[0018] The technical effects of the second to sixth aspects refer to the technical effects of the first aspect and any of its embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of an IC chip provided in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of the structure of an LFSR decompression circuit provided in an embodiment of the present application;

[0021] Figure 3 A schematic diagram of the structure of a decompression circuit provided in an embodiment of the present application;

[0022] Figure 4 A schematic structural diagram of a phase shifter in a decompression circuit provided in an embodiment of the present application;

[0023] Figure 5 A schematic diagram of the layout and wiring of a decompression circuit provided in an embodiment of the present application;

[0024] Figure 6 A schematic flow chart of a method for generating a decompression circuit provided in an embodiment of the present application;

[0025] Figure 7 A schematic diagram of the structure of a decompression circuit generation device provided in an embodiment of the present application;

[0026] Figure 8 A schematic structural diagram of another decompression circuit generation device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] During the electronic design automation (EDA) design process for IC chips, users input configurations into the EDA software, which then generates the logic circuits. The IC chip is then produced through plate making and tape-out. During IC chip testing, the IC chip is mounted on an ATE system, which then inputs test stimuli to the IC chip's input pins. The ATE then measures the IC chip's output and compares it with the expected test results to determine whether the IC chip has design flaws.

[0028] In order to reduce testing costs and improve testing efficiency, EDA software can be used to achieve deterministic automatic test pattern generation (ATPG). Figure 1As shown, when designing an IC chip, the EDA software not only generates a circuit to be tested 11 in the IC chip, but also generates a decompression circuit 12 and a compression circuit 13 in the IC chip. Furthermore, it can generate multiple sets of test vectors for testing, each set of test vectors including a test stimulus and an expected test result. Each set of test vectors can be used to detect some manufacturing defects within the IC chip. Determinism means that the inputs (test stimulus) and outputs (expected test results) of the circuit to be tested in the IC chip are certain, and these inputs and outputs are designed to target specific defects.

[0029] The ATE inputs test stimuli to the decompression circuit 12 of the IC chip through a small number of input pins of the IC chip. The decompression circuit 12 on the IC chip expands the test stimuli into a large number of scan chain test signals, which are input to the circuit to be tested 11 on the IC chip. The circuit to be tested 11 then inputs a large number of test results to the compression circuit 13. The compression circuit 13 compresses the test results and outputs them through a small number of output pins of the IC chip. By comparing the test results with the expected test results, it can be determined whether the design of the circuit to be tested 11 has defects.

[0030] Currently, the commonly used decompression circuit is a linear feedback shift register (LFSR) decompressor or a ring generator decompressor, for example, Figure 2 As shown, a linear feedback shift register (LFSR) decompression circuit includes a register R, an XOR gate (denoted by a plus sign in the figure), and a shift register 21. The input channel for the test stimulus and internal connection lines couple register R, the XOR gate, and the shift register 21, ultimately fanning out a scan chain 22 through the shift register 21. Shift register 21 is used to eliminate the structural dependencies of the pseudo-random test pattern generator driving the parallel scan chains. It typically consists of N three-input, one-output XOR gates. Its input comes from the sequential unit of the LFSR or ring generator, and its output is coupled to N scan chains.

[0031] An LFSR decompressor or ring generator decompressor contains multiple feedback and injection lines. To minimize the routing distance of these lines, the LFSR decompressor or ring generator decompressor must be located in a small, localized area. However, it also needs to drive a large number of scan chains through phase shifters. When driving tens of thousands of scan chains, a localized LFSR decompressor or ring generator decompressor can lead to routing congestion. Furthermore, the routing of the LFSR decompressor's internal connections is extremely congested. The primitive polynomial structure of the LFSR decompressor forces internal connections to span long distances, connecting distant registers. This long distance, combined with the congested routing, makes routing very complex and difficult.

[0032] The present application provides a decompression circuit, such as Figure 3 As shown, the decompression circuit includes multiple subcircuits 30, each of which includes multiple cellular automata (CA) circuits 301 and phase shifters 302. Optionally, subcircuit 30 also includes a second XOR circuit XOR2. The CA registers and phase shifters can be placed adjacent to each other, reducing the difficulty of layout and routing. Values ​​on different input channels can be injected into CA registers at different locations through XOR gates, ensuring encoding capabilities comparable to those of LFSR decompressors or Ring Generator decompressors.

[0033] Each sub-circuit 30 may be independent of each other. For example, the input terminal of any CA register in the first sub-circuit has no coupling relationship with the output terminal of any CA register in the second sub-circuit, and the output terminal of any CA register in the first sub-circuit has no coupling relationship with the input terminal of any CA register in the second sub-circuit. Figure 3 As shown, the sub-circuits 30 can be coupled to each other, for example, the output end of a CA register of the first sub-circuit is coupled to the input end of a CA register of the second sub-circuit, and the input end of a CA register of the first sub-circuit is coupled to the output end of a CA register of the second sub-circuit.

[0034] Figure 3 It can be called a one-dimensional decompression circuit, that is, the mutual coupling between each CA register is realized through a specific CA register; for example, the CA registers in a sub-circuit 30 are coupled in series, and the last CA register can be coupled with the first CA register in another sub-circuit 30. From another perspective, the CA registers 301 between different sub-circuits 30 are connected in series.

[0035] It should be noted that the left, right, up and down directions in the embodiment of the present application refer to the directions specified in the schematic diagram for the convenience of describing the coupling relationship. In the actual IC chip, due to reasons such as wiring layout, their positional relationship is not limited and is still based on the actual circuit coupling relationship.

[0036] In the same sub-circuit 30 , an output terminal of one CA register 301 is coupled to an input terminal of the phase shifter 302 and an input terminal of at least one other CA register 301 .

[0037] Optionally, the output end of one CA register 301 may also be coupled to an input end of another CA register 301 through a second XOR circuit XOR2.

[0038] Specifically, the second XOR circuit XOR2 includes an output end and two input ends, one input end of the second XOR circuit XOR2 is used to input a test stimulus through an input channel, the other input end of the second XOR circuit XOR2 is coupled to the output end of at least one other CA register 301, and the output end of the second XOR circuit XOR2 is coupled to an input end of the CA register 301.

[0039] The second XOR circuit XOR2 is configured to perform an XOR operation on the data input from the two input terminals and output the XOR result through the output terminal of the second XOR circuit XOR2. In other words, the second XOR circuit XOR2 introduces a test stimulus into the decompression circuit. By controlling the test stimulus, the output of CA register 301 and, in turn, the output of phase shifter 302 can be controlled. The test stimulus input to each sub-circuit 30 is independent and can be the same or different. Furthermore, the test stimulus can be input to any CA register 301.

[0040] In the same subcircuit 30, each CA register 301 can be coupled to the same clock signal source. Optionally, each CA register 301 can also be coupled to the same debug tool chain, such as a Joint Test Action Group (JTAG) chain or an Internet JTAG (IJTAG) chain. The debug tool chain is used to output control signals to each CA register to configure the CA register, which will be described in detail later.

[0041] It should be noted that although Figure 3 There are multiple output terminals of a CA register, but the signal sources are the same.

[0042] In the decompression circuit described above, the CA register and phase shifter within the same subcircuit can be placed adjacent to each other. Adjacent CA registers within the same subcircuit are coupled, eliminating long crossover wires and thus reducing layout and routing complexity. Furthermore, different test stimuli can be input into any CA register in different subcircuits via a second XOR gate, ensuring decompression encoding capabilities.

[0043] The phase shifter 302 is used to perform XOR calculation on the data input from the input end and output the test signal through multiple output ends. Figure 4 and Figure 5 As shown, the phase shifter includes multiple XOR gates, multiple input terminals, and multiple output terminals. Exemplarily, the XOR gate is a three-input XOR gate, each input terminal of the XOR gate is coupled to a CA register, and at least one of the CA registers coupled to any two XOR gates is different.

[0044] Phase shifter 302 may include an intermediate XOR gate and a driven XOR gate. One input of the intermediate XOR gate is coupled to the output of a CA register, and the output of the intermediate XOR gate is coupled to one input of the driven XOR gate. The output of the driven XOR gate is coupled to the input of the scan chain. For example, a three-input XOR gate may be decomposed into two stages of two-input XOR gates, with the first stage being the intermediate XOR gate and the second stage being the driven XOR gate.

[0045] To optimize the layout of the decompression circuit and reduce wiring complexity, this application decomposes the problem into the following questions:

[0046] 1. Determine the position coordinates of the driving XOR gate and the coupling relationship between the driving XOR gate and the input end of the scan chain.

[0047] 2. Determine the position coordinates of the middle XOR gate and the coupling relationship between the middle XOR gate and the driving XOR gate.

[0048] 3. Determine the location coordinates of the CA register and the coupling relationship between the CA register and the middle XOR gate.

[0049] like Figure 6 As shown, an embodiment of the present application provides a method for generating a decompression circuit, including:

[0050] S601 : Determine the position coordinates of a driving XOR gate and the coupling relationship between the driving XOR gate and the input end of the scan chain according to the position coordinates of the input end of the scan chain.

[0051] Since the input and output of the scan chain are fixed, and the driver XOR gate is placed as close to the scan chain input as possible, the position coordinates of the driver XOR gate can be within a first threshold of the position coordinates of the scan chain input. Furthermore, each driver XOR gate drives one scan chain, so the output of each driver XOR gate is coupled to the input of one scan chain.

[0052] S602 : Determine the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate according to the position coordinates of the input end of the scan chain.

[0053] The input end of the scan chain can be abstracted as a first charge (i.e., the first charge corresponds to the input end of the scan chain), and the intermediate XOR gate can be abstracted as a second charge (i.e., the second charge corresponds to the intermediate XOR gate). The first charge and the second charge are of different types, for example, one is positive and the other is negative. The position coordinates of the first charge are fixed, and the position coordinates of the second charge are iteratively updated to achieve electrostatic equilibrium between the first and second charges, thereby determining the position coordinates of the intermediate XOR gate (i.e., the second charge). The charge amount of the first charge is the number of CA registers driven by each scan chain, and the charge amount of the second charge is the number of scan chains driven by the intermediate XOR gate.

[0054] After determining the position coordinates of the intermediate XOR gates, the input of the driving XOR gate is coupled to the output of at least one of the nearest intermediate XOR gates. For example, if the driving XOR gate has two inputs, the two inputs of the driving XOR gate are coupled to the two nearest intermediate XOR gates, respectively.

[0055] Specifically, it is assumed that the decompression circuit includes M scan chains and N CA registers, each scan chain is driven by C CA registers, and C=3 as an example.

[0056] Then the minimum number of intermediate XOR gates is This is because each intermediate XOR gate is driven by two CA registers, and its output is only XORed with the remaining (N-(C-1)) CA registers. Each intermediate XOR gate will drive Scan chains.

[0057] Assume that each intermediate XOR gate can be represented as a physical particle with D positive charges, and the input end of each scan chain can be represented as a physical particle with C negative charges.

[0058] Since the scan chain layout is fixed, the repulsive forces between the inputs of each scan chain and the repulsive forces between the driven XOR gates can be ignored. Only the attractive forces between the scan chain inputs and the intermediate XOR gates are considered (to keep the intermediate XOR gates as close to the scan chain inputs as possible), as well as the repulsive forces between the intermediate XOR gates (to avoid wiring congestion). By continuously changing the position coordinates of the intermediate XOR gates (i.e., the second charge), the electrostatic equilibrium state of these positive and negative charges is achieved.

[0059] For example, electrostatic system modeling can be used to solve the position coordinates of the middle XOR gate (ie, positive charge) in an electrostatic equilibrium state.

[0060] Combine the position coordinates of the first charge (i.e., the input end of the scan chain) and the position coordinates of the second charge (i.e., the middle XOR gate) into a vector (x, y). The electric potential of each charge is ψ(x, y). In the vector (x, y), the position coordinates of the first charge (i.e., the input end of the scan chain) are fixed. Iteratively update the position coordinates of the second charge (i.e., the middle XOR gate), substitute them into the following Poisson equation and solve it. Select the Neumann boundary condition so that the integral of the electric potential ψ(x, y) over the layout area R is ∫∫ R When ψ(x,y) is less than the threshold or equal to zero, the vector (x,y) obtained by solution includes the position coordinates of the optimal second charge (i.e., the middle XOR gate):

[0061] ▽·▽ψ(x,y)=-ρ(x,y)

[0062]

[0063] ∫∫ R ψ(x,y)=0

[0064] where ^n is the exterior unit normal, It is the boundary of the second charge (ie, the middle XOR gate) layout region R. is a differential operator. ρ(x,y) is the charge density, which is the average charge on the vector (x,y). ∫∫ R ψ(x,y) is the integral of the potential ψ(x,y) over the layout region R, and ▽ψ(x,y) is the gradient of the potential ψ(x,y).

[0065] By specifying the wiring problem of the decompression circuit as the layout problem of the intermediate XOR gate and the CA register, and effectively treating the input ends of the intermediate XOR gate and the scan chain as physical particles with different positive and negative charges, and based on the principle that like charges repel each other and unlike charges attract, the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate are found, the overall wiring can be shortened and congestion can be avoided.

[0066] S603 : Determine the position coordinates of the CA register and the coupling relationship between the CA register and the intermediate XOR gate according to the position coordinates of the intermediate XOR gate.

[0067] The middle XOR gate can be abstracted as a third charge (i.e., the third charge corresponds to the middle XOR gate), and the CA register can be abstracted as a fourth charge (i.e., the fourth charge corresponds to the CA register). The third and fourth charges are of different types, for example, one is positive and the other is negative. The position coordinates of the third charge are fixed, and the position coordinates of the fourth charge are iteratively updated to achieve electrostatic equilibrium between the third and fourth charges, thereby determining the position coordinates of the CA register (i.e., the fourth charge). The charge of the third charge is equal to the number of scan chains driven by the middle XOR gate, and the charge of the fourth charge is equal to the number of scan chains driven by the CA register.

[0068] After determining the position coordinates of the CA register, the input of the intermediate XOR gate is coupled to the output of at least one of the closest CA registers. For example, assuming the intermediate XOR gate has two inputs, the two inputs of the intermediate XOR gate are coupled to the two closest CA registers, respectively.

[0069] Specifically, each CA register driver scan chains, then assuming that each CA register can be represented as a CA Each scan chain input can be represented as a physical particle with C positive charges. Each intermediate XOR gate drives scan chains, each intermediate XOR gate can be represented as A negatively charged physical particle.

[0070] Since the layout of the scan chain and the intermediate XOR gate is fixed, the repulsive force between the input ends of each scan chain, the repulsive force between the driven XOR gates, and the repulsive force of the intermediate XOR gates can all be ignored. Only the attractive force between the CA register and the input end of the scan chain (to make the CA register as close to the input end of the scan chain as possible), or the attractive force between the CA register and the intermediate XOR gate (to make the CA register as close to the intermediate XOR gate as possible), and the repulsive force between the CA registers (to avoid wiring congestion) are considered. By continuously changing the position coordinates of the CA register (that is, the fourth charge), the electrostatic equilibrium state of these positive and negative charges is reached.

[0071] The method for determining the position coordinates of the CA register (i.e., the fourth charge) can be referred to in step S602 for determining the position coordinates of the intermediate XOR gate (i.e., the second charge). The first charge is equivalent to the third charge, and the second charge is equivalent to the fourth charge. This will not be repeated here.

[0072] By specifying the wiring problem of the decompression circuit as the layout problem of the intermediate XOR gate and the CA register, and equating the intermediate XOR gate and the CA register to physical particles with different positive and negative charges, and based on the principle that like charges repel each other and unlike charges attract, the position coordinates of the CA register and the coupling relationship between the CA register and the intermediate XOR gate are found, the overall wiring can be shortened and congestion can be avoided.

[0073] The method for generating a decompression circuit provided in an embodiment of the present application optimizes the layout of the decompression circuit and reduces the complexity of wiring by hierarchically designing the position coordinates and mutual coupling relationships of the CA register, the driving XOR gate of the phase shifter, and the intermediate XOR gate in the decompression circuit.

[0074] The embodiment of the present application also provides a method for generating a decompression circuit, which can be executed by EDA software. The EDA software can obtain the number of CA registers and the number of scan chains, and execute Figure 6 The method for generating a decompression circuit generates the decompression circuit as described above. Optionally, it can also generate a circuit comprising an IC chip of the decompression circuit as described above.

[0075] like Figure 7 As shown, an embodiment of the present application also provides a device for generating a decompression circuit, the device 70 including a processor 702 and a memory 701, the processor 702 and the memory 701 are coupled via a bus 703, computer instructions are stored in the memory 701, and when the processor 702 executes the computer instructions in the memory 701, the above-mentioned method for generating a decompression circuit is executed.

[0076] like Figure 8 As shown, an embodiment of the present application further provides another device for generating a decompression circuit. The device 80 includes a processing module 801, and the processing module 801 is used to execute the above-mentioned method for generating a decompression circuit.

[0077] An embodiment of the present application also provides a computer-readable storage medium, which is non-volatile and stores computer-readable instructions. When the computer-readable instructions are executed on a computer or processor, the computer or processor executes the above-mentioned circuit generation method.

[0078] An embodiment of the present application further provides a computer program product comprising computer-readable instructions, which, when executed on a computer or a processor, causes the computer or processor to execute the above-mentioned circuit generation method.

[0079] The technical effects of the above-mentioned circuit generation method, computer-readable storage medium, and computer program product refer to the technical effects of the decompression circuit and IC chip mentioned above, and will not be repeated here.

[0080] The processor involved in the embodiments of the present application may be a chip. For example, it may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD), or other integrated chips.

[0081] The memory involved in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0082] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0083] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0084] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0086] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0087] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0088] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center by wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode to another website, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that contains one or more media that can be integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0089] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for generating a decompression circuit, characterized in that: The decompression circuit includes a plurality of cellular automaton (CA) registers and a phase shifter; the phase shifter includes an intermediate XOR gate and a driven XOR gate; an input of the intermediate XOR gate is coupled to an output of the CA register, an output of the intermediate XOR gate is coupled to an input of the driven XOR gate, and an output of the driven XOR gate is coupled to an input of a scan chain; the method includes: Determining the position coordinates of the driven XOR gate and the coupling relationship between the driven XOR gate and the input end of the scan chain according to the position coordinates of the input end of the scan chain; Determining the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate according to the position coordinates of the input end of the scan chain; Determining the position coordinates of the CA register and the coupling relationship between the CA register and the intermediate XOR gate according to the position coordinates of the intermediate XOR gate; The determining of the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate according to the position coordinates of the input end of the scan chain includes: The position coordinates of the first charge are fixed, and the position coordinates of the second charge are iteratively updated so that the first charge and the second charge reach electrostatic equilibrium, thereby determining the position coordinates of the intermediate XOR gate; wherein the first charge corresponds to the input end of the scan chain, and the second charge corresponds to the intermediate XOR gate; the first charge and the second charge are of different types; the charge amount of the first charge is the number of CA registers driven by each scan chain, and the charge amount of the second charge is the number of scan chains driven by the intermediate XOR gate.

2. The method according to claim 1, characterized in that The position coordinates of the driven XOR gates are located within a first range of the position coordinates of the input ends of the scan chains; the output end of each driven XOR gate is coupled to the input end of a scan chain.

3. The method according to any one of claims 1-2, characterized in that Determining the position coordinates of the intermediate XOR gate and the coupling relationship between the intermediate XOR gate and the driving XOR gate according to the position coordinates of the input end of the scan chain, further comprising: The input terminal of the driving XOR gate is coupled to the output terminal of at least one nearest intermediate XOR gate.

4. The method according to claim 3, characterized in that The determining the position coordinates of the CA register according to the position coordinates of the intermediate XOR gate, and the coupling relationship between the CA register and the intermediate XOR gate, includes: The position coordinates of the third charge are fixed, and the position coordinates of the fourth charge are iteratively updated so that the third charge and the fourth charge reach electrostatic equilibrium, thereby determining the position coordinates of the CA register; wherein the third charge corresponds to the intermediate XOR gate, and the fourth charge corresponds to the CA register; the third charge and the fourth charge are of different types; the charge amount of the third charge is the number of scan chains driven by the intermediate XOR gate, and the charge amount of the fourth charge is the number of scan chains driven by the CA register; An input terminal of the intermediate XOR gate is coupled to an output terminal of the at least one CA register closest thereto.

5. A method for generating a decompression circuit, characterized in that: include: Obtain the number of CA registers and the number of scan chains of the cellular automaton, execute the method for generating a decompression circuit according to any one of claims 1 to 4, and generate a decompression circuit.

6. A device for generating a decompression circuit, characterized in that: include: A processor and a memory, wherein: the memory stores computer instructions, and the processor executes the computer instructions to implement the method for generating a decompression circuit according to any one of claims 1 to 5.

7. A computer-readable storage medium, characterized in that The computer-readable storage medium is non-volatile and stores computer-readable instructions. When the computer-readable instructions are executed on a computer, the computer is enabled to execute the method according to any one of claims 1 to 5.

8. A computer program product, characterized in that The computer program product includes computer-readable instructions, and when the computer-readable instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 5.

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