An adaptive dual-threshold generator based on nonlinear energy operator for action potential detection

Abstract

An adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection, wherein a NEO circuit generates suitable positive and negative thresholds by processing a signal to be detected. The positive and negative thresholds are transmitted to a peak voltage comparator and a valley voltage comparator via a peak hold circuit and a valley hold circuit. The signal to be detected is compared with the positive and negative thresholds by the peak voltage comparator and the negative voltage comparator, respectively. After the negative threshold is detected, a window delay circuit is used. Only when a positive peak is captured within a window period and exceeds the positive threshold, authentication detection of the action point is achieved. An adder is then used to superimpose the positive and negative peaks, and a synthesized detection result is output. Finally, a counter is used to count the number of action potentials contained in the signal to be detected, thereby achieving action potential detection based on an adaptive dual-threshold generator of a nonlinear energy operator.

Description

Technical Field

[0001] The present invention relates to medical signal detection electronic integrated circuit technology, and in particular to a dual-threshold generator based on a nonlinear energy operator for action potential detection. Background Art

[0002] Single-threshold detection and the non-linear energy operator (NEO) method are currently the most widely used methods for action potential detection. Both methods have the following drawbacks: The single-threshold method is difficult to estimate the threshold; setting it too low can misinterpret noise as an action potential, while setting it too high can miss true action potentials. Furthermore, false detections are prone to occur when only one threshold is used. The non-linear energy operator-based detection method has a drawback in that it has difficulty detecting small-amplitude signals, which can lead to missed detection of relatively low-amplitude action potentials.

[0003] In addition, both of the above methods cannot detect the period of action potential. Summary of the Invention

[0004] The object of the present invention is to provide a method for detecting an action potential signal with a relatively low amplitude, so as to reduce the false detection rate and missed detection rate of the action potential and detect the period of the action potential.

[0005] An adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection includes a NEO circuit, a peak hold circuit, a valley hold circuit, a valley voltage comparator, a peak voltage comparator, a delay window circuit, an adder, and a counter;

[0006] The NEO circuit has an input connected to the signal input, and an output that outputs positive and negative threshold values. The valley hold circuit has an input connected to the output of the NEO circuit, and the output maintains a valley output. The peak hold circuit has an input connected to the output of the NEO circuit, and the output maintains a peak output. The valley detector has an input connected to the signal input, and the output outputs a valley value detected in the input signal. The peak detector has an input connected to the signal input, and the output outputs a peak value detected in the input signal. The valley voltage comparator has an input connected to the output of the valley hold circuit and the output of the valley detector, respectively, and the output outputs a detection result of an action potential signal. The peak voltage comparator has an input connected to the output of the peak hold circuit and the output of the peak detector, respectively, and the output outputs a detection result of an action potential signal. The delay window circuit has an input connected to the output of the valley voltage comparator, and the output outputs a delayed signal. The adder has an input connected to the output of the delay window circuit and the output of the peak voltage comparator, respectively, and the output outputs a synthesized new signal. The counter has an input connected to the output of the adder, and the output outputs the number of action potentials detected.

[0007] In the above technical solution, the NEO circuit can generate appropriate positive and negative thresholds by processing the signal to be detected. The positive and negative thresholds are then transmitted to the peak voltage comparator and valley voltage comparator via the peak hold circuit and valley hold circuit. The signal to be detected is compared with the positive and negative thresholds by the peak voltage comparator and the negative voltage comparator, respectively. After the negative threshold is detected, the window delay circuit is used to detect the action point only when the positive peak is captured within the window period and exceeds the positive threshold. The positive and negative peaks are then superimposed by an adder, and the combined detection result is output. The time difference between the positive and negative peaks can be seen from the detection result, and the action potential period is calculated. Finally, a counter is used to count the number of action potentials contained in the signal to be detected. Ultimately, adaptive dual-threshold action potential detection based on a nonlinear energy operator is achieved.

[0008] Compared with the prior art, the dual-threshold generator based on a nonlinear energy operator for action potential detection of the present invention has the following beneficial effects:

[0009] 1) It can generate positive and negative thresholds to accurately detect action potentials, reducing the probability of false detection and missed detection;

[0010] 2) Ability to detect action potential signals with smaller amplitudes;

[0011] 3) It can detect the duration of the peak potential and afterpotential of the action potential, thereby determining the period of the action potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 14 is a structural block diagram of the present invention in an embodiment of the present invention.

[0013] Figure 2 4 is a circuit diagram of a valley detector in an embodiment of the present invention.

[0014] Figure 3 4 is a circuit diagram of a valley comparator in an embodiment of the present invention.

[0015] Figure 4 4 is a circuit diagram of the delay window in an embodiment of the present invention.

[0016] Figure 5 4 is a circuit diagram of a peak hold circuit in an embodiment of the present invention.

[0017] Figure 6 This is a circuit simulation diagram after valley value detection in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The technical solution of the present invention is further described in detail below with reference to the accompanying drawings.

[0019] The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection includes a NEO circuit 10, a dual-threshold detection circuit 20, and a counter 30. The action potential preprocessing circuit 10 includes an input terminal and an output terminal. The input terminal is connected to the action potential signal to be detected, and processes the received signal to generate appropriate positive and negative thresholds.

[0020] like Figure 1 As shown, the dual-threshold detection circuit 20 includes a peak detector 201, a peak hold circuit 202, a valley hold circuit 203, a valley detector 204, a peak voltage comparator 205, a valley voltage comparator 206, a delay window 207, and an adder 208. The peak detector 201 and the valley detector 204 have the same structure, and the peak hold circuit 202 and the valley hold circuit 203 have the same structure. The peak hold circuit 202, the valley hold circuit 203, the peak voltage comparator 205, the valley voltage comparator 206, and the delay window 207 are all circuit modules with single-ended input and single-ended output. The peak detector 201, the valley detector 204, and the adder 208 have two input terminals and one output terminal.

[0021] like Figure 2As shown, valley detector 204 includes resistor R20401, resistor R20402, resistor R20403, capacitor C20404, diode D20405, diode D20406, NMOS transistor M20407, and a dual-input, single-output operational amplifier gm1. Resistor R20401 has a resistance of 100 kΩ, resistor R20402 has a resistance of 100 MΩ, resistor R20403 has a resistance of 1Ω, capacitor C20404 has a capacitance of 1 μF, diodes D20405 and D20406 have a W / L ratio of 10 μm / 10 μm, and M20407 has a W / L ratio of 2 μm / 350 nm. One end of R20401 is connected to the input signal (Vin204), and the other end is connected to the non-inverting input of op amp gm1. The detection process of this circuit is as follows: Vin204 begins to decrease, op amp gm1 outputs a negative voltage, diode D20405 turns on, diode D20406 turns off, and capacitor C20404 begins to charge. Because the capacitor charging voltage is equal to Vout204, when the charging voltage is less than Vin204, op amp gm1 outputs a positive supply voltage, diode D20405 turns off, diode D20406 turns on, and capacitor C20404 begins to discharge. When the capacitor discharges to a value greater than Vin204, diode D20405 turns on, and diode D20406 turns off. This process repeats until the capacitor reaches a valley value. The inverting input terminal of the operational amplifier gm1 is connected to the resistor R20402 and the diode D20405. The output terminal of the operational amplifier gm1 is fed back to the inverting input terminal of the operational amplifier gm1 through the diode D20406. The output terminal (Vout204) of the valley detector 204 is the positive input signal terminal (Vin206+) of the valley voltage comparator 206.

[0022] The peak detector and the valley detector have the same structure, similar detection process and form, and the same principle.

[0023] like Figure 3As shown, the valley voltage comparator 206 (the peak voltage comparator adopts a similar structure) includes NMOS transistors M20601, M20602, M20603, M20604, M20605, M20606, M20607, M20608, and M20609, PMOS transistors M20610, M20611, M20612, M20613, M20614, M20615, M20616, and M20617, a Schmitt trigger S20618, inverters F20619 and F20620, and a resistor R20621. Among them, the W / L of NMOS tube M20601 is 5μm / 5μm, the W / L of NMOS tube M20602 is 40μm / 5μm, the W / L of NMOS tube M20603 and M20608 is 10μm / 5μm, the W / L of NMOS tube M20604 and M20607 is 8μm / 3μm, the W / L of NMOS tube M20605 and M20606 is 4μm / 3μm, the W / L of NMOS tube M20609 is 8μm / 180nm, and the PMOS tube The W / L ratios of M20610 and M20311 are 5μm / 5μm, the W / L ratio of PMOS transistor M20612 is 10μm / 5μm, the W / L ratio of PMOS transistor M20613 is 8μm / 180nm, the W / L ratio of PMOS transistor M20614 is 40μm / 5μm, the W / L ratio of PMOS transistor M20615 is 1μm / 5μm, and the W / L ratios of PMOS transistors M20616 and M20617 are 10μm / 1.5μm. The resistance of resistor R20621 is 292Ω. Voltage Vin206 is connected to the gate of PMOS transistor M20616. Voltage Vin206 is Vout204. Vin206 is connected to the gate of PMOS transistor M20617.The gate and drain of NMOS tube M20601 and the drain of PMOS tube M20610 are connected. The gate of NMOS tube M20601 is connected to the gate of M20602. The source of NMOS tube M20601 is connected to resistor R20621. The source of NMOS tube M20603, the gate and drain of M20604, the drain of M20605, the gate of M20606, and the drain of PMOS tube M20616 are connected. The gate of NMOS tube M20605, the drain of M20606, and the drain of M20607 are connected. , the gate and drain of M20606, the gate of M20608, and the drain of PMOS tube M20617 are connected, the drain of NMOS tube M20608, the drain of M20609, the drain of PMOS tube M20615, and the input end of Schmitt trigger S20618 are connected, the gate of NMOS tube M20609, the gate of PMOS tube M20617, and the enable end EN206 are connected, the gate of PMOS tube M20610, the gate and drain of M20611, the drain of M20613, and M20614 are connected. The drain of the NMOS tube M20602 is connected, the gate of the PMOS tube M20612 is connected, the gate of M20615 is connected, the drain of the PMOS tube M20612 is connected, the drain of the NMOS tube M20603 is connected, the drain of the PMOS tube M20614, the source of M20616, and the source of M20617 are connected, the source of the NMOS tube M20601, the source of M20603, the source of M20604, the source of M20605, the source of M20606, the source of M20607, and the source of M20618 are connected. The sources of M20608 and M20609 are grounded. The sources of PMOS transistors M20610, M20611, M20612, M20613, M20614, and M20615 are connected to the power supply. The output of Schmitt trigger S20618 is connected to the input of inverter F20619, which is connected to the input of inverter F20620. The output of inverter F20620 is the valley voltage, the output of voltage comparator 206. The output of valley voltage comparator 206 (Vout206) is the input of delay window circuit 207.

[0024] like Figure 4As shown, the delay window circuit 207 includes PMOS transistors M20701, M20702, and M20703, NMOS transistors M20704 and M20705, a Schmitt trigger S20706, and inverters F20707 and F20708. The W / L ratio of the PMOS transistors M20701, M20702, and M20703 is 500 nm / 10 μm, the W / L ratio of the NMOS transistor M20704 is 10 μm / 500 nm, and the W / L ratio of the NMOS transistor M20705 is 30 μm / 20 μm. The drain of the PMOS tube M20701 and the source of M20702 are connected, the drain of the PMOS tube M20702 and the source of M20703 are connected, the drain of the PMOS tube M20703, the drain of the NMOS tube M20704, the gate of the NMOS tube M20705, and the input end of the Schmitt trigger S20706 are connected, the source of the NMOS tube M20704, and the source and drain of the NMOS tube M20705 are connected to ground, and the PMOS tube M20703 is connected to the drain of the NMOS tube M20704 and the source and drain of the NMOS tube M20705 are connected to ground. The gates of OS transistor M20701, M20702, M20703, and NMOS transistor M20704 are connected to the input terminal Vin207 of delay window circuit 207. The output terminal of Schmitt trigger S20706 is connected to the input terminal of inverter F20707. The output terminal of inverter F20707 is connected to the input terminal of inverter F20708. The output terminal of inverter F20708 outputs the delayed result. The output terminal (Vout207) of delay window circuit 207 is the input terminal of adder 208.

[0025] like Figure 5As shown, peak hold circuit 202 includes a dual-input, single-ended-output operational amplifier gm2, resistor R20201, diode D20202, capacitor C20203, and voltage buffer B20404. Resistor R20201 has a resistance of 100 kΩ, capacitor C20203 has a capacitance of 1 μF, and diode D20202 has a W / L ratio of 10 μm / 10 μm. One end of R20201 is connected to the input signal (Vout10), and the other end is connected to the non-inverting input of operational amplifier gm2. The output of operational amplifier gm2 is connected to one end of diode D20202, and the inverting input of operational amplifier gm2 is connected to one end of voltage buffer B20404. The other end of diode D20202 is connected to one end of voltage buffer B20404 and one end of capacitor C20203. The other end of capacitor C20203 is connected to ground. The detection process of this circuit is as follows: a voltage pulse signal is applied to input terminal Vin202. When the voltage of the signal increases, the voltage at the non-inverting pin of operational amplifier gm2 is greater than the voltage at its inverting pin. Based on the transfer characteristics of operational amplifier gm2, the voltage output by operational amplifier gm2 exceeds the conduction voltage of diode D20202, causing diode D20202 to conduct, and the output voltage charges capacitor C20203. The voltage on capacitor C20203 is fed back to the inverting input of operational amplifier gm2 via the output of voltage buffer B20404. When the voltage of the input signal decreases, the voltage at the non-inverting pin of operational amplifier gm2 is less than the voltage at its inverting pin, causing the voltage at the output pin of operational amplifier gm2 to fall below zero. At this point, diode D20202 is cut off, and capacitor C20203 is no longer charged, leaving the charge stored on it essentially unchanged.

[0026] In the above scheme, the NEO circuit 10 can generate positive and negative thresholds by processing the signal to be detected. The peak hold circuit 201 and the valley hold circuit 203 transmit the positive and negative thresholds to the peak voltage comparator 205 and the valley voltage comparator 206. The peak voltage comparator 205 and the valley voltage comparator 206 compare the signal to be detected with the positive and negative thresholds, respectively. Then, when the positive peak value is captured within the window period and exceeds the positive threshold value through the window delay circuit 207, the action point is authenticated and detected. The adder 208 superimposes the positive and negative peaks and outputs a combined detection result. The counter 30 outputs the detection result and the number of action potentials.

[0027] Figure 6In the simulation, 1 is the processed signal. At v1, a falling edge is observed. 2 is the valley detector detecting the signal starting to fall, which is then compared with the comparator and reversed. 3 is the comparator outputting a high level, and 4 is the output of the comparator after being delayed by the delay circuit. At v2, a rising edge is observed. 2 is the peak detector detecting the signal starting to rise, which is then compared with the comparator. 3 is the comparator outputting a low level, and 4 is the output of the comparator after being delayed by the delay circuit.

[0028] The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiment. Any equivalent modifications or changes made by ordinary technicians in this field based on the contents disclosed in the present invention should be included in the protection scope recorded in the claims.

Claims

1. An adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection, characterized by: It includes a NEO circuit, a peak detector, a peak hold circuit, a valley hold circuit, a valley detector, a peak voltage comparator, a valley voltage comparator, a delay window circuit, an adder and a counter; The input signal to be detected is processed by the NEO circuit to generate appropriate positive and negative thresholds, and the positive and negative thresholds are passed to the peak voltage comparator and the valley voltage comparator through the peak hold circuit and the valley hold circuit. The signal to be detected passes through the peak detector and the valley detector respectively, and then is compared with the positive and negative thresholds by the peak voltage comparator and the valley voltage comparator. When the negative threshold is detected, it passes through the window delay circuit. Only when the positive peak is captured within the window period and exceeds the positive threshold, it is regarded as an action potential, thereby realizing the authentication detection of the action potential. Then, the positive and negative peaks are superimposed together by the adder, and then the synthesized detection result is output. The time difference between the positive and negative peaks can be seen from the detection result, and the action potential period is calculated. Finally, the number of action potentials contained in the signal to be detected is counted by the counter, realizing the adaptive dual-threshold action potential detection based on the nonlinear energy operator.

2. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 1, characterized in that: The input terminal of the NEO circuit is connected to the signal input terminal, and the output terminal outputs positive threshold and negative threshold; The input end of the valley hold circuit is connected to the output end of the NEO circuit, and the output end maintains the valley output; the input end of the peak hold circuit is connected to the output end of the NEO circuit, and the output end maintains the peak output; the input end of the valley detector is connected to the signal input end, and the output end outputs the detected valley value of the input signal; The peak detector input terminal is connected to the signal input terminal, and the output terminal outputs the peak value of the input signal detected; The input end of the valley voltage comparator is connected to the output end of the valley hold circuit and the output end of the valley detector respectively, and the output end outputs the detection result of the action potential signal; the input end of the peak voltage comparator is connected to the output end of the peak hold circuit and the output end of the peak detector respectively, and the output end outputs the detection result of the action potential signal; the input end of the delay window circuit is connected to the output end of the valley voltage comparator, and the output end outputs the delayed signal; the input end of the adder is connected to the output end of the delay window circuit and the output end of the peak voltage comparator respectively, and the output end outputs a synthesized new signal; the input end of the counter is connected to the output end of the adder, and the output end outputs the number of detected action potentials.

3. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 1, characterized in that: The peak hold circuit, the valley hold circuit, the peak voltage comparator, the valley voltage comparator and the delay window all have single-ended input and single-ended output, and the peak detector, the valley detector and the adder have two input terminals and one output terminal.

4. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 1, characterized in that: The peak detector and the valley detector have the same structure, and the peak hold circuit and the valley hold circuit have the same structure.

5. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 4, characterized in that: The valley detector includes resistor R20401, resistor R20402, resistor R20403, capacitor C20404, diode D20405, diode D20406, NMOS transistor M20407, and a dual-input, single-ended-output operational amplifier gm1. Resistor R20401 has a resistance of 100 kΩ, resistor R20402 has a resistance of 100 MΩ, resistor R20403 has a resistance of 1Ω, capacitor C20404 has a capacitance of 1 μF, diodes D20405 and D20406 have a W / L ratio of 10 μm / 10 μm, and M20407 has a W / L ratio of 2 μm / 350 nm.

6. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 5, characterized in that: In the valley detector, one end of R20401 is connected to the input signal Vin204, and the other end is connected to the non-inverting input of the operational amplifier gm1. During the detection process, Vin204 decreases, the operational amplifier gm1 outputs a negative voltage, the diode D20405 is turned on, the diode D20406 is turned off, and the capacitor C20404 starts to charge; when the capacitor charging voltage is less than Vin204, the operational amplifier gm1 outputs a positive power supply voltage, the diode D20405 is turned off, the diode D20406 is turned on, and the capacitor C 20404 starts to discharge; the capacitor discharges to a value greater than Vin204, then diode D20405 turns on and diode D20406 turns off, and this process is repeated until the capacitor is charged to a valley value. The inverting input terminal of the operational amplifier gm1 is connected to the resistor R20402 and the diode D20405, and the output terminal of the operational amplifier gm1 is fed back to the inverting input terminal of the operational amplifier gm1 through the diode D20406. The output terminal of the valley detector 204 is the positive input signal terminal of the valley voltage comparator 206.

7. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 1, characterized in that: The valley voltage comparator includes NMOS tubes M20601, M20602, M20603, M20604, M20605, M20606, M20607, M20608, M20609, and PMOS tubes M20610, M20611, M20612, M20613, M20614, M20615, M20616, M 20617, Schmitt trigger S20618, inverters F20619, F20620 and resistor R20621; among them, the W / L of NMOS transistor M20601 is 5μm / 5μm, the W / L of NMOS transistor M20602 is 40μm / 5μm, the W / L of NMOS transistors M20603 and M20608 is 10μm / 5μm, the W / L of NMOS transistors M20604 and M20607 is 8μm / 3μm, the W / L of NMOS transistors M20605 and M20606 is 4μm / 3μm, the W / L of NMOS transistor M20609 is 8μm / 180nm, the W / L of PMOS transistors M20610 and M20611 is 5μm / 5μm, and the W / L of PMOS transistor M20612 is 10 μm / 5μm, the W / L of the PMOS tube M20613 is 8μm / 180nm, the W / L of the PMOS tube M20614 is 40μm / 5μm, the W / L of the PMOS tube M20615 is 1μm / 5μm, the W / L of the PMOS tubes M20616 and M20617 is 10μm / 1.5μm, and the resistance of the resistor R20621 is 292Ω.

8. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 7, characterized in that: In the valley voltage comparator, the input voltage Vin206 is connected to the gate of the PMOS tube M20616. The voltage Vin206 is Vout204. Vin206 is connected to the gate of the PMOS tube M20617. The gate and drain of the NMOS tube M20601 and the drain of the PMOS tube M20610 are connected. The gate of the NMOS tube M20601 is connected to the gate of M20602. The source of the NMOS tube M20601 is connected to the resistor R20621. The source of the NMOS tube M20603, the gate and drain of M20604, the drain of M20605, the gate of M20606, The drain of the PMOS tube M20616 is connected, the gate of the NMOS tube M20605, the drain of M20606, the drain of M20607, the gate and drain of M20606, the gate of M20608, and the drain of the PMOS tube M20617 are connected, the drain of the NMOS tube M20608, the drain of M20609, the drain of the PMOS tube M20615, and the input end of the Schmitt trigger S20618 are connected, the gate of the NMOS tube M20609, the gate of the PMOS tube M20617, and the enable end EN206 are connected, and the gate of the PMOS tube M20610, M206 11 The gate is connected to the drain, the drain of M20613, the drain of M20614, and the drain of NMOS tube M20602. The gate of PMOS tube M20612 and the gate of M20615 are connected. The drain of PMOS tube M20612 and the drain of NMOS tube M20603 are connected. The drain of PMOS tube M20614, the source of M20616, and the source of M20617 are connected. The source of NMOS tube M20601, the source of M20603, the source of M20604, the source of M20605, the source of M20606, the source of M20607, and the source of M20608 are connected. The source of 608 and the source of M20609 are grounded, the source of the PMOS tube M20610, the source of M20611, the source of M20612, the source of M20613, the source of M20614, and the source of M20615 are connected to the power supply, the output end of the Schmitt trigger S20618 is connected to the input end of the inverter F20619, the output end of the inverter F20619 is connected to the input end of the inverter F20620, and the output end of the inverter F20620 is the output end of the valley voltage comparator. The output end Vout206 of the valley voltage comparator is the input end of the delay window circuit.

9. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 1, characterized in that: The delay window circuit includes PMOS transistors M20701, M20702, and M20703, NMOS transistors M20704 and M20705, a Schmitt trigger S20706, and inverters F20707 and F20708. Among them, the W / L of the PMOS transistors M20701, M20702, and M20703 is 500nm / 10μm, the W / L of the NMOS transistor M20704 is 10μm / 500nm, and the W / L of the NMOS transistor M20705 is 30μm / 20μm.

10. The adaptive dual-threshold generator based on a nonlinear energy operator for action potential detection according to claim 9, characterized in that: In the delay window circuit, the drain of the PMOS tube M20701 and the source of M20702 are connected, the drain of the PMOS tube M20702 and the source of M20703 are connected, the drain of the PMOS tube M20703, the drain of the NMOS tube M20704, the gate of the NMOS tube M20705, and the input end of the Schmitt trigger S20706 are connected, the source of the NMOS tube M20704, the source and drain of the NMOS tube M20705 are connected to ground, and the PMOS tube M20701 The gate of M20702, the gate of M20703, the gate of NMOS tube M20704, and the input terminal Vin207 of the delay window circuit are connected. The output terminal of Schmitt trigger S20706 is connected to the input terminal of inverter F20707, and the output terminal of inverter F20707 is connected to the input terminal of inverter F20708. The output terminal of inverter F20708 outputs the delayed result. The output terminal Vout207 of the delay window circuit is the input terminal of the adder.

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