Storage unit, storage array and storage array preparation method

Abstract

The present disclosure relates to a memory cell, a memory array and a method for preparing the memory array. The memory cell includes: a first vertical transistor, including a first gate, a first vertical channel, and a first source region and a first drain region located at both ends of the first vertical channel, and the first drain region includes a charge storage structure; a second vertical transistor, including a second gate, a second vertical channel, and a second source region and a second drain region located at both ends of the second vertical channel, and the second gate is electrically connected to the charge storage structure, wherein the second vertical transistor and the first vertical transistor are not only staggered in the first direction, but also staggered in the second direction, and the first direction intersects the second direction. The present disclosure improves the arrangement density of the memory cell and improves the performance of the semiconductor device with a 2T0C structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a memory cell, a memory array, and a method for manufacturing the memory array. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor device commonly used in electronic devices such as computers. It consists of multiple storage cells, multiple word lines and multiple bit lines electrically connected to the multiple storage cells, and each storage cell usually includes a switch element and a storage element electrically connected to the switch element. The word line voltage on the word line can control the opening and closing of the switch element, so that the data information stored in the storage element can be read through the bit line, or the data information can be written into the storage element.

[0003] Storage elements mostly use capacitors, but because capacitors occupy a large area, one transistor and one capacitor (i.e., 1T1C) are difficult to meet the needs of semiconductor structures such as DRAM to increase storage density. The storage unit of the 2T0C (i.e., two transistors without capacitors) structure occupies a small area and can adapt to the requirements of the continuous miniaturization of semiconductor structures such as DRAM and the continuous increase in storage density, so as to become the current mainstream storage unit structure. In the current 2T0C structure, each of the storage units needs to be connected to two bit lines (a read bit line and a write bit line) and two word lines (a write word line and a read word line), thereby increasing the size of semiconductor structures such as DRAM, and causing the read and write operations of the storage unit to be more complicated. The setting will also cause problems such as voltage drop in the word line (e.g., the read word line), which seriously affects the performance of the semiconductor structure.

[0004] Therefore, how to improve the performance of a semiconductor structure having a 2T0C structure and increase the storage density of the semiconductor structure is a technical problem that needs to be solved urgently. Summary of the invention

[0005] Some embodiments of the present disclosure provide a memory cell, a memory array, and a method for manufacturing the memory array, which are used to improve the performance of a semiconductor device having a 2T0C structure and to increase the storage density of the semiconductor structure.

[0006] According to some embodiments, the present disclosure provides a storage unit, comprising:

[0007] A first vertical transistor, comprising a first gate, a first vertical channel, and a first source region and a first drain region located at two ends of the first vertical channel, wherein the first drain region comprises a charge storage structure;

[0008] The second vertical transistor includes a second gate, a second vertical channel, and a second source region and a second drain region located at both ends of the second vertical channel, wherein the second gate is electrically connected to the charge storage structure, wherein the second vertical transistor and the first vertical transistor are staggered not only in the first direction but also in the second direction, and the first direction intersects with the second direction.

[0009] In some embodiments, the first source region is located above the first drain region, and the second source region is located above the second drain region;

[0010] The first source region is located above the second source region, and the first drain region is located above the second drain region.

[0011] In some embodiments, the first drain region is located above the first source region, and the second drain region is located above the second source region;

[0012] The second drain region is located above the first drain region, and the second source region is located above the first source region.

[0013] In some embodiments, the first direction is parallel to an extension direction of the first vertical channel, the second vertical channel also extends along the first direction, and the second direction is parallel to an extension direction of the charge storage structure;

[0014] The first gate is located at one side of the first vertical channel along a third direction, and the third direction intersects both the first direction and the second direction.

[0015] In some embodiments, the first direction is parallel to an extension direction of the first vertical channel, the second vertical channel also extends along the first direction, and the second direction is parallel to an extension direction of the charge storage structure;

[0016] The second gate includes a first sub-portion and a second sub-portion that are distributed along a third direction on opposite sides of the second vertical channel and are independent of each other. The third direction intersects both the first direction and the second direction.

[0017] In some embodiments, the material of the first vertical channel and the material of the second vertical channel are both oxide semiconductor materials.

[0018] According to some other embodiments, the present disclosure further provides a storage array, including:

[0019] A plurality of memory cells as described above, each of the memory cells comprising a first vertical transistor and a second vertical transistor, which are not only staggered in a first direction but also staggered in a second direction, so that the plurality of memory cells are stacked in a staircase shape;

[0020] a bit line electrically connected to a first source region of a first vertical transistor in a plurality of the memory cells;

[0021] a first word line, the first word line being electrically connected to first gates of first vertical transistors in a plurality of the memory cells;

[0022] A second word line is electrically connected to second gates of second vertical transistors in the plurality of memory cells.

[0023] In some embodiments, a plurality of the storage units are arranged at intervals along the second direction;

[0024] The first vertical transistors in two memory cells adjacent to each other along the second direction are adjacent to each other, and the first word line continuously and electrically connects the first gates in two memory cells adjacent to each other along the second direction.

[0025] In some embodiments, a plurality of the storage units are arranged at intervals along the second direction;

[0026] The second vertical transistors in two adjacent memory cells along the second direction are adjacently distributed, and the second word line continuously and electrically connects the second gates in two adjacent memory cells along the second direction.

[0027] In some embodiments, the plurality of storage units are arranged at intervals along a third direction, and the third direction intersects both the first direction and the second direction;

[0028] The bit line continuously and electrically connects the first source regions in two memory cells adjacent to each other along the third direction.

[0029] According to some further embodiments, the present disclosure further provides a method for preparing a storage array, comprising the following steps:

[0030] providing a substrate;

[0031] A plurality of memory cells stacked and arranged in a staircase shape are sequentially formed on the substrate, and a bit line, a first word line and a second word line electrically connected to the memory cells are formed, the memory cell comprises a first vertical transistor and a second vertical transistor which are staggered in a first direction and a second direction, the first vertical transistor comprises a first gate, a first vertical channel, and a first source region and a first drain region located at both ends of the first vertical channel, the first drain region comprises a charge storage structure, the second vertical transistor comprises a second gate, a second vertical channel, and a second source region and a second drain region located at both ends of the second vertical channel, the second gate is electrically connected to the charge storage structure, the bit line is electrically connected to the first source region of the first vertical transistor in the plurality of the memory cells, the first word line is electrically connected to the first gate of the first vertical transistor in the plurality of the memory cells, and the second word line is electrically connected to the second gate of the second vertical transistor in the plurality of the memory cells, wherein the first direction intersects with the second direction.

[0032] The memory cell, memory array and memory array preparation method provided by some embodiments of the present disclosure form a 2T0C stacking structure by connecting a vertical single-gate write transistor (i.e., a first vertical transistor) to a vertical dual-gate read transistor (i.e., a second vertical transistor), and controlling the different offsets of the threshold voltage of the read transistor by the voltage written on the storage node of the write transistor, and applying a voltage on the read word line at the same time, so that the current of different sizes is read on the bit line to realize the read operation of the 2T0C architecture. The first vertical transistor and the second vertical transistor in the memory cell in some embodiments of the present disclosure are arranged in a staggered manner in the first direction and the second direction, which helps to improve the arrangement density of the memory cell, thereby improving the storage density of the semiconductor device including the memory cell, so as to improve the performance of the semiconductor device with a 2T0C structure. The stacking structure in which the plurality of memory cells are arranged in a stepped ascending manner in other embodiments of the present disclosure greatly saves the space of the transistor stacking compared to the stacking of the planar transistor, and can further improve the storage density. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Attached Figure 1 is a circuit diagram of a memory array including a plurality of memory cells in a specific embodiment of the present disclosure;

[0034] Attached Figure 2 is a circuit diagram of a storage unit in a specific embodiment of the present disclosure;

[0035] Attached Figure 3 is a schematic diagram of the structure of a storage unit in a specific implementation manner of the present disclosure;

[0036] Attached Figure 4is a schematic diagram of the structure of another storage unit in a specific embodiment of the present disclosure;

[0037] Attached Figure 5 is a schematic diagram of the three-dimensional structure of a region in a storage array in a specific embodiment of the present disclosure;

[0038] Attached Figure 6 is a schematic cross-sectional view of a region of a storage array in a specific embodiment of the present disclosure;

[0039] Attached Figure 7 is a schematic diagram of the three-dimensional structure of another area in the storage array in a specific embodiment of the present disclosure;

[0040] Attached Figure 8 is a schematic cross-sectional view of another area of ​​a storage array in a specific embodiment of the present disclosure;

[0041] Attached Fig. 9 It is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] The specific implementation manners of the memory cell, memory array and memory array manufacturing method provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0043] This specific implementation provides a storage unit, Figure 1 is a circuit diagram of a memory array including a plurality of memory cells in a specific embodiment of the present disclosure, Figure 2 is a circuit diagram of a storage unit in a specific embodiment of the present disclosure, and Figure 3 is a schematic diagram of a storage unit in a specific embodiment of the present disclosure, Figure 4 FIG. 1 is a schematic diagram of the structure of another storage unit in a specific embodiment of the present disclosure. Figure 1-Figure 4 As shown, the storage unit 10 includes:

[0044] The first vertical transistor T1 includes a first gate G2, a first vertical channel 31, and a first source region 32 and a first drain region 33 located at two ends of the first vertical channel 31, wherein the first drain region 33 includes a charge storage structure SN;

[0045] The second vertical transistor T2 includes a second gate, a second vertical channel 30, and a second source region 34 and a second drain region 35 located at both ends of the second vertical channel 30, wherein the second gate is electrically connected to the charge storage structure SN, wherein the second vertical transistor T2 and the first vertical transistor T1 are not only staggered in the first direction D1, but also staggered in the second direction D2, and the first direction D1 intersects with the second direction D2.

[0046] The semiconductor structure described in this specific embodiment may be, but is not limited to, a DRAM. This specific embodiment is described by taking the semiconductor structure being a DRAM as an example. In one example, the storage unit 10 is located on the top surface of the substrate, the first direction D1 is perpendicular to the top surface of the substrate, and the second direction D2 is parallel to the top surface of the substrate. Among them, the substrate may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate being a silicon substrate as an example. In other embodiments, the substrate may also be a semiconductor substrate such as gallium nitride, gallium arsenide, gallium carbide, silicon carbide or SOI. The top surface of the substrate refers to the surface of the substrate facing the storage unit 10. The storage unit 10 includes the first vertical transistor T1 and the second vertical transistor T2, the first vertical transistor T1 includes the first vertical channel 31, and the first source region 32 and the first drain region 33 are distributed at opposite ends of the first vertical channel 31 along the first direction D1. The first drain region also includes the charge storage structure SN. The second vertical transistor T2 is located above the first vertical transistor T1 along the first direction D1, and is staggered with the first vertical transistor T1 in both the first direction D1 and the second direction D2. In the storage unit 10, the first vertical transistor T1 is used as a write transistor, and the second vertical transistor T2 is used as a read transistor. When the storage unit 10 is written, the first vertical transistor T1 is turned on, and the voltage applied to the charge storage structure SN is controlled to be different to control the different offsets of the threshold voltage of the second vertical transistor T2, so that different data signals (for example, data 0 or data 1) are written into the second vertical transistor T2. When the storage unit 10 is read, a read voltage is applied to the second gate, and the first vertical transistor T1 is turned on at the same time, so that the data signal stored in the second vertical transistor T2 is read on the bit line BL electrically connected to the first vertical transistor T1.

[0047] In this specific embodiment, the first vertical transistor T1 and the second vertical transistor T2 are arranged in the memory cell 10, and the first vertical transistor T1 is used as a write transistor, and the second vertical transistor T2 is used as a read transistor, so as to help improve the arrangement density of the memory cell 10, and further improve the storage density of the semiconductor device including the memory cell 10. In addition, the first vertical transistor T1 and the second vertical transistor T2 are arranged staggered along the first direction D1 and the second direction D2, which helps to reduce the facing area between the first vertical transistor T1 and the second vertical transistor T2, thereby reducing the capacitive coupling effect between the first vertical transistor T1 and the second vertical transistor T2. The first vertical transistor T1 is electrically connected to the second gate of the second vertical transistor T2 through the charge storage structure SN, so that the memory cell 10 only needs to be electrically connected to one bit line BL, reducing the number of bit lines BL required to be set, thereby helping to further improve the storage density. At the same time, since the number of the bit lines BL in the semiconductor structure is reduced, the signal crosstalk between the bit lines BL and the word lines (including the first word line WL1 and the second word line WL2) in the semiconductor structure is reduced, thereby reducing the leakage current and voltage drop on the word lines, and improving the performance of the semiconductor structure. Moreover, in this specific embodiment, the memory cell 10 only needs to be electrically connected to one bit line BL, thereby simplifying the read and write operations of the memory cell 10 and improving the response speed of the semiconductor structure.

[0048] In some embodiments, the first source region 32 is located above the first drain region 33 , and the second source region 34 is located above the second drain region 35 ;

[0049] The first source region 32 is located above the second source region 34 , and the first drain region 33 is located above the second drain region 35 .

[0050] For example, if Figure 4 As shown, along the first direction D1, the first source region 32 is located above the first drain region 33, the second source region 34 is located above the second drain region 35, the first source region 32 is located on the second source region 34, and the first drain region 33 is located above the second drain region 35, that is, the first vertical transistor T1 is at least partially located above the second vertical transistor T2, so that the first vertical transistor T1 and the second vertical transistor T2 are partially staggered in the first direction D1 and the second direction D2, without causing an increase in the size of the storage unit 10.

[0051] In some other embodiments, the first drain region 33 is located above the first source region 32 , and the second drain region 35 is located above the second source region 34 ;

[0052] The second drain region 35 is located above the first drain region 33 , and the second source region 34 is located above the first source region 32 .

[0053] For example, if Figure 3 As shown, along the first direction D1, the first drain region 33 is located above the first source region 32, the second drain region 35 is located above the second source region 34, the second drain region 35 is located above the first drain region 33, and the second source region 34 is located above the first source region 32, that is, the first vertical transistor T1 is at least partially located above the second vertical transistor T2, so that the first vertical transistor T1 and the second vertical transistor T2 are partially staggered in the first direction D1 and the second direction D2, without causing an increase in the size of the storage unit 10.

[0054] In some embodiments, the first direction is parallel to an extension direction of the first vertical channel, the second vertical channel also extends along the first direction, and the second direction is parallel to an extension direction of the charge storage structure;

[0055] The first gate is located at one side of the first vertical channel along a third direction, and the third direction intersects both the first direction and the second direction.

[0056] In some embodiments, the first direction D1 is parallel to the extension direction of the first vertical channel 31, the second vertical channel 30 also extends along the first direction D1, and the second direction D2 is parallel to the extension direction of the charge storage structure SN;

[0057] The second gate includes a first sub-portion G11 and a second sub-portion G12 that are distributed along a third direction D3 on opposite sides of the second vertical channel 30 and are independent of each other. The third direction D3 intersects both the first direction D1 and the second direction D2.

[0058] Specifically, the first sub-portion G11 and the second sub-portion G12 in the second gate are not connected (i.e., independent of each other), thereby forming a dual-gate transistor structure. When performing a read operation on the memory cell 10, a read voltage is applied to the first sub-portion G11. In one example, Figure 3 and Figure 4As shown, the charge storage structure SN extends along the second direction D2, one end of the charge storage structure SN is located on the first drain region 33 and is electrically connected to the first drain region 33, and the portion of the charge storage structure SN covering the second vertical channel 30 serves as the second sub-portion G12 of the second gate, so as to simplify the preparation process of the storage unit 10 while reducing the contact resistance between the first vertical transistor T1 and the second vertical transistor T2. In another example, the charge storage structure SN extends along the second direction D2, one end of the charge storage structure SN is located on the first drain region 33 along the first direction D1 and is electrically connected to the first drain region 33, and the other end of the charge storage structure SN is electrically connected to the second sub-portion G12 of the second gate, so as to improve the preparation flexibility of the storage unit 10 and meet different usage requirements. In this specific embodiment, the second direction D2 and the third direction D3 may be perpendicularly intersected (i.e., orthogonal), or may be obliquely intersected.

[0059] In some embodiments, the material of the first vertical channel 31 and the material of the second vertical channel 30 are both oxide semiconductor materials. Among them, the oxide semiconductor material is any one of In2O3 (indium oxide), ZnO (zinc oxide), IZO (indium zinc oxide), IGZO (indium gallium zinc oxide), IZTO (indium tin zinc oxide), and ZnON (zinc oxynitride), or a combination of two or more thereof. The charge storage structure SN may be in the shape of a long strip, and the material of the charge storage structure may be a conductive material such as metal or TiN. In other embodiments, the material of the first vertical channel 31 and the material of the second vertical channel 30 may also be both silicon.

[0060] This specific embodiment also provides a storage array, Figure 5 is a schematic diagram of a three-dimensional structure of a region in a storage array in a specific embodiment of the present disclosure, and Figure 6 is a cross-sectional schematic diagram of a region of a storage array in a specific embodiment of the present disclosure, and Figure 7 is a schematic diagram of the three-dimensional structure of another area in the storage array in a specific embodiment of the present disclosure, and Figure 8 is a cross-sectional schematic diagram of another area of ​​the memory array in the specific implementation mode of the present disclosure. The structural schematic diagram of the memory unit constituting the memory array in the specific implementation mode can be found in Figure 1-Figure 4 .like Figure 1-Figure 8 As shown, the storage array comprises:

[0061] Multiple as above (e.g. Figure 1-Figure 4) the memory cells 10, each of the memory cells 10 comprises a first vertical transistor T1 and a second vertical transistor T2, which are not only staggered in the first direction D1, but also staggered in the second direction D2, so that the plurality of memory cells 10 are stacked in a stepped arrangement;

[0062] A bit line BL, the bit line BL being electrically connected to the first source region 32 of the first vertical transistor T1 in the plurality of memory cells 10;

[0063] A first word line WL1, the first word line WL1 is electrically connected to a first gate G2 of a first vertical transistor T1 in a plurality of the memory cells 10;

[0064] The second word line WL2 is electrically connected to the second gates of the second vertical transistors T2 in the plurality of memory cells 10 .

[0065] For example, if Figure 1 , Figure 2 , Figure 5 and Figure 7 As shown, the semiconductor structure includes a plurality of the memory cells 10 arranged at intervals along the second direction D2 and the third direction D3, and a plurality of the bit lines BL (for example, Figure 1 The first bit line BL0 and the second bit line BL1 are shown in FIG. 1 ), and a plurality of the second word lines WL2 (eg, Figure 1 , and a plurality of first word lines WL1 (eg, Figure 1 , word lines WL10 and WL11 are shown in FIG. 1 ). In one example, the bit line BL extends along the third direction D3, and the portion of the bit line BL located below the first vertical channel 31 along the first direction D1 serves as the first source region 32 of the first vertical transistor T1, that is, the manufacturing process of the bit line BL is combined with the manufacturing process of the first source region 32 in the vertical transistor T1 to further simplify the process of the memory array. In another example, the bit line BL and the first source region 32 in the first vertical transistor T1 can be formed in steps to flexibly adjust the relative position relationship between the bit line BL and the first vertical transistor T1 to meet different memory array preparation requirements.

[0066] The material of the bit line BL may be a metal or a conductive material such as TiN. In one example, the bit line BL and the charge storage structure SN are located on opposite sides of the first vertical channel 31 along the first direction D1, thereby increasing the distance between the bit line BL and the charge storage structure SN, reducing the capacitive coupling effect between the bit line BL and the charge storage structure SN, and further improving the electrical performance of the memory array and the memory including the memory array.

[0067] In this specific embodiment, the first vertical transistor T1 and the second vertical transistor T2 in each of the memory cells 10 are staggered in the first direction D1 and the second direction D2, so that the plurality of memory cells 10 arranged at intervals along the second direction D2 in the memory array can be stacked in a stepped manner, thereby greatly saving the space for stacking the plurality of memory cells 10 in the memory array, and helping to further improve the storage density of the memory including the memory array. The plurality of memory cells 10 are stacked in a stepped manner, which means that, of the two adjacent memory cells 10 arranged at intervals along the second direction D2, one memory cell 10 is at least partially located above the other memory cell 10 along the first direction D1.

[0068] In some embodiments, the plurality of storage units 10 are arranged at intervals along the second direction D2;

[0069] The first vertical transistors T1 in two adjacent memory cells 10 along the second direction D2 are adjacently distributed, and the first word line WL1 continuously and electrically connects the first gates G2 in two adjacent memory cells 10 along the second direction D2.

[0070] For example, if Figure 1 , Figure 2 , Figure 7 and Figure 8As shown, the memory array may include a first region, and for two memory cells 10 arranged at intervals along the second direction D2 in the first region, the first vertical transistor T1 in one memory cell 10 is adjacent to the first vertical transistor T1 in the other memory cell 10. For the two memory cells 10 arranged at intervals along the second direction D2 in the first region, the first word line WL1 continuously electrically connects the first gates G2 in the two memory cells 10, and the second vertical transistors T2 in the two memory cells 10 are electrically connected to the two second word lines WL2 in a one-to-one correspondence. For the two memory cells 10 arranged at intervals along the second direction D2, the charge storage structure SN in one memory cell 10 is located above the bit line BL electrically connected to the one memory cell 10 along the first direction D1, and the charge storage structure SN in the other memory cell 10 is located below the bit line BL electrically connected to the other memory cell 10 along the first direction D1, thereby increasing the distance between the two adjacent bit lines BL, reducing the facing area between the two adjacent bit lines BL, and reducing the capacitive coupling effect between the adjacent bit lines BL. The plurality of storage units 10 arranged at intervals along the second direction D2 are arranged in a stepped ascending manner along the first direction D1, for example Figure 8 In the two storage cells 10 arranged at intervals along the second direction D2, the second vertical transistor T2 in one storage cell 10 is located above the second vertical transistor T2 in the other storage cell 10 along the first direction D1, thereby further improving the density of the storage cells in the semiconductor structure, that is, improving the storage density of the semiconductor structure.

[0071] In some embodiments, the plurality of storage units 10 are arranged at intervals along the second direction D2;

[0072] The second vertical transistors T2 in two adjacent memory cells 10 along the second direction D2 are adjacently distributed, and the second word line WL2 continuously and electrically connects the second gates in two adjacent memory cells 10 along the second direction D2.

[0073] For example, if Figure 1 , Figure 2 , Figure 5 and Figure 6As shown, the memory array may further include a second region, and for two memory cells 10 arranged at intervals along the second direction D2 in the second region, the second vertical transistor T2 in one memory cell 10 is adjacent to the second vertical transistor T2 in the other memory cell 10. For two memory cells 10 arranged at intervals along the second direction D2 in the second region, the second word line WL2 continuously electrically connects the second gates in the two memory cells 10, and the first gates G2 in the first vertical transistors T1 in the two memory cells 10 are electrically connected to the two switch word lines WL in a one-to-one correspondence. For two memory cells 10 arranged at intervals along the second direction D2, the charge storage structure SN in one memory cell 10 is located above the bit line BL electrically connected to the one memory cell 10 along the first direction D1, and the charge storage structure SN in the other memory cell 10 is located below the bit line BL electrically connected to the other memory cell 10 along the first direction D1, thereby increasing the distance between the two adjacent bit lines BL and reducing the capacitive coupling effect between the adjacent bit lines BL. The plurality of storage units 10 arranged at intervals along the second direction D2 are arranged in a stepped ascending manner along the first direction D1, for example Figure 6 In the two storage cells 10 arranged at intervals along the second direction D2, the first vertical transistor T1 in one storage cell 10 is located above the first vertical transistor T1 in the other storage cell 10 along the first direction D1, thereby further improving the density of the storage cells 10 in the storage array, that is, improving the storage density of the memory including the storage array.

[0074] In one example, the storage array includes a plurality of the first regions and a plurality of the second regions, and the first regions and the second regions are alternately arranged along the second direction to improve space utilization inside the semiconductor structure.

[0075] In some embodiments, the plurality of storage units 10 are arranged at intervals along a third direction D3, and the third direction D3 intersects both the first direction D1 and the second direction D2;

[0076] The bit line BL continuously and electrically connects the first source regions 32 in two adjacent memory cells 10 along the third direction D3 .

[0077] This specific embodiment also provides a method for preparing a storage array, Fig. 9 is a flow chart of the method for forming a semiconductor structure in a specific embodiment of the present disclosure. The structural schematic diagram of the memory array prepared in this specific embodiment can be found in Figure 1-Figure 8 .like Figure 1-Figure 9 As shown, the method for preparing the storage array comprises the following steps:

[0078] Step S91, providing a substrate;

[0079] Step S92, sequentially forming a plurality of memory cells 10 stacked and arranged in a staircase shape on the substrate, and forming a bit line BL, a first word line WL1 and a second word line WL2 electrically connected to the memory cell 10, wherein the memory cell 10 includes a first vertical transistor T1 and a second vertical transistor T2 arranged in a staggered manner in a first direction D1 and a second direction D2, wherein the first vertical transistor T1 includes a first gate G2, a first vertical channel 31, and a first source region 32 and a first drain region 33 located at both ends of the first vertical channel 31, wherein the first drain region 33 includes a charge storage structure SN, and the second vertical transistor T2 includes a second gate, a second vertical channel 30, and a second source region 34 and a second drain region 35 located at both ends of the second vertical channel 30, the second gate is electrically connected to the charge storage structure SN, the bit line BL is electrically connected to the first source region 32 of the first vertical transistor T1 in the plurality of storage cells 10, the first word line WL1 is electrically connected to the first gate G2 of the first vertical transistor T1 in the plurality of storage cells 10, and the second word line WL2 is electrically connected to the second gate of the second vertical transistor T2 in the plurality of storage cells 10, wherein the first direction D1 intersects with the second direction D2.

[0080] In some embodiments of the present specific implementation, a memory cell, a memory array, and a method for preparing a memory array are provided. A 2T0C stacking structure is formed by connecting a vertical single-gate write transistor (i.e., a first vertical transistor) to a vertical dual-gate read transistor (i.e., a second vertical transistor). The different offsets of the threshold voltage of the read transistor are controlled by the voltage written on the storage node of the write transistor, and a voltage is applied to the read word line at the same time, so that currents of different sizes are read on the bit line to realize the read operation of the 2T0C architecture. The first vertical transistor and the second vertical transistor in the memory cell in some embodiments of the present disclosure are arranged in a staggered manner in the first direction and the second direction, which helps to improve the arrangement density of the memory cell, thereby improving the storage density of the semiconductor device including the memory cell, so as to improve the performance of the semiconductor device with a 2T0C structure. The stacking structure in which the plurality of memory cells are arranged in a stepped ascending manner in other embodiments of the present disclosure greatly saves the space of the transistor stacking compared to the stacking of the planar transistor, and can further improve the storage density.

[0081] The above is only a preferred embodiment of the present disclosure. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present disclosure. These improvements and modifications should also be regarded as within the scope of protection of the present disclosure.

Claims

1. A storage unit, characterized in that: include: A first vertical transistor, comprising a first gate, a first vertical channel, and a first source region and a first drain region located at two ends of the first vertical channel, wherein the first drain region comprises a charge storage structure; The second vertical transistor includes a second gate, a second vertical channel, and a second source region and a second drain region located at both ends of the second vertical channel, wherein the second gate is electrically connected to the charge storage structure, wherein the second vertical transistor and the first vertical transistor are staggered not only in the first direction but also in the second direction, and the first direction intersects with the second direction.

2. The storage unit according to claim 1, characterized in that The first source region is located above the first drain region, and the second source region is located above the second drain region; The first source region is located above the second source region, and the first drain region is located above the second drain region.

3. The storage unit according to claim 1, characterized in that The first drain region is located above the first source region, and the second drain region is located above the second source region; The second drain region is located above the first drain region, and the second source region is located above the first source region.

4. The storage unit according to claim 1, characterized in that The first direction is parallel to an extension direction of the first vertical channel, the second vertical channel also extends along the first direction, and the second direction is parallel to an extension direction of the charge storage structure; The first gate is located at one side of the first vertical channel along a third direction, and the third direction intersects both the first direction and the second direction.

5. The storage unit according to claim 1, characterized in that The first direction is parallel to an extension direction of the first vertical channel, the second vertical channel also extends along the first direction, and the second direction is parallel to an extension direction of the charge storage structure; The second gate includes a first sub-portion and a second sub-portion that are distributed along a third direction on opposite sides of the second vertical channel and are independent of each other. The third direction intersects both the first direction and the second direction.

6. The storage unit according to claim 1, characterized in that The material of the first vertical channel and the material of the second vertical channel are both oxide semiconductor materials.

7. A storage array, characterized in that: include: A plurality of memory cells as claimed in claim 1, each of the memory cells comprising a first vertical transistor and a second vertical transistor, which are not only staggered in a first direction but also staggered in a second direction, so that the plurality of memory cells are stacked in a staircase shape; a bit line electrically connected to a first source region of a first vertical transistor in a plurality of the memory cells; a first word line, the first word line being electrically connected to first gates of first vertical transistors in a plurality of the memory cells; A second word line is electrically connected to second gates of second vertical transistors in the plurality of memory cells.

8. The storage array according to claim 7, characterized in that: A plurality of the storage units are arranged at intervals along the second direction; The first vertical transistors in two memory cells adjacent to each other along the second direction are adjacent to each other, and the first word line continuously and electrically connects the first gates in two memory cells adjacent to each other along the second direction.

9. The storage array according to claim 7, characterized in that: A plurality of the storage units are arranged at intervals along the second direction; The second vertical transistors in two adjacent memory cells along the second direction are adjacently distributed, and the second word line continuously and electrically connects the second gates in two adjacent memory cells along the second direction.

10. The storage array according to claim 8 or 9, characterized in that: The plurality of storage units are arranged at intervals along a third direction, and the third direction intersects both the first direction and the second direction; The bit line continuously and electrically connects the first source regions in two memory cells adjacent to each other along the third direction.

11. A method for preparing a storage array, characterized in that: The steps include: providing a substrate; A plurality of memory cells stacked and arranged in a staircase shape are sequentially formed on the substrate, and a bit line, a first word line and a second word line electrically connected to the memory cells are formed, the memory cell comprises a first vertical transistor and a second vertical transistor which are staggered in a first direction and a second direction, the first vertical transistor comprises a first gate, a first vertical channel, and a first source region and a first drain region located at both ends of the first vertical channel, the first drain region comprises a charge storage structure, the second vertical transistor comprises a second gate, a second vertical channel, and a second source region and a second drain region located at both ends of the second vertical channel, the second gate is electrically connected to the charge storage structure, the bit line is electrically connected to the first source region of the first vertical transistor in the plurality of the memory cells, the first word line is electrically connected to the first gate of the first vertical transistor in the plurality of the memory cells, and the second word line is electrically connected to the second gate of the second vertical transistor in the plurality of the memory cells, wherein the first direction intersects with the second direction.

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