Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises an active pillar, a gate oxide layer and a gate layer. The active pillar comprises a source region, a channel region and a drain region distributed in sequence along the extension direction of the active pillar. The channel region comprises a first region and a second region distributed adjacently. The first region is distributed adjacently with the source region and / or the drain region. The first region and the source region or the drain region are different in doping type. The gate oxide layer covers the surface of the source region, the channel region and the drain region. The gate layer covers the surface of the gate oxide layer. The orthographic projection of the gate layer on the active pillar coincides with the channel region. The semiconductor structure can reduce the probability of breakdown between the source region and the drain region, and improve the reliability of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as smartphones and tablets due to its advantages of small size, high integration, and high transfer speed. Transistors, as the core component of DRAM, play a crucial role in the device's electrical performance. With the continuous advancement of semiconductor technology, the spatial dimensions of transistors are constantly shrinking. However, with this shrinking size, the stability of transistors deteriorates.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce the probability of breakdown between the source and drain regions and improve device reliability.

[0005] According to one aspect of this disclosure, a semiconductor structure is provided, comprising:

[0006] An active pillar includes a source region, a channel region, and a drain region sequentially distributed along the extension direction of the active pillar. The channel region includes a first region and a second region distributed adjacent to each other. The first region is distributed adjacent to the source region and / or the drain region. The first region and the source region or the drain region have different doping types.

[0007] A gate oxide layer covers the surfaces of the source region, the channel region, and the drain region;

[0008] A gate layer, covering the surface of the gate oxide layer, and its orthogonal projection on the active pillar coincides with the channel region.

[0009] In an exemplary embodiment of this disclosure, the first region includes a first sub-region and a second sub-region spaced apart along the extension direction of the active pillar. The first sub-region is distributed adjacent to the source region, and the second sub-region is distributed adjacent to the drain region. The boundary of the orthogonal projection of the gate layer onto the active pillar coincides with the boundary of the first sub-region near the source region and the boundary of the second sub-region near the drain region.

[0010] In one exemplary embodiment of this disclosure, the cross-sections of both the first sub-region and the second sub-region are annular in a direction perpendicular to the extension direction of the active column;

[0011] Alternatively, the first sub-region is located between the second region and the source region; the second sub-region is located between the second region and the drain region.

[0012] In one exemplary embodiment of this disclosure, the source region and the drain region are both n-type doped, and the first region is p-type doped.

[0013] In one exemplary embodiment of this disclosure, the source region includes a first doped region and a first lightly doped region, the first lightly doped region being located between the channel region and the first doped region, the first doped region and the first lightly doped region having the same doped ion type, and the doped ion concentration of the first lightly doped region being less than the doped ion concentration of the first doped region; the drain region includes a second doped region and a second lightly doped region, the second lightly doped region being located between the channel region and the second doped region, the second doped region and the second lightly doped region having the same doped ion type, and the doped ion concentration of the second lightly doped region being less than the doped ion concentration of the second doped region.

[0014] In one exemplary embodiment of this disclosure, the surface in the channel region located in the extension direction of the active post is curved.

[0015] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0016] An active pillar is formed, the active pillar including a source region, a channel region and a drain region distributed sequentially along the extension direction of the active pillar, the channel region including a first region and a second region distributed adjacent to each other, the first region being distributed adjacent to the source region and / or the drain region, and the first region and the source region and / or the drain region having different doping types.

[0017] A gate oxide layer is formed covering the surfaces of the source region, the channel region, and the drain region;

[0018] A gate layer is formed covering the surface of the gate oxide layer, wherein the orthogonal projection of the gate layer on the active pillar coincides with the channel region.

[0019] In an exemplary embodiment of this disclosure, the first region includes a first sub-region and a second sub-region spaced apart along the extension direction of the active pillar. The first sub-region is distributed adjacent to the source region, and the second sub-region is distributed adjacent to the drain region. The boundary of the orthogonal projection of the gate layer onto the active pillar coincides with the boundary of the first sub-region near the source region and the boundary of the second sub-region near the drain region.

[0020] In one exemplary embodiment of this disclosure, the cross-sections of both the first sub-region and the second sub-region are annular in a direction perpendicular to the extension direction of the active column;

[0021] Alternatively, the first sub-region is located between the second region and the source region; the second sub-region is located between the second region and the drain region.

[0022] In one exemplary embodiment of this disclosure, the source region includes a first doped region and a first lightly doped region, the first lightly doped region being located between the channel region and the first doped region, the first doped region and the first lightly doped region having the same doped ion type, and the doped ion concentration of the first lightly doped region being less than the doped ion concentration of the first doped region; the drain region includes a second doped region and a second lightly doped region, the second lightly doped region being located between the channel region and the second doped region, the second doped region and the second lightly doped region having the same doped ion type, and the doped ion concentration of the second lightly doped region being less than the doped ion concentration of the second doped region.

[0023] The semiconductor structure and its formation method disclosed herein can jointly constitute a transistor, comprising a source region, a drain region, a channel region, a gate oxide layer, and a gate layer. Since the first region of the channel region is adjacent to the source and / or drain regions, and the doping types of the first region and the source and / or drain regions are different, a pn junction can be formed between the first region and the source and / or drain regions. The pn junction can block the migration of electrons from the source (or drain) region into the channel region, thus blocking leakage current and reducing the probability of breakdown between the source and drain regions, which helps improve device stability and product yield. Simultaneously, since the leakage current is blocked by the pn junction, electrons are prevented from accumulating in the channel region, preventing electrons from tunneling into the oxide layer and changing the threshold voltage, which helps improve device reliability.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.

[0027] Figure 2 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.

[0028] Figure 3 This is a schematic diagram of a semiconductor structure in one embodiment of the present disclosure.

[0029] Figure 4 This is a flowchart of a method for forming a semiconductor structure according to an embodiment of this disclosure.

[0030] Explanation of reference numerals in the attached figures:

[0031] 1. Active pillar; 11. Source region; 111. First doped region; 112. First lightly doped region; 12. Channel region; 121. First region; 1211. First sub-region; 1212. Second sub-region; 122. Second region; 13. Drain region; 131. Second doped region; 132. Second lightly doped region; 2. Gate oxide layer; 3. Gate layer. Detailed Implementation

[0032] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0033] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0034] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first” and “second” are used only as markers and are not a limitation on the number of objects.

[0035] This disclosure provides a semiconductor structure, such as... Figures 1-3 As shown, the semiconductor structure includes an active pillar 1, a gate oxide layer 2, and a gate layer 3, wherein:

[0036] The active pillar 1 includes a source region 11, a channel region 12, and a drain region 13 distributed sequentially along the extension direction of the active pillar 1. The channel region 12 includes a first region 121 and a second region 122 distributed adjacent to each other. The first region 121 is distributed adjacent to the source region 11 and / or the drain region 13. The first region 121 and the source region 11 and / or the drain region 13 have different doping types.

[0037] Gate oxide layer 2 covers the surfaces of source region 11, channel region 12 and drain region 13;

[0038] The gate layer 3 covers the surface of the gate oxide layer 2, and its orthogonal projection on the active pillar 1 coincides with the channel region 12.

[0039] The semiconductor structure disclosed herein comprises a source region 11, a drain region 13, a channel region 12, a gate oxide layer 2, and a gate layer 3, which together constitute a transistor. Since the first region 121 of the channel region 12 is adjacent to the source region 11 and / or the drain region 13, and the doping types of the first region 121 and the source region 11 and / or the drain region 13 are different, a pn junction can be formed between the first region 121 and the source region 11 and / or the drain region 13. The pn junction can block the migration of electrons from the source region 11 (or the drain region 13) into the channel region 12, reducing leakage current and thus reducing the probability of breakdown between the source region 11 and the drain region 13, which helps improve device stability and product yield. Simultaneously, since the leakage current is blocked by the pn junction, electrons are prevented from accumulating in the channel region 12, preventing electrons from tunneling into the gate oxide layer 2 and changing the threshold voltage, which helps improve device reliability.

[0040] The following provides a detailed description of the various parts of the semiconductor structure disclosed herein, along with their specific details:

[0041] Please continue reading Figures 1-3 As shown, the active pillar 1 can be columnar, and its cross-section can be rectangular, circular, polygonal, or irregular in shape, without any special limitation. The material of the active pillar 1 can be silicon or other semiconductor materials, which are not listed here.

[0042] The active pillar 1 may include a source region 11, a channel region 12, and a drain region 13 sequentially distributed along its extension direction. In some embodiments of this disclosure, the shape and size of each region of the active pillar 1 are equal everywhere along its extension direction; that is, the active pillar 1 is a straight columnar structure. In other embodiments of this disclosure, such as... Figure 2 and Figure 3 As shown, the surface of the channel region 12 located in the extension direction of the active pillar 1 can be curved, which can increase the effective length of the channel region 12 without changing the overall size of the device, thus helping to reduce the short-channel effect. For example, the surface of the channel region 12 can be a concave surface that is recessed inward along a direction perpendicular to the active pillar 1. For instance, the concave surface can be a curved surface of the channel region 12 that is recessed inward along a direction perpendicular to the active pillar 1. Taking the horizontal central axis surface of the channel region 12 as the starting surface, the horizontal dimension of the channel region 12 with a concave surface increases as the distance from the top surface and / or bottom surface of the channel region 12 decreases. In some other embodiments of this disclosure, the surface of the channel region 12 can also be a convex surface that protrudes outward along a direction perpendicular to the active pillar 1, which is not particularly limited here.

[0043] In one exemplary embodiment of this disclosure, the source region 11 and the drain region 13 have the same doping type, while the channel region 12 has a different doping type than the source region 11. For example, the source region 11 and the drain region 13 are both n-type doped, and the channel region 12 is p-type doped; or, the source region 11 and the drain region 13 are both p-type doped, and the channel region 12 is n-type doped.

[0044] In some embodiments of this disclosure, the source region 11 may include a first doped region 111 and a first lightly doped region 112. The doping type of the first doped region 111 is the same as that of the first lightly doped region 112. For example, the doping type of both the first doped region 111 and the first lightly doped region 112 may be n-type. The doping concentrations of the first doped region 111 and the first lightly doped region 112 are different, and the doping concentration of the first lightly doped region 112 is less than that of the first doped region 111. The first lightly doped region 112 may be located between the first doped region 111 and the channel region 12, and in the extension direction of the active pillar 1, one end of the first lightly doped region 112 is adjacent to the channel region 12, and the other end is adjacent to the first doped region 111.

[0045] In some embodiments of this disclosure, the drain region 13 may include a second doped region 131 and a second lightly doped region 132. The doping type of the second doped region 131 is the same as that of the second lightly doped region 132. For example, both the second doped region 131 and the second lightly doped region 132 may be n-type. The doping concentrations of the second doped region 131 and the second lightly doped region 132 are different, and the doping concentration of the second lightly doped region 132 is less than that of the second doped region 131. The second lightly doped region 132 may be located between the second doped region 131 and the channel region 12, and in the extension direction of the active pillar 1, one end of the second lightly doped region 132 is adjacent to the channel region 12, and the other end is adjacent to the second doped region 131. In the embodiments of this disclosure, the first lightly doped region 132 and the second lightly doped region 132 can bear a portion of the voltage, reducing the electric field strength, thereby alleviating the hot carrier effect, reducing structural leakage current, and improving structural performance.

[0046] The channel region 12 may include a first region 121 and a second region 122 that are adjacent to each other. The first region 121 may be adjacent to the source region 11, for example, it may be adjacent to a first lightly doped region 112; or, the first region 121 may be adjacent to the drain region 13, for example, it may be adjacent to a second lightly doped region 132; or, the first region 121 may include a first sub-region 1211 and a second sub-region 1212 that are spaced apart along the extension direction of the active pillar 1, wherein the first sub-region 1211 is adjacent to the source region 11, and the second sub-region 1212 is adjacent to the drain region 13. The second region 122 may be any other region in the channel region 12 that is not occupied by the first region 121.

[0047] In some embodiments of this disclosure, the first region 121 has a different doping type than the source region 11 or the drain region 13. For example, the first region 121 is p-type doped, while the source region 11 or the drain region 13 is n-type doped. When the first region 121 is adjacent to the source region 11 and / or the drain region 13, and the doping types of the first region 121 and the source region 11 and / or the drain region 13 are different, a pn junction can be formed between the first region 121 and the source region 11 and / or the drain region 13. The pn junction can block the migration of electrons from the source region 11 (or the drain region 13) into the channel region 12, reducing the leakage current and thus reducing the probability of breakdown between the source region 11 and the drain region 13, which helps to improve device stability and product yield. At the same time, since the leakage current is blocked by the pn junction, electrons can be prevented from accumulating in the channel region 12, preventing electrons from tunneling into the gate oxide layer 2 and changing the threshold voltage, which helps to improve device reliability.

[0048] It should be noted that when the first region 121 includes the first sub-region 1211 and the second sub-region 1212, a pn junction will be formed between the source region 11 and the first sub-region 1211. At the same time, a pn junction will also be formed between the second sub-region 1212 and the drain region 13. The two pn junctions can prevent electrons in the source region 11 and the drain region 13 from migrating into the channel region 12, which can enhance the leakage current blocking effect and further reduce the probability of breakdown between the source region 11 and the drain region 13.

[0049] In some embodiments of this disclosure, the first region 121 and the second region 122 have the same doping type, but different from the doping type of the source region 11 or the channel region 12. For example, the doping type of the dopant ions in the first doped region 111, the first lightly doped region 112, the second doped region 131, and the second lightly doped region 132 can all be n-type, and the doping type of the dopant ions in the first region 121 and the second region 122 is p-type. In some embodiments of this disclosure, in order to facilitate the formation of a pn junction between the first region 121 and the source region 11 or the drain region 13, the doping concentrations of the first region 121 and the second region 122 are different; for example, the doping concentration of the dopant ions in the first region 121 is greater than the doping concentration of the dopant ions in the second region 122.

[0050] In an exemplary embodiment of this disclosure, the cross-section of the first region 121 may be annular in the direction perpendicular to the extension direction of the active pillar 1, and the boundary of its outer ring coincides with the boundary of the surface of the channel region 12. The area within its inner ring is filled by the second region 122, that is, the second region 122 may also be in contact with the source region 11 and the drain region 13. In this structure, pn junctions can be formed in the channel region 12 near the boundaries of the source region 11 and the drain region 13, respectively. The pn junctions block leakage current. At the same time, after applying a voltage to the gate layer 3, electrons in the source region 11 and the drain region 13 can be controlled to flow through the second region 122 in the channel region 12 under the action of the electric field. That is, the gate control capability can be improved while reducing leakage current, thereby improving the stability of the transistor.

[0051] In one exemplary embodiment of this disclosure, the width of the first region 121 in the extension direction of the active column 1 can be one-tenth to one-thirtieth of the width of the channel region 12. For example, its width can be one-tenth, one-fifteenth, one-twentieth, one-twenty-fifth or one-thirtieth of the width of the channel region 12. Of course, it can also be other widths, which will not be listed here.

[0052] For example, when the first region 121 includes a first sub-region 1211 and a second sub-region 1212, both the cross-sections of the first sub-region 1211 and the second sub-region 1212 can be annular. In the first sub-region 1211, taking the end of the first sub-region 1211 furthest from the source region 11 as the starting surface, the spacing between the inner and outer rings of the first sub-region 1211 increases as the distance from the source region 11 decreases. Simultaneously, in the second sub-region 1212, taking the end of the second sub-region 1212 furthest from the drain region 13 as the starting surface, the spacing between the inner and outer rings of the second sub-region 1212 increases as the distance from the drain region 13 decreases. This design results in a smaller current drop in the on-state and a larger current drop in the off-state, leading to a relatively high on / off ratio and improving the gate control capability of the gate layer 3.

[0053] In some other embodiments of this disclosure, the first region 121 may be located between the second region 122 and the source region 11, and the second region 122 may be isolated from the source region 11 by the first region 121; or, the first region 121 may be located between the second region 122 and the drain region 13, and the second region 122 may be isolated from the drain region 13 by the first region 121. When the first region 121 includes a first sub-region 1211 and a second sub-region 1212, the first sub-region 1211 may be located between the second region 122 and the source region 11, and the second region 122 may be isolated from the source region 11 by the first sub-region 1211; at the same time, the second sub-region 1212 may be located between the second region 122 and the drain region 13, and the second region 122 may be isolated from the drain region 13 by the second sub-region 1212.

[0054] The gate oxide layer 2 can cover the surfaces of the source region 11, the channel region 12, and the drain region 13. The gate oxide layer 2 can be a thin film or coating that conformally covers the surface of the active pillar 1; the specific form of the gate oxide layer 2 is not specifically limited here. The material of the gate oxide layer 2 can be silicon oxide, and the gate oxide layer 2 can be formed on the surface of the sidewall of the active pillar 1 by means of thermal oxidation, in-situ water vapor oxidation, or atomic layer deposition. Of course, the gate oxide layer 2 can also be formed by other means; the formation method of the gate oxide layer 2 is not specifically limited here. The gate oxide layer 2 can cover part of the surface of the sidewall of the active pillar 1. For example, when the cross-section of the active pillar 1 is rectangular, the gate oxide layer 2 can cover the surface of one sidewall of the active pillar 1; or, the gate oxide layer 2 can cover the surfaces of two oppositely distributed sidewalls in the active pillar 1; or, the gate oxide layer 2 can cover the entire perimeter of the sidewall of the active pillar 1.

[0055] In one exemplary embodiment of this disclosure, a conformally conformal first gate dielectric layer can be formed on the surface of the active pillar 1 by atomic layer deposition or other methods. The thickness of the first gate dielectric layer can be 2 nm to 3 nm, for example, its thickness can be 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm or 3 nm. Of course, the first gate dielectric layer can also have other thicknesses, which will not be listed here. Subsequently, a conformally conformal second gate dielectric layer can be formed on the surface of the active pillar 1 by an in-situ water vapor oxidation process. The thickness of the second gate dielectric layer can be 2 nm to 5 nm, for example, its thickness can be 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm. Of course, the second gate dielectric layer can also have other thicknesses, which will not be listed here. The first gate dielectric layer and the second gate dielectric layer can together constitute the gate oxide layer 2.

[0056] The gate layer 3 may cover the surface of the gate oxide layer 2, and its orthogonal projection on the active pillar 1 coincides with the channel region 12. For example, the boundary of the orthogonal projection of the gate layer 3 on the active pillar 1 coincides with the boundary of the first sub-region 1211 near the source region 11 and the boundary of the second sub-region 1212 near the drain region 13. The material of the gate layer 3 may be a conductive material, such as titanium nitride, tungsten, or polysilicon. The gate layer 3 may be formed on the surface of the gate oxide layer 2 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods may also be used to form the gate layer 3, and no special limitation is made here on the formation method of the gate layer 3. In some embodiments of this disclosure, when the cross-section of the active pillar 1 is rectangular and the gate oxide layer 2 covers the surfaces of two oppositely distributed sidewalls in the active pillar 1, the gate layer 3 can cover the surfaces of the two gate oxide layers 2 respectively, thereby forming a dual-gate structure; or, when the gate oxide layer 2 covers the circumference of the sidewalls of the active pillar 1, the gate layer 3 can cover the outer perimeter of the active pillar 1, thereby forming a full-ring gate structure. For example, the semiconductor structure of this disclosure can be a Vertical Gate-All-Around (VGAA) transistor.

[0057] It should be noted that, since the gate oxide layer 2 surrounding the surfaces of the source region 11 and the drain region 13 is formed simultaneously in the above process, the gate oxide layer 2 between the source region 11 and the drain region 13 (i.e., the gate oxide layer 2 below the gate layer 3) can be protected from damage by the setting of the gate oxide layer 2 on the surfaces of the source region 11 and the drain region 13, which helps to reduce structural leakage current and further improve device reliability.

[0058] This disclosure also provides a method for forming a semiconductor structure, which is used to form the semiconductor structure in any of the above embodiments. Figure 4 A flowchart illustrating the method for forming the semiconductor structure of this disclosure is shown below. Figure 4As shown, the forming method includes steps S110-S130, wherein:

[0059] Step S110: Form an active pillar 1, the active pillar 1 including a source region 11, a channel region 12 and a drain region 13 distributed sequentially along the extension direction of the active pillar 1, the channel region 12 including a first region 121 and a second region 122 distributed adjacent to each other, the first region 121 being distributed adjacent to the source region 11 and / or the drain region 13, and the first region 121 and the source region 11 and / or the drain region 13 having different doping types;

[0060] Step S120: Form a gate oxide layer 2 covering the surfaces of the source region 11, the channel region 12 and the drain region 13;

[0061] Step S130: A gate layer 3 is formed covering the surface of the gate oxide layer 2, and the orthogonal projection of the gate layer 3 on the active pillar 1 coincides with the channel region 12.

[0062] The semiconductor structure formation method disclosed herein allows the source region 11, drain region 13, channel region 12, gate oxide layer 2, and gate layer 3 to jointly constitute a transistor. Since the first region 121 of the channel region 12 is adjacent to the source region 11 and / or drain region 13, and the doping types of the first region 121 and the source region 11 and / or drain region 13 are different, a pn junction can be formed between the first region 121 and the source region 11 and / or drain region 13. The pn junction can block the migration of electrons from the source region 11 (or drain region 13) into the channel region 12, reducing leakage current and thus reducing the probability of breakdown between the source region 11 and drain region 13, which helps improve device stability and product yield. Simultaneously, since the leakage current is blocked by the pn junction, electrons are prevented from accumulating in the channel region 12, preventing electrons from tunneling into the gate oxide layer 2 and changing the threshold voltage, which helps improve device reliability.

[0063] The following provides a detailed description of each step and specific details of the method for forming the semiconductor structure disclosed herein:

[0064] like Figure 4 As shown, in step S110, an active pillar 1 is formed. The active pillar 1 includes a source region 11, a channel region 12, and a drain region 13 distributed sequentially along the extension direction of the active pillar 1. The channel region 12 includes a first region 121 and a second region 122 distributed adjacent to each other. The first region 121 is distributed adjacent to the source region 11 and / or the drain region 13. The doping types of the first region 121 and the source region 11 and / or the drain region 13 are different.

[0065] Please continue reading Figures 1-3As shown, the active pillar 1 can be columnar, and its cross-section can be rectangular, circular, polygonal, or irregular in shape, without any special limitation. The material of the active pillar 1 can be silicon or other semiconductor materials, which are not listed here.

[0066] The active pillar 1 may include a source region 11, a channel region 12, and a drain region 13 sequentially distributed along its extension direction. In some embodiments of this disclosure, the shape and size of each region of the active pillar 1 are equal everywhere along its extension direction; that is, the active pillar 1 is a straight columnar structure. In other embodiments of this disclosure, such as... Figure 2 and Figure 3 As shown, the surface of the channel region 12 located in the extension direction of the active pillar 1 can be curved, which can increase the effective length of the channel region 12 without changing the overall size of the device, thus helping to reduce the short-channel effect. For example, the surface of the channel region 12 can be a concave surface that is recessed inward along a direction perpendicular to the active pillar 1. For instance, the concave surface can be a curved surface of the channel region 12 that is recessed inward along a direction perpendicular to the active pillar 1. Taking the horizontal central axis surface of the channel region 12 as the starting surface, the horizontal dimension of the channel region 12 with a concave surface increases as the distance from the top surface and / or bottom surface of the channel region 12 decreases. In some other embodiments of this disclosure, the surface of the channel region 12 can also be a convex surface that protrudes outward along a direction perpendicular to the active pillar 1, which is not particularly limited here.

[0067] In one exemplary embodiment of this disclosure, the source region 11 and the drain region 13 have the same doping type, while the channel region 12 has a different doping type than the source region 11. For example, the source region 11 and the drain region 13 are both n-type doped, and the channel region 12 is p-type doped; or, the source region 11 and the drain region 13 are both p-type doped, and the channel region 12 is n-type doped.

[0068] In some embodiments of this disclosure, lightly doped regions can be formed in the source region 11 and the drain region 13 using a lightly doped drain (LDD) implantation process. Specifically, the source region 11 may include a first doped region 111 and a first lightly doped region 112. The doping type of the first doped region 111 is the same as that of the first lightly doped region 112. For example, both the first doped region 111 and the first lightly doped region 112 may be n-type. The doping concentrations of the first doped region 111 and the first lightly doped region 112 are different, and the doping concentration of the first lightly doped region 112 is less than that of the first doped region 111. The first lightly doped region 112 may be located between the first doped region 111 and the channel region 12, and in the extension direction of the active pillar 1, one end of the first lightly doped region 112 is adjacent to the channel region 12, and the other end is adjacent to the first doped region 111.

[0069] In some embodiments of this disclosure, the drain region 13 may include a second doped region 131 and a second lightly doped region 132. The doping type of the second doped region 131 is the same as that of the second lightly doped region 132. For example, both the second doped region 131 and the second lightly doped region 132 may be n-type. The doping concentrations of the second doped region 131 and the second lightly doped region 132 are different, and the doping concentration of the second lightly doped region 132 is less than that of the second doped region 131. The second lightly doped region 132 may be located between the second doped region 131 and the channel region 12, and in the extension direction of the active pillar 1, one end of the second lightly doped region 132 is adjacent to the channel region 12, and the other end is adjacent to the second doped region 131. In the embodiments of this disclosure, the first lightly doped region 132 and the second lightly doped region 132 can bear a portion of the voltage, reducing the electric field strength, thereby alleviating the hot carrier effect, reducing structural leakage current, and improving structural performance.

[0070] For example, the source region 11 and the drain region 13 can be initially ion-doped using an ion implantation process. The source region 11 can be divided into a first undoped region and a first lightly doped region 112, and the drain region 13 can be divided into a second undoped region and a second lightly doped region 132. The first undoped region is located on the side of the first lightly doped region 112 away from the channel region 12, and the second undoped region is located on the side of the second lightly doped region 132 away from the channel region 12. After the undoped ions diffuse, the first undoped region and the second undoped region can be ion-doped again. The first undoped region after the second doping can be designated as the first doped region 111, and the second undoped region after the second doping can be designated as the second doped region 131.

[0071] It should be noted that during the second ion doping process, the first lightly doped region 112 and the second lightly doped region 132 are no longer subjected to ion doping. The dopant ion types are the same in both doping processes, and the dopant ion concentration of the first doped region 111 formed after the two doping processes is greater than that of the first lightly doped region 112, and the dopant ion concentration of the second doped region 131 is greater than that of the second lightly doped region 132.

[0072] In another exemplary embodiment of this disclosure, the active pillar 1 may be pre-doped before the gate oxide layer 2 is formed to form a first doped region, a first lightly doped region 112, a second doped region, and a second lightly doped region 132. After the gate oxide layer 2 is formed, the first doped region and the second doped region are doped a second time to form a first doped region 111 and a second doped region 131.

[0073] The channel region 12 may include a first region 121 and a second region 122 that are adjacent to each other. The first region 121 may be adjacent to the source region 11, for example, it may be adjacent to a first lightly doped region 112; or, the first region 121 may be adjacent to the drain region 13, for example, it may be adjacent to a second lightly doped region 132; or, the first region 121 may include a first sub-region 1211 and a second sub-region 1212 that are spaced apart along the extension direction of the active pillar 1, wherein the first sub-region 1211 is adjacent to the source region 11, and the second sub-region 1212 is adjacent to the drain region 13. The second region 122 may be any other region in the channel region 12 that is not occupied by the first region 121.

[0074] In some embodiments of this disclosure, the first region 121 has a different doping type than the source region 11 or the drain region 13. For example, the first region 121 is p-type doped, and the source region 11 or the drain region 13 is n-type doped. When the first region 121 is adjacent to the source region 11 and / or the drain region 13, and the doping types of the first region 121 and the source region 11 and / or the drain region 13 are different, a pn junction can be formed between the first region 121 and the source region 11 and / or the drain region 13. The pn junction can block the migration of electrons in the source region 11 (or the drain region 13) into the channel region 12, reducing the current and thus reducing the probability of breakdown between the source region 11 and the drain region 13, which helps to improve device stability and product yield. At the same time, since the leakage current is blocked by the pn junction, electrons can be prevented from accumulating in the channel region 12, preventing electrons from tunneling into the gate oxide layer 2 and changing the threshold voltage, which helps to improve device reliability.

[0075] It should be noted that when the first region 121 includes the first sub-region 1211 and the second sub-region 1212, a pn junction will be formed between the source region 11 and the first sub-region 1211. At the same time, a pn junction will also be formed between the second sub-region 1212 and the drain region 13. The two pn junctions can prevent electrons in the source region 11 and the drain region 13 from migrating into the channel region 12, which can enhance the leakage current blocking effect and further reduce the probability of breakdown between the source region 11 and the drain region 13.

[0076] In some embodiments of this disclosure, the first region 121 and the second region 122 have the same doping type, but different from the doping type of the source region 11 or the channel region 12. For example, the doping type of the dopant ions in the first doped region 111, the first lightly doped region 112, the second doped region 131, and the second lightly doped region 132 can all be n-type, and the doping type of the dopant ions in the first region 121 and the second region 122 is p-type. In some embodiments of this disclosure, in order to facilitate the formation of a pn junction between the first region 121 and the source region 11 or the drain region 13, the doping concentrations of the first region 121 and the second region 122 are different; for example, the doping concentration of the dopant ions in the first region 121 is greater than the doping concentration of the dopant ions in the second region 122.

[0077] In an exemplary embodiment of this disclosure, the cross-section of the first region 121 may be annular in the direction perpendicular to the extension direction of the active pillar 1, and the boundary of its outer ring coincides with the boundary of the surface of the channel region 12. The area within its inner ring is filled by the second region 122, that is, the second region 122 may also be in contact with the source region 11 and the drain region 13. In this structure, pn junctions can be formed in the channel region 12 near the boundaries of the source region 11 and the drain region 13, respectively. The pn junctions block leakage current. At the same time, after applying a voltage to the gate layer 3, electrons in the source region 11 and the drain region 13 can be controlled to flow through the second region 122 in the channel region 12 under the action of the electric field. That is, the gate control capability can be improved while reducing leakage current, thereby improving the stability of the transistor.

[0078] In an exemplary embodiment of this disclosure, the width of the first region 121 in the extension direction of the active column 1 can be one-tenth to one-thirtieth of the width of the channel region 12. For example, its width can be one-tenth, one-fifteenth, one-twentieth, one-twenty-fifth or one-thirtieth of the width of the channel region 12. Of course, it can also be other widths, which will not be listed here.

[0079] For example, when the first region 121 includes a first sub-region 1211 and a second sub-region 1212, both the cross-sections of the first sub-region 1211 and the second sub-region 1212 can be annular. In the first sub-region 1211, taking the end of the first sub-region 1211 furthest from the source region 11 as the starting surface, the spacing between the inner and outer rings of the first sub-region 1211 increases as the distance from the source region 11 decreases. Simultaneously, in the second sub-region 1212, taking the end of the second sub-region 1212 furthest from the drain region 13 as the starting surface, the spacing between the inner and outer rings of the second sub-region 1212 increases as the distance from the drain region 13 decreases. This design results in a smaller current drop in the on-state and a larger current drop in the off-state, leading to a relatively high on / off ratio and improving the gate control capability of the gate layer 3.

[0080] In some other embodiments of this disclosure, the first region 121 may be located between the second region 122 and the source region 11, and the second region 122 may be isolated from the source region 11 by the first region 121; or, the first region 121 may be located between the second region 122 and the drain region 13, and the second region 122 may be isolated from the drain region 13 by the first region 121. When the first region 121 includes a first sub-region 1211 and a second sub-region 1212, the first sub-region 1211 may be located between the second region 122 and the source region 11, and the second region 122 may be isolated from the source region 11 by the first sub-region 1211; at the same time, the second sub-region 1212 may be located between the second region 122 and the drain region 13, and the second region 122 may be isolated from the drain region 13 by the second sub-region 1212.

[0081] like Figure 4 As shown, in step S120, a gate oxide layer 2 is formed covering the surfaces of the source region 11, the channel region 12, and the drain region 13.

[0082] The gate oxide layer 2 can cover the surfaces of the source region 11, the channel region 12, and the drain region 13. The gate oxide layer 2 can be a thin film or coating that conformally covers the surface of the active pillar 1; the specific form of the gate oxide layer 2 is not specifically limited here. The material of the gate oxide layer 2 can be silicon oxide, and the gate oxide layer 2 can be formed on the surface of the sidewall of the active pillar 1 by means of thermal oxidation, in-situ water vapor oxidation, or atomic layer deposition. Of course, the gate oxide layer 2 can also be formed by other means; the formation method of the gate oxide layer 2 is not specifically limited here. The gate oxide layer 2 can cover part of the surface of the sidewall of the active pillar 1. For example, when the cross-section of the active pillar 1 is rectangular, the gate oxide layer 2 can cover the surface of one sidewall of the active pillar 1; or, the gate oxide layer 2 can cover the surfaces of two oppositely distributed sidewalls in the active pillar 1; or, the gate oxide layer 2 can cover the entire perimeter of the sidewall of the active pillar 1.

[0083] In one exemplary embodiment of this disclosure, a conformally conformal first gate dielectric layer can be formed on the surface of the active pillar 1 by atomic layer deposition or other methods. The thickness of the first gate dielectric layer can be 2 nm to 3 nm, for example, its thickness can be 2 nm, 2.2 nm, 2.4 nm, 2.6 nm, 2.8 nm or 3 nm. Of course, the first gate dielectric layer can also have other thicknesses, which will not be listed here. Subsequently, a conformally conformal second gate dielectric layer can be formed on the surface of the active pillar 1 by an in-situ water vapor oxidation process. The thickness of the second gate dielectric layer can be 2 nm to 5 nm, for example, its thickness can be 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm or 5 nm. Of course, the second gate dielectric layer can also have other thicknesses, which will not be listed here. The first gate dielectric layer and the second gate dielectric layer can together constitute the gate oxide layer 2.

[0084] like Figure 4 As shown, in step S130, a gate layer 3 is formed covering the surface of the gate oxide layer 2, and the orthogonal projection of the gate layer 3 on the active pillar 1 coincides with the channel region 12.

[0085] The gate layer 3 may cover the surface of the gate oxide layer 2, and its orthogonal projection on the active pillar 1 coincides with the channel region 12. For example, the boundary of the orthogonal projection of the gate layer 3 on the active pillar 1 coincides with the boundary of the first sub-region 1211 near the source region 11 and the boundary of the second sub-region 1212 near the drain region 13. The material of the gate layer 3 may be a conductive material, such as titanium nitride, tungsten, or polysilicon. The gate layer 3 may be formed on the surface of the gate oxide layer 2 by means of chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, other methods may also be used to form the gate layer 3, and no special limitation is made here on the formation method of the gate layer 3. In some embodiments of this disclosure, when the cross-section of the active pillar 1 is rectangular and the gate oxide layer 2 covers the surfaces of two oppositely distributed sidewalls in the active pillar 1, the gate layer 3 can cover the surfaces of the two gate oxide layers 2 respectively, thereby forming a dual-gate structure; or, when the gate oxide layer 2 covers the sidewalls of the active pillar 1, the gate layer 3 can cover the outer periphery of the active pillar 1, thereby forming a full-ring gate structure.

[0086] It should be noted that, since the gate oxide layer 2 surrounding the surfaces of the source region 11 and the drain region 13 is formed simultaneously in the above process, the gate oxide layer 2 between the source region 11 and the drain region 13 (i.e., the gate oxide layer 2 below the gate layer 3) can be protected from damage by the setting of the gate oxide layer 2 on the surfaces of the source region 11 and the drain region 13, which helps to reduce structural leakage current and further improve device reliability.

[0087] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0088] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: An active pillar includes a source region, a channel region, and a drain region sequentially distributed along the extension direction of the active pillar. The channel region includes a first region and a second region distributed adjacent to each other. The first region is distributed adjacent to the source region and / or the drain region. The first region and the source region or the drain region have different doping types. A gate oxide layer covers the surfaces of the source region, the channel region, and the drain region; A gate layer, covering the surface of the gate oxide layer, and its orthogonal projection on the active pillar coincides with the channel region; The source region includes a first doped region and a first lightly doped region. The first lightly doped region is located between the channel region and the first doped region. The doped ion types of the first doped region and the first lightly doped region are the same, and the doped ion concentration of the first lightly doped region is less than that of the first doped region. The drain region includes a second doped region and a second lightly doped region. The second lightly doped region is located between the channel region and the second doped region. The doped ion types of the second doped region and the second lightly doped region are the same, and the doped ion concentration of the second lightly doped region is less than that of the second doped region.

2. The semiconductor structure according to claim 1, characterized in that, The first region includes a first sub-region and a second sub-region spaced apart along the extension direction of the active pillar. The first sub-region is distributed adjacent to the source region, and the second sub-region is distributed adjacent to the drain region. The boundary of the orthogonal projection of the gate layer on the active pillar coincides with the boundary of the first sub-region near the source region and the boundary of the second sub-region near the drain region.

3. The semiconductor structure according to claim 2, characterized in that, In a direction perpendicular to the extension direction of the active column, the cross-sections of both the first sub-region and the second sub-region are annular. Alternatively, the first sub-region is located between the second region and the source region; the second sub-region is located between the second region and the drain region.

4. The semiconductor structure according to claim 1, characterized in that, The source region and the drain region are both n-type doped, and the first region is p-type doped.

5. The semiconductor structure according to claim 1, characterized in that, The surface in the channel region located in the extension direction of the active column is curved.

6. A method for forming a semiconductor structure, characterized in that, include: An active pillar is formed, the active pillar including a source region, a channel region and a drain region distributed sequentially along the extension direction of the active pillar, the channel region including a first region and a second region distributed adjacent to each other, the first region being distributed adjacent to the source region and / or the drain region, and the first region and the source region and / or the drain region having different doping types. A gate oxide layer is formed covering the surfaces of the source region, the channel region, and the drain region; A gate layer is formed covering the surface of the gate oxide layer, wherein the orthogonal projection of the gate layer on the active pillar coincides with the channel region.

7. The forming method according to claim 6, characterized in that, The first region includes a first sub-region and a second sub-region spaced apart along the extension direction of the active pillar. The first sub-region is distributed adjacent to the source region, and the second sub-region is distributed adjacent to the drain region. The boundary of the orthogonal projection of the gate layer on the active pillar coincides with the boundary of the first sub-region near the source region and the boundary of the second sub-region near the drain region. The source region includes a first doped region and a first lightly doped region. The first lightly doped region is located between the channel region and the first doped region. The doped ion types of the first doped region and the first lightly doped region are the same, and the doped ion concentration of the first lightly doped region is less than that of the first doped region. The drain region includes a second doped region and a second lightly doped region. The second lightly doped region is located between the channel region and the second doped region. The doped ion types of the second doped region and the second lightly doped region are the same, and the doped ion concentration of the second lightly doped region is less than that of the second doped region.

8. The forming method according to claim 7, characterized in that, In a direction perpendicular to the extension direction of the active column, the cross-sections of both the first sub-region and the second sub-region are annular. Alternatively, the first sub-region is located between the second region and the source region; the second sub-region is located between the second region and the drain region.

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