An accumulation-type wide bandgap semiconductor trench MOSFET device structure and its preparation method

Abstract

The present invention specifically relates to an accumulation-type wide bandgap semiconductor trench MOSFET device structure and a method for preparing the same. The structure comprises at least a substrate, an epitaxial layer, a source P+ region, and a gate electrode; an N+ current channel is provided below the gate electrode trench, and N-accumulation-type channels and / or P-inversion channels are provided on both sides of the gate electrode trench. The N+ current channel is prepared by ion implantation and is located in the epitaxial layer. The N-accumulation-type channels and / or P-inversion channels are formed by the lateral diffusion effect during ion implantation of the N+ current channel. The present invention forms the N+ current channel through a trench bottom ion implantation process, and utilizes the lateral diffusion effect of this process during ion implantation to naturally form the N-accumulation-type channel and / or P-inversion channel. Furthermore, the channel doping concentration and thickness can be carefully controlled by controlling the mask thickness of the trench sidewalls during ion implantation of the N+ current channel, thereby achieving the purpose of enhancing channel mobility and reducing device on-resistance without the need for additional processes.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to an accumulation-type wide-bandgap semiconductor trench MOSFET device structure and a preparation method thereof. Background Art

[0002] There are still several problems in the actual process manufacturing and application of accumulation-type wide bandgap semiconductor trench MOSFET devices: (1) The inversion layer trench mobility used in traditional devices is low, the device on-resistance is large, and the production of the accumulation-type channel requires additional process steps. The use of additional ion implantation or epitaxial process will increase the complexity and cost of the device; (2) The high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the trench corners, causing the gate dielectric to quickly break down under high drain voltages, and the ability to withstand electrostatic effects in harsh environments and high-voltage spikes in the circuit is poor. Summary of the Invention

[0003] In order to solve at least one of the above technical problems, the present invention provides an accumulation-type wide bandgap semiconductor trench MOSFET device structure. In the process of forming an N+ current channel by ion implantation under the gate electrode, the lateral diffusion effect during ion implantation is utilized to naturally form an N-accumulation-type channel and / or a P-inversion channel on the outer side wall of the gate electrode trench. Without the need for additional processes, the purpose of enhancing the channel mobility and reducing the on-resistance of the device can be achieved, thereby greatly reducing the complexity and cost of the device.

[0004] The present invention adopts the following technical solutions to achieve the above technical objectives: an accumulation-mode wide bandgap semiconductor trench MOSFET device structure, comprising at least a substrate, an epitaxial layer epitaxially grown on the substrate, a source P+ region formed in the epitaxial layer, and gate electrodes formed on both sides of the source P+ region;

[0005] An N+ current channel is arranged directly below the gate electrode trench, and an N-accumulation channel and / or a P-inversion channel are arranged on both sides of the gate electrode trench. The N+ current channel is prepared by an ion implantation process at the bottom of the trench and is located in the epitaxial layer. The N-accumulation channel and / or the P-inversion channel are formed by the lateral diffusion effect during the ion implantation of the N+ current channel, and the N-accumulation channel and / or the P-inversion channel are adjacent to the outer side wall of the gate electrode trench.

[0006] As a preferred embodiment, the N-accumulation channel and the P-inversion channel are realized by controlling the mask thickness of the gate electrode trench sidewall during N+ current channel ion implantation.

[0007] As a preferred embodiment, the structure also includes a P+ shielding layer, which is located between the bottom of the gate electrode trench and the N+ current channel and is electrically connected to the source P+ region. The P+ shielding layer protects the gate electrode trench corners and improves device reliability.

[0008] As a preferred embodiment, the structure also includes a P+ buried layer and a P+ grounding column, the epitaxial layer includes an epitaxial layer one and an epitaxial layer two stacked in sequence, the P+ buried layer is located between the epitaxial layer one and the epitaxial layer two, the source P+ region is electrically connected to the P+ buried layer, the N+ current channel is formed in the P+ buried layer by ion implantation, and the P+ grounding column is used to electrically connect the P+ shielding layer and the P+ buried layer.

[0009] By constructing a P+ shielding layer, a P+ grounding column, a P+ buried layer, and an N+ current channel under the trench to form a deep shielding structure, the device can conduct current while providing better protection for the gate trench corners.

[0010] As a preferred embodiment, the structure also includes a P-well region and a source N+ region sequentially formed on the epitaxial layer, a source electrode formed on the source N+ region and the source P+ region, and a drain electrode formed on the back side of the substrate, the source P+ region is formed in the epitaxial layer and penetrates and electrically connects the P-well region and the source N+ region, and the source N+ region and the source P+ region form an ohmic contact with the source electrode.

[0011] As a preferred embodiment, the P-inversion channel is located in the P-well region near the sidewall of the gate electrode trench.

[0012] As a preferred embodiment, the bottom of the trench of the gate electrode is located in the epitaxial layer or the P-well region; and the P+ shielding layer is located in the epitaxial layer or the P-well region.

[0013] As a preferred embodiment, the trench sidewalls of the gate electrode are perpendicular or inclined to the upper surface of the epitaxial layer.

[0014] The present invention also provides a method for preparing the above-mentioned accumulation-mode wide bandgap semiconductor trench MOSFET device structure, comprising the following steps:

[0015] Epitaxially grow an epitaxial layer on the substrate, then form a P-well region through ion implantation, secondary epitaxy, and growth of a P-type oxide, and then form a source N+ region on the P-well region through ion implantation;

[0016] Further, a source P+ region penetrating the source N+ region and the P-well region is formed by ion implantation, and gate electrode trenches are formed on both sides of the source P+ region by dry etching;

[0017] An N+ current channel is formed in the epitaxial layer by ion implantation, and an N-accumulation channel and / or a P-inversion channel are naturally formed by utilizing the lateral diffusion effect;

[0018] Finally, the gate dielectric is grown, the gate polysilicon is grown and etched, the interlayer dielectric is deposited and etched, the source electrode is deposited and etched, and the drain electrode is deposited.

[0019] As a preferred embodiment, the following steps are also included: when epitaxially growing an epitaxial layer on a substrate, epitaxially growing an epitaxial layer 1, a P+ buried layer and an epitaxial layer in sequence, forming a P+ masking layer and a P+ grounding column at the bottom of the trench by P-type ion implantation; and ions are implanted into the P+ buried layer to form an N+ current channel.

[0020] The present invention forms an N+ current channel through a trench bottom ion implantation process, and utilizes the lateral diffusion effect of this process during ion implantation to naturally form an N-accumulation channel and / or a P-inversion channel. Furthermore, by controlling the mask thickness of the trench sidewalls during ion implantation of the N+ current channel, the channel doping concentration and thickness can be carefully regulated so that the channel is completely depleted by the built-in potential of the PN junction and the MOS gate under zero gate bias, thereby forming a normally-off device that can improve channel mobility and reduce device on-resistance. No additional process steps are required, reducing the complexity and cost of the device.

[0021] Furthermore, by constructing a P+ shielding layer, a P+ grounding column, a P+ buried layer, and an N+ current channel below the gate trench to form a deep shielding structure, the device can conduct current while providing better protection for the trench corners. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 7 Schematic diagrams of several structures of the accumulation-type wide bandgap semiconductor trench MOSFET device structure provided by the present invention;

[0023] Figure 8 Schematic diagram of the principle of forming an N- accumulation channel using N+ current channel ion implantation;

[0024] Figure 9 A cross-sectional view of forming an N- accumulation channel using N+ current channel ion implantation;

[0025] Figure 10 This is a process flow chart for preparing one of the accumulation-mode wide bandgap semiconductor trench MOSFET device structures described in the present invention;

[0026] Figure 11 Comparison of breakdown characteristics of devices with different channel types at different gate voltages;

[0027] Figure 12 Comparison of conduction characteristics of different types of channel devices;

[0028] Figure 13 Comparison of the breakdown characteristics of P-inversion channel and N-accumulation channel devices;

[0029] Figure 14 Comparison of conduction characteristics of P-inversion channel and N-accumulation channel devices under the same chip area conditions.

[0030] In the figure: 1 substrate, 2 epitaxial layer, 21 epitaxial layer 1, 22 epitaxial layer 2, 3P well region, 4 source N+ region, 5 source electrode, 6 drain electrode, 7P+ masking layer, 8N+ current channel, 9N- accumulation channel, 10 source P+ region, 11P+ grounding column, 12 source ohmic contact region, 13 gate electrode, 14P- inversion channel, 15P+ buried layer. DETAILED DESCRIPTION

[0031] The present invention will be further described in detail below with reference to specific embodiments so that those skilled in the art can understand the present invention more clearly.

[0032] The following embodiments are only used to illustrate the present invention, but are not used to limit the scope of the present invention. Based on the specific embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0033] It will be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be understood that in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other element will be oriented as "on" the other element or feature. Therefore, the exemplary terms "on the front side of" and "on the back side of" are only used to define two opposite sides. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In the following embodiments, "connection" should be understood as "electrical connection", "communication connection", etc., if the connected circuits, modules, units, etc. can transmit electrical signals or data to each other.

[0035] like Figures 1 to 7As shown, an accumulation-mode wide bandgap semiconductor trench MOSFET device structure at least includes a substrate 1, an epitaxial layer 2 epitaxially grown on the substrate 1, a source P+ region 10 made in the epitaxial layer 2, and gate electrodes 13 made on both sides of the source P+ region 10.

[0036] An N+ current channel 8 is arranged directly below the gate electrode 13 trench, and an N-accumulation channel 9 and / or a P-inversion channel 14 are arranged on both sides of the gate electrode 13 trench, wherein the N+ current channel 8 is prepared by an ion implantation process at the bottom of the trench and is located in the epitaxial layer 2, and the N-accumulation channel 9 and the P-inversion channel 14 are formed by the lateral diffusion effect during the ion implantation of the N+ current channel 8, and the N-accumulation channel 9 and the P-inversion channel 14 are both adjacent to the outer side wall of the gate electrode 13 trench.

[0037] It is understood that before ion implantation to form the N+ current channel 8, a mask layer needs to be made inside the gate electrode 13 trench. By controlling the thickness of the trench sidewall mask, the lateral diffusion effect can be controlled. For details, see Figure 8 、 9 .

[0038] When the thickness of the gate electrode 13 trench sidewall mask is relatively thick, the lateral diffusion effect of the N+ current channel 8 during ion implantation is reduced, thereby reducing the channel concentration of the P-well region close to the gate dielectric layer, and naturally forming a P-inversion channel 14, that is, the P-inversion trench 14 is located in the P-well region close to the gate electrode 13 trench sidewall position, for details, see Figure 3 By adjusting the doping and thickness of the P-inversion channel, the threshold voltage and on-resistance of the device can be controlled. When the thickness of the gate electrode 13 trench sidewall mask is thin, the lateral diffusion effect of the N+ current channel ion implantation is increased, thereby naturally forming an N+ accumulation channel 9, forming a normally-on device. Figure 4 , the normally-on device has a large leakage current under zero gate voltage, and the device can be turned off under -20V gate voltage. The breakdown voltage is basically the same as that of the normally-on device. The normally-on device has a high channel mobility and a higher current conduction capability than the normally-off device, and a lower specific on-resistance. See Figure 11 、 Figure 12 .

[0039] The device structure obtained when the thickness of the gate electrode 13 trench sidewall mask is uniform is as described above. When the thickness of the gate electrode 13 trench sidewall mask is unevenly distributed, a portion of the channel can form a P-inversion channel 14, and another portion of the channel can form an N-accumulation channel 9, naturally forming a short channel device, which can reduce the device channel resistance. Figure 2 、 Figure 5 、 Figure 7 .

[0040] It can also be understood that when the gate electrode trench formed by dry etching has a certain angle, an N-accumulation type channel 9 and / or a P-inversion type channel 14 with a certain angle can also be formed. That is, in the present invention, the trench sidewall of the gate electrode 13 can be perpendicular to the upper surface of the epitaxial layer 2 or inclined to the upper surface of the epitaxial layer 2 at a certain angle. Correspondingly, the N-accumulation type channel 9 and / or the P-inversion type channel 14 are also perpendicular or have a certain angle. For details, please refer to Figure 2 、 Figure 5 、 Figure 6 、 Figure 7 .

[0041] The present invention forms an N+ current channel through an ion implantation process at the bottom of the trench, and simultaneously utilizes the lateral diffusion effect of this process during ion implantation to naturally form an N-accumulation channel and / or a P-inversion trench 14. Furthermore, by controlling the mask thickness of the trench sidewall during ion implantation of the N+ current channel, the channel doping and thickness can be carefully regulated so that the channel is completely depleted by the built-in potential of the PN junction and the MOS gate under zero gate bias, thereby forming a normally-off device that can improve channel mobility and reduce device on-resistance, and does not require additional process steps, thereby reducing the complexity and cost of the device.

[0042] Furthermore, the accumulation-mode wide bandgap semiconductor trench MOSFET device structure further includes a P+ shielding layer 7 , which is located between the bottom of the gate electrode 13 trench and the N+ current channel 8 and is electrically connected to the source P+ region 10 .

[0043] It is understood that the distance between the P+ shielding layer 7 and the bottom of the gate electrode 13 can be greater than 0, equal to 0, or less than 0. When the distance is less than 0, the P+ shielding layer 7 covers the bottom of the trench. In this application, it is preferably equal to 0.

[0044] Furthermore, it also includes a P+ buried layer 15 and a P+ grounding column 11. The epitaxial layer two includes an epitaxial layer 1 21 and an epitaxial layer 2 22 stacked in sequence. The P+ buried layer 15 is located between the epitaxial layer 1 21 and the epitaxial layer 2 22. The source P+ region 10 is electrically connected to the P+ buried layer 15. The N+ current channel 8 is formed by ion implantation into the P+ buried layer 15. The P+ grounding column 11 is used to electrically connect the P+ shielding layer 7 and the P+ buried layer 15, thereby realizing the grounding of the P+ shielding layer 7.

[0045] It is understood that the N+ current channel 8 can adopt a plurality of square-shaped structures or a rectangular structure with the same length as the gate electrode 13 trench. Among them, the plurality of square-shaped structures are preferred. In this case, one end of the P+ grounding column 11 is connected to the P+ shielding layer 7, and the other end is connected to the P+ buried layer 15 between the square-shaped structures, which is relatively simple to manufacture. In this case, the N-accumulation channel 9 and / or the P-inversion channel 14 also have a corresponding spacer structure.

[0046] It can also be understood that the source P+ region 10 can be electrically connected to the P+ buried layer 15 in the following manner: when the source P+ region 10 is prepared by ion implantation, it is directly implanted into the contact P+ buried layer 15, or is otherwise connected through a terminal or the like.

[0047] Furthermore, it also includes a P-well region 3 and a source N+ region 4 formed on the epitaxial layer 2, a source electrode 5 formed on the source N+ region 4 and the source P+ region 10, and a drain electrode 6 formed on the back side of the substrate 1. The source P+ region is formed in the epitaxial layer 2 and penetrates and electrically connects the P-well region 3 and the source N+ region 4. The source N+ region 4 and the source P+ region 10 form an ohmic contact with the source electrode 5 through the source ohmic contact region 12.

[0048] That is, the P+ shielding layer 7, P+ grounding column 11, P+ buried layer 15, and N+ current channel 8 form a deep shielding structure, allowing the device to conduct current while also providing good protection for the gate electrode corners. By forming an ohmic contact at the source, the source N+ region 4, source P+ region 10, P+ buried layer 15, P+ grounding column 11, and P+ shielding layer 7 are short-circuited together.

[0049] Furthermore, the bottom of the trench of the gate electrode 13 is located in the epitaxial layer 2 or the P-well region 3, and the P+ shielding layer 7 can be located in either the epitaxial layer 2 or the P-well region 3. For details, see Figure 2 and Figure 7 .

[0050] See also Figure 2 When there is no P+ buried layer, a deeper P-well region 3 is injected, and at the same time, a deeper source P+ region is injected to form a current expansion layer at the bottom of the trench. At the same time, the uneven distribution of the trench sidewall mask is used to naturally form a short channel device, thereby reducing the device channel resistance. Moreover, the deeper P-well region 3 and the source P+ region 10 can better protect the gate groove corner and improve device reliability.

[0051] See also Figure 7 , injecting a deeper P-well region 3, and at the same time using the uneven distribution of the trench sidewall mask to naturally form a short channel device, reducing the device channel resistance, and at the same time using the deeper P-well region 3 to better protect the gate groove corner and improve device reliability.

[0052] The present invention also provides a method for preparing the above-mentioned accumulation-mode wide bandgap semiconductor trench MOSFET device structure, comprising the following steps:

[0053] An epitaxial layer 2 is epitaxially grown on a substrate 1 (a wide bandgap semiconductor material such as SiC, GaN, Ga2O3, C, or AlN), and then a P-type oxide is grown to form a P-well region 3 by ion implantation, secondary epitaxy, and further a source N+ region 4 is formed on the P-well region 3 by ion implantation.

[0054] Further, a source P+ region 10 is formed by ion implantation, penetrating the source N+ region 4 and the P-well region 3, and trenches for the gate electrode 13 are formed by dry etching on both sides of the source P+ region 10;

[0055] After making a mask on the trench sidewalls, an N+ current channel 8 is formed in the epitaxial layer 2 by ion implantation, and an N- accumulation channel 9 and / or a P- inversion channel 14 are naturally formed by utilizing the lateral diffusion effect;

[0056] Finally, gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, source electrode deposition and etching, drain electrode deposition, and the prepared structure is as follows: Figure 2 shown.

[0057] Furthermore, the present invention further includes the following steps: when epitaxially growing the epitaxial layer 2 on the substrate 1, epitaxially growing the epitaxial layer 21, the P+ buried layer 15 and the epitaxial layer 22 in sequence, forming the P+ masking layer 7 and the P+ grounding column 11 at the bottom of the trench by P ion implantation, and implanting ions into the P+ buried layer 15 to form the N+ current channel 8, and the obtained structure is as follows: Figure 1 shown.

[0058] The present invention is described in more detail below using a specific case. The specific preparation process is as follows: Figure 12 As shown:

[0059] (1) (Cross-section A) An N-epitaxial layer 1 is grown on a substrate 1 made of a wide bandgap semiconductor material (SiC, GaN, Ga2O3, C, AlN, etc.);

[0060] (2) (Section A) Growth of a P+ buried layer on the N- epitaxial layer;

[0061] (3) (Section A) Growth of N-epitaxial layer 2 on the P+ buried layer;

[0062] (4) (Section A) A P-well region is formed by ion implantation, secondary epitaxy, and growth of a P-type oxide, and a source N+ region is formed by ion implantation;

[0063] (5) (Section A) Forming the source P+ region by ion implantation;

[0064] (6) (Section A) Dry etching to form a gate trench;

[0065] (7) (Section A) Forming a P+ masking layer by P-type ion implantation;

[0066] (8) (Cross-section A) N+ current channel is formed by N-type ion implantation, while N- accumulation channel is naturally formed by lateral diffusion effect;

[0067] (9) (Section B) P+ grounding pillars are formed by P-type ion implantation;

[0068] (10) (Section A) Gate electrode dielectric growth, gate polysilicon growth and etching, interlayer dielectric deposition and etching, gate electrode deposition and etching, drain electrode deposition.

[0069] The structure prepared by the above preparation method is as follows Figure 1 This structure forms a deep shielding structure by constructing a P+ shielding layer 7, a P+ grounding column 11, a P+ buried layer 15, and an N+ current channel 8 below the gate trench. This allows the device to conduct current while providing relatively good protection for the gate trench corners. An ohmic contact is formed at the source, shorting the source N+ region 3, the source P+ region 10, the P+ buried layer 15, the P+ grounding column 11, and the P+ shielding layer 7 together. An N+ current channel 8 is formed by an ion implantation process at the bottom of the trench. The lateral diffusion effect of this process during ion implantation naturally forms an N-accumulation channel 9. The doping and thickness of the N-accumulation channel can be carefully controlled by the thickness of the sidewall mask so that it is completely depleted by the built-in potential of the PN junction and the MOS gate under zero gate bias, thereby forming a normally-off device that can improve channel mobility and reduce device on-resistance. The above structure has at least the following advantages:

[0070] First, the deep masking structure can better protect the corners of the gate electrode trench, reduce the gate oxide electric field strength, and improve the reliability of the device;

[0071] Second, the ion implantation process at the bottom of the trench forms an N+ current channel. The lateral diffusion of the ion implantation can be controlled by the trench sidewall mask process, thereby naturally forming an N- accumulation channel, enhancing the channel mobility, and reducing the on-resistance of the device. No additional process steps are required, reducing the complexity and cost of the device.

[0072] Third, devices with N-accumulation channels can be turned off at zero gate voltage, with the breakdown voltage remaining the same as that of P-inversion channels, see Figure 13 ; Under the same chip area, the conduction capability of accumulation trench MOSFET devices is better than that of P-inversion channel devices, see Figure 14 By regulating the N-accumulation channel doping and thickness, a normally-off device with high channel mobility and low on-resistance can be formed.

[0073] It is important to note that the above embodiments are intended only to further illustrate and describe the technical solutions of the present invention and are not intended to further limit the technical solutions of the present invention. The methods of the present invention are merely preferred implementations and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. An accumulation-mode wide bandgap semiconductor trench MOSFET device structure, characterized in that: The device comprises at least a substrate (1), an epitaxial layer (2) epitaxially grown on the substrate (1), a source P+ region (10) formed in the epitaxial layer (2), and gate electrodes (13) formed on both sides of the source P+ region (10); An N+ current channel (8) is provided directly below the gate electrode (13) trench, and an N-accumulation channel (9) and / or a P-inversion channel (14) are provided on both sides of the gate electrode (13) trench. The N+ current channel (8) is prepared by an ion implantation process at the bottom of the trench and is located in the epitaxial layer (2). The N-accumulation channel (9) and the P-inversion channel (14) are formed by a lateral diffusion effect during ion implantation of the N+ current channel (8). The N-accumulation channel (9) and the P-inversion channel (14) are realized by controlling the mask thickness of the sidewall of the gate electrode (13) trench during ion implantation of the N+ current channel (8), and the N-accumulation channel (9) and / or the P-inversion channel (14) are adjacent to the outer sidewall of the gate electrode (13) trench.

2. The accumulation-mode wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: It also includes a P+ shielding layer (7), which is located between the bottom of the gate electrode (13) trench and the N+ current channel (8), and is electrically connected to the source P+ region (10).

3. The accumulation-mode wide bandgap semiconductor trench MOSFET device structure according to claim 2, characterized in that: The invention also includes a P+ buried layer (15) and a P+ grounding column (11); the epitaxial layer includes an epitaxial layer 1 (21) and an epitaxial layer 2 (22) stacked in sequence; the P+ buried layer (15) is located between the epitaxial layer 1 (21) and the epitaxial layer 2 (22); the source P+ region (10) is electrically connected to the P+ buried layer (15); the N+ current channel (8) is formed by ion implantation into the P+ buried layer (15); and the P+ grounding column (11) is used to electrically connect the P+ shielding layer (7) and the P+ buried layer (15).

4. The accumulation-mode wide bandgap semiconductor trench MOSFET device structure according to claim 3, characterized in that: The invention also includes a P-well region (3) and a source N+ region (4) sequentially formed on the epitaxial layer (2), a source electrode (5) formed on the source N+ region (4) and the source P+ region (10), and a drain electrode (6) formed on the back side of the substrate (1); the source P+ region (10) is formed in the epitaxial layer (2) and penetrates and electrically connects the P-well region (3) and the source N+ region (4); the source N+ region (4) and the source P+ region (10) form an ohmic contact with the source electrode (5).

5. The accumulation-mode wide bandgap semiconductor trench MOSFET device structure according to claim 4, characterized in that: The P-inversion channel (14) is located in the P well region near the side wall of the gate electrode (13) trench.

6. The accumulation-mode wide bandgap semiconductor trench MOSFET device structure according to claim 4, characterized in that: The bottom of the trench of the gate electrode (13) is located in the epitaxial layer (2) or the P-well region (3); and the P+ shielding layer (7) is located in the epitaxial layer (2) or the P-well region (3).

7. The accumulation-mode wide bandgap semiconductor trench MOSFET device structure according to claim 1, characterized in that: The trench sidewall of the gate electrode (13) is perpendicular or inclined to the upper surface of the epitaxial layer (2).

8. The method for preparing an accumulation-mode wide bandgap semiconductor trench MOSFET device structure according to any one of claims 1 to 7, characterized in that: The following steps are involved: Epitaxially growing an epitaxial layer (2) on a substrate (1), then forming a P-well region (3) by ion implantation, secondary epitaxy, and growing a P-type oxide, and then forming a source N+ region (4) on the P-well region (3) by ion implantation; Further, a source P+ region (10) penetrating the source N+ region (4) and the P-well region (3) is formed by ion implantation, and gate electrode (13) grooves are formed by dry etching on both sides of the source P+ region (10); An N+ current channel (8) is formed in the epitaxial layer (2) by ion implantation, and an N-accumulation channel (9) and / or a P-inversion channel (14) are naturally formed by utilizing a lateral diffusion effect; Finally, the gate dielectric is grown, the gate polysilicon is grown and etched, the interlayer dielectric is deposited and etched, the source electrode is deposited and etched, and the drain electrode is deposited.

9. The preparation method according to claim 8, characterized in that The following steps are also included: When epitaxially growing an epitaxial layer (2) on a substrate (1), an epitaxial layer 1 (21), a P+ buried layer (15) and an epitaxial layer 2 (22) are epitaxially grown in sequence, a P+ masking layer (7) and a P+ grounding column (11) are formed at the bottom of a trench by P-type ion implantation, and ions are implanted into the P+ buried layer (15) to form an N+ current channel (8).

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