Method and system for common-mode resonance suppression in high efficiency modulation mode of three-level inverter

Abstract

The application discloses a common-mode resonance suppression method and system of a three-level inverter under a high-efficiency modulation mode, and comprises the following steps: obtaining low-frequency and medium-frequency component information of three-phase bridge arm output currents of the three-level inverter, and obtaining corresponding d-axis components, q-axis components and common-mode components through coordinate transformation; when performing differential-mode control, the d-axis components and the q-axis components enter a differential-mode current controller for differential-mode current control, and the output of the differential-mode current controller is subjected to coordinate transformation to obtain three-phase sinusoidal modulation waves; based on the three-phase sinusoidal modulation waves, a clamping phase and a non-clamping phase in the three phases are determined; when performing common-mode suppression, the common-mode components are sent into a common-mode resonance suppression link to obtain a common-mode control quantity; the common-mode control quantity is injected into the non-clamping phase to obtain a final three-phase modulation wave, and then a driving signal of a switching device is obtained, so that the three-level inverter is controlled. The application can eliminate the influence of switching frequency components and multiple frequency components, and improve sampling precision.

Description

Technical Field

[0001] This invention relates to the field of power electronic control technology, and in particular to a common-mode resonance suppression method and system for a three-level inverter under high-efficiency modulation mode. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] Inverters play a crucial role as the interface for converting DC to AC power. Three-level inverter topologies, due to their combination of simplicity and low output harmonics, are widely used in photovoltaic power generation, motor drives, and microgrid systems. In particular, the ability of three-level inverters to control the DC-side neutral point potential allows for easy integration with improved LCL filters, effectively suppressing leakage current in non-isolated systems. Three-level inverters employing improved LCL filters have seen extensive application in photovoltaic power generation and motor control, generating significant economic benefits.

[0004] On the other hand, conversion efficiency is one of the important indicators for measuring inverter performance. From the perspective of energy conservation, improving conversion efficiency can reduce energy loss during AC-DC conversion, improve energy utilization, and save valuable natural resources. From the perspective of the inverter's own operation, low conversion efficiency means increased system losses. Since this energy is ultimately dissipated as heat, low efficiency will cause severe overheating of components, reducing system reliability and lifespan. Attempting to improve heat dissipation performance will further increase system costs.

[0005] To improve inverter efficiency, event-triggered current control or discontinuous pulse width modulation (DPWM) methods can be employed. DPWM is a high-efficiency modulation mode that reduces switching losses by keeping devices in a normally on or normally off state for a period of time, and it is widely used in engineering. However, when DPWM is applied to improved LCL filters, it can cause severe common-mode resonance problems, leading to increased losses and even damage to inverter switching devices and filter components, endangering equipment safety. Therefore, research and solutions to this problem are of great significance.

[0006] There are various implementation methods for DPWM, including common ones such as DPWM1, DPWM2, DPWM3, DPWMA, DPWMMAX, and DPWMMIN. However, DPWM1, DPWM2, and DPWM3 methods require a discontinuous zero-sequence voltage injection, which can exacerbate common-mode resonance problems in improved three-level LCL filter topologies. DPWMMAX and DPWMMIN methods require either a consistently negative or consistently positive zero-sequence voltage injection, which is detrimental to midpoint balance control in three-level inverters. The DPWMA method, on the other hand, requires a continuous zero-sequence voltage injection with alternating positive and negative values, making it more suitable for the aforementioned improved three-level LCL filter topologies.

[0007] However, the derivative of the zero-sequence voltage in the DPWMA method is not continuous. Studies show that the transfer function from the zero-sequence voltage derivative to the common-mode current approximates an underdamped second-order system, thus the common-mode resonance problem persists. To overcome this deficiency, various methods for improving the zero-sequence voltage have been proposed in the literature. These methods aim to smooth the zero-sequence voltage, reduce its harmonic content, and thereby lower the common-mode resonant current. However, a common drawback of these methods is that they reduce the clamping time of the DPWMA method, leading to increased system losses. Summary of the Invention

[0008] To address the aforementioned issues, this invention proposes a common-mode resonance suppression method and system for a three-level inverter under high-efficiency modulation mode. This method achieves common-mode resonance suppression in non-isolated three-level inverters while maintaining the power consumption reduction effect of the high-efficiency modulation mode. By introducing common-mode current feedback control to suppress common-mode resonance, a lead compensation stage is introduced into the control loop to compensate for filtering delay, calculation delay, and PWM delay, ensuring the system has a large phase margin and good stability. To avoid affecting the power consumption reduction effect of the discontinuous modulation mode, the clamped phase remains unchanged during common-mode control injection, and the common-mode control is only injected into the unclamped two-phase modulation wave, thus ensuring that the clamping time of the switching devices remains constant.

[0009] In some implementations, the following technical solutions are adopted:

[0010] A common-mode resonance suppression method in a three-level inverter under high-efficiency modulation mode includes:

[0011] The output current of the three-phase bridge arm of the three-level inverter is sampled at a set frequency;

[0012] The sampled current is digitally filtered to obtain the low-frequency and mid-frequency components of the current.

[0013] Perform abc / dq0 coordinate transformation on the low-frequency and mid-frequency components to obtain the corresponding d-axis components, q-axis components and common-mode components, respectively.

[0014] During differential mode control, the d-axis and q-axis components are fed into the differential mode current controller for differential mode current control. The output of the differential mode current controller is transformed by dq / abc coordinates to obtain a three-phase sinusoidal modulation wave. Based on the three-phase sinusoidal modulation wave, the clamped and unclamped phases in the three phases are determined.

[0015] When performing common-mode suppression, the common-mode component is fed into the common-mode resonance suppression circuit to obtain the common-mode control quantity;

[0016] The common-mode control signal is injected into the non-clamped phase to obtain the final three-phase modulation wave, which in turn generates the drive signal for the switching devices, thereby enabling control of the three-level inverter.

[0017] Specifically, the output current of the three-phase bridge arm of the three-level inverter is sampled as follows:

[0018] Within one switching cycle, the output current of the three-phase bridge arm of the three-level inverter is sampled N times.

[0019] The design bandwidth of the differential mode current controller is no higher than 1 / 2 of the common mode resonant frequency.

[0020] The common-mode resonance suppression circuit includes a proportional circuit and a lead compensation circuit connected in sequence.

[0021] The clamped and unclamped phases in the three-phase system are determined based on the three-phase sinusoidal modulation wave, specifically as follows:

[0022] For each three-phase sinusoidal modulation wave, the zero-sequence component required to be injected when it is clamped in the three states of P, O, and N is calculated, and the zero-sequence component with the smallest absolute value for each phase is determined.

[0023] The zero-sequence components with the smallest absolute values ​​of the three phases are compared. The phase corresponding to the zero-sequence component with the smallest absolute value among the three phases is taken as the final clamped phase, and the other phases are unclamped phases.

[0024] In other embodiments, the following technical solutions are adopted:

[0025] A common-mode resonance suppression system for a three-level inverter in a high-efficiency modulation mode includes:

[0026] The data acquisition module is used to sample the output current of the three-phase bridge arm of the three-level inverter at a set frequency;

[0027] The data filtering module is used to perform digital filtering on the sampled current to obtain the low-frequency and mid-frequency components of the current.

[0028] The coordinate transformation module is used to perform abc / dq0 coordinate transformation on the low-frequency and mid-frequency components to obtain the corresponding d-axis components, q-axis components and common-mode components, respectively.

[0029] The differential mode control module is used to input the d-axis and q-axis components into the differential mode current controller for differential mode current control during differential mode control. The output of the differential mode current controller is transformed into a three-phase sinusoidal modulation wave after dq / abc coordinate transformation. Based on the three-phase sinusoidal modulation wave, the clamped and unclamped phases in the three phases are determined.

[0030] The common-mode rejection module is used to send the common-mode component into the common-mode resonance rejection circuit to obtain the common-mode control quantity during common-mode rejection.

[0031] The inverter control module is used to inject common-mode control signals into the non-clamped phase to obtain the final three-phase modulation wave, and then obtain the drive signals for the switching devices to achieve control of the three-level inverter.

[0032] In other embodiments, the following technical solutions are adopted:

[0033] A terminal device includes a processor and a memory, the processor being used to implement instructions; the memory being used to store multiple instructions, the instructions being adapted to be loaded and executed by the processor to perform the common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described above.

[0034] In other embodiments, the following technical solutions are adopted:

[0035] A computer-readable storage medium storing a plurality of instructions adapted for loading and execution by a processor of a terminal device of the aforementioned common-mode resonance suppression method in a high-efficiency modulation mode of a three-level inverter.

[0036] Compared with the prior art, the beneficial effects of the present invention are:

[0037] (1) The current sampling method in this invention is to sample the three-phase current N times within one switching cycle and then perform digital filtering on it, which can eliminate the influence of the switching frequency component and its multiple frequency components and improve the sampling accuracy.

[0038] When performing differential mode control and common mode suppression, the data obtained at the most recent sampling time is selected to reduce the computation delay.

[0039] (2) In this invention, the clamped phase and the non-clamped phase are recorded when DPWMA control is performed. The common mode control quantity is only injected into the non-clamped phase, which can ensure that the clamping time of the DPWMA method remains unchanged, thereby ensuring high system efficiency.

[0040] Other features and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the T-type three-level non-isolated photovoltaic inverter system structure based on an improved LCL filter in an embodiment of the present invention;

[0042] Figure 2 This is a schematic diagram of the equivalent circuit of the common-mode loop in an embodiment of the present invention;

[0043] Figure 3 The zero-sequence voltage u in this embodiment of the invention zo u zo Derivative and common-mode current i z1 A waveform diagram;

[0044] Figure 4 This is an overall control block diagram of the photovoltaic inverter system in an embodiment of the present invention;

[0045] Figure 5 This is a timing diagram of common-mode current update and common-mode controller execution in an embodiment of the present invention;

[0046] Figures 6(a)-(c) show the DC side voltage U. dc The common-mode resonant current suppression effect at 580V, 650V and 750V;

[0047] Figures 7(a) and (b) show the transient control waveforms when given a sudden change in active current and a sudden change in reactive current, respectively. Detailed Implementation

[0048] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0049] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0050] Example 1

[0051] In one or more embodiments, a common-mode resonance suppression method for a three-level inverter under high-efficiency modulation mode is disclosed; the main circuit topology to which this method is applicable is a T-type three-level inverter, an I-type three-level inverter, and an active clamped three-level inverter. Figure 1The image shows an example of a non-isolated photovoltaic power generation system using a T-type three-level inverter. The system includes a DC unit, DC-side supporting capacitors C1 and C2, a T-type three-level power topology, an improved LCL filter, and an AC grid. The DC-side voltage is U. dc The common point n1 of the AC filter capacitors is connected to the connection point O of capacitors C1 and C2 to form an improved LCL filter.

[0052] Figure 2 The diagram shows the equivalent circuit of the common-mode loop in the above system. Considering the effects of the common-mode choke and line impedance in the actual system, the system leakage current i lk Much smaller than the return current i no Therefore, the zero-sequence voltage u of the system zo to common-mode current i z1 The transfer function can be approximated as:

[0053]

[0054] And zero-sequence voltage u zo The derivative of the common-mode current i z1 The transfer function can be approximated as:

[0055]

[0056] Because the equivalent resistance R1 of the circuit is small, the poles of the two transfer functions mentioned above are very close to the imaginary axis of the complex plane, thus easily generating common-mode resonance. It can be seen that not only the zero-sequence voltage u... zo Sudden changes in the derivative can easily trigger common-mode resonant current, and sudden changes in its derivative can also trigger common-mode resonant current.

[0057] Figure 3 The figure shows a DC voltage U with a modulation index of 1.05. dc The zero-sequence voltage u of the DPWMA method at 630V zo u zo Derivative and common-mode current i z1 The response waveform shows that, under the condition that the zero-sequence voltage is continuous but its derivative has a sudden change, the amplitude of the common-mode resonant current is still very large.

[0058] Figure 4 This is a block diagram of the overall control of the photovoltaic inverter system in an embodiment of the present invention. Wherein, i a1 i b1 i c1 The inverter bridge arm output current is obtained after hardware filtering, i. 1_pf After digital filtering, i is obtained. 1_ma i dq i represents the d-axis and q-axis current components. z1 For the common-mode current component, and iz1 =i a1 +i b1 +i c1 ;I ref The differential mode current is given by u. fa u fb u fc This refers to the voltage of the AC filter capacitor; m dq For differential controller output; m abc It is a three-phase sinusoidal modulated wave; m abc_D To achieve the three-phase modulated waveform after the DPWMA strategy; m0 is the common-mode control quantity; m abc_L This is the final three-phase modulated wave, used to determine the on and off states of the switching devices.

[0059] Combination Figure 4 The method in this embodiment specifically includes the following processes:

[0060] (1) Sample the output current of the three-phase bridge arm of the three-level inverter at a set frequency;

[0061] In this embodiment, the inverter bridge arm output current i a1 i b1 i c1 Sampling is performed at a frequency N times the switching frequency, where N = 16. Simultaneously, appropriate RC filters are incorporated into the hardware sampling conditioning circuit to reduce external noise interference and improve sampling accuracy.

[0062] (2) The sampled current is digitally filtered to obtain the low-frequency and mid-frequency components of the current;

[0063] Specifically, the sampled current is digitally filtered. Digital filtering methods can include moving average filters, improved repetitive filters, etc., which can eliminate the ripple of the sampled current at the switching frequency and its multiples, and obtain the low-frequency and mid-frequency components of the current.

[0064] The discretization implementation methods for the moving average filter and the improved repetitive filter are as follows:

[0065]

[0066]

[0067] (3) Perform abc / dq0 coordinate transformation on the low-frequency and mid-frequency components to obtain the corresponding d-axis components, q-axis components and common-mode components respectively;

[0068] In this embodiment, the low-frequency component and the mid-frequency component information are transformed by abc / dq0 coordinates to obtain the corresponding d-axis component, q-axis component and common-mode component, wherein the d-axis and q-axis components are defined as differential-mode components.

[0069] (4) When performing differential mode control, the d-axis component and the q-axis component enter the differential mode current controller for differential mode current control. The output of the differential mode current controller is transformed by dq / abc coordinates to obtain a three-phase sinusoidal modulation wave. Based on the three-phase sinusoidal modulation wave, the clamped phase and the non-clamped phase in the three phases are determined.

[0070] First, it should be noted that because differential mode control and common mode suppression have different timings, the sampling data used by them also differs. For example, differential mode control uses the d-axis and q-axis components obtained by processing the 9th sample data in the first sampling period through steps (1), (2), and (3) above; while common mode suppression uses the common mode component obtained by processing the 10th sample data in the first sampling period through steps (1), (2), and (3) above. This reduces the computational delay, and the update time is similar to the execution time of the common mode resonance suppression stage. Figure 5 As shown.

[0071] In this embodiment, the differential mode current controller mainly includes a current PI regulator section and an AC filter capacitor voltage feedforward section. The current PI regulator section is used to eliminate current tracking steady-state error and improve differential mode current response speed. Its control loop design bandwidth is no higher than 1 / 2 of the common mode resonant frequency. The AC filter capacitor voltage feedforward section is used to compensate for disturbances caused by grid voltage.

[0072] In this embodiment, based on the obtained three-phase sinusoidal modulation wave m a m b m c Implement the DPWMA modulation algorithm and record the clamped and unclamped phases.

[0073] First, the clamping states of each of the three-phase modulation waves are determined. For example, for the A-phase modulation wave, the zero-sequence components required for clamping in the P, O, and N states are calculated, and the zero-sequence component with the smallest absolute value is recorded. The same process is performed for phases B and C. Then, the absolute values ​​of the smallest zero-sequence components of phases A, B, and C are compared. The zero-sequence component with the smallest absolute value among the three phases corresponds to the final clamped phase, and the zero-sequence component of the final clamped phase is the final zero-sequence component.

[0074] In this embodiment, the clamped phase and the unclamped phase are recorded to facilitate the implementation of the proposed common-mode control injection method.

[0075] (5) When performing common-mode resonance suppression, the common-mode component is fed into the common-mode resonance suppression circuit to obtain the common-mode control quantity;

[0076] In this embodiment, the common-mode resonance suppression circuit includes a proportional circuit and a lead compensation circuit connected in sequence.

[0077] The proportional gain stage is primarily used for system bandwidth design, while the lead compensation stage is mainly used to increase system stability margin and perform low-frequency filtering. The main delays in the common-mode resonance suppression circuit include hardware filtering delay, digital filtering delay, calculation delay, and PWM delay. Since the common-mode resonant frequency in practical applications is generally in the range of 2kHz to 4kHz, these delays have a significant impact on the system stability margin. Compensating for these delays using the lead characteristic of the lead compensation stage can effectively improve the system's phase margin, enabling the system to resist the effects of parameter perturbations. Furthermore, the lead compensation stage has low gain at low frequencies, thus reducing the amplitude of the low-frequency common-mode current after passing through this stage, effectively preventing it from participating in the common-mode circuit regulation and reducing the control burden on the common-mode controller.

[0078] The parameters of the proportional element and the lead compensation element are derived and calculated based on the given system bandwidth, phase margin, and DC voltage.

[0079] The transfer function of the advance compensation stage is:

[0080]

[0081] in,

[0082] This embodiment specifies a fixed DC voltage U. dc0 Based on this, the desired system bandwidth and crossover frequency ω are obtained by adjusting the gain k1. c k1 is obtained by solving the following equation:

[0083]

[0084] In the formula, F hw (s) is the transfer function of the hardware filter circuit, F df (s) is the continuous transfer function expression of the digital filter, T d Calculate the sum of the delay and PWM delay for the controller.

[0085] Then based on the desired phase margin θ p Calculate the maximum lead angle of the lead compensation stage. and the corresponding angular frequency ω m :

[0086]

[0087] ω m =ω c (8)

[0088] In the formula G o (s) is the open-loop transfer function of the common-mode loop, and its expression is:

[0089]

[0090] The coefficients a and T are determined based on the characteristic parameters of the lead element. At the same time, another gain k2 is introduced to ensure that the original crossover frequency and phase margin remain unchanged.

[0091]

[0092] Among them, F lead (jω c ) is F lead (s) in s=jω c The value at that location.

[0093] Finally, it was determined that in U dc0 The proportionality coefficient K under the condition p0 and the proportional coefficient K of the proportional element p The adaptive law:

[0094] K p0 =k1k2 (11)

[0095]

[0096] Among them, K p This refers to the proportional coefficient of the proportional element.

[0097] (6) Inject the common-mode control quantity into the non-clamped phase to obtain the final three-phase modulation wave, and then obtain the drive signal of the switching device to realize the control of the three-level inverter.

[0098] Specifically, if the clamping phase is phase A (i.e., phase A is in the clamped state), then the common-mode control quantity is injected into phases B and C; if the clamping phase is phase B, then the common-mode control quantity is injected into phases A and C; and if the clamping phase is phase C, then the common-mode control quantity is injected into phases A and B. This common-mode control quantity injection method ensures that the clamping time of the DPWMA method remains constant, thereby guaranteeing high system efficiency.

[0099] Finally, the three-phase modulation waves A, B, and C are obtained and sent to the PWM module of the DSP for carrier comparison to obtain the drive signal for the switching device, thereby realizing the control of the three-level inverter.

[0100] Figures 6(a)-(c) show the DC side voltage U. dc The common-mode resonant current suppression effect at 580V, 650V, and 750V is shown. Before the proposed common-mode current control method is applied, the current i... a1 i z1 and voltage u faThe waveforms all exhibited resonance, which is detrimental to the stable operation of the system. After incorporating the proposed common-mode current control method, the resonance was effectively suppressed.

[0101] Figures 7(a) and (b) show the transient control waveforms when the given active current and reactive current change abruptly, respectively. It can be seen that the system can effectively suppress resonance and ensure stability even when the active and reactive currents change.

[0102] Example 2

[0103] In one or more embodiments, a common-mode resonance suppression system for a three-level inverter in a high-efficiency modulation mode is disclosed, comprising:

[0104] The data acquisition module is used to sample the output current of the three-phase bridge arm of the three-level inverter at a set frequency;

[0105] The data filtering module is used to perform digital filtering on the sampled current to obtain the low-frequency and mid-frequency components of the current.

[0106] The coordinate transformation module is used to perform abc / dq0 coordinate transformation on the low-frequency and mid-frequency components to obtain the corresponding d-axis components, q-axis components and common-mode components, respectively.

[0107] The differential mode control module is used to input the d-axis and q-axis components into the differential mode current controller for differential mode current control during differential mode control. The output of the differential mode current controller is transformed into a three-phase sinusoidal modulation wave after dq / abc coordinate transformation. Based on the three-phase sinusoidal modulation wave, the clamped and unclamped phases in the three phases are determined.

[0108] The common-mode rejection module is used to send the common-mode component into the common-mode resonance rejection circuit to obtain the common-mode control quantity during common-mode rejection.

[0109] The inverter control module is used to inject common-mode control signals into the non-clamped phase to obtain the final three-phase modulation wave, and then obtain the drive signals for the switching devices to achieve control of the three-level inverter.

[0110] It should be noted that the specific implementation methods of the above modules have been described in Example 1, and will not be detailed here.

[0111] Example 3

[0112] In one or more embodiments, a terminal device is disclosed, including a server. The server includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the common-mode resonance suppression method in the high-efficiency modulation mode of the three-level inverter described in Embodiment 1. For the sake of brevity, further details are omitted here.

[0113] It should be understood that in this embodiment, the processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor, etc.

[0114] Memory may include read-only memory and random access memory, and provides instructions and data to the processor. A portion of memory may also include non-volatile random access memory. For example, memory may also store information about the device type.

[0115] In the implementation process, each step of the above method can be completed by the integrated logic circuits in the processor hardware or by software instructions.

[0116] Example 4

[0117] In one or more embodiments, a computer-readable storage medium is disclosed, wherein a plurality of instructions are stored, the instructions being adapted to be loaded by a processor of a terminal device and executed by the common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described in Embodiment 1.

[0118] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A common-mode resonance suppression method in a three-level inverter under high-efficiency modulation mode, characterized in that, include: The output current of the three-phase bridge arm of the three-level inverter is sampled at a set frequency; The sampled current is digitally filtered to obtain the low-frequency and mid-frequency components of the current. Perform abc / dq0 coordinate transformation on the low-frequency and mid-frequency components to obtain the corresponding d-axis components, q-axis components and common-mode components, respectively. During differential mode control, the d-axis and q-axis components are fed into the differential mode current controller for differential mode current control. The output of the differential mode current controller is transformed by dq / abc coordinates to obtain a three-phase sinusoidal modulation wave. Based on the three-phase sinusoidal modulation wave, the clamped and unclamped phases in the three phases are determined. The clamped and unclamped phases in the three-phase system are determined based on the three-phase sinusoidal modulation wave, specifically as follows: For each three-phase sinusoidal modulation wave, the zero-sequence component required to be injected when it is clamped in the three states of P, O, and N is calculated, and the zero-sequence component with the smallest absolute value for each phase is determined. The zero-sequence components with the smallest absolute values ​​of the three phases are compared. The phase corresponding to the zero-sequence component with the smallest absolute value among the three phases is taken as the final clamped phase, and the other phases are unclamped phases. When performing common-mode suppression, the common-mode component is fed into the common-mode resonance suppression circuit to obtain the common-mode control quantity; The common-mode control signal is injected into the non-clamped phase to obtain the final three-phase modulation wave, which in turn generates the drive signal for the switching devices, thereby enabling control of the three-level inverter.

2. The common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described in claim 1, characterized in that, The output current of the three-phase bridge arm of the three-level inverter is sampled, specifically as follows: Within one switching cycle, the output current of the three-phase bridge arm of the three-level inverter is... N Secondary sampling.

3. The common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described in claim 1, characterized in that, The design bandwidth of the differential mode current controller is no higher than 1 / 2 of the common mode resonant frequency.

4. The common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described in claim 1, characterized in that, The common-mode resonance suppression circuit includes a proportional circuit and a lead compensation circuit connected in sequence.

5. The common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described in claim 4, characterized in that, The proportional coefficient of the proportional element is specifically: in, U dc DC side voltage U dc0 The set fixed DC voltage; k 1 and k Both 2 are for adjusting gain.

6. The common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described in claim 4, characterized in that, The transfer function of the advance compensation stage is: ； ； ； in, , These are the maximum lead angle and the corresponding angular frequency of the lead compensation stage, respectively.

7. A common-mode resonance suppression system for a three-level inverter under high-efficiency modulation mode, characterized in that, A common-mode resonance suppression method for a three-level inverter in a high-efficiency modulation mode according to any one of claims 1-6 includes: The data acquisition module is used to sample the output current of the three-phase bridge arm of the three-level inverter at a set frequency; The data filtering module is used to perform digital filtering on the sampled current to obtain the low-frequency and mid-frequency components of the current. The coordinate transformation module is used to perform abc / dq0 coordinate transformation on the low-frequency and mid-frequency components to obtain the corresponding d-axis components, q-axis components and common-mode components, respectively. The differential mode control module is used to input the d-axis and q-axis components into the differential mode current controller for differential mode current control during differential mode control. The output of the differential mode current controller is transformed into a three-phase sinusoidal modulation wave after dq / abc coordinate transformation. Based on the three-phase sinusoidal modulation wave, the clamped and unclamped phases in the three phases are determined. The common-mode rejection module is used to send the common-mode component into the common-mode resonance rejection circuit to obtain the common-mode control quantity during common-mode rejection. The inverter control module is used to inject common-mode control signals into the non-clamped phase to obtain the final three-phase modulation wave, and then obtain the drive signals for the switching devices to achieve control of the three-level inverter.

8. A terminal device comprising a processor and a memory, the processor for implementing instructions; the memory for storing multiple instructions, characterized in that, The instructions are adapted to be loaded by a processor and executed by the processor to perform the common-mode resonance suppression method in the high-efficiency modulation mode of a three-level inverter as described in any one of claims 1-6.

9. A computer-readable storage medium storing a plurality of instructions, characterized in that, The instructions are adapted to be loaded by the processor of the terminal device and executed by the common-mode resonance suppression method of the three-level inverter in high-efficiency modulation mode according to any one of claims 1-6.

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