Nonvolatile ferroelectric semiconductor memory and preparation method thereof

Abstract

The present invention provides a non-volatile ferroelectric semiconductor memory and a preparation method thereof, wherein the memory comprises a substrate, a control gate and a storage gate sequentially arranged above the substrate; wherein a source and a drain are arranged on the substrate, and a substrate region between the source and the drain forms a channel isolating the source and the drain; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the control gate is used to control the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate, the source, the control gate and the drain. The above invention can improve storage density, reduce power consumption and enhance reliability.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and more specifically, to a non-volatile ferroelectric semiconductor memory and a preparation method thereof. Background Art

[0002] Nonvolatile memory devices have the characteristic of not losing data after power failure and can be found everywhere in the contemporary information society. With the development of the semiconductor industry and the popularization of embedded applications such as specialized hardware and the Internet of Things, the industry has also put forward higher requirements for the performance of nonvolatile memory such as power consumption, speed, storage density, reliability, and endurance.

[0003] At present, ferroelectric field effect transistors (FeFETs) use ferroelectric thin films to replace the gate oxide in the MOSFET structure, so as to use the polarization of the ferroelectric thin film to adjust the on and off states of the channel; by applying voltages of different polarities to the gate, the residual polarization of the ferroelectric layer can be controlled to switch between two directions to achieve the purpose of storing "0" and "1", which has the advantages of fast erase speed, low operating voltage, high storage density, non-destructive readout and strong repeated erase and write capabilities. However, there are still some problems with the traditional structure of FeFET.

[0004] First, the traditional 1T structure FeFET memory has storage density and reliability problems due to the existence of write crosstalk. The traditional memory array programming operation requires the gate (word line) and drain (bit line) to apply voltage at the same time, so the storage cells at the intersection of specific word lines and bit lines can be selected and programmed individually in the cross array structure. In contrast, the 1T structure FeFET cannot achieve cross selection by itself because the programming operation is only controlled by the voltage of the gate relative to the channel. When constructing the cross array structure, additional gating devices are required, resulting in reduced integration density.

[0005] Secondly, potential leakage current reduces the reliability of memory data and increases power consumption. Since the threshold voltage of FeFET fluctuates strongly and the threshold voltage of the device is low when the ferroelectric layer is polarized downward, the threshold voltage offset may cause the threshold voltage of FeFET with polarization downward to be lower than 0V, and remain in the on state when not selected, which significantly increases the leakage current, resulting in poor reliability and increased power consumption. In order to reduce the impact of leakage current, a higher threshold voltage is often used in FeFET memory design. However, a higher threshold voltage makes the gate voltage higher when reading data, which will cause a stronger electric field in the ferroelectric layer and interfere with the polarization state of the ferroelectric layer; that is, the corresponding storage unit will be weakly programmed when reading data. Therefore, the use of a higher threshold voltage cannot effectively improve the reliability of the memory. Summary of the invention

[0006] In view of the above problems, the present invention provides a non-volatile ferroelectric semiconductor memory and a preparation method thereof to solve the problems of limited storage density, low reliability and high power consumption existing in existing FeFET memory devices.

[0007] The nonvolatile ferroelectric semiconductor memory provided by the present invention comprises a substrate, a control gate and a storage gate which are sequentially arranged on the substrate; wherein a source electrode and a drain electrode are arranged on the substrate, and a substrate region located between the source electrode and the drain electrode forms a channel for isolating the source electrode and the drain electrode; a ferroelectric layer is arranged between the channel and the storage gate, and the storage gate is used for applying a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; the control gate is used for controlling the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate, the source electrode, the control gate and the drain electrode.

[0008] In addition, an optional technical solution is that the substrate is of a first doping type, and the source and the drain are of a second doping type opposite to the first doping type.

[0009] In addition, an optional technical solution is that the channel includes a channel under the control gate and a channel under the storage gate; the material of the substrate includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, indium gallium zinc oxide, indium aluminum zinc oxide, indium tin zinc oxide, and indium tin oxide; and the channel is formed on the substrate in a manner including: shallow trench isolation or field oxide isolation.

[0010] In addition, an optional technical solution is that the ferroelectric layer covers a partial area of ​​the channel, and the material of the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate, PZT, SBT, BLT, and is composed of a single layer of any one of the above materials or a multilayer of a combination of multiple materials, and the formation method of the ferroelectric layer on the substrate includes: atomic layer deposition, physical vapor deposition, low pressure chemical vapor deposition, and plasma chemical deposition.

[0011] In addition, an optional technical solution is to provide a buffer medium on the upper and lower surfaces of the ferroelectric layer respectively; the buffer medium includes at least one dielectric layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO.

[0012] In addition, an optional technical solution is that the cross-section of the storage gate is consistent with the ferroelectric layer, and the control gate covers the area of ​​the channel except the ferroelectric layer; the material of the storage gate includes: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, metal silicide; an insulating medium is arranged between the storage gate and the control gate.

[0013] In addition, an optional technical solution is that, when implementing data writing, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage unit to be written, and a positive voltage greater than the threshold voltage is applied to the control gate; the channel of the storage unit is fully opened, and the positive voltage of the drain drops at the drain end of the channel. Except for the position intersecting with the drain, the surface potential of the channel is the source voltage 0V; the voltage on the upper surface of the ferroelectric layer is the positive voltage of the storage gate, and the voltage on the lower surface is the channel surface potential 0V. The positive voltage of the storage gate drops in the ferroelectric layer, and there is a downward electric field in the ferroelectric layer, and the polarization state changes; after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the storage unit is written with "1".

[0014] In addition, an optional technical solution is that, when erasing data, a negative voltage with an amplitude greater than the polarization reversal threshold is applied to the storage gate of the storage unit to be erased; at this time, the upper surface potential of the ferroelectric layer is the negative voltage applied by the storage gate, and the voltage of the lower surface is the substrate voltage of 0V, and there is an upward electric field in the ferroelectric layer; after the voltage is removed, the ferroelectric layer retains the residual polarization in the upward direction, and the unit is erased to "0".

[0015] In addition, an optional technical solution is that, when realizing data reading, a voltage greater than the threshold voltage is applied to the control gate, and a read voltage is applied to the storage gate, and the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric layer; if the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read; otherwise, the channel is turned off and "0" is read.

[0016] On the other hand, the present invention also provides a method for preparing a non-volatile ferroelectric semiconductor memory, comprising: forming a gate dielectric and a buffer dielectric under the ferroelectric layer on a substrate by thermal oxidation or chemical vapor deposition; forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer dielectric, and patterning them by reactive ion etching or wet etching; depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer; depositing a control gate material on the insulating layer, and patterning it by dry etching or reactive ion etching until the substrate is exposed to form a control gate; forming source and drain epitaxy on the substrate by lightly doped implantation or oblique implantation, depositing sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form sidewalls of the control gate; forming heavily doped source and drain regions on the substrate by ion implantation or diffusion.

[0017] By utilizing the above-mentioned non-volatile ferroelectric semiconductor memory and preparation method, a control gate and a storage gate are set, and a ferroelectric layer is set between the storage gate and the substrate. By changing the polarization state of the ferroelectric layer through the voltage of the control gate and the storage gate, cross-selection of the NOR array structure can be achieved, write crosstalk can be eliminated, leakage current can be eliminated, threshold voltage, operating voltage and read voltage can be reduced, storage density can be improved, reliability and erasure resistance of the memory can be enhanced, data retention time can be improved, storage window and erasure speed can be increased, leakage current and power consumption can be reduced, and the overall performance and reliability of the memory can be improved.

[0018] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0020] Figure 1 A schematic diagram of the structure of a non-volatile ferroelectric semiconductor memory according to an embodiment of the present invention;

[0021] Figure 2 A schematic diagram of a write state of a nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention;

[0022] Figure 3 A potential distribution diagram of each point on the channel surface in a write state of a nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention;

[0023] Figure 4 A schematic diagram of a semi-selected state of a nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention;

[0024] Figure 5 A potential distribution diagram of each point on the channel surface of a half-selected memory cell of a nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention;

[0025] Figure 6 The figure is a flow chart of a method for preparing a nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention.

[0026] The reference numerals include: substrate 1 , drain 2 , source 3 , ferroelectric layer 4 , storage gate 6 , and control gate 7 .

[0027] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0028] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0029] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0030] In order to solve the problems of limited storage density, low reliability and high power consumption in existing memory solutions, the present invention provides a non-volatile ferroelectric semiconductor memory and a preparation method thereof, wherein a control gate and a storage gate are arranged, and a ferroelectric layer is arranged between the storage gate and the substrate. The polarization state of the ferroelectric layer is changed by the voltage of the control gate and the storage gate, so that cross-selection of a NOR array structure can be achieved, write crosstalk can be eliminated, leakage current can be eliminated, threshold voltage, operating voltage and read voltage can be reduced, storage density can be increased, reliability and erase and write resistance of the memory can be enhanced, data retention time can be increased, storage window and erase and write speed can be increased, leakage current and power consumption can be reduced, and the overall performance and reliability of the memory can be improved.

[0031] To describe the nonvolatile ferroelectric semiconductor memory and the preparation method of the present invention in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 FIG. 4 shows a schematic structure of a nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention.

[0033] like Figure 1As shown, the non-volatile ferroelectric semiconductor memory of the embodiment of the present invention comprises a substrate 1, a control gate 7 and a storage gate 6 which are sequentially arranged on the substrate 1; wherein a source 3 and a drain 2 are arranged on the substrate 1, and a region of the substrate 1 between the source 3 and the drain 2 forms a channel for isolating the source 3 and the drain 2; a ferroelectric layer 4 is arranged between the channel and the storage gate 6, and the storage gate 6 is used to apply a voltage to the upper surface of the ferroelectric layer 4 to change the polarization state of the ferroelectric layer 4; the control gate 7 is used to control the conduction or closing of the channel; and data writing, reading and erasing are realized by controlling the voltages of the storage gate 6, the source 3, the control gate 7 and the drain 2.

[0034] Specifically, the memory may include five terminals, namely, a substrate 1, a control gate 7 (CG), a memory gate 6 (MG), a source 3, and a drain 2. A ferroelectric layer 4 composed of materials having ferroelectric properties such as hafnium zirconium oxide and hafnium oxide is arranged under the memory gate 6. A buffer material such as silicon dioxide may be added between the ferroelectric layer 4 and the substrate 1 to form a buffer medium. An insulating medium is arranged between the memory gate 6 and the control gate 7, and the insulating medium may be formed of an insulating layer made of insulating materials such as silicon nitride.

[0035] During the use of the non-volatile ferroelectric semiconductor memory, the control gate 7 (CG) can be connected to the word line (WL), the drain 2 can be connected to the bit line (BL), the control gate 7 can be connected to the same voltage as the bit line, the source 3 can be grounded through the common source line (Common SL), and the substrate 1 can be grounded, together forming a NOR type cross array structure, thereby realizing random access, random writing, and block erasing of data.

[0036] In a specific embodiment of the present invention, the substrate 1 is located at the bottom and has a first doping type; its upper part includes source and drain regions, and the source and drain regions are doped with a second doping type opposite to the doping type of the substrate 1; the region between the source 3 and the drain 2 forms a channel, and the channel includes a control gate under-channel and a storage gate under-channel; the material of the substrate 1 includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide).

[0037] The substrate can be a silicon substrate, which is located at the bottom and has P-type doping; its upper part contains source and drain regions, which have N+ doping; the region between the source and drain is a channel. The gate dielectric, control gate, storage gate, ferroelectric layer, and various insulating layers are stacked on the substrate. Ion implantation is used to form a p-well with a high doping concentration in the substrate, and then shallow trench isolation (STI) and field oxide (field oxide) processes are used to isolate each storage unit.

[0038] Specifically, the gate dielectric, control gate 7, storage gate 6, ferroelectric layer 4, and insulating dielectrics located between the lower surface of the control gate 7 and the upper surface of the substrate 1 are stacked on the substrate 1. According to the corresponding relationship in the vertical direction, the channel can be divided into a control gate lower channel and a storage gate lower channel. Available substrate 1 materials include elemental semiconductors, such as silicon and germanium; compound semiconductors, such as gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, and indium antimonide; oxide semiconductors, such as IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide); alloy compound semiconductors; organic materials; flexible materials and combinations of the above materials. The material is doped with the substrate 1 by diffusion, ion implantation, etc., and the material is divided into each substrate 1 region by isolation technology such as shallow trench isolation (STI) and field oxide. In addition, a high doping concentration region can be further formed in the substrate 1 by diffusion or ion implantation to improve the performance of the memory, such as p-well (n-well) and EPM implantation.

[0039] In a specific embodiment of the present invention, the ferroelectric layer 4 is a thin layer made of a material having ferroelectric properties, which is located above the substrate 1 and covers the middle part of the channel. The lower surface of the ferroelectric layer 4 is connected to the substrate 1, and the upper surface is connected to the storage gate 6. A buffer medium or an insulating layer can be added between the lower surface of the ferroelectric layer 4 and the substrate 1, and between the upper surface and the storage gate 6 to improve the properties of the interface.

[0040] In addition, the material of the ferroelectric layer 4 has a residual polarization when there is no electric field, and its polarization state can be reversed. The materials of the ferroelectric layer 4 can include metal oxides, such as hafnium oxide, doped hafnium oxide, zirconium oxide, hafnium zirconium oxide (HZO), hafnium aluminum oxide (HAlO), hafnium lanthanum oxide; salts, such as lead titanate, PZT, SBT, BLT, etc. The method of forming the ferroelectric layer 4 on the substrate 1 includes one or more of atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD) and the like.

[0041] In addition, buffer media are provided on the upper and lower surfaces of the ferroelectric layer 4, respectively. The buffer media includes at least one layer of dielectric material of silicon dioxide, silicon carbide, aluminum oxide, hafnium oxide, HfAlO, HfSiO, Ta2O5 or TaSiO, and the buffer media forms a dielectric layer.

[0042] As an example, the ferroelectric layer is a thin layer made of hafnium zirconium oxide (HZO), which is located above the substrate and covers the right area of ​​the channel. The lower surface of the ferroelectric layer is connected to the substrate, and the upper surface is connected to the storage gate; there is a thin layer of silicon dioxide between the lower surface of the ferroelectric layer and the substrate to improve the interface properties. In addition, the ferroelectric layer can be formed by atomic layer deposition (ALD).

[0043] In a specific embodiment of the present invention, the storage gate 6 is located directly above the ferroelectric layer 4, and its cross section coincides with the ferroelectric layer 4. The left side of the storage gate 6 and the ferroelectric layer 4 (the side where the source is located) is the control gate 7, and the control gate 7 and the storage gate 6 are isolated by an insulating layer. The storage gate 6 serves as a gate electrode for applying a large voltage to the upper surface of the ferroelectric layer 4. Available materials for the storage gate 6 include semiconductors, such as doped polysilicon; metals, such as tantalum and neodymium; metal nitrides and oxides, such as titanium nitride, tungsten nitride, and tantalum nitride; metal silicides, etc.

[0044] In addition, the method for forming the storage gate 6 on the ferroelectric layer 4 includes low pressure chemical vapor deposition (LPCVD), plasma chemical deposition (PECVD), etc. If a polysilicon gate is used, in-situ doping can be performed during deposition. After the ferroelectric layer 4 and the storage gate 6 are formed successively, the two can be patterned, and the patterning process includes wet etching (WE) after photolithography, reactive ion etching (RIE) after photolithography, etc. Further, the materials for the insulating layer that can be selected include one or more layers of insulating media such as silicon dioxide, silicon nitride, and common compounds and organic composite isolation materials. After the ferroelectric layer 4 and the storage gate 6 are formed, the insulating layer can be formed by etching for a short time after forming a thin layer of insulating medium by chemical deposition methods such as LPCVD and PECVD. The etching method can be dry etching, reactive ion etching (RIE), etc.

[0045] As a specific example, the memory gate can be an N+ polysilicon gate, which is located directly above the ferroelectric layer, and the cross section overlaps with the ferroelectric layer. The control gate is on the left side of the memory gate and the ferroelectric layer, and the two are isolated from the control gate by a silicon nitride insulating layer; the memory gate and the right side of the ferroelectric layer are separated by a sidewall spacer. In the preparation process, the polysilicon film is first deposited using low-pressure chemical vapor deposition (LPCVD) technology, and N+ in-situ doping is performed during deposition. Then, the memory gate pattern is defined on the photoresist by photolithography, and then reactive ion etching (RIE) is performed, and the photoresist is stopped and removed when silicon dioxide is exposed. Thereafter, a thin layer of silicon nitride is deposited by LPCVD, and RIE is used to etch for a short time until silicon dioxide is exposed to form an insulating layer. The sidewall isolation can be formed by the same method after the ferroelectric layer, memory gate, control gate, and insulating layer are all formed.

[0046] In a specific embodiment of the present invention, the control gate is located above the substrate 1 and the gate dielectric, covering the remaining area of ​​the channel edge, and controlling the opening and closing of the channel below. In the embodiment shown in the accompanying drawings, the control gate covers the left side of the channel, the gate dielectric is between the lower surface of the control gate and the upper surface of the substrate 1, the left side of the control gate and the right side of the storage gate and the ferroelectric layer are side-wall spacers, and the control gate and the storage gate are isolated by an insulating layer. Among them, the gate dielectric material includes one or more layers of silicon dioxide; silicon nitride; high dielectric constant metal oxide materials, such as titanium dioxide, hafnium oxide, aluminum oxide, tantalum oxide, lanthanum oxide, etc.

[0047] In addition, the gate dielectric is formed before forming each gate, and the method includes deposition techniques such as LPCVD, PECVD, HDP-CVD, ALD, etc. If silicon dioxide is used as the gate dielectric, thermal oxidation can be used to form a gate dielectric with better quality. The available materials for the control gate are similar to those for the storage gate 6, including polysilicon, metal, metal oxide or nitride, etc. The process flow for forming the control gate includes deposition, planarization, and patterning. Deposition can use chemical vapor deposition such as LPCVD, PECVD, HDP-CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), etc., planarization can use techniques such as chemical mechanical polishing (CMP), and patterning can be completed by etching techniques such as reactive ion etching (RIE) after photolithography masking.

[0048] Furthermore, the control gate can be formed after the storage gate 6 is formed and before the sidewall isolation is formed. The sidewall isolation can be formed by the same method after the ferroelectric layer 4, the storage gate 6, the control gate and the insulating layer are all formed; the available materials include one or more layers of insulating media such as silicon dioxide, silicon nitride, and common compounds and organic composite isolation materials, and the specific reference can be made to the insulating materials in the above content.

[0049] As a specific example, the control gate is also an N+ polysilicon gate, located above the substrate and the gate dielectric, covering the remaining area on the left side of the channel. There is a thin layer of silicon dioxide between the lower surface of the control gate and the upper surface of the substrate, with a sidewall isolation on the left and a silicon nitride insulating layer on the right to isolate it from the storage gate. During the preparation process, a thin layer of silicon dioxide is first formed by thermal oxidation, and then a polysilicon film is deposited by LPCVD, and in-situ doping is performed during the process. Thereafter, the chemical mechanical polishing (CMP) technology is used for flattening, and the control gate pattern is defined by photolithography. After photolithography, RIE is used for etching until the silicon substrate is exposed, and the photoresist is removed to form the control gate. The control gate can be formed after the storage gate is formed and before the sidewall isolation is formed. The materials and formation methods of the sidewall isolation and the gate insulation layer have been described above.

[0050] In a specific embodiment of the present invention, the source region and the drain region are located on both sides of the channel of the substrate 1, with a high doping concentration and a doping type opposite to that of the channel. Doping processes such as diffusion and ion implantation can be used to form them. The source and drain regions can be doped before or after the gate stack and the sidewall are formed. If doped after formation, self-aligned ion implantation can be used. Furthermore, short-time diffusion, low-concentration ion implantation or oblique ion implantation can be performed after the gate stack is formed and before the sidewall is formed to form source and drain epitaxy to reduce the short channel effect.

[0051] Specifically, the source and drain regions are located in the substrate, on both sides of the channel, with N+ doping. After the gate stack is formed, low-concentration ion implantation and oblique ion implantation (Halo Implant) are first performed to form source and drain epitaxy. After the sidewall isolation is formed, self-aligned ion implantation is used to form source and drain doping.

[0052] When writing data using the non-volatile ferroelectric semiconductor memory of the embodiment of the present invention, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage unit to be written, and a positive voltage greater than the threshold voltage is applied to the control gate; the channel of the storage unit is fully opened, the positive voltage of the drain drops at the drain end of the channel, and except for the position intersecting with the drain, the surface potential of the channel is the source voltage 0V; the voltage on the upper surface of the ferroelectric layer is the positive voltage of the storage gate, and the voltage on the lower surface is the channel surface potential 0V, the positive voltage of the storage gate drops in the ferroelectric layer, there is a downward electric field in the ferroelectric layer, and the polarization state changes; after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the storage unit is written with "1".

[0053] Specifically, Figure 2 FIG. 2 shows the writing principle of the nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention. Figure 3 The corresponding potential distribution diagram of each point on the channel surface is shown.

[0054] like Figure 2 and Figure 3 As shown together, the horizontal axis represents the various positions on the channel surface, and the vertical axis represents the potential. The ferroelectric layer takes hafnium zirconium oxide HZO as an example. At this time, a positive voltage greater than the polarization reversal threshold is applied to the MG and the drain (BL) of the storage unit to be written, and a positive voltage greater than the threshold voltage is applied to the CG (WL), and a high level can be used. At this time, the channel of the selected storage unit is fully opened, and the positive voltage of the drain drops at the drain end of the channel. Except for the junction with the drain, the surface potential of the main part of the channel is close to the source voltage 0V. The upper surface voltage of the ferroelectric layer is the positive voltage of MG, and the lower surface voltage is the channel surface potential 0V. The larger positive voltage applied to MG drops in the ferroelectric layer, and there is a downward and strong electric field in the ferroelectric layer, and the polarization state changes; after the voltage is removed, the ferroelectric layer has a residual polarization in the downward direction, and the unit is written with "1".

[0055] also, Figure 4 The principle of a semi-selected state of a nonvolatile ferroelectric semiconductor memory according to an embodiment of the present invention is shown; Figure 5 The potential distribution of each point on the channel surface of the corresponding half-selected memory cell is shown.

[0056] like Figure 4 and Figure 5 As shown, the horizontal axis represents the various positions on the channel surface, and the vertical axis represents the potential. The ferroelectric layer takes hafnium zirconium oxide HZO as an example. When the remaining memory cells that share BL with the programmed memory cell are half-selected, a positive voltage greater than the polarization reversal threshold is applied to the MG and the drain, and the CG voltage is 0. At this time, there is no inversion layer under the CG, but an inversion layer appears under the MG. The inversion layer under the MG is connected to the drain, and its potential is close to the positive voltage of the drain. The upper surface voltage of the ferroelectric layer is the positive voltage of the MG, and the lower surface voltage is the positive voltage of the drain; because the voltage applied to the MG and the drain is the same during use, the electric field inside the ferroelectric layer is very weak. The large positive voltage applied by the MG and the drain falls on the reverse biased PN junction between the drain, the inversion layer and the substrate. The ferroelectric layer is shielded by the inversion layer below it, and the polarization state does not change. Therefore, the memory cells half-selected by BL are not affected. For the remaining memory cells, the MG, drain, and source voltages are all 0V. Therefore, regardless of whether CG applies a positive voltage, the upper and lower surface voltages of the ferroelectric layer are 0V, the polarization state does not change, and the memory cells are not affected, thereby eliminating the crosstalk of the memory.

[0057] When erasing data using the non-volatile ferroelectric semiconductor memory of the embodiment of the present invention, a strong negative voltage with an amplitude greater than the polarization reversal threshold is applied to the memory cell MG to be erased. At this time, the upper surface potential of the ferroelectric layer is the negative voltage applied by MG, and the lower surface voltage is the substrate voltage 0V, which is subjected to a strong upward electric field; after the voltage is removed, the ferroelectric layer retains the residual polarization in the upward direction, and the cell is erased to "0". Since erasure is only controlled by the MG voltage, the voltage on the entire BL is erased.

[0058] When using the non-volatile ferroelectric semiconductor memory of the embodiment of the present invention to read data, CG applies a voltage greater than the threshold voltage, and MG applies a read voltage; the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric. If the polarization direction of the ferroelectric layer is downward, the MG voltage is greater than the threshold voltage, the channel is turned on, and "1" is read; otherwise, the channel is turned off, and "0" is read.

[0059] Corresponding to the above non-volatile ferroelectric semiconductor memory, the present invention also provides a method for preparing a non-volatile ferroelectric semiconductor memory, specifically Figure 6 The flowchart of the method for preparing a non-volatile ferroelectric semiconductor memory according to an embodiment of the present invention is shown.

[0060] like Figure 6As shown, the method for preparing the non-volatile ferroelectric semiconductor memory of the embodiment of the present invention comprises:

[0061] S100: forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition;

[0062] Before step A100, a doped substrate may be first formed, and each memory cell may be formed by shallow trench isolation or field oxidation segmentation to form a memory array; then, a gate dielectric of two control gates and a buffer layer under the ferroelectric layer may be formed by thermal oxidation or chemical vapor deposition.

[0063] S200: forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer medium, and patterning them by reactive ion etching or wet etching;

[0064] S300: depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer;

[0065] S400: depositing a control gate material on the insulating layer, and patterning the material until the substrate is exposed by dry etching or reactive ion etching to form a control gate;

[0066] S500: forming source and drain epitaxy on the substrate by light doping implantation or oblique implantation, depositing a sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form a sidewall of the control gate;

[0067] S600: forming heavily doped source and drain regions on the substrate by ion implantation or diffusion.

[0068] As a specific example, the method for preparing the non-volatile ferroelectric semiconductor memory according to the embodiment of the present invention may include:

[0069] 1) Forming substrate doping by diffusion, ion implantation, etc., and dividing the material into storage unit substrates by isolation technologies such as shallow trench isolation (STI) and field oxide;

[0070] 2) Forming a control gate dielectric and a buffer layer under the ferroelectric layer by using deposition techniques such as LPCVD, PECVD, HDP-CVD, and ALD;

[0071] 3) Depositing ferroelectric layer materials using techniques such as atomic layer deposition (ALD), physical vapor deposition (PVD), low pressure chemical vapor deposition (LPCVD), and plasma induced chemical deposition (PECVD);

[0072] 4) Depositing storage gate materials using low pressure chemical vapor deposition (LPCVD), plasma assisted chemical deposition (PECVD) and other technologies;

[0073] 5) Using photolithography to define the memory gate and ferroelectric layer patterns on the photoresist, using wet etching (WE), reactive ion etching (RIE) and other etching techniques for patterning, and then removing the photoresist;

[0074] 6) Depositing insulating layer materials by chemical deposition methods such as LPCVD and PECVD, followed by short-term etching using dry etching, reactive ion etching (RIE) and other techniques until the gate dielectric deposited in step 2 is exposed, thereby forming an insulating layer between the control gate and the storage gate;

[0075] 7) Depositing control gate materials using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) and other technologies such as LPCVD, PECVD, HDP-CVD, etc.;

[0076] 8) Planarization using techniques such as chemical mechanical polishing (CMP);

[0077] 9) Using photolithography to define a control gate pattern on the photoresist, using etching techniques such as reactive ion etching (RIE) to pattern, and then removing the photoresist to form a control gate;

[0078] 10) Depositing sidewall isolation materials using CVD, ALD or other techniques, and then etching using dry etching, RIE or other techniques until the substrate described in step 1 is exposed to form sidewall isolation;

[0079] 11) Heavy doping is performed using diffusion, ion implantation or other doping processes, with the doping type being opposite to the substrate doping type described in step 1, to form source and drain regions.

[0080] Furthermore, a high doping concentration region may be formed in the substrate by diffusion or ion implantation to improve device performance, such as p-well (n-well) and EPM implantation.

[0081] It should be noted that the above-mentioned embodiment of the method for preparing the non-volatile ferroelectric semiconductor memory may refer to the description in the embodiment of the non-volatile ferroelectric semiconductor memory, and will not be described in detail here.

[0082] According to the above-mentioned scheme of the non-volatile ferroelectric semiconductor memory and the preparation method of the present invention, CG can be used to implement cross-selection during programming, the storage density is improved compared with FeFETs with additional transistors or transmission gates, the write crosstalk is eliminated compared with FeFETs without additional transistors, the reliability is enhanced, and the leakage current is cut off by CG, so that a lower threshold voltage and read voltage can be used, and the impact of the read operation on the data is reduced, so that the reliability is enhanced and the power consumption is reduced.

[0083] As described above, the non-volatile ferroelectric semiconductor memory and the preparation method according to the present invention are described by way of example with reference to the accompanying drawings. However, it should be understood by those skilled in the art that various improvements can be made to the non-volatile ferroelectric semiconductor memory and the preparation method proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A nonvolatile semiconductor memory, characterized in that: It includes a substrate, a control gate and a storage gate sequentially arranged on the substrate; wherein, A source electrode and a drain electrode are arranged on the substrate, and a substrate region between the source electrode and the drain electrode forms a channel isolating the source electrode and the drain electrode; A ferroelectric layer is provided between the channel and the storage gate, and the storage gate is used to apply a voltage to the upper surface of the ferroelectric layer to change the polarization state of the ferroelectric layer; The control gate is used to control the channel to be turned on or off, and to control the surface potential of the channel during the data writing process; By controlling the voltages of the storage gate, the source, the control gate and the drain, data writing, reading and erasing are realized; Wherein, when implementing data writing, a positive voltage greater than the polarization reversal threshold is applied to the storage gate and drain of the storage unit to be written, and a positive voltage greater than the threshold voltage is applied to the control gate; The channel of the memory cell is fully opened, the positive voltage of the drain electrode drops at the drain end of the channel, and the surface potential of the channel is 0V, excluding the position intersecting with the drain electrode; The voltage on the upper surface of the ferroelectric layer is the positive voltage of the storage gate, and the voltage on the lower surface is the potential of the channel surface 0V. The positive voltage of the storage gate drops in the ferroelectric layer, and a downward electric field exists in the ferroelectric layer, and the polarization state changes. After the voltage is removed, the ferroelectric layer has a residual polarization in a downward direction, and the storage unit is written with "1".

2. The nonvolatile semiconductor memory according to claim 1, wherein: The substrate is of a first doping type, and the source and the drain are of a second doping type opposite to the first doping type.

3. The nonvolatile semiconductor memory according to claim 1, wherein: The channel includes a control gate lower channel and a storage gate lower channel; The material of the substrate includes at least one of silicon, germanium, gallium nitride, gallium arsenide, indium arsenide, indium phosphide, silicon carbide, indium antimonide, IGZO (indium gallium zinc oxide), IAZO (indium aluminum zinc oxide), ITZO (indium tin zinc oxide), and ITO (indium tin oxide); The channel is formed on the substrate in a manner including shallow trench isolation or field oxide isolation.

4. The nonvolatile semiconductor memory according to claim 1, wherein: The ferroelectric layer covers a part of the channel, and the material of the ferroelectric layer includes hafnium oxide, zirconium oxide, hafnium zirconium oxide, hafnium aluminum oxide, hafnium lanthanum oxide, lead titanate, PZT, SBT, BLT, and is composed of a single layer of any one of the above materials or a multilayer of a combination of multiple materials, and The ferroelectric layer is formed on the substrate by atomic layer deposition, physical vapor deposition, low pressure chemical vapor deposition and plasma chemical deposition.

5. The nonvolatile semiconductor memory according to claim 1 or 4, characterized in that: Buffer media are respectively arranged on the upper and lower surfaces of the ferroelectric layer; The buffer medium includes at least one dielectric layer of silicon dioxide or silicon carbide or aluminum oxide or hafnium oxide or HfAlO or HfSiO or Ta2O5 or TaSiO.

6. The nonvolatile semiconductor memory according to claim 1, wherein: The cross section of the storage gate is consistent with the ferroelectric layer, and the control gate covers the area of ​​the channel except the ferroelectric layer; The material of the storage gate includes: doped polysilicon, tantalum, neodymium, titanium nitride, tungsten nitride, tantalum nitride, and metal silicide; An insulating medium is arranged between the storage gate and the control gate.

7. The nonvolatile semiconductor memory according to claim 1, wherein: When erasing data, a negative voltage having an amplitude greater than a polarization reversal threshold is applied to the storage gate of the storage cell to be erased; At this time, the upper surface potential of the ferroelectric layer is the negative voltage applied by the storage gate, the lower surface voltage is the substrate voltage 0V, and an upward electric field exists in the ferroelectric layer; After the voltage is removed, the ferroelectric layer retains the remnant polarization in the upward direction, and the cell is erased to "0".

8. The nonvolatile semiconductor memory according to claim 1, wherein: When data is read, a voltage greater than a threshold voltage is applied to the control gate, and a read voltage is applied to the storage gate, wherein the read voltage is between the threshold voltages corresponding to the two polarization states of the ferroelectric layer; If the polarization direction of the ferroelectric layer is downward, the voltage of the storage gate is greater than the threshold voltage, the channel is turned on, and "1" is read out; otherwise, the channel is turned off, and "0" is read out.

9. A method for preparing a non-volatile semiconductor memory, characterized in that: For forming the non-volatile semiconductor memory according to any one of claims 1 to 8, the method comprising: Forming a gate dielectric and a buffer dielectric under the ferroelectric layer on the substrate by thermal oxidation or chemical vapor deposition; forming a ferroelectric layer and a storage gate located on the ferroelectric layer on the buffer medium, and patterning them by reactive ion etching or wet etching; Depositing an insulating layer material on the gate dielectric, and performing dry etching or reactive ion etching until the gate dielectric is exposed to form an insulating layer; Depositing a control gate material on the insulating layer, and patterning the layer by dry etching or reactive ion etching until the substrate is exposed to form a control gate; Forming source and drain epitaxy on the substrate by light doping implantation or oblique implantation, depositing sidewall isolation material on the source and drain epitaxy, and etching until the substrate is exposed to form the sidewall of the control gate; Heavily doped source and drain regions are formed on the substrate by ion implantation or diffusion.

Images