Semiconductor structure preparation method, semiconductor structure and semiconductor device

Abstract

The present application provides a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device, the method comprising: providing a substrate formed with a fin structure; wherein the fin structure comprises a device region and a field region arranged in a first direction; removing a first portion of the fin structure located in the field region and retaining a second portion of the field region; forming a first semiconductor structure based on an upper portion of the fin structure, the first semiconductor structure comprising a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer; flipping and removing the substrate to expose a lower portion of the fin structure; removing the second portion of the field region to expose the first interlayer dielectric layer; forming a second semiconductor structure based on the lower portion of the fin structure, the second semiconductor structure comprising a second source-drain structure, a second source-drain metal and a second interlayer dielectric layer; forming an interconnection through-hole structure in the first interlayer dielectric layer and the second interlayer dielectric layer; and connecting the interconnection through-hole structure to the first source-drain metal and the second source-drain metal.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device. Background Art

[0002] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors integrate two or more layers of transistors in a vertical space to further increase the integration density of transistors, becoming one of the important technologies to continue the miniaturization of integrated circuit size.

[0003] When a stacked transistor is prepared using a conventional sequential scheme, the interconnection structure between upper and lower transistors is set in a single manner, which limits the degree of freedom of signal transmission. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device to enhance the degree of freedom of signal transmission.

[0005] The method comprises: providing a substrate formed with a fin structure; wherein the fin structure comprises a device region and a field region arranged in a first direction; the first direction is the same as the extension direction of the fin structure; removing a first part of the fin structure located in the field region and retaining a second part of the field region; wherein the first part is away from the substrate relative to the second part; forming a first semiconductor structure based on the upper part of the fin structure, the first semiconductor structure comprising a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer; wherein the first source-drain structure is located in the device region and the first interlayer dielectric layer is located above the second part of the field region; flipping and removing the substrate to expose the lower part of the fin structure; removing the second part of the field region to expose the first interlayer dielectric layer; forming a second semiconductor structure based on the lower part of the fin structure, the second semiconductor structure comprising a second source-drain structure, a second source-drain metal and a second interlayer dielectric layer; wherein the second source-drain structure is located in the device region and the second interlayer dielectric layer is located above the first interlayer dielectric layer in the field region; an interconnection through-hole structure is formed in the first interlayer dielectric layer and the second interlayer dielectric layer; the interconnection through-hole structure is connected to the first source-drain metal and the second source-drain metal.

[0006] In some possible embodiments, a first semiconductor structure is formed based on the upper part of the fin structure, including: forming a first source-drain structure based on the upper part of the device region; forming a first interlayer dielectric layer on the second part of the field region; and forming a second semiconductor structure based on the lower part of the fin structure, including: forming a second source-drain structure based on the lower part of the device region; and forming a second interlayer dielectric layer on the first interlayer dielectric layer.

[0007] In some possible implementations, the interconnection via structure includes: a first interconnection via structure and a second interconnection via structure; forming a first interlayer dielectric layer on the second part of the field region, including: depositing a semiconductor material on the second part to form a first interlayer dielectric layer; etching the first interlayer dielectric layer to form a first interconnection via structure; forming a first metal interconnection layer on the first source-drain metal and the first interlayer dielectric layer formed with the first interconnection via structure, the first metal interconnection layer connecting the first source-drain metal and the first interconnection via structure. Forming a second interlayer dielectric layer on the first interlayer dielectric layer includes: depositing a semiconductor material on the first interlayer dielectric layer to form a second interlayer dielectric layer; etching the second interlayer dielectric layer until it is connected to the first interconnection via structure to form a second interconnection via structure, the second interconnection via structure and the first interconnection via structure forming an interconnection via structure; forming a second metal interconnection layer on the second source-drain metal and the second interlayer dielectric layer, the second metal interconnection layer connecting the second source-drain metal and the second interconnection via structure.

[0008] In some possible embodiments, forming a second interlayer dielectric layer on the first interlayer dielectric layer also includes: depositing a semiconductor material on the first interlayer dielectric layer to form a second interlayer dielectric layer; depositing a metal material on the second source and drain metal and the second interlayer dielectric layer to form a second metal interconnection layer; etching the second metal interconnection layer and the second interlayer dielectric layer until they are connected to the first interconnection through-hole structure to form a second interconnection through-hole structure.

[0009] In some possible implementations, forming a first interlayer dielectric layer on the second portion of the field region includes: depositing a semiconductor material on the second portion to form a first interlayer dielectric layer; forming a first metal interconnection layer on the first source-drain metal and the first interlayer dielectric layer. Forming a second interlayer dielectric layer on the first interlayer dielectric layer includes: depositing a semiconductor material on the first interlayer dielectric layer to form a second interlayer dielectric layer; etching the second interlayer dielectric layer and the first interlayer dielectric layer until they are connected to the first metal interconnection layer to form an interconnection via structure; forming a second metal interconnection layer on the second source-drain metal and the second interlayer dielectric layer, the second metal interconnection layer connecting the second source-drain metal and the interconnection via structure.

[0010] In some possible embodiments, forming a second interlayer dielectric layer on the first interlayer dielectric layer also includes: depositing a semiconductor material on the first interlayer dielectric layer to form a second interlayer dielectric layer; depositing a metal material on the second source and drain metal and the second interlayer dielectric layer to form a second metal interconnection layer; etching the second metal interconnection layer, the second interlayer dielectric layer and the first interlayer dielectric until they are connected to the first metal interconnection layer to form an interconnection through-hole structure.

[0011] In some possible embodiments, a first source-drain structure is formed based on the upper part of the device area, including: forming a plurality of dummy gates spaced apart along a first direction on the fin-shaped structure; forming a first source-drain structure in the gaps between the plurality of dummy gates in the device area; forming a third interlayer dielectric layer on the first source-drain structure; removing the plurality of dummy gates and depositing metal material to form a first gate structure; photolithography of the metal material in the field area to expose the second portion; removing the third interlayer dielectric layer to expose the first source-drain structure to form a first source-drain metal.

[0012] In some possible embodiments, a second source-drain structure is formed based on the lower portion of the device area, including: forming a plurality of dummy gates spaced apart along a first direction on the fin-shaped structure; forming a second source-drain structure in the gaps between the plurality of dummy gates in the device area; forming a fourth interlayer dielectric layer on top of the second source-drain structure; removing the plurality of dummy gates and depositing metal material to form a second gate structure; photolithography of the metal material in the field area to expose the first interlayer dielectric layer; removing the fourth interlayer dielectric layer to expose the second source-drain structure to form a second source-drain metal.

[0013] In the second aspect, an embodiment of the present application provides a semiconductor structure, including: a first transistor; a second transistor, the second transistor being arranged back to back with the first transistor; wherein the first source and drain metal of the first transistor is connected to the second source and drain metal of the second transistor through an interconnection through-hole structure, and the interconnection through-hole structure passes through the first interlayer dielectric layer of the first transistor and the second interlayer dielectric layer of the second transistor.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the above embodiment.

[0015] In an embodiment of the present application, an interconnection via structure in the semiconductor structure connects a first source-drain metal of the first semiconductor structure and a second source-drain metal of the second semiconductor structure, thereby realizing interconnection between the first source-drain structure of the first semiconductor structure and the second source-drain structure of the second semiconductor structure.

[0016] In addition, the embodiment of the present application introduces a field region by removing a portion of the active structure, and forms a metal interconnection structure connecting the first transistor and the second transistor in the field region, so that the metal interconnection structure is independently arranged from the source and drain metal in the device region, so that the signal transmission between the first transistor and the second transistor can pass through the field region or the device region, effectively improving the degree of freedom of signal transmission. Furthermore, the metal interconnection structure has multiple implementation methods, which greatly enhances the diversity of signal transmission methods.

[0017] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0019] Figure 1 This is a schematic diagram of a first implementation process of the method for preparing a semiconductor structure in an embodiment of the present application;

[0020] Figure 2 A schematic diagram of a first structure of a semiconductor structure in an embodiment of the present application;

[0021] Figures 3 to 18 A schematic diagram of a first preparation process of a semiconductor structure in an embodiment of the present application;

[0022] Figures 19 to 20 A schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application;

[0023] Fig.21 A second structural schematic diagram of a semiconductor structure in an embodiment of the present application;

[0024] Fig. 22 A third structural schematic diagram of a semiconductor structure in an embodiment of the present application;

[0025] Fig.23 A fourth structural schematic diagram of a semiconductor structure in an embodiment of the present application;

[0026] Fig.24 A fifth structural schematic diagram of a semiconductor structure in an embodiment of the present application;

[0027] Fig.25 This is a sixth structural schematic diagram of the semiconductor structure in the embodiment of the present application.

[0028] The above pictures:

[0029] 10. semiconductor structure; 11. first transistor; 112. first source-drain structure; 113. first interlayer dielectric layer; 114. first source-drain metal; 115. first metal interconnect layer; 12. second transistor; 122. second source-drain structure; 123. second interlayer dielectric layer; 124. second source-drain metal; 125. second metal interconnect layer; 1251. first interconnect sublayer; 1252. second interconnect sublayer; 13. device region; 14. field region; 141. first part of fin structure; 142. The second part of the fin-like structure; 15. The interconnection through-hole structure; 151. The first interconnection through-hole structure; 152. The second interconnection through-hole structure; 16. The second shallow trench isolation layer; 17. The first shallow trench isolation layer; 21. The substrate; 211. The fin-like structure; 22. The first dummy gate structure; 23. The dummy gate sidewall structure; 24. The insulating dielectric layer; 25. The anti-reflective coating; 26. The photoresist; 27. The gate dielectric layer; 28. The gate electrode layer; 29. ​​The insulating layer; 30. The carrier; 31. The source-drain groove. DETAILED DESCRIPTION

[0030] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0031] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot topic in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size.

[0032] In one embodiment, there are two schemes for manufacturing a stacked transistor, the first is a monolithic scheme, and the second is a sequential scheme.

[0033] The first solution is to make N-channel field effect transistors (NFET) and P-channel field effect transistors (PFET) on the same substrate without using wafer bonding technology. This determines that the transistors on the same layer must be of the same type, namely NFET or PFET. In addition, the upper and lower layer transistors must be strictly in the same plane space without alignment deviation. The advantage of this solution is that it has a better integration density. The disadvantages of this solution include the following two points: (1) The process is complex and requires a lot of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and two layers of transistors must be relied on to form a basic complementary metal-oxide-semiconductor (CMOS) circuit, which has poor design flexibility.

[0034] The second solution is based on wafer bonding and layer-by-layer processing. Specifically, the upper transistor is prepared by bonding the wafer on top of the already manufactured lower transistor, and the two transistors are stacked vertically. However, the temperature needs to be strictly controlled during the thermal process of processing the upper transistor to avoid affecting the lower transistor and the interconnection lines. The advantage of this solution is that thanks to wafer bonding, the device structure, channel crystal orientation and even channel material used by the upper and lower transistors can be optimized accordingly to obtain better and more matched device performance.

[0035] The current challenges of this solution are: because the manufacturing process is fixed, the interconnection structure between the upper and lower layer transistors is relatively simple, which limits the freedom of signal transmission.

[0036] In order to solve the above technical problems, an embodiment of the present application provides a method for preparing a semiconductor structure to provide more metal interconnection solutions and improve the degree of freedom of signal transmission.

[0037] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as memory and processor.

[0038] In one embodiment, the semiconductor structure may include at least two transistors, for example, a first transistor and a second transistor. The first transistor and the second transistor are arranged back to back. The first active structure in the first transistor and the second active structure in the second transistor are formed by the same process, and in this case, it can be understood that the first transistor and the second transistor are self-aligned.

[0039] In the embodiment of the present application, the first transistor and the second transistor in the semiconductor structure may be fin field effect transistors whose active structures are fin-shaped structures.

[0040] Figure 1This is a schematic diagram of the first implementation process of the method for preparing a semiconductor structure in the embodiment of the present application, see Figure 1 As shown, the method for preparing the semiconductor structure may include:

[0041] S101, providing a substrate with a fin structure formed thereon.

[0042] The fin-shaped structure may include a device region and a field region arranged in a first direction. Here, the first direction may be the same as the extension direction of the fin-shaped structure, and the first direction may also be understood as the same as the direction of the connection line formed between the fin-shaped structure and the substrate. (For the sake of simplicity of the specification, the first direction is hereinafter represented by the length direction of the fin-shaped structure).

[0043] In one embodiment, the device region of the fin structure is used to form a source-drain structure, a channel structure, etc. of a semiconductor device, and the field region of the fin structure is used to form an interconnection structure connecting the first transistor and the second transistor, such as an interconnection via structure.

[0044] It can be understood that a plurality of fin structures can be formed by etching the semiconductor substrate.

[0045] Among them, the height of the fin-shaped structure is formed by etching from top to bottom. In the embodiment of the present application, since the semiconductor structure includes two transistors (i.e., the first transistor and the second transistor), and the first active structure of the first transistor and the second active structure of the second transistor are formed by the same etching process, a larger etching depth can be used when etching the semiconductor substrate. For example, the height of the fin-shaped structure obtained by etching can be greater than 100nm.

[0046] It should be noted that the height of the fin-shaped structure can be set according to actual conditions, and the embodiments of the present application do not make any specific limitations on this.

[0047] In one embodiment, the substrate may be a silicon (Si) substrate or a silicon-on-insulator (SOI) substrate. Of course, the substrate may also be a substrate made of other semiconductor materials, which is not specifically limited in the embodiment of the present application.

[0048] S102, removing a first portion of the fin structure located in the field region, and retaining a second portion of the field region.

[0049] The first portion is farther away from the substrate than the second portion.

[0050] It is understandable that by performing photolithography on the substrate with the fin structure formed thereon, a portion of the fin structure located above the field region can be removed by photolithography, and a portion below can be retained, thereby reducing the length of the upper fin structure. In other words, a portion of the fin structure is removed in the length direction of the fin structure.

[0051] The steps of the photolithography technology may include: depositing a photoresist material, exposing and developing the photoresist material, removing a portion of the photoresist material, etching to remove a material layer corresponding to the portion of the photoresist material, etc.

[0052] It can be understood that removing a portion of the fin structure corresponding to the field region in S102 can free up the space occupied by the portion of the fin structure, thereby facilitating the use of the freed space to form an interconnection via structure for source-drain connection in a subsequent process flow.

[0053] In one embodiment, after removing the first portion of the fin structure located in the field region and retaining the second portion of the field region, the method further includes:

[0054] An oxide is deposited on the second portion to form a shallow trench isolation layer.

[0055] It can be understood that after the shallow trench isolation layer is formed on the second portion, the first transistor can still be isolated from the second transistor after the second portion of the field region is removed in a subsequent process flow.

[0056] The oxide forming the shallow trench isolation structure may be any one of the following: silicon nitride (SiN, Si3N4), silicon dioxide (SiO2) or silicon oxycarbide (SiCO), etc.

[0057] In one embodiment, the substrate includes an isolation layer, such as a BOX layer in an SOI substrate. When removing the first portion of the fin structure corresponding to the field region, the photolithography can be stopped at the isolation layer, so that after the second portion of the field region is removed in a subsequent process flow, the first transistor and the second transistor can still be isolated by the isolation layer.

[0058] S103 , forming a first semiconductor structure based on the upper portion of the fin structure.

[0059] The first semiconductor structure includes a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer. The first source-drain structure is located in the device region, and the first interlayer dielectric layer is located in the field region and on the second portion retained in S102.

[0060] It can be understood that after the first part of the fin structure in the field region is removed through S102 , a first semiconductor structure can be formed based on the structure formed in S102 , so that the preparation of the first transistor is completed.

[0061] Here, forming the first semiconductor structure at least requires forming a first source-drain structure located in the device region, a first source-drain metal located on the first source-drain structure, and a first interlayer dielectric layer located in the field region.

[0062] In some embodiments, forming a first semiconductor structure based on an upper portion of the fin structure in S103 includes: forming a first source-drain structure based on an upper portion of the device region; and forming a first interlayer dielectric layer on a second portion of the field region.

[0063] It can be understood that the fin-shaped structure can be used to form a channel structure. When forming the first semiconductor structure, the first source-drain structure can be first formed based on the fin-shaped structure at the upper part of the device region (the end away from the substrate). After the first source-drain structure is formed, a first interlayer dielectric layer can be formed on the second part of the field region to isolate the field region from the device region. Finally, a first source-drain metal is formed on the first source-drain structure.

[0064] Among them, the process of forming the first source-drain structure can be selected according to actual needs, and the embodiment of the present application does not make any specific limitation on this.

[0065] Exemplarily, a fin recess deep etching process can be used to form source and drain grooves of the first transistor on the fin structure, and then a spacer (pseudo-gate sidewall structure) is used as a mask to form a strained material such as silicon germanium or silicon carbide in the source and drain grooves by selective epitaxial growth to fill the source and drain grooves of the first transistor, and then a first source and drain structure is formed on the above-mentioned strained material through a heavy doping process.

[0066] It should be noted that, for ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source electrode structure and / or the first drain electrode structure. In addition, the second source-drain structure, the first source-drain metal, the second source-drain metal, the source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source electrode and / or drain electrode".

[0067] In one embodiment, a first source-drain structure is formed based on the upper part of the device region, including: forming a plurality of dummy gates spaced along a first direction on the fin structure; forming a first source-drain structure in the gaps between the plurality of dummy gates in the device region; forming a third interlayer dielectric layer on the first source-drain structure; removing the plurality of dummy gates, depositing a metal material to form a first gate structure; photolithography the metal material in the field region to expose the second portion. Removing the third interlayer dielectric layer to expose the first source-drain structure to form a first source-drain metal.

[0068] It can be understood that before forming the first source and drain structure, multiple dummy gate structures can be formed; dummy gate sidewall structures are formed on both sides of the multiple dummy gate structures. In the gaps between the multiple dummy gate structures in the device area, source and drain grooves can be formed using a fin-shaped structure deep etching process. Afterwards, a first source and drain structure can be formed based on the source and drain grooves, and a semiconductor material can be deposited on the upper part of the first source and drain structure, between the two dummy gate sidewall structures, to form a third interlayer dielectric layer. Then, the multiple dummy gates can be removed, and a metal material can be deposited on the semiconductor structure. The deposited metal material is used to form a first gate structure in the area where the removed dummy gate structure is located; if the deposited metal material is in the field area, the metal material must be removed by a photolithography process to expose the second part of the fin-shaped structure. Then, the third interlayer dielectric layer can be removed to expose the first source and drain structure, and a metal material can be deposited on the first source and drain structure to form a first source and drain metal.

[0069] The semiconductor material forming the third interlayer dielectric layer is an insulating material having a very high insulating property.

[0070] In one embodiment, the first gate structure at least includes: a first gate dielectric layer and a first gate electrode layer. The materials of the gate dielectric layer and the gate electrode layer can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0071] Exemplarily, the first gate dielectric layer may be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the first transistor. The first gate electrode layer may be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0072] In one example, the first gate dielectric layer may include: a 0.6 nm silicon oxide layer and a 1.7 nm hafnium oxide layer.

[0073] It should be noted that the process of forming the dummy gate structure is used to form the first gate structure of the first transistor, and the process of forming the third interlayer dielectric layer is used to form the first source and drain metal of the first transistor. Both processes are for forming the structure in the device area. Therefore, during the two processes, if there is an impact on the field area, such impact should be eliminated to ensure that the second part of the field area is exposed.

[0074] For example, when a metal material is deposited, the metal material is deposited into the field area, and at this time, the field area can be photolithographically processed to remove the metal material in the field area. For another example, a pseudo gate sidewall structure is also formed in the field area, so that when a semiconductor material is deposited, the field area can be photolithographically processed to remove the semiconductor material and the pseudo gate sidewall in the field area.

[0075] In one embodiment, the field region of the fin-like structure is covered by a complete dummy gate structure, so that after removing multiple dummy gate structures, the second part of the fin-like structure can be directly exposed without removing multiple dummy gate sidewall structures of the field region through a photolithography process, thereby reducing the number of photolithography steps and improving preparation efficiency.

[0076] In some embodiments, the interconnection via structure includes: a first interconnection via structure and a second interconnection via structure. Forming a first interlayer dielectric layer on the second portion of the field region includes: depositing a semiconductor material on the second portion to form a first interlayer dielectric layer; etching the first interlayer dielectric layer to form a first interconnection via structure; forming a first metal interconnection layer on the first source and drain metal and the first interlayer dielectric layer formed with the first interconnection via structure, wherein the first metal interconnection layer connects the first source and drain metal and the first interconnection via structure.

[0077] It can be understood that after forming the first source-drain structure and the first gate structure in the device area, a first interlayer dielectric layer can be formed on the second part of the field area. Specifically, a semiconductor material can be first deposited on the second part to form a first interlayer dielectric layer. Then, the first interlayer dielectric layer is etched to form a through hole that penetrates the first interlayer dielectric layer, and a metal material is deposited in the through hole to form a first interconnection through hole structure; then, a post-process (such as interconnection line dielectric deposition, metal line formation, lead pad formation, etc.) is performed on the device area and the field area to form a first metal interconnection layer, and the first metal interconnection layer can connect the first source-drain metal and the first interconnection through hole structure.

[0078] The semiconductor material forming the first interlayer dielectric layer is an insulating material with high insulating properties. The metal material forming the interconnection through-hole structure can be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0079] In some embodiments, the first metal interconnection layer includes: a first interconnection sublayer and a second interconnection sublayer, wherein the first interconnection sublayer is in direct contact with the first source and drain metal and the first interconnection through-hole structure, and can also be understood as M0 metal; the second interconnection sublayer is in direct contact with the first interconnection sublayer, and can also be understood as M1 metal.

[0080] It can be understood that the first source-drain metal and the first interconnection via structure are electrically connected through the M0 metal and the M1 metal.

[0081] In some other possible embodiments, during the process of preparing the first transistor, the first interconnection via structure in the first transistor may not be prepared, and a first interlayer dielectric layer is formed on the second portion of the field region without preparing the first interconnection via structure, including: depositing a semiconductor material on the second portion to form a first interlayer dielectric layer; and forming a first metal interconnection layer on the first source and drain metal and the first interlayer dielectric layer.

[0082] It is understandable that after forming the first source-drain structure and the first gate structure in the device region, a first interlayer dielectric layer may be formed on the second portion of the field region. Specifically, a semiconductor material may be first deposited on the second portion to form the first interlayer dielectric layer. Then, a first metal interconnect layer may be formed on the device region and the field region.

[0083] S104 , flipping the wafer and removing the substrate to expose the lower portion of the fin structure.

[0084] It is understandable that after forming the first semiconductor structure including the first source-drain structure, the first interlayer dielectric layer and the first source-drain metal, the other structures in the first transistor can be prepared according to standard steps. After the first transistor is prepared, the first transistor is flipped and the semiconductor substrate is removed so that the lower part of the fin structure is placed upward, so as to facilitate the subsequent preparation of the second transistor using the lower part of the fin structure.

[0085] In some embodiments, before S104, the method may further include: bonding the first semiconductor structure to a carrier wafer.

[0086] It can be understood that in S103, a first metal interconnection layer is formed on the first source and drain metal and the first interlayer dielectric layer. Then, an insulating material (such as silicon oxide) can be deposited on the first metal interconnection layer to form a first insulating layer, and the first insulating layer is bonded to the carrier wafer.

[0087] In the embodiment of the present application, the bonded carrier wafer can provide physical support for the flipped first transistor after inversion, thereby effectively preventing the first transistor from being broken by external force during the preparation of the second transistor.

[0088] In one embodiment, the substrate removal after flipping may be performed by polishing or chemical-mechanical planarization (CMP).

[0089] S105 , removing the second portion of the field region to expose the first interlayer dielectric layer.

[0090] It can be understood that the second part of the lithography field area can remove the fin structure in the field area and vacate the space occupied by the fin structure, which is beneficial for forming an interconnection through-hole structure for connecting metal interconnection layers by using the vacated space in the subsequent process flow.

[0091] In one embodiment, removing the second portion of the field region to expose the first interlayer dielectric layer includes: removing the second portion to expose the shallow trench isolation layer deposited in S102. The shallow trench isolation layer can be used to isolate the first transistor from the second transistor.

[0092] In one embodiment, removing the second portion of the field region to expose the first interlayer dielectric layer includes: performing photolithography until the isolation layer is stopped, and isolating the first transistor from the second transistor through the isolation layer.

[0093] S106 , forming a second semiconductor structure based on the lower portion of the fin structure.

[0094] The second semiconductor structure includes a second source-drain structure, a second source-drain metal and a second interlayer dielectric layer. The second source-drain structure is located in the device region, and the second interlayer dielectric layer is located in the field region and on the first interlayer dielectric layer formed in S103.

[0095] It can be understood that after the second part of the fin-shaped structure in the field region is removed through S105 , a second semiconductor structure can be formed based on the structure formed in S105 , so that the preparation of the second transistor is completed.

[0096] Here, forming the second semiconductor structure at least requires forming a second source-drain structure located in the device region, a second source-drain metal located on the second source-drain structure, and a second interlayer dielectric layer located in the field region.

[0097] In some embodiments, forming a second semiconductor structure based on the lower portion of the fin structure in S106 includes: forming a second source-drain structure based on the lower portion of the device region; and forming a second interlayer dielectric layer on the first interlayer dielectric layer.

[0098] It can be understood that the fin-shaped structure can be used to form a channel structure. When forming the second semiconductor structure, the second source-drain structure can be first formed based on the fin-shaped structure at the lower part of the device region (the end facing upward after flipping). After the second source-drain structure is formed, a second interlayer dielectric layer can be formed on the first interlayer dielectric layer in the field region to isolate the field region from the device region. Finally, a second source-drain metal is formed on the second source-drain structure.

[0099] The process of forming the second source-drain structure can refer to the process of forming the first source-drain structure, and will not be described here for the sake of brevity. The semiconductor material forming the second interlayer dielectric layer is an insulating material with high insulating properties.

[0100] In one embodiment, a second source-drain structure is formed based on the lower part of the device area, including: forming a plurality of dummy gate structures arranged at intervals along a first direction on the fin-shaped structure; forming a second source-drain structure in the gaps between the plurality of dummy gate structures in the device area; forming a fourth interlayer dielectric layer on the second source-drain structure; removing the plurality of dummy gate structures and depositing metal material to form a second gate structure; photolithography of the metal material in the field area to expose the first interlayer dielectric layer; removing the fourth interlayer dielectric layer to expose the second source-drain structure to form a second source-drain metal.

[0101] It can be understood that before forming the second source-drain structure, multiple dummy gate structures can be formed; dummy gate sidewall structures are formed on both sides of the multiple dummy gate structures. In the gaps between the multiple dummy gate structures in the device area, a source-drain groove can be formed using a fin-type structure deep etching process. Afterwards, a second source-drain structure can be formed based on the source-drain groove, and a semiconductor material can be deposited on the upper part of the second source-drain structure, between the two dummy gate sidewall structures, to form a fourth interlayer dielectric layer. Then, the multiple dummy gates can be removed, and a metal material can be deposited on the semiconductor structure. The deposited metal material is used to form a second gate structure in the area where the removed dummy gate structure is located; if the deposited metal material is in the field area, the metal material must be removed by a photolithography process to expose the first interlayer dielectric layer. Then, the fourth interlayer dielectric layer can be removed to expose the second source-drain structure, and a metal material can be deposited on the second source-drain structure to form a second source-drain metal.

[0102] It should be noted that, similar to S103, the process of forming the dummy gate structure and the process of forming the fourth interlayer dielectric layer are both for forming the structure in the device region. Therefore, during the two processes, if there is an impact on the field region, such impact should be eliminated to ensure that the first interlayer dielectric layer in the field region is exposed.

[0103] In some embodiments, the interconnection via structure includes: a first interconnection via structure and a second interconnection via structure. Forming a second interlayer dielectric layer on the first interlayer dielectric layer includes: depositing semiconductor material on the first interlayer dielectric layer to form a second interlayer dielectric layer; etching the second interlayer dielectric layer until it is connected to the first interconnection via structure to form a second interconnection via structure, the second interconnection via structure and the first interconnection via structure forming an interconnection via structure; forming a second metal interconnection layer on the second source and drain metal and the second interlayer dielectric layer, the second metal interconnection layer connecting the second source and drain metal and the second interconnection via structure.

[0104] It is understandable that if a first interconnection through hole is formed when preparing the first transistor, after forming the second source-drain structure and the second gate structure in the device area, a second interlayer dielectric layer can be formed on the first interlayer dielectric layer in the field area. Specifically, a semiconductor material can be first deposited on the first interlayer dielectric layer to form a second interlayer dielectric layer. Then the second interlayer dielectric layer is etched to form a through hole that penetrates the second interlayer dielectric layer, and the through hole is connected to the first interconnection through hole structure. Metal material is deposited in the through hole to form a second interconnection through hole structure. The second interconnection through hole structure and the first interconnection through hole structure form an interconnection through hole structure. Then, a post-process (such as interconnection line dielectric deposition, metal line formation, lead pad formation, etc.) is performed on the device area and the field area to form a second metal interconnection layer, and the second metal interconnection layer can connect the second source-drain metal and the second interconnection through hole structure.

[0105] In some embodiments, the second metal interconnection layer includes: a third interconnection sublayer and a fourth interconnection sublayer, wherein the third interconnection sublayer is in direct contact with the second source and drain metal and the second interconnection via structure, and can also be understood as M0 metal; the fourth interconnection sublayer is in direct contact with the third interconnection sublayer, and can also be understood as M1 metal.

[0106] It can be understood that the second source-drain metal is electrically connected to the second interconnection via structure through the M0 metal and the M1 metal. The second interconnection via structure and the first interconnection via structure form an interconnection via structure, and the first source-drain metal is electrically connected to the first interconnection via structure, so that the interconnection via structure connects the first source-drain metal and the second source-drain metal.

[0107] In some other possible embodiments, during the process of preparing the first transistor, the first interconnection through-hole structure in the first transistor may not be prepared, and a second interlayer dielectric layer is formed on the first interlayer dielectric layer without preparing the first interconnection through-hole structure, including: depositing semiconductor material on the first interlayer dielectric layer to form a second interlayer dielectric layer; etching the second interlayer dielectric layer and the first interlayer dielectric layer until they are connected to the first metal interconnection layer to form an interconnection through-hole structure; forming a second metal interconnection layer on the second source-drain metal and the second interlayer dielectric layer, the second metal interconnection layer connecting the second source-drain metal and the interconnection through-hole structure.

[0108] It is understandable that if the first interconnection through hole is not formed when preparing the first transistor, after forming the second source-drain structure and the second gate structure in the device area, a semiconductor material can be deposited on the first interlayer dielectric layer in the field area to form a second interlayer dielectric layer. Then, the second interlayer dielectric layer and the first interlayer dielectric layer are etched to form a through hole that penetrates the second interlayer dielectric layer and the first interlayer dielectric layer at the same time, and a metal material is deposited in the through hole to form an interconnection through hole structure. The interconnection through hole structure can connect the first metal interconnection layer. Then, a post-process (such as interconnection line dielectric deposition, metal line formation, lead pad formation, etc.) is performed on the device area and the field area to form a second metal interconnection layer, and the second metal interconnection layer can connect the interconnection through hole structure, and then connect the first metal interconnection layer.

[0109] It should be noted that in the above embodiments, the interconnection via structure is prepared first, and then the metal interconnection layer is prepared, so that the interconnection via structure and the metal interconnection layer are prepared through different steps.

[0110] In some other possible implementations, the interconnection via structure and the metal interconnection layer may also be prepared by the same steps.

[0111] In one embodiment, when the interconnection via structure and the metal interconnection layer are prepared by the same steps, if the interconnection via structure includes: a first interconnection via structure and a second interconnection via structure; then forming a second interlayer dielectric layer on the first interlayer dielectric layer includes: depositing a semiconductor material on the first interlayer dielectric layer to form a second interlayer dielectric layer; depositing a metal material on the second source and drain metal and the second interlayer dielectric layer to form a second metal interconnection layer; etching the second metal interconnection layer and the second interlayer dielectric layer until they are connected to the first interconnection via structure to form a second interconnection via structure.

[0112] It can be understood that if a first interconnection through hole is formed when preparing the first transistor, after forming the second source-drain structure and the second gate structure in the device area, a semiconductor material can be first deposited on the first interlayer dielectric layer to form a second interlayer dielectric layer. Then, a back-end process (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) is performed on the device area and the field area to form a second metal interconnection layer. Then, the second metal interconnection layer and the second interlayer dielectric layer are etched to form a through hole that penetrates the second metal interconnection layer and the second interlayer dielectric layer, and the through hole is connected to the first interconnection through hole structure. Metal material is deposited in the through hole to form a second interconnection through hole structure. The second interconnection through hole structure and the first interconnection through hole structure form an interconnection through hole structure.

[0113] It can be seen that the above steps can connect the second metal interconnection layer with the first interconnection through hole, thereby reducing the process complexity.

[0114] In one embodiment, when the interconnection via structure and the metal interconnection layer are prepared by the same steps, a second interlayer dielectric layer is formed on the first interlayer dielectric layer, and the method further includes: depositing a semiconductor material on the first interlayer dielectric layer to form the second interlayer dielectric layer; depositing a metal material on the second source / drain metal and the second interlayer dielectric layer to form a second metal interconnection layer; etching the second metal interconnection layer, the second interlayer dielectric layer and the first interlayer dielectric until they are connected to the first metal interconnection layer to form the interconnection via structure.

[0115] It is understandable that if the first interconnection through hole is not formed when preparing the first transistor, after forming the second source-drain structure and the second gate structure in the device area, a semiconductor material can be first deposited on the first interlayer dielectric layer to form a second interlayer dielectric layer. Then, a post-process (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) is performed on the device area and the field area to form a second metal interconnection layer. Then, the second metal interconnection layer, the second interlayer dielectric layer and the first interlayer dielectric layer are etched to form a through hole that penetrates the second metal interconnection layer, the second interlayer dielectric layer and the first interlayer dielectric layer, and the through hole is connected to the first metal interconnection layer. Metal material is deposited in the through hole to form an interconnection through hole structure. The interconnection through hole structure is connected to the first interconnection through hole structure, and then connected to the first source-drain metal.

[0116] It can be seen that the above steps can connect the second metal interconnection layer with the first metal interconnection layer, thereby reducing the process complexity.

[0117] In an embodiment of the present application, a substrate is provided and an active structure is formed on the substrate, so that an active structure of two transistors can be formed through one process; a first transistor is formed by utilizing the upper portion of the active structure, and a second transistor is formed by utilizing the second portion of the active structure after flipping the wafer, so that the upper and lower layers of transistors are self-aligned.

[0118] In addition, the embodiment of the present application introduces a field region by removing a portion of the active structure, and forms a metal interconnection structure connecting the first transistor and the second transistor in the field region, so that the metal interconnection structure is independently arranged from the source and drain metal in the device region, so that the signal transmission between the first transistor and the second transistor can pass through the field region or the device region, effectively improving the degree of freedom of signal transmission. Furthermore, the metal interconnection structure has multiple implementation methods, which greatly enhances the diversity of signal transmission methods.

[0119] The following is a specific example to illustrate the method for preparing the semiconductor structure provided in the embodiment of the present application. Figure 2 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application. Figure 2 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view only shows the fin structure, gate structure, source-drain structure and interconnection via structure; (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., AA' direction); (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., BB' direction).

[0120] See also Figure 2As shown, the semiconductor structure 10 includes a first transistor 11 and a second transistor 12, and the active structure in the semiconductor structure 10 is a plurality of fin-shaped structures. The fin-shaped structure is divided into two parts, namely, the first part and the second part, the first part is used as the first active structure in the first transistor 11, and the second part is used as the second active structure in the second transistor 12.

[0121] In one embodiment, along the BB' direction, the fin structure includes a device region 13 (shown by a dotted line frame in the figure) and a field region 14 (shown by a dotted line frame in the figure), wherein the device region 13 is formed with a first source-drain structure 112 and a second source-drain structure 122 disposed opposite to each other, and the field region 14 is formed with a first interlayer dielectric layer 113 and a second interlayer dielectric layer 123. The first source-drain structure 112 is connected to a first source-drain metal 114, and the first source-drain metal 114 is connected to a first metal interconnection layer 115. The second source-drain structure 122 is connected to a second source-drain metal 124, and the second source-drain metal 124 is connected to a second metal interconnection layer 125. The first source-drain metal 114 of the first transistor 11 is connected to the second source-drain metal 124 of the second transistor 12 through an interconnection via structure 15, and the interconnection via structure 15 penetrates the first interlayer dielectric layer 113 of the first transistor 11 and the second interlayer dielectric layer 123 of the second transistor 12.

[0122] In one embodiment, see Figure 2 As shown, the interconnection via structure 15 may include two parts, one part is the first interconnection via structure 151, and the first interconnection via structure 151 is connected to the first metal interconnection layer 115; the other part is the second interconnection via structure 152, and the second interconnection via structure 152 is connected to the second metal interconnection layer 125; the first interconnection via structure 151 and the second interconnection via structure 152 are connected.

[0123] In combination with the above preparation method, Figure 2 The preparation process of the semiconductor structure shown is described. Figures 3 to 18 Schematic diagram of the first preparation process of the semiconductor structure in the embodiment of the present application, wherein: Figure 3 (a) to Fig.18 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., the AA' direction). Figure 3 (b) to Fig.18 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (ie, the BB' direction).

[0124] In one example, a first preparation process of the semiconductor structure 10 may include the following steps:

[0125] Step 1: Provide a semiconductor substrate 21 having a fin structure 211 formed thereon, and obtain Figure 3 The structure shown.

[0126] It is understandable that the fin structure can be formed on the silicon substrate using an etching process. The fin structure includes a device region 13 and a field region 14 arranged along a first direction. The first direction is the same as the extension direction of the fin structure, and the first direction is the same as the BB' direction.

[0127] It should be noted that the height of the fin structure may be greater than 100 nm.

[0128] Step 2: Right Figure 3 The structure shown in FIG. 1 is subjected to photolithography to remove the first portion 141 of the fin structure near the right side (field region 14) in the BB' direction, and retain the second portion 142 of the fin structure. A semiconductor material is deposited on the second portion 142 of the fin structure to form a first shallow trench isolation layer 17 (i.e., the first shallow trench isolation layer), and the structure shown in FIG. 1 is obtained. Figure 4 The structure shown.

[0129] Here, the first shallow trench isolation layer 17 covers the top of the second portion 142 of the fin structure and fills the trenches between the fin structures.

[0130] Step 3: In Figure 4 The first dummy gate structure 22 and the dummy gate sidewall structure 23 are formed on the structure shown in FIG. 1 , and the source-drain groove 31 of the source-drain region is formed by a selective etching process to obtain the structure shown in FIG. Figure 5 The structure shown.

[0131] Here, the first dummy gate structures 22 are arranged at intervals in the BB′ direction.

[0132] Step 4: Figure 5 A first source-drain structure 112 is formed at the source-drain groove 31 shown in the figure, and a semiconductor material is deposited on the first source-drain structure 112 to form an insulating dielectric layer 24 (i.e., a third interlayer dielectric layer). Subsequently, after a planarization process, the first dummy gate structure 22 is removed to obtain Figure 6 The structure shown.

[0133] Step 5: Figure 6 A bottom anti-reflection coating 25 (ARC) and a photoresist 26 are deposited on the structure shown in FIG. Figure 7 The structure shown.

[0134] It should be noted that the morphology of the photoresist is Figure 6 The photoresist 26 is shown in the middle. The purpose of this photolithography is to remove the insulating dielectric layer 24 and the pseudo gate sidewall structure 23 in the field region.

[0135] Step 6: Etch away Figure 7The anti-reflective coating 25, the insulating dielectric layer 24 and the pseudo gate sidewall structure 23 not covered by the photoresist 26 in the structure shown in FIG. Figure 8 The structure shown.

[0136] It should be noted that the removal of the insulating dielectric layer 24 in this step is self-aligned and allows a certain degree of deviation as long as the insulating dielectric layer 24 region on the left device region is not etched.

[0137] Step 7: Removal Figure 8 The photoresist 26 and the anti-reflective coating 25 in the embodiment are used to form the gate structure using a standard semiconductor manufacturing process to obtain a gate structure such as Fig. 9 The structure shown.

[0138] Here, forming the gate structure may include depositing a gate dielectric layer 27 and a gate electrode layer 28 .

[0139] Step 8: Fig. 9 A bottom anti-reflective coating 25 and a photoresist 26 are deposited on the structure shown in FIG. Fig.10 The structure shown.

[0140] It should be noted that the morphology of the photoresist is Fig. 9 As shown in the middle photoresist 26. The purpose of this photolithography is to remove the gate structure of the field region.

[0141] Step 9: Etch away Fig.10 The anti-reflective coating 25, the gate dielectric layer 27 and the gate electrode layer 28 not covered by the photoresist 26 in the structure shown in FIG. Fig.11 The structure shown.

[0142] It should be noted that this step is self-aligned, allowing the etching window to be slightly offset within the range corresponding to the right device area without affecting the subsequent structure formation.

[0143] It should be noted that the range of the layout used for etching the gate structure in this step is larger than the range of the layout used for etching the insulating dielectric layer in the sixth step.

[0144] Step 10: Removal Fig.11 After the semiconductor material is deposited on the semiconductor structure, a planarization process is performed to obtain a first interlayer dielectric layer 113. The insulating dielectric layer 24 on the first source-drain structure 112 is removed, and a metal material is deposited to form a first source-drain metal 114, and the semiconductor material is deposited on the semiconductor structure. Fig.12 The structure shown.

[0145] Step 11: Fig.12The field region in the structure shown in the figure is etched, and the first shallow trench isolation layer 17 is used as an etching stop layer to etch a through hole penetrating the first interlayer dielectric layer 113 and the gate dielectric layer 27, and a metal material is deposited in the through hole to form a first interconnection through hole structure 151, so as to obtain Fig.13 The structure shown.

[0146] Step 12: Complete the back-end interconnection process of the first transistor to form a first metal interconnection layer 115. The first metal interconnection layer 115 is connected to the first source and drain metal 114 to obtain Fig.14 The structure shown.

[0147] Step 13: Fig.14 Oxide is deposited on the structure shown in the figure to form an insulating layer 29; above the insulating layer 29, a carrier 30 is bonded to the first transistor 11, and then the wafer is flipped to obtain a structure as shown in the figure. Fig.15 The structure shown.

[0148] Step 14: After flipping, the substrate 21 is removed, and the structure after the substrate 21 is removed is photolithographically to remove the second portion 142 of the fin structure near the left side (field region 14) in the BB' direction. Subsequently, the first shallow trench isolation layer 17 is thinned to a certain height to form a second shallow trench isolation layer 16 (i.e., the second shallow trench isolation layer), and the following is obtained: Fig.16 The structure shown.

[0149] It should be noted that after this step, the fin-shaped structures in the field area 14 have been completely removed.

[0150] Step 15: Using the same process as steps 3 to 10, the second transistor 12 is prepared to obtain Fig.17 The structure shown.

[0151] It can be understood that the preparation of the second transistor 12 includes: forming a second dummy gate structure and a dummy gate sidewall structure, forming source and drain grooves, forming a second source and drain structure, removing the dummy gate structure, forming a gate structure and forming a second source and drain metal.

[0152] Step 16: Etching Fig.17 The second interlayer dielectric layer 123 corresponding to the field region in the structure shown in the figure is etched with the second shallow trench isolation layer 16 as an etching stop layer to etch a through hole penetrating the second interlayer dielectric layer 123, and a metal material is deposited in the through hole to form a second interconnection through hole structure 152, so as to obtain Fig.18 The structure shown.

[0153] Step 17: Complete the back-end interconnection process of the first transistor to form a second metal interconnection layer 125. The second metal interconnection layer 125 is connected to the second source and drain metal 124 to obtain Figure 2 The structure shown.

[0154] At this point, the first transistor and the second transistor are completed, and the first source-drain metal 114 and the second source-drain metal 124 are interconnected through the first interconnection via structure 151 and the second interconnection via structure 152 .

[0155] In one example, the semiconductor structure 10 may have a second manufacturing process. Figures 19 to 20 is a schematic diagram of a second preparation process of a semiconductor structure in an embodiment of the present application, Figure 2 The semiconductor structure shown can also be Figures 3 to 18 Combination Figures 19 to 20 The process shown is prepared. Fig.19 (a) to Fig. 20 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., the AA' direction). Fig.19 (b) to Fig. 20 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (ie, the BB' direction).

[0156] The second preparation process can refer to the description of the first to seventeenth steps above. The difference from the first preparation process is that in the third step, the field region 14 can be covered by a dummy gate through layout design, that is, a wider first dummy gate structure 22 is formed, and the following is obtained: Fig.19 Then, after the first source-drain structure 112 and the insulating dielectric layer 24 are completed in the fourth step, the first dummy gate structure 22 is removed to obtain a target structure in which the field region does not include the first dummy gate structure 22, and the structure shown in FIG. Fig. 20 It can be seen that the second preparation process does not need to perform the fifth to seventh steps of photolithography, thereby reducing one photolithography process and reducing the difficulty of preparation.

[0157] It should be noted that the second preparation process can use the same process as the first transistor when preparing the second transistor. For the sake of brevity of the specification, it will not be repeated here.

[0158] In one example, Fig.21 Schematic diagram of the second structure of the semiconductor structure in the embodiment of the present application. Fig.21 (a) is a top view of the semiconductor structure. It should be noted that, for ease of understanding, the top view only shows the fin structure, gate structure, source-drain structure and interconnection via structure; (b) is a cross-sectional view of the semiconductor structure taken along the cross-sectional direction of the gate structure (i.e., BB' direction).

[0159] Different from the first structure, the interconnection through-hole structure 15 in the second structure is a complete structure. The above two preparation processes can be formed by changing some steps. Fig.21Specifically, when preparing the first transistor, the formation of the first interconnection through-hole structure 151 in the eleventh step may not be performed, and when preparing the second transistor, the second interlayer dielectric layer 123 and the first interlayer dielectric layer 113 corresponding to the field region may be etched in the sixteenth step, and the first metal interconnection layer 115 may be used as an etching stop layer to etch a through hole penetrating the second interlayer dielectric layer 123 and the first interlayer dielectric layer 113, and a metal material may be deposited in the through hole to form an interconnection through-hole structure 15, and obtain the following. Fig.21 The structure shown.

[0160] In one example, Fig. 22 This is a schematic diagram of the third structure of the semiconductor structure in the embodiment of the present application. Fig. 22 A cross-sectional view of a semiconductor structure taken along the cross-sectional direction of a gate structure.

[0161] like Figure 2 and Fig. 22 As shown, in the first structural schematic diagram of the semiconductor structure, the second metal interconnection layer 125 includes: a first interconnection sublayer 1251 (i.e., M0 metal) and a second interconnection sublayer 1252 (i.e., M1 metal). Among them, the interconnection between the M0 metal and the M1 metal does not realize direct interconnection. In the third structural schematic diagram, the M0 metal and the M1 metal realize direct interconnection, thereby making the signal transmission method between the first transistor and the second transistor more flexible.

[0162] In one example, Fig.23 This is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present application. Fig.23 A cross-sectional view of a semiconductor structure taken along the cross-sectional direction of a gate structure.

[0163] like Fig.21 and Fig.23 As shown, in the second schematic diagram of the semiconductor structure, the M0 metal and the M1 metal of the second metal interconnection layer 125 are not directly interconnected. In the fourth schematic diagram of the structure, the M0 metal and the M1 metal are directly interconnected, thereby making the signal transmission method between the first transistor and the second transistor more flexible.

[0164] In one example, Fig.24 This is a fifth structural schematic diagram of the semiconductor structure in the embodiment of the present application. Fig.24 A cross-sectional view of a semiconductor structure taken along the cross-sectional direction of a gate structure.

[0165] like Fig.24As shown, in the fifth structural schematic diagram of the semiconductor structure, the M0 gold M0 metal of the second metal interconnection layer 125 and the M1 metal and the second interconnection through-hole structure 152 are directly interconnected, thereby making the signal transmission method between the first transistor and the second transistor more flexible.

[0166] In one example, Fig.25 This is a sixth structural schematic diagram of the semiconductor structure in the embodiment of the present application. Fig.25 A cross-sectional view of a semiconductor structure taken along the cross-sectional direction of a gate structure.

[0167] like Fig.25 As shown, in the sixth structural schematic diagram of the semiconductor structure, the M0 gold M0 metal of the second metal interconnection layer 125 is directly interconnected with the M1 metal and the interconnection through-hole structure 15, thereby making the signal transmission method between the first transistor and the second transistor more flexible.

[0168] In one or more of the above embodiments, a variety of metal interconnection schemes can be implemented, and can be implemented in a self-aligned manner, so that the signal transmission method of the first transistor and the second transistor is more flexible and is not constrained by the source-drain direct connection structure. In addition, after the field region independent of the device region forms an interconnection through-hole structure, the low-level metal (M0 metal and M1 metal) between the first transistor and the second transistor can be interconnected, thereby making the signal transmission through the field region and the signal transmission through the internal structure such as the source-drain metal and the metal through-hole independent of each other.

[0169] It should be noted that the preparation method of one or more of the above embodiments may refer to the description in one or more of the embodiments S101 to S106, and for the sake of brevity of the specification, it will not be repeated here.

[0170] The present application embodiment provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 21 to Figure 25 The semiconductor structure shown will not be described in detail here.

[0171] The present application embodiment provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, wherein the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be found in the above Figure 2 , Figure 21 to Figure 25 The semiconductor structure shown will not be described in detail here.

[0172] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms is not necessarily for the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine different embodiments or examples described in the present application and the features of different embodiments or examples without contradiction.

[0173] The above are only preferred embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: A substrate having a fin-shaped structure is provided; wherein the fin-shaped structure includes a device region and a field region arranged in a first direction; and the first direction is the same as an extension direction of the fin-shaped structure; Removing a first portion of the fin structure located in the field region and retaining a second portion of the field region; wherein the first portion is farther away from the substrate than the second portion; Based on the upper part of the fin structure, a first semiconductor structure is formed, wherein the first semiconductor structure includes a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer; wherein the first source-drain structure is located in the device region, and the first interlayer dielectric layer is located on the second part of the field region; Flipping the wafer and removing the substrate to expose the lower portion of the fin structure; removing a second portion of the field region to expose the first interlayer dielectric layer; Based on the lower part of the fin structure, a second semiconductor structure is formed, wherein the second semiconductor structure includes a second source-drain structure, a second source-drain metal, and a second interlayer dielectric layer; wherein the second source-drain structure is located in the device region, and the second interlayer dielectric layer is located on the first interlayer dielectric layer in the field region; An interconnection through-hole structure is formed in the first interlayer dielectric layer and the second interlayer dielectric layer; the interconnection through-hole structure is connected to the first source-drain metal and the second source-drain metal.

2. The method according to claim 1, characterized in that The forming of a first semiconductor structure based on the upper portion of the fin-shaped structure comprises: forming a first source-drain structure based on the upper portion of the device region; forming the first interlayer dielectric layer on the second portion of the field region; The forming of a second semiconductor structure based on the lower portion of the fin-shaped structure comprises: forming a second source-drain structure based on the lower portion of the device region; The second interlayer dielectric layer is formed on the first interlayer dielectric layer.

3. The method according to claim 2, characterized in that The interconnected through-hole structure comprises: a first interconnected through-hole structure and a second interconnected through-hole structure; The forming of the first interlayer dielectric layer on the second portion of the field region comprises: depositing a semiconductor material on the second portion to form the first interlayer dielectric layer; Etching the first interlayer dielectric layer to form the first interconnection via structure; Forming a first metal interconnection layer on the first source-drain metal and the first interlayer dielectric layer having the first interconnection via structure, wherein the first metal interconnection layer connects the first source-drain metal and the first interconnection via structure; The forming of the second interlayer dielectric layer on the first interlayer dielectric layer comprises: Depositing a semiconductor material on the first interlayer dielectric layer to form the second interlayer dielectric layer; Etching the second interlayer dielectric layer until it is connected with the first interconnection through-hole structure to form the second interconnection through-hole structure, wherein the second interconnection through-hole structure and the first interconnection through-hole structure constitute the interconnection through-hole structure; A second metal interconnection layer is formed on the second source-drain metal and the second interlayer dielectric layer, and the second metal interconnection layer is connected to the second source-drain metal and the second interconnection via structure.

4. The method according to claim 3, characterized in that The forming of the second interlayer dielectric layer on the first interlayer dielectric layer further comprises: Depositing a semiconductor material on the first interlayer dielectric layer to form the second interlayer dielectric layer; Depositing a metal material on the second source / drain metal and the second interlayer dielectric layer to form a second metal interconnect layer; The second metal interconnection layer and the second interlayer dielectric layer are etched until they are connected to the first interconnection via structure to form the second interconnection via structure.

5. The method according to claim 2, characterized in that: The forming of the first interlayer dielectric layer on the second portion of the field region comprises: depositing a semiconductor material on the second portion to form the first interlayer dielectric layer; forming a first metal interconnection layer on the first source / drain metal and the first interlayer dielectric layer; The forming of the second interlayer dielectric layer on the first interlayer dielectric layer comprises: Depositing a semiconductor material on the first interlayer dielectric layer to form the second interlayer dielectric layer; Etching the second interlayer dielectric layer and the first interlayer dielectric layer until they are connected to the first metal interconnection layer to form the interconnection through-hole structure; A second metal interconnection layer is formed on the second source-drain metal and the second interlayer dielectric layer, and the second metal interconnection layer connects the second source-drain metal and the interconnection via structure.

6. The method according to claim 5, characterized in that The forming of the second interlayer dielectric layer on the first interlayer dielectric layer further comprises: Depositing a semiconductor material on the first interlayer dielectric layer to form the second interlayer dielectric layer; Depositing a metal material on the second source / drain metal and the second interlayer dielectric layer to form a second metal interconnect layer; The second metal interconnection layer, the second interlayer dielectric layer and the first interlayer dielectric are etched until they are connected to the first metal interconnection layer to form the interconnection via structure.

7. The method according to claim 3 or 5, characterized in that: The forming of a first source-drain structure based on the upper portion of the device region comprises: forming a plurality of dummy gates arranged at intervals along a first direction on the fin-shaped structure; forming the first source-drain structure in the gaps between the plurality of dummy gates in the device region; forming a third interlayer dielectric layer on the first source-drain structure; removing the plurality of dummy gates and depositing a metal material to form a first gate structure; Photolithography the metal material of the field region to expose the second portion; The third interlayer dielectric layer is removed to expose the first source-drain structure to form the first source-drain metal.

8. The method according to claim 7, characterized in that The forming of a second source-drain structure based on the lower portion of the device region comprises: forming a plurality of dummy gates arranged at intervals along a first direction on the fin-shaped structure; forming the second source-drain structure in the gaps between the plurality of dummy gates in the device region; forming a fourth interlayer dielectric layer on the second source-drain structure; removing the plurality of dummy gates and depositing a metal material to form a second gate structure; Photolithography the metal material in the field region to expose the first interlayer dielectric layer; The fourth interlayer dielectric layer is removed to expose the second source-drain structure to form the second source-drain metal.

9. A semiconductor structure, prepared using the preparation method according to any one of claims 1 to 8, characterized in that: include: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged opposite to each other; and the active structures in the first transistor and the second transistor are fin structures; The first source-drain metal of the first transistor is connected to the second source-drain metal of the second transistor through an interconnection via structure, and the interconnection via structure penetrates the first interlayer dielectric layer of the first transistor and the second interlayer dielectric layer of the second transistor; The first source-drain metal and the second source-drain metal are located in the device region of the fin structure, the first interlayer dielectric layer and the second interlayer dielectric layer are located in the field region of the fin structure, and the device region and the field region are arranged in a first direction, which is the same as the extension direction of the fin structure.

10. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 9.

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