Reconfigurable strong puf circuit with strong nonlinear response and method

Abstract

The application discloses a reconfigurable strong PUF circuit and method with strong nonlinear response, an STT-MRAM storage unit array is used for storing data information "0" or "1", an odd array access transistor is used for accessing the STT-MRAM storage unit of an odd bit, and an even array access transistor is used for accessing the STT-MRAM storage unit of an even bit; an odd array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the odd bit, and an even array excitation selection transistor is used for controlling the write signal of the STT-MRAM storage unit of the even bit; an array selection circuit ASC selects an odd row STT-MRAM storage unit and an even row STT-MRAM storage unit from the STT-MRAM storage unit array, inputs the resistance comparison into a sensing amplifier circuit SA, and outputs a comparison result. The application makes the PUF response have strong nonlinearity, thereby significantly improving the security, and improving the performance of the PUF in speed, power consumption, area and the like.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and information security hardware encryption technology, specifically to a reconfigurable strong PUF circuit and method with strong nonlinear response. Background Technology

[0002] A physically unclonable function (PUF) is a security primitive that uses random physical variations introduced by manufacturing processes as a source of entropy to obtain a security fingerprint of a specific instance of hardware. Physical variations caused by manufacturing process deviations affect the physical dimensions and material properties of a device, leading to changes in its electrical and magnetic properties, ultimately determining the behavior of the PUF. A PUF is a fundamental building block for hardware security, enabling secure device authentication without requiring a memory-resident key. Mathematically, a PUF can be represented as a function that transforms stimuli into responses, generating a space of stimulus-response pairs (CRPs) that is unique and unclonable for each instance. PUFs can be classified into weak and strong PUFs based on the number of CRPs. Weak PUFs support only a finite CRP space that grows linearly with area, while strong PUFs support an extremely large CRP space that grows exponentially with area.

[0003] Chinese patent application CN116738504A discloses a PUF module and an MRAM with integrated PUF functionality. First, a breakdown circuit outputs a breakdown voltage to the PUF data array to randomly break down some magnetic tunnel junctions in the PUF data array into a short-circuit state. Then, a failure control circuit randomly writes the remaining magnetic tunnel junctions in the PUF data array into a parallel or anti-parallel state and controls the write operation function of the PUF data write circuit to fail, preventing accidental data tampering in the PUF data cells. Finally, two sets of reference cells are selected, and two PUF data read circuits are used to read the current state of the MRAM cells. The results of the reads are then used to construct the Physically Unclonable Function (PUF) of the MRAM chip. This scheme requires an additional breakdown circuit to obtain short-circuit MRAM memory cells when initializing the state of each memory cell in the MRAM chip. However, due to the high breakdown voltage, it may cause irreversible damage to the rest of the MRAM chip in a short time, resulting in the chip failing to function properly. At the same time, to increase the CRP space, short-circuit and open-circuit states of the MTJ are introduced, and two read circuits with different reference resistors and two cycles are used to read the current state of the MTJ, increasing the area and time overhead. In addition, the selection of the reference resistor adopts the average method, that is, using the average between the high and low resistances of the MTJ as the reference resistor, which reduces the reliability of the read. Furthermore, directly reading the current state of the MTJ to generate the PUF output, its CRP space increases linearly with the increase of the number of MRAM cells. Although the MTJ has more states, the CRP space is still relatively small.

[0004] Chinese patent application CN110706727A discloses a magnetic random access memory (MRM) and a reconfigurable PUF method based on STT MRAM. This method uses all memory cell locations and their corresponding currents as inputs. During initialization, it arranges possible parallel configurations of bit lines (MTJs) on the left and right sides and calculates the corresponding parallel currents of each configuration. It then uses the K pairs of bit line pairs with the largest differences in their parallel currents as the excitation, and the comparison results of the parallel currents of the bit line pairs as the response; K represents the required number of bits in the response. This scheme requires pairwise comparisons and sorting from largest to smallest to select the K bit line pairs when determining the parallel MTJ configurations used as excitations. This necessitates numerous and complex peripheral circuits for logic control and incurs significant time overhead. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention provides a reconfigurable strong PUF circuit and method with strong nonlinear response, which enables the PUF response to have strong nonlinearity, thereby significantly improving security, while also improving the performance of the PUF in terms of speed, power consumption, area, etc.

[0006] To achieve the above technical objectives, the present invention adopts the following technical solution: a reconfigurable strong PUF circuit with strong nonlinear response, comprising: an STT-MRAM memory cell array, odd array memory access transistors, even array memory access transistors, odd array drive selection transistors, even array drive selection transistors, array selection circuit ASC, sensing amplifier circuit SA, second row decoder, and third row decoder.

[0007] Each STT-MRAM storage cell in the STT-MRAM storage cell array is used to store data information "0" or "1" respectively;

[0008] The odd-numbered array memory access transistors consist of all odd-numbered array memory access transistors, and the odd-numbered array memory access transistors access the corresponding odd-numbered STT-MRAM memory cells in the STT-MRAM memory cell array.

[0009] The even-numbered array memory access transistors consist of all even-numbered array memory access transistors, and the even-numbered array memory access transistors access the STT-MRAM memory cells corresponding to even-numbered bits in the STT-MRAM memory cell array.

[0010] The odd array excitation selection transistor is composed of all odd-numbered array excitation selection transistors, and the odd array excitation selection transistor is used to control the write signal of the corresponding odd-numbered STT-MRAM memory cell in the STT-MRAM memory cell array.

[0011] The even-numbered array excitation selection transistor is composed of all even-numbered array excitation selection transistors, and the even-numbered array excitation selection transistor is used to control the write signal of the STT-MRAM memory cell corresponding to the even-numbered bit in the STT-MRAM memory cell array.

[0012] The array selection circuit ASC selects an odd-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the second row decoder, and selects an even-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the third row decoder. The selected odd-numbered row of STT-MRAM memory cells and the selected even-numbered row of STT-MRAM memory cells are input into the sensing amplifier circuit SA for resistance comparison, and the comparison result is output.

[0013] Furthermore, the STT-MRAM memory cell array is composed of n×n magnetic tunnel junctions.

[0014] Furthermore, the array selection circuit ASC consists of n transmission gates and n OR gates. The gate of each odd-numbered OR gate is connected to the output of a second-row decoder, and the drain of each odd-numbered OR gate is connected to the enable of an odd-numbered transmission gate. The outputs of all odd-numbered transmission gates are connected to one input of the sensing amplifier circuit SA. The gate of each even-numbered OR gate is connected to the output of a third-row decoder, and the drain of each even-numbered OR gate is connected to the enable of an even-numbered transmission gate. The outputs of all even-numbered transmission gates are connected to the other input of the sensing amplifier circuit SA.

[0015] Furthermore, for the magnetic tunnel junctions in each row with an odd number of bits, the electrode leading out from one end of the pinned layer of the magnetic tunnel junction is connected to the drain of an odd array memory access transistor and the source of an odd array excitation selection transistor, respectively, and the electrode leading out from one end of the free layer of the magnetic tunnel junction is connected to the excitation of the odd array BLs.

[0016] Furthermore, the gate of each row of odd-numbered array memory access transistors is connected to the first control signal WLs, and the source of each row of odd-numbered array memory access transistors is connected to the second control signal SLs; the gate of each row of odd-numbered array excitation selection transistors is connected to the output of the corresponding second column decoder, and the drain of each row of odd-numbered array excitation selection transistors is connected to the input of the corresponding odd-numbered bit transmission gate in the array selection circuit ASC.

[0017] Furthermore, for the even-numbered magnetic tunnel junctions in each row, the electrode leading out from one end of the pinned layer of the magnetic tunnel junction is connected to the drain of an even-numbered array memory access transistor and the source of an even-numbered array excitation selection transistor, respectively, and the electrode leading out from one end of the free layer of the magnetic tunnel junction is connected to the excitation of the even-numbered array BLs.

[0018] Furthermore, the gate of each row of even-numbered array memory access transistors is connected to the first control signal WLs, and the source of each row of even-numbered array memory access transistors is connected to the second control signal SLs; the gate of each row of even-numbered array excitation selection transistors is connected to the output of the corresponding second column decoder, and the drain of each row of even-numbered array excitation selection transistors is connected to the input of the corresponding even-numbered bit transmission gate in the array selection circuit ASC.

[0019] Furthermore, the odd-numbered array BLs excitation and the even-numbered array BLs excitation are both controlled by the output signals of the corresponding first column decoders.

[0020] Furthermore, the first control signal WLs is controlled by the output signal of the corresponding first row decoder.

[0021] Furthermore, the present invention also provides a reconfigurable method for the reconfigurable strong PUF circuit with strong nonlinear response, specifically including the following steps:

[0022] a. By enabling the odd array BLs activation, even array BLs activation, odd array memory access transistor activation, and even array memory access transistor activation, all STT-MRAM memory cell bits in the STT-MRAM memory cell array are initialized to the set state;

[0023] b. Input PUF stimulus, and write the stimulus of odd array stimulus selection transistor and even array stimulus selection transistor into the STT-MRAM memory cell array to obtain the stimulus-response pair of each STT-MRAM memory cell in the STT-MRAM memory cell array;

[0024] c. The array selection circuit ASC selects an odd-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the second row decoder. The array selection circuit ASC selects an even-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the third row decoder. The selected odd-numbered row STT-MRAM memory cell and the selected even-numbered row STT-MRAM memory cell are input to the sensing amplifier circuit SA for resistance comparison. If the resistance of the odd-numbered row STT-MRAM memory cell is greater than the resistance of the even-numbered row STT-MRAM memory cell, the sensing amplifier circuit SA outputs "1"; otherwise, the sensing amplifier circuit SA outputs "0".

[0025] d. By resetting the state of the STT-MRAM memory cell array through step a, a new physically unclonable function (PUF) is obtained. Steps b and c are repeated to realize a reconfigurable physically unclonable function (PUF).

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] (1) This invention only uses the high-resistance and low-resistance states of the magnetic tunnel junction (MTJ), and does not require the use of a breakdown circuit to obtain the short-circuit state of the MTJ as mentioned in the previous scheme, resulting in higher stability. At the same time, this invention can select any odd-numbered row of STT-MRAM memory cells and any even-numbered row of STT-MRAM memory cells, and the number of STT-MRAM memory cells connected in parallel in each row of STT-MRAM memory cells is determined by the excitation given by the user. Its CRP increases exponentially, and it has higher security, unpredictability and reliability.

[0028] (2) The present invention selects two discharge paths in the STT-MRAM memory cell by the array selection circuit ASC to obtain the PUF result, avoiding the need to compare the data cell with the reference cell to obtain the data stored in the STT-MRAM memory cell. On the one hand, the present invention does not introduce a reference cell, which simplifies the circuit design and reduces the area overhead; on the other hand, by comparing with its own cell, the difference in the comparison path will be greater, which improves the reliability of the read circuit.

[0029] (3) In this invention, the parallel connection method of each STT-MRAM memory cell in the two discharge paths is determined by the excitation given by the user, thereby greatly improving nonlinearity. Compared with existing solutions, the strong magnetic PUF proposed in this invention exhibits better resistance to machine learning attacks and provides a higher level of security.

[0030] (4) The strong magnetic PUF proposed in this invention can write different states to some or all of the MTJ bits of the magnetic tunnel junction for reconstruction, thus giving it a wider range of applications. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the reconfigurable strong PUF circuit with strong nonlinear response of the present invention;

[0032] Figure 2 This is a circuit diagram of the reconfigurable strong PUF circuit with strong nonlinear response of the present invention;

[0033] Figure 3 This is a flowchart of the reconfigurable method for a reconfigurable strong PUF circuit with strong nonlinear response according to the present invention. Detailed Implementation

[0034] The technical solution of the present invention will be further explained and described below with reference to the accompanying drawings.

[0035] like Figure 1This is a schematic diagram of the reconfigurable strong PUF circuit with strong nonlinear response of the present invention. The reconfigurable strong PUF circuit includes: an STT-MRAM memory cell array, odd-numbered array memory access transistors, even-numbered array memory access transistors, odd-numbered array drive selection transistors, even-numbered array drive selection transistors, an array selection circuit ASC, a sensing amplifier circuit SA, a second row decoder, and a third row decoder. Each STT-MRAM memory cell in the STT-MRAM memory cell array is used to store data information "0" or "1". The odd-numbered array memory access transistors consist of all odd-numbered array memory access transistors, which access the corresponding odd-numbered STT-MRAM memory cells in the STT-MRAM memory cell array. The even-numbered array memory access transistors consist of all even-numbered array memory access transistors, which access the corresponding even-numbered STT-MRAM memory cells in the STT-MRAM memory cell array. The odd-numbered array drive selection transistors... The selection transistors consist of array-driven selection transistors for all odd-numbered bits, which control the write signal of the corresponding odd-numbered STT-MRAM memory cell in the STT-MRAM memory cell array. The even-numbered array-driven selection transistors consist of array-driven selection transistors for all even-numbered bits, which control the write signal of the corresponding even-numbered STT-MRAM memory cell in the STT-MRAM memory cell array. The array selection circuit ASC selects one odd-numbered row STT-MRAM memory cell from the STT-MRAM memory cell array according to the instruction of the second row decoder, and selects one even-numbered row STT-MRAM memory cell from the STT-MRAM memory cell array according to the instruction of the third row decoder. The selected odd-numbered row STT-MRAM memory cell and one even-numbered row STT-MRAM memory cell are input to the sensing amplifier circuit SA for resistance comparison, and the comparison result is output. The PUF excitation of this invention consists of the outputs of a second column decoder, a second row decoder, and a third row decoder, allowing for multiple parallel combinations of STT-MRAM memory cells in each row. Simultaneously, the enable input of the second column decoder is also used as an excitation, further increasing the number of excitations and the parallel combinations of STT-MRAM memory cells. By using two row decoders, combinations between different STT-MRAM memory cell rows are achieved, further increasing the CRP space of the PUF. Furthermore, the odd-even row separation method not only doubles the number of excitations but also avoids errors caused by simultaneously connecting the same memory cell row to both ends of the sensing amplifier circuit SA.

[0036] like Figure 2In this invention, the STT-MRAM memory cell array consists of n×n magnetic tunnel junctions (MTJs). Only the high-resistance and low-resistance states of the MTJs are used. By grounding the bit line BL (source line SL), the storage state of the STT-MRAM memory cell can be configured as antiparallel AP (parallel P) to indicate logic "1" (logic "0"). Simultaneously, a reconfigurable PUF is achieved by writing different states to some or all of the MTJ bits.

[0037] like Figure 2 In this invention, the array selection circuit ASC consists of n transmission gates and n OR gates. The gate of each odd-numbered OR gate is connected to the output of a second-row decoder, and the drain of each odd-numbered OR gate is connected to the enable of an odd-numbered transmission gate. The outputs of all odd-numbered transmission gates are connected to one input of the sensing amplifier circuit SA. The gate of each even-numbered OR gate is connected to the output of a third-row decoder, and the drain of each even-numbered OR gate is connected to the enable of an even-numbered transmission gate. The outputs of all even-numbered transmission gates are connected to the other input of the sensing amplifier circuit SA. The array selection circuit ASC selects an odd-numbered row of STT-MRAM memory cells and an even-numbered row of STT-MRAM memory cells for comparison to obtain the PUF result. This avoids the need to compare a reference cell with a data cell to obtain the data stored in the STT-MRAM memory cell. On the one hand, this invention simplifies the circuit design and reduces area overhead by eliminating the need for a reference cell; on the other hand, by comparing with its own cells, the difference in the comparison path is greater, improving the reliability of the read circuit.

[0038] For each odd-numbered magnetic tunnel junction in a row, the electrode leading out from one end of the pinned layer of the magnetic tunnel junction is connected to the drain of an odd-numbered array memory access transistor and the source of an odd-numbered array excitation selection transistor, respectively. The electrode leading out from one end of the free layer of the magnetic tunnel junction is connected to the odd-numbered array BLs excitation (B0, B1, ..., B...). n-1 The odd-numbered array BLs is connected, and its excitation is controlled by the output signal of the corresponding first column decoder. The gate of each row of the odd-numbered array memory access transistors is connected to the first control signal WLs (W0, W1, ..., W...). n-1The circuit is configured such that the first control signal WLs is controlled by the output signal of the corresponding first row decoder, the source of each row of odd-numbered array memory access transistors is connected to the second control signal SLs (S0), the gate of each row of odd-numbered array excitation selection transistors is connected to the output of the corresponding second column decoder, and the drain of each row of odd-numbered array excitation selection transistors is connected to the input of the corresponding odd-numbered transmission gate in the array selection circuit ASC. Odd-numbered magnetic tunnel junctions can be written to individually, making their states different from even-numbered magnetic tunnel junctions; alternatively, odd-numbered magnetic tunnel junctions can be given individual excitation signals, making their excitation signals different from even-numbered magnetic tunnel junctions. The purpose of this is twofold: first, to increase the number of CRPs in the PUF, as different excitations for odd and even-numbered magnetic tunnel junctions lead to more combinations; and second, to prevent the same row from being simultaneously selected by the array selection circuit ASC and connected to both ends of the sensing amplifier circuit SA, which would cause errors.

[0039] For each even-numbered magnetic tunnel junction in a row, the electrode leading out from one end of the pinned layer of the magnetic tunnel junction is connected to the drain of an even-numbered array memory access transistor and the source of an even-numbered array excitation selection transistor, respectively. The electrode leading out from one end of the free layer of the magnetic tunnel junction is connected to the even-numbered array BLs excitation (E0, E1, ..., E...). n-1 The even-numbered array BLs is connected, and the excitation of each even-numbered array BLs is controlled by the output signal of the corresponding first column decoder. The gate of each even-numbered array memory access transistor is connected to the first control signal WLs (W0, W1, ..., W...). n-1 The first control signal WLs is controlled by the output signal of the corresponding first row decoder. The source of each row even array memory access transistor is connected to the second control signal SLs (S1). The gate of each row even array excitation selection transistor is connected to the output of the corresponding second column decoder. The drain of each row even array excitation selection transistor is connected to the input of the corresponding even bit transmission gate in the array selection circuit ASC.

[0040] In this invention, the rows and columns of the PUF generation path can be customized by the user. The excitation can be achieved by connecting a portion of the STT-MRAM memory cells in each row of STT-MRAM memory cells in parallel through the second column decoder. Odd-numbered rows and even-numbered rows can have different parallel connection methods. Then, the row selection signal is used to select two different rows of memory cells through the array selection circuit ASC for comparison and output the final PUF result.

[0041] like Figure 3 The present invention also provides a reconfigurable method for a reconfigurable strong PUF circuit with strong nonlinear response, specifically including the following steps:

[0042] a. By enabling the odd-numbered array BLs and even-numbered array BLs excitation through the first column decoder, and by enabling the odd-numbered array memory access transistors and even-numbered array memory access transistors through the first and second control signals of the first row decoder, all magnetic tunnel junction bits in the STT-MRAM memory array are initialized to the user-defined state. Specifically, by enabling the odd-numbered array BLs and even-numbered array BLs excitation through the first column decoder, and by enabling the odd-numbered array memory access transistors and even-numbered array memory access transistors through the first and second control signals of the first row decoder, the initial state of the STT-MRAM memory array is written, using the first control signal WLs(W0, W1, ..., W...). n-1 Each STT-MRAM memory cell can be individually written to either a parallel P or antiparallel AP state. Parallel P and antiparallel AP states represent "0" and "1" respectively. During the write phase, the second column decoder controls the activation of both the odd-array excitation selection transistor and the even-array excitation selection transistor to be written to "0". To write an STT-MRAM memory cell from parallel P to antiparallel AP, a high voltage VDD needs to be applied to the bit line BL while the source line SL is grounded, and the word line WL is written to "1" to complete the writing of logic "1". Conversely, to write an STT-MRAM memory cell from antiparallel AP to parallel P, a high voltage VDD needs to be applied to the source line SL while the bit line BL is grounded, and the word line WL is written to "1" to complete the writing of logic "0".

[0043] b. Input PUF excitation: The excitations of the odd-array excitation selection transistors and even-array excitation selection transistors are written into the STT-MRAM memory cell array through the second column decoder, obtaining the excitation-response pair of each STT-MRAM memory cell MRAM-PUF in the STT-MRAM memory cell array. During the read phase, the excitation C(D) of the odd (even) array excitation selection transistor can be written through the second column decoder. For an array with n columns, the input signals of the odd (even) array excitation selection transistors are provided by n second column decoders. Each second column decoder has two inputs: an enable signal H and an input signal I. When the decoder enable signal EN = H = "0", its 2-bit output is always "00"; when the decoder enable signal EN = H = "1", the decoder can output "01" and "10" respectively, depending on the input signal I. Specifically, when I = "0", the decoder outputs "01", and when I = "1", the decoder outputs "10". Therefore, both the enable signal H and the input signal I are used as part of the PUF excitation. The array selection circuit ASC selects one odd-numbered row STT-MRAM memory cell and one even-numbered row STT-MRAM memory cell for comparison. For an array with n rows, the input signals of the array selection circuit ASC are provided by two n-bit output second-row decoders and third-row decoders, with the input signals of the two row decoders being J0, J1, ..., J... m-1 and K0, K1, ..., K m-1For different input signals J and K, the second-row decoder and the third-row decoder can output signals X and Y respectively to select one odd-numbered row STT-MRAM memory cell and one even-numbered row STT-MRAM memory cell, and connect them to the sensing amplifier circuit SA. Therefore, both input signals J and K are used as part of the PUF excitation. When all second-column decoder enable signals are "0", the odd (even) array excitation selection transistors C(D) are all written to "0", and the odd (even) array excitation selection transistors are all in the off state. At this time, there is no discharge path in any array. When one second-column decoder enable signal is "1", a certain odd (even) array excitation selection transistor C(D) will be written to "1" through the decoder, causing the odd (even) array excitation selection transistor to turn on. At the same time, the corresponding odd (even) bit line BLs excitation B(E) is written to "0". The discharge current discharges through the odd (even) array excitation selection transistor and the magnetic tunnel junction MTJ. Due to manufacturing process errors, the resistance of different magnetic tunnel junctions MTJs is slightly different, resulting in different discharge rates in the discharge paths of different arrays. Finally, a comparison result is formed and output by the sensing amplifier circuit SA. Furthermore, when the enable signals of multiple second-column decoders are input as "1", multiple odd (even) array excitation selection transistors C(D) will be written as "1", thereby simultaneously selecting multiple odd (even) array excitation selection transistors in the STT-MRAM cell row to further increase the CRP space. When the odd (even) array excitation selection transistors C(D) select multiple excitation selection transistors in the STT-MRAM cell, the resistance consisting of one odd-numbered row of STT-MRAM cells or one even-numbered row of STT-MRAM cells is formed by connecting the resistances of all selected magnetic tunnel junctions (MTJs) in parallel.

[0044] Taking an n×n STT-MRAM memory cell array as an example, the specific input stimulus writing method during the read phase is illustrated in the diagram below. Figure 2 The second and third row decoders write array selection stimuli to select the two arrays to be compared, thus setting X... n-1 X n-2 …Write “00…10” to X1X0 to select the second row (the first row of even-numbered rows) of memory, and set Y… n-1 Y n-2 …Y1Y0 writes “01…00” to select the second-to-last row (the last row of odd-numbered rows) of memory cells. At this time, the odd (even) array excitation selection transistor excitation C(D) is written through the second column decoder, assuming… Figure 2If the enable pins of the second column decoder (omitted in the original text) are all input as "0", then the corresponding excitation signals C(D) are all written as "0", and the corresponding excitation selection transistors are all turned off, so that the STT-MRAM memory cells controlled by these excitation selection transistors do not participate in the discharge process. Then, the enable pin H0 of the second column decoder is set to "1", the input signal I0 is set to "1", and the enable pin H0 of the second column decoder n / 2-1 is set to "1". n / 2-1 Set to "1", input signal I n / 2-1 Set to "1", and finally C n-1 C n-2 …C1C0 is written as “01…01”, while B0 and B n-2 Writing "0" will result in two discharge current paths for the selected memory cells in odd-numbered rows. One path will discharge through the transistor controlled by C0 and the magnetic tunnel junction MTJ via B0 (the discharge path is indicated by the arrows), and the other path will discharge through C... n-2 Controlled transistors and magnetic tunnel junctions (MTJs) via B n-2 Discharge (discharge path is indicated by arrows), the total resistance of the current circuit is obtained by connecting the resistors of the two discharge branches in parallel. The stimulus is written through the second column decoder, enabling the decoder's n / 2 input H. n / 2 Set to "1", input signal I n / 2 Set to "0" to enable the second column decoder n-1 input H. n-1 Set to "1", input signal I n-1 Set to "1", and finally D n-1 D n-2 …D1D0 is written as “01…10”, while E1 and E n-2 Writing "0" will result in two discharge current paths for the selected memory cells in even rows. One path will discharge through the transistor controlled by D1 and the magnetic tunnel junction MTJ via E1 (the discharge path is indicated by the arrows), and the other path will discharge through D... n-2 Controlled transistors and magnetic tunnel junctions (MTJs) via E n-2 Discharge (discharge paths are indicated by arrows), the total resistance of the current circuit is obtained by connecting the resistances of the two discharge branches in parallel. The resistances between the transistors in the two rows of memory cells and the MRAM cells are compared, and a response is generated based on the discharge rates of the two discharge paths.

[0045] c. The array selection circuit ASC selects an odd-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the second row decoder, and selects an even-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the third row decoder. The selected odd-numbered row and even-numbered row STT-MRAM memory cells are input to the sensing amplifier circuit SA for resistance comparison. If the resistance of the odd-numbered row STT-MRAM memory cell is greater than that of the even-numbered row STT-MRAM memory cell, the sensing amplifier circuit SA outputs "1"; otherwise, the sensing amplifier circuit SA outputs "0". Specifically, because the transistors and STT-MRAM memory cells in an odd-numbered row STT-MRAM memory cell and an even-numbered row STT-MRAM memory cell have different resistances, the current discharge rates in the two discharge paths are different. If the resistance of path P2 is smaller, the current discharge rate of path P... n-2 If the resistance of path P2 is large, then Q discharges faster than QB, and Q will be pulled down to GND (logo "0"). The charging transistor corresponding to QB will turn on, and QB will be pulled up to VDD (logo "1"). If the resistance of path P2 is large, then the resistance of path P... n-2 If the resistance of Q is small, the discharge rate of Q is slower than that of QB. QB will be pulled down to GND, i.e., logic "0"; the charging transistor corresponding to Q will turn on, and Q will be pulled up to VDD, i.e., logic "1". The 1-bit output generated by the sensing amplifier circuit is the PUF output response generated by the MRAM-based strong magnetic PUF described in this invention under this excitation. Furthermore, if the array selection circuit is excited X... n-2 If Y1 is written with "1", then Q will pass through path P. n-2 During discharge, QB will discharge through path P2. Therefore, the discharge paths of Q and QB are reversed, which further increases the nonlinearity and robustness of the proposed strong magnetic PUF.

[0046] d. The user can re-execute step a to reset the state of the STT-MRAM memory cell array, obtaining a new physically unclonable function (PUF). Steps b and c are repeated to implement a reconfigurable physically unclonable function (PUF). The CRP space of the physically unclonable function (PUF) of this invention is very large. The decoder input signals H and I of the excitation selection signal, and the decoder input signals J and K of the array selection signal, are all used as the excitation signals of the PUF. For an N x M PUF, the length of its excitation signal is 2M + 2log2N, then the number of CRPs is... The CRP space of this PUF increases quadratically with the number of array rows and increases exponentially with the number of array columns.

[0047] In one technical solution of the present invention, a phase-change random access memory (PRAM) or a resistive random access memory (RRAM) based on phase change materials can be used to replace the magnetic tunnel junction, thereby utilizing the difference in resistance to control the discharge rate of the selected discharge path to achieve PUF.

[0048] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A reconfigurable strong PUF circuit with strong nonlinear response, characterized in that, include: STT-MRAM memory cell array, odd array memory access transistor, even array memory access transistor, odd array drive selection transistor, even array drive selection transistor, array selection circuit ASC, sense amplifier circuit SA, second row decoder, third row decoder. Each STT-MRAM storage cell in the STT-MRAM storage cell array is used to store data information "0" or "1" respectively; The odd-numbered array memory access transistors consist of all odd-numbered array memory access transistors, and the odd-numbered array memory access transistors access the corresponding odd-numbered STT-MRAM memory cells in the STT-MRAM memory cell array. The even-numbered array memory access transistors consist of all even-numbered array memory access transistors, and the even-numbered array memory access transistors access the STT-MRAM memory cells corresponding to even-numbered bits in the STT-MRAM memory cell array. The odd array excitation selection transistor is composed of all odd-numbered array excitation selection transistors, and the odd array excitation selection transistor is used to control the write signal of the corresponding odd-numbered STT-MRAM memory cell in the STT-MRAM memory cell array. The even-numbered array excitation selection transistor is composed of all even-numbered array excitation selection transistors, and the even-numbered array excitation selection transistor is used to control the write signal of the STT-MRAM memory cell corresponding to the even-numbered bit in the STT-MRAM memory cell array. The array selection circuit ASC selects an odd-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the second row decoder, and selects an even-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the third row decoder. The selected odd-numbered row of STT-MRAM memory cells and the selected even-numbered row of STT-MRAM memory cells are input into the sensing amplifier circuit SA for resistance comparison, and the comparison result is output.

2. The reconfigurable strong PUF circuit with strong nonlinear response according to claim 1, characterized in that, The STT-MRAM memory cell array consists of n×n magnetic tunnel junctions.

3. A reconfigurable strong PUF circuit with strong nonlinear response according to claim 2, characterized in that, The array selection circuit ASC consists of n transmission gates and n OR gates. The gate of each odd-numbered OR gate is connected to the output of a second-row decoder, and the drain of each odd-numbered OR gate is connected to the enable of an odd-numbered transmission gate. The outputs of all odd-numbered transmission gates are connected to one input of the sensing amplifier circuit SA. The gate of each even-numbered OR gate is connected to the output of a third-row decoder, and the drain of each even-numbered OR gate is connected to the enable of an even-numbered transmission gate. The outputs of all even-numbered transmission gates are connected to the other input of the sensing amplifier circuit SA.

4. A reconfigurable strong PUF circuit with strong nonlinear response according to claim 3, characterized in that, For each row of odd-numbered magnetic tunnel junctions, the electrode leading out from one end of the pinned layer of the magnetic tunnel junction is connected to the drain of an odd-numbered array memory access transistor and the source of an odd-numbered array excitation selection transistor, respectively, and the electrode leading out from one end of the free layer of the magnetic tunnel junction is connected to the excitation of the odd-numbered array BLs.

5. A reconfigurable strong PUF circuit with strong nonlinear response according to claim 4, characterized in that, The gate of each row of odd-numbered array memory access transistors is connected to the first control signal WLs, and the source of each row of odd-numbered array memory access transistors is connected to the second control signal SLs; the gate of each row of odd-numbered array excitation selection transistors is connected to the output of the corresponding second column decoder, and the drain of each row of odd-numbered array excitation selection transistors is connected to the input of the corresponding odd-numbered bit transmission gate in the array selection circuit ASC.

6. A reconfigurable strong PUF circuit with strong nonlinear response according to claim 3, characterized in that, For each even-numbered magnetic tunnel junction in a row, the electrode leading out from one end of the pinned layer of the magnetic tunnel junction is connected to the drain of an even-numbered array memory access transistor and the source of an even-numbered array excitation selection transistor, respectively, and the electrode leading out from one end of the free layer of the magnetic tunnel junction is connected to the excitation of the even-numbered array BLs.

7. A reconfigurable strong PUF circuit with strong nonlinear response according to claim 6, characterized in that, The gate of each row of even-numbered array memory access transistors is connected to the first control signal WLs, and the source of each row of even-numbered array memory access transistors is connected to the second control signal SLs; the gate of each row of even-numbered array excitation selection transistors is connected to the output of the corresponding second column decoder, and the drain of each row of even-numbered array excitation selection transistors is connected to the input of the corresponding even-numbered bit transmission gate in the array selection circuit ASC.

8. A reconfigurable strong PUF circuit with strong nonlinear response according to claim 4 or 6, characterized in that, The odd-numbered array BLs excitation and the even-numbered array BLs excitation are both controlled by the output signal of the corresponding first column decoder.

9. A reconfigurable strong magnetic PUF circuit with strong nonlinear response according to claim 5 or 7, characterized in that, The first control signal WLs is controlled by the output signal of the corresponding first row decoder.

10. A reconfigurable method for a reconfigurable strong PUF circuit with strong nonlinear response as described in claim 1, characterized in that, Specifically, the steps include the following: a. By enabling the odd array BLs activation, even array BLs activation, odd array memory access transistor activation, and even array memory access transistor activation, all STT-MRAM memory cell bits in the STT-MRAM memory cell array are initialized to the set state; b. Input PUF stimulus, and write the stimulus of odd array stimulus selection transistor and even array stimulus selection transistor into the STT-MRAM memory cell array to obtain the stimulus-response pair of each STT-MRAM memory cell in the STT-MRAM memory cell array; c. The array selection circuit ASC selects an odd-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the second row decoder. The array selection circuit ASC selects an even-numbered row of STT-MRAM memory cells from the STT-MRAM memory cell array according to the instructions of the third row decoder. The selected odd-numbered row STT-MRAM memory cell and the even-numbered row STT-MRAM memory cell are input to the sensing amplifier circuit SA for resistance comparison. If the resistance of the odd-numbered row STT-MRAM memory cell is greater than the resistance of the even-numbered row STT-MRAM memory cell, the sensing amplifier circuit SA outputs "1"; otherwise, the sensing amplifier circuit SA outputs "0". d. By resetting the state of the STT-MRAM memory cell array through step a, a new physically unclonable function (PUF) is obtained. Steps b and c are repeated to realize a reconfigurable physically unclonable function (PUF).

Images