Process temperature measurement device manufacturing technology and its calibration and data interpolation method

Abstract

The present application relates to process temperature measurement device manufacturing techniques and methods for calibration and data interpolation thereof. The present invention discloses a process condition measurement wafer assembly. In one embodiment, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit elements and interposed between the top and bottom substrates. In another embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom and top substrates. In one embodiment, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and diffuse a voltage potential across the bottom and top substrates.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of September 6, 2019, application number 201980057820.5, and invention name “Process temperature measurement device manufacturing technology and its correction and data interpolation method”.

[0003] Cross-reference to related applications

[0004] This application claims priority under 35 U.S.C. §119(e) to U.S. Provisional Patent Application No. 62 / 727,633, filed on September 6, 2018, entitled “PROCESS TEMPERATURE MEASUREMENT DEVICE FABRICATION TECHNIQUES AND METHODS OF CALIBRATION AND DATA INTERPOLATION OF THE SAME,” which designates Farhat A. Quli, Andrew Nguyen, and James Richard Bella as inventors, the entire contents of which are incorporated herein by reference. Technical Field

[0005] The present invention relates generally to monitoring wafers along a semiconductor process line, and in particular to a system and method for process condition measurement of a wafer assembly. Background Art

[0006] As the tolerances of process conditions in semiconductor device processing environments continue to shrink, the need for improved process monitoring systems continues to increase. Thermal uniformity within a processing system is one such condition. Current methods are unable to monitor temperatures at the extreme conditions (e.g., high temperatures) required by current processing technologies without contaminating the associated chambers. One previous method of monitoring process conditions involves the use of process condition measurement wafers. Conventional process condition measurement wafers may include a wireless data acquisition system that measures and records process conditions (e.g., temperature). However, conventional process condition measurement wafers are often subject to temperature inaccuracies attributable to internal structural variations and may not be able to withstand the energy flux of current and future processing systems (e.g., epitaxial chambers, plasma etch chambers). Therefore, it would be desirable to provide a system and method that allows high-temperature measurements to be made using instrumented wafers to monitor the conditions of semiconductor device processing lines. Summary of the Invention

[0007] A process condition measurement wafer assembly is disclosed. In one embodiment, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit assemblies and interposed between the top substrate and the bottom substrate. In another embodiment, the process condition measurement wafer assembly includes one or more shielding layers formed between the bottom substrate and the top substrate. In one embodiment, the one or more shielding layers are configured to electromagnetically shield the one or more electronic components and to diffuse a voltage potential across the bottom substrate and the top substrate.

[0008] A process condition measurement wafer assembly is disclosed. In one embodiment, the process condition measurement wafer assembly includes a bottom substrate and a top substrate. In another embodiment, the process condition measurement wafer assembly includes one or more electronic components disposed on one or more printed circuit assemblies and interposed between the top substrate and the bottom substrate. In another embodiment, at least one of the bottom substrate or the top substrate is configured to electromagnetically shield the one or more electronic components and to diffuse a voltage potential across the bottom substrate and the top substrate.

[0009] A method is disclosed. In one embodiment, the method may include: obtaining a set of temperature measurements from a set of temperature sensors distributed across a process condition measurement wafer and a set of heat flux measurements from a set of heat flux sensors distributed across the process condition measurement wafer under isothermal conditions; calibrating the set of temperature measurements and the set of heat flux measurements obtained under isothermal conditions; applying a known heat flux to the process condition measurement wafer; obtaining an additional set of temperature measurements from the set of temperature sensors and an additional set of heat flux measurements from the set of heat flux sensors during application of the known heat flux; identifying a temperature variation observed across the set of temperature sensors during application of the known heat flux; identifying a heat flux-temperature variation relationship by correlating the known heat flux with the identified temperature variation of the set of temperature sensors; obtaining a set of test temperature measurements from the set of temperature sensors and a set of test heat flux measurements from the heat flux sensors under unknown heat flux conditions; and adjusting the set of test temperature measurements based on the set of test heat flux measurements and the identified heat flux-temperature variation relationship.

[0010] It should be understood that both the foregoing summary and the following detailed description are exemplary and explanatory only and are not necessarily restrictive of the claimed invention.The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and together with the summary, serve to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The numerous advantages of the present invention may be better understood by those skilled in the art with reference to the accompanying drawings, in which:

[0012] Figure 1A is a simplified cross-sectional view of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0013] Figure 1B is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0014] Figure 1C is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0015] Figure 1D is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0016] Figure 1E is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0017] Figure 1F is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0018] Figure 2A is a simplified cross-sectional view of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0019] Figure 2B is a simplified cross-sectional view of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0020] Figure 3 is a simplified cross-sectional view of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0021] Figure 4A is a simplified cross-sectional view of a process condition measurement wafer assembly communicatively coupled to a remote data system in accordance with one or more embodiments of the present invention.

[0022] Figure 4B is a simplified block diagram illustration of a process condition measurement wafer assembly communicatively coupled to a remote data system in accordance with one or more embodiments of the present invention.

[0023] Figure 5 is a simplified cross-sectional view of a process condition measurement wafer assembly according to one or more embodiments of the present invention.

[0024] Figure 6 is a flow chart of a method for calculating the temperature of a measured wafer assembly across process conditions in accordance with one or more embodiments of the present invention. DETAILED DESCRIPTION

[0025] Reference will now be made in detail to the disclosed subject matter as illustrated in the accompanying drawings.

[0026] Generally speaking Figures 1A to 5 , shows and describes a system and method for process condition measurement of a wafer assembly according to one or more embodiments of the present invention.

[0027] Conventional process condition measurement wafers contain measurement electronics placed between silicon wafers. The silicon wafers are designed to shield the measurement electronics from the extreme conditions within the process chamber (e.g., high RF, high heat flux, high electromagnetic radiation). The silicon wafers within these conventional process condition measurement wafers are typically coupled via one or more discrete ohmic contacts between the respective silicon wafers. However, these ohmic contacts result in high current density within and around the contacts, potentially leading to high potentials across the process condition measurement wafer. Furthermore, the complex internal structure of conventional process condition measurement wafers can further lead to temperature inaccuracies due to the internal structure of the wafers themselves.

[0028] Accordingly, embodiments of the present invention relate to a system and method that addresses one or more of the shortcomings of previous approaches identified above. Embodiments of the present invention relate to a process condition measurement wafer assembly that improves the accuracy, precision, and construction of wafer-based process condition measurement devices. Additional embodiments of the present invention relate to a process condition measurement wafer assembly that includes one or more electromagnetic shielding layers disposed between a top substrate and a bottom substrate. Further embodiments of the present invention relate to a process condition measurement wafer assembly that includes one or more thermal pillars configured to facilitate heat transfer throughout the apparatus.

[0029] Embodiments of the present invention relate to a process condition measurement wafer assembly capable of operating at high temperatures (e.g., 600° C. to 800° C.). This process condition measurement wafer assembly can be used with semiconductor processing chambers operating at high temperatures (e.g., epitaxial chambers, plasma etching chambers). In some embodiments, the process condition measurement wafer assembly of the present invention includes a top substrate, a bottom substrate, and one or more shielding layers, whereby onboard electronic components (e.g., sensors, processors, memory, power supplies) and / or other sensitive devices are interposed between the top and bottom substrates and shielded by the one or more shielding layers. The use of instrumented substrates is described in U.S. patent application Ser. No. 15 / 277,753, filed Sep. 27, 2016, the entire contents of which are incorporated herein by reference. Instrumented substrates are described in further detail in U.S. Patent No. 7,540,188B2, filed on May 1, 2016, entitled “PROCESS CONDITION MEASURING DEVICE WITH SHIELDING,” and U.S. Patent Application No. 15 / 277,792, filed on September 27, 2016, entitled “ENCAPSULATED INSTRUMENTED SUBSTRATE APPARATUS FORACQUIRING MEASUREMENT PARAMETERS IN HIGH TEMPERATURE PROCESS APPLICATIONS,” both of which are incorporated herein by reference in their entireties.

[0030] Figure 1A FIG2 is a simplified cross-sectional view of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention. The process condition measurement wafer assembly 100 may include, but is not limited to, a top substrate 104 and a bottom substrate 102. The process condition measurement wafer assembly 100 may include one or more electronic components 106.

[0031] like Figure 1A, the top substrate 104 can be mechanically coupled to the bottom substrate 102. The top substrate 104 and / or the bottom substrate 102 of the process condition measurement wafer assembly 100 can include any substrate known in the art. In some embodiments, the top substrate 104 and / or the bottom substrate 102 of the process condition measurement wafer assembly 100 can include a wafer. For example, the top substrate 104 and / or the bottom substrate 102 can include, but are not limited to, a semiconductor substrate, a glass wafer (e.g., a fused silica glass wafer, a borosilicate glass wafer), a crystallized wafer (e.g., a crystallized quartz wafer, a silicon wafer), a wafer formed of one or more compounds (e.g., silicon carbide, silicon nitride), and the like. For example, the process condition measurement wafer assembly 100 can include any substrate that results in negligible contamination in a semiconductor processing environment, such as, but not limited to, a wafer formed of one or more of silicon, silicon carbide, silicon nitride, gallium nitride, gallium arsenide, germanium, gallium, indium, or silicon dioxide (e.g., quartz).

[0032] In one embodiment, the process condition measurement wafer assembly 100 may include one or more cavities 107 between the top substrate 104 and the bottom substrate 102. For example, Figure 1A , the process condition measurement wafer assembly 100 may include a cavity 107 within the bottom substrate 102. It should be noted herein that the process condition measurement wafer assembly 100 may include one or more cavities 107 within the top substrate 104 and / or the bottom substrate 102. For example, the cavity 107 may include a portion of the cavity 107 within the top substrate 104 and a portion of the cavity 107 within the bottom substrate 102.

[0033] In another embodiment, one or more electronic components 106 may be interposed between the top substrate 104 and the bottom substrate 102. For example, Figure 1A , one or more electronic components 106 may be disposed within one or more cavities 107. In an embodiment, the one or more electronic components 106 are disposed between the top substrate 104 and the bottom substrate 102 such that the one or more electronic components 106 are sealed (e.g., hermetically sealed) between the top substrate 104 and the bottom substrate 102. The one or more electronic components 106 may include any electronic components configured to monitor process conditions within a process system (e.g., an epitaxial chamber, a plasma etch chamber). In this regard, the one or more electronic components 106 may include any electronic components known in the art, including, but not limited to, sensor devices (e.g., temperature sensors, pressure sensors, chemical sensors, radiation sensors, heat flux sensors, voltage sensors), power supplies, one or more processors, memory, communication circuitry, and the like.

[0034] In some embodiments, a plurality of electronic components 106 may be communicatively coupled to one another within the process condition measurement wafer assembly 100. In another embodiment, the one or more electronic components 106 may be disposed on one or more printed circuit components 105, interposed between the top substrate 104 and the bottom substrate 102. In this regard, the one or more electronic components 106 may be communicatively coupled via the one or more printed circuit components 105. The one or more printed circuit components 105 may include any electronic component known in the art, including but not limited to a printed circuit board, a printed wiring board, and the like. Similarly, the one or more printed circuit components 105 may be formed from any material known in the art, including but not limited to ceramics, silicon, inorganic materials, and the like.

[0035] Figure 1B is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention.

[0036] As previously described herein, the top substrate 104 and the bottom substrate 102 may be mechanically coupled to each other. In some embodiments, the process condition measurement wafer assembly 100 may further include one or more shielding layers 108. The one or more shielding layers 108 may be formed between the top substrate 104 and the bottom substrate 102. For example, the one or more shielding layers 108 may include one or more films disposed / deposited on the surface of the top substrate 104 and / or the bottom substrate 102. For example, Figure 1B As shown in , one or more shielding layers 108 may be disposed across at least a portion of the upper surface of the bottom substrate 102 and / or across at least a portion of the lower surface of the top substrate 104 .

[0037] It is contemplated herein that the one or more shielding layers 108 may comprise any layer / film known in the art that is configured to electromagnetically shield the one or more electronic components 106 and / or spread a voltage potential across the top substrate 104 and / or the bottom substrate 102. In some embodiments, the one or more shielding layers 108 may be formed of a conductive material. In additional and / or alternative embodiments, the one or more shielding layers 108 may comprise a light blocking film. In this regard, the one or more shielding layers 108 may comprise one or more opaque films. For example, the one or more shielding layers 108 may include, but are not limited to, a material that absorbs radiation that passes through the top substrate 104 to the bottom substrate 102.

[0038] refer to Figures 1C to 1F One or more shielding layers 108 are further contemplated.

[0039] Figure 1C FIG. 1 is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention. Figure 1CAs shown in FIG. 1 , the one or more shielding layers 108 may include, but are not limited to, an adhesive layer 110 and a plurality of conductive particles 112 .

[0040] In some embodiments, shielding layer 108 formed between at least a portion of top substrate 104 and at least a portion of bottom substrate 102 may include adhesive layer 110. Adhesive layer 110 may be formed of any adhesive material known in the art that is configured to mechanically couple substrates. In another embodiment, shielding layer 108 may include conductive particles 112 suspended within adhesive layer 110. For example, Figure 1C , shielding layer 108 may include a plurality of conductive particles 112 suspended within adhesive layer 110. In some embodiments, conductive particles 112 may be evenly distributed throughout adhesive layer 110. In some embodiments, the inclusion of conductive particles 112 within shielding layer 108 may create electrical contact between at least a portion of top substrate 104 and at least a portion of bottom substrate 102. Accordingly, conductive particles 112 may be formed using any conductive material known in the art. Similarly, adhesive layer 110 may be formed from a conductive material to further facilitate electrical contact between top substrate 104 and bottom substrate 102.

[0041] It is contemplated herein that the inclusion of the conductive particles 112 within the shielding layer 108 can create electrical contacts between the top substrate 104 and the bottom substrate 102 and / or between conductive layers deposited on these respective substrates. These electrical contacts can facilitate spreading the voltage potential throughout the process condition measurement wafer assembly 100 and / or between the top substrate 104 and the bottom substrate 102. Furthermore, these electrical contacts and the conductive particles / layer can provide electrical and electromagnetic shielding for the electronic components 106 of the process condition measurement wafer assembly 100.

[0042] Figure 1D FIG. 1 is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention. Figure 1D As shown in FIG. 1 , the one or more shielding layers 108 may include, but are not limited to, an adhesive layer 110 and a plurality of conductive structures 114 .

[0043] In additional and / or alternative embodiments, electrical contact between portions of the top substrate 104 and portions of the bottom substrate 102 may be facilitated by using conductive structures 114. Figure 1D, a plurality of conductive structures 114 may be fabricated on a surface of at least one of the top substrate 104 or the bottom substrate 102 such that the conductive structures 114 electrically couple at least a portion of the top substrate 104 and at least a portion of the bottom substrate 102. The plurality of conductive structures 114 may include any shape or type of conductive structures known in the art. For example, the plurality of conductive structures 114 may include a plurality of protrusions formed on a surface of at least one of the top substrate 104 or the bottom substrate 102. As another example, the plurality of conductive structures 114 may include a plurality of conical segments (e.g., cones) and / or bumps formed on a surface of the top substrate 104 and / or a surface of the bottom substrate 102. The plurality of conductive structures 114 may be formed using any material known in the art, including, but not limited to, one or more conductive metals.

[0044] The plurality of conductive structures 114 can be formed / fabricated on the surface of the top substrate 104 and / or the bottom substrate 102 using any technique known in the art. For example, the conductive structures 114 can be deposited onto the surface of the top substrate 104 and / or the bottom substrate 102 using an electroplating process or a wire bonding bump process. In another embodiment, the adhesive layer 110 can be formed around the plurality of conductive structures 114.

[0045] Figure 1E is a simplified cross-sectional view of a portion of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention.

[0046] In one embodiment, the one or more shielding layers 108 are formed via direct wafer-to-wafer bonding. Figure 1E , one or more shielding layers 108 may be formed between the top substrate 104 and the bottom substrate 102 via adhesive-free silicon-to-silicon bonding. In some embodiments, the top substrate 104 and / or the bottom substrate 102 may serve as the one or more shielding layers 108. Thus, the top substrate 104 and / or the bottom substrate 102 may be configured as the one or more shielding layers 108. In this regard, in addition to or in lieu of the one or more shielding layers 108, the top substrate 104 and / or the bottom substrate 102 may also be used to electromagnetically shield the one or more electronic components 106 and diffuse voltage potentials. For example, as Figure 1E As shown in , the top substrate 104 directly bonded to the bottom substrate 102 may include a doped silicon substrate such that the top substrate 104 acts as a shielding layer 108 .

[0047] It is contemplated herein that forming the shield layer 108 via direct wafer-to-wafer bonding (eg, silicon-to-silicon bonding) may be carried out with one or more intermediate films 116 interposed between the top substrate 104 and the bottom substrate 102 .

[0048] In some embodiments, as Figure 1F As shown in FIG, the one or more shielding layers 108 of the process condition measurement wafer assembly 100 include one or more intermediate films 116 and one or more metal contacts 118. It is contemplated herein that the electrical coupling between the top substrate 104 and the bottom substrate 102 can be further facilitated by direct metal-to-metal thermocompression bonding at discrete locations to improve electrical conductivity. Accordingly, electrical conductivity can be improved by including one or more additional metal contacts 118 within the adhesive-free silicon-to-silicon bond. For example, Figure 1F , the one or more intermediate films 116 interposed between the top substrate 104 and the bottom substrate 102 may include a plurality of metal contacts 118. As another example, the one or more intermediate films 116 may include one or more metal film layers in order to improve electrical coupling between the top substrate 104 and the bottom substrate 102.

[0049] In additional and / or alternative embodiments, the one or more shielding layers 108 may include one or more films deposited via a transient liquid phase bonding process on at least one of the top substrate 104 or the bottom substrate 102. For example, metal films deposited on the surfaces of the top substrate 104 and the bottom substrate 102 may react with each other to form an alloy in order to form the one or more shielding layers 108 and bond the top substrate 104 and the bottom substrate 102.

[0050] Figure 2A 1 is a simplified cross-sectional view of the process condition measurement wafer assembly 100. The process condition measurement wafer assembly 100 may include, but is not limited to, a top substrate 104, a bottom substrate 102, one or more electronic components 106, one or more printed circuit components 105, and one or more layers 208. It should be noted herein that the one or more layers 208 may include the top substrate 104, the bottom substrate 102, the one or more electronic components 106, the one or more printed circuit components 105, and the one or more layers 208. Figures 1B to 1F One or more adhesive layers and / or one or more shielding layers 108 are discussed.

[0051] As previously described herein, one problem associated with measuring wafers at conventional process conditions is poor thermal management and heat accumulation, which can lead to failure of electronic components, adhesive layers, or both. Figure 2A As shown in FIG, the process condition measurement wafer assembly 100 may be exposed to a high heat flux 202. Although an effective thermal conductive path may exist between the direct coupling of the substrate 104 and the bottom substrate 102, the thermal conductive path may be substantially reduced at locations where the electronic components 106 and / or printed circuit components 105 are interposed between the top substrate 104 and the bottom substrate 102. These reduced thermal conductive paths may therefore result in high temperature areas 203 and heat accumulation, such as Figure 2A As shown in .

[0052] Accordingly, some embodiments of the present invention relate to a process condition measurement wafer assembly 100 having an improved thermal management configuration to improve the thermal robustness of the process condition measurement wafer assembly 100. Figure 2B To further understand.

[0053] Figure 2B is a simplified cross-sectional view of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention.

[0054] In some embodiments, the process condition measurement wafer assembly 100 may include one or more thermal pillar structures 206a, 206b configured to facilitate an efficient thermal conductive path between at least a portion of the top substrate 104 and at least a portion of the bottom substrate 102. For example, the one or more thermal pillar structures 206a, 206b may be machined into at least one of the top substrate 104 or the bottom substrate 102. As another example, the one or more thermal pillar structures 206a, 206b may be metal-plated onto at least one of the top substrate 104 or the bottom substrate 102. In some embodiments, the one or more printed circuit components 105 may include one or more ports, holes, or apertures configured to receive the one or more pillar structures 206a, 206b. Accordingly, the one or more pillar structures 206a, 206b can be configured to create an effective thermally conductive path from the top substrate 104 through one or more ports (e.g., holes, apertures, or the like) within the printed circuit assembly 105 to the bottom substrate 102. The one or more pillar structures 206a, 206b can be formed of any material known in the art, including but not limited to semiconductor materials, metal materials, or the like. For example, the one or more pillar structures 206a, 206b can include silicon pillars, conductive metal pillars, and the like.

[0055] Figure 3 1 is a simplified cross-sectional view of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention. The process condition measurement wafer assembly 100 may include, but is not limited to, a top substrate 104, a bottom substrate 102, one or more electronic components 106, one or more printed circuit components 105, and one or more layers 208. It should be noted herein that the one or more layers 208 may include the layers previously described herein. Figures 1B to 1F One or more adhesive layers and / or one or more shielding layers 108 are discussed. Figure 3 A first cavity 107a, a second cavity 107b, and a third cavity 107c are shown.

[0056] In one embodiment, the one or more printed circuit components 105 can be coupled to at least one of the top substrate 104 or the bottom substrate 102. For example, the one or more printed circuit components 105 can be brazed and / or directly bonded to at least one of the top substrate 104 or the bottom substrate 102. For example, as previously described herein, the inorganic printed circuit components 105 can be directly bonded to the bottom substrate 102. It should be noted herein that directly bonding the one or more printed circuit components 105 to the top substrate 104 and / or the bottom substrate can improve thermal conductivity and thermal management of the process condition measurement wafer assembly 100.

[0057] Figure 4A is a simplified cross-sectional view of a process condition measurement wafer assembly 100 communicatively coupled to a remote data system 402 in accordance with one or more embodiments of the present invention. Figure 4B is a simplified block diagram illustration of a process condition measurement wafer assembly communicatively coupled to a remote data system in accordance with one or more embodiments of the present invention.

[0058] In some embodiments, as previously described herein, the process condition measurement wafer assembly 100 includes one or more electronic components 106, which may include one or more sensors. In another embodiment, the one or more electronic components 106 may be disposed at one or more locations across the printed circuit assembly 105 and communicatively coupled to each other via one or more wired and / or wireless connections. The one or more electronic components 106 may include, but are not limited to, a communication circuit 410, one or more processors 412, a memory 414, one or more sensors 416, and a power supply 418. In some embodiments, the power supply 418 may include any power source known in the art, including, but not limited to, a battery, a wirelessly rechargeable battery, and the like.

[0059] For purposes of the present invention, the term "processor" may be broadly defined to encompass any device having one or more processors (e.g., CPUs) or logic components (e.g., ASICs) that execute instructions from internal or external memory 414. In this sense, the one or more processors 412 may include any microprocessor-type or logic device configured to execute algorithms and / or instructions. It should be recognized that the steps described throughout the present invention may be performed by a single processor 412 or, alternatively, multiple processors 412. The memory 414 may include read-only memory, random access memory, a solid-state drive, flash memory, EPROM, EEPROM, and the like.

[0060] In one embodiment, the one or more processors 412 are configured to execute a set of program instructions stored in the memory 414, which are configured to cause the one or more processors 412 to perform various steps / functions of the present invention. For example, the one or more processors 412 may be configured to: generate one or more control signals configured to cause the one or more sensors 416 to acquire one or more measurement parameters; store the acquired measurement parameters in the memory 414; calculate one or more values ​​based on the one or more measurement parameters; and transmit the one or more measurement parameters and / or one or more determined values ​​to the remote data system 402 via the communication circuit 410. Each of these steps will be described herein.

[0061] In one embodiment, the one or more processors 412 of the process condition measurement wafer assembly 100 are configured to generate one or more control signals configured to cause one or more sensors 416 to acquire one or more measurement parameters. In this regard, the one or more sensors 416 positioned at one or more locations within the process condition measurement wafer assembly 100 / printed circuit assembly 105 may be configured to acquire one or more measurement parameters (e.g., thermocouple voltage, resistance from a resistance temperature device, voltage / signal from a pressure sensor, voltage / signal from a radiation sensor, voltage / signal from a chemical sensor, and the like). It should be noted herein that the one or more sensors 416 may be configured to acquire measurement parameters associated with any parameter or characteristic to be monitored throughout the processing system (e.g., temperature, heat flux, pressure, and the like).

[0062] It should be noted that the one or more sensors 416 can be formed to have any shape and distributed in any manner across the process conditions measuring the wafer assembly 100 (e.g., across the bottom substrate 102). In this regard, the one or more sensors 416 can be selectively distributed across the process conditions measuring the wafer assembly 100 in order to obtain measurement parameters in selected locations associated with each sensor 416. It is further contemplated herein that the one or more sensors 416 can comprise discrete sensor devices and / or can be integrated into the top substrate 104 and / or the bottom substrate 102.

[0063] It should be further noted that the one or more sensors 416 may include any measuring device known in the art. For example, the one or more sensors 416 may include, but are not limited to, heat / temperature sensors, pressure sensors, radiation sensors, chemical sensors, voltage sensors, heat flux sensors, and the like. For example, in the case of temperature measurement, the one or more sensors 416 may include, but are not limited to, one or more thermocouple (TC) devices (e.g., thermoelectric junctions) or one or more resistance temperature devices (RTDs) (e.g., thin film RTDs). In another example, in the case of pressure measurement, the one or more sensors 416 may include, but are not limited to, piezoelectric sensors, capacitive sensors, optical sensors, potentiometric titration sensors, and the like. In another example, in the case of radiation measurement, the one or more sensors 416 may include, but are not limited to, one or more photodetectors (e.g., photovoltaic cells, photoresistors, and the like) or other radiation detectors (e.g., solid-state detectors). In another example, in the case of chemical sensors, the one or more sensors 416 may include, but are not limited to, one or more chemistors, gas sensors, pH sensors, and the like.

[0064] In another embodiment, the one or more processors 412 of the process condition measurement wafer assembly 100 are configured to store the acquired measurement parameters in the memory 414 .

[0065] In another embodiment, the one or more processors 412 of the process condition measurement wafer assembly 100 are configured to calculate one or more values ​​based on one or more acquired measurement parameters. The one or more processors 412 can be configured to calculate any value known in the art based on the acquired measurement parameters. For example, in the case of temperature, the one or more sensors 416 can be configured to acquire a thermocouple voltage (measurement parameter) indicating temperature, and the one or more processors 412 can be configured to calculate the temperature based on the thermocouple voltage.

[0066] In another embodiment, the one or more processors 412 of the process condition measurement wafer assembly 100 are configured to transmit the one or more measurement parameters and / or the one or more determined values ​​to the remote data system 402 via the communication circuit 410. In this regard, the one or more electronic components 106 of the process condition measurement wafer assembly 100 may be communicatively coupled to the remote data system 402 via the communication circuit 410. The one or more electronic components 106 of the process condition measurement wafer assembly 100 may be communicatively coupled to the remote data system 402 using any wired or wireless communication protocol known in the art.

[0067] In one embodiment, one or more electronic components 106 of the process condition measurement wafer assembly 100 may be wirelessly coupled to a remote data system 402. The one or more electronic components 106 may be wirelessly coupled to the remote data system 402 in any suitable manner. The communication circuit 410 may include any communication circuit and / or communication device known in the art of communication. For example, the communication circuit 410 may include, but is not limited to, one or more communication antennas (e.g., communication coils).

[0068] In one embodiment, the communication circuit 410 is configured to establish a communication link between the process condition measurement wafer assembly 100 and the off-substrate remote data system 402. Furthermore, the communication circuit 410 may be communicatively coupled to one or more processors 412, a memory 414, one or more sensors 416, and a power supply 418. In this regard, the one or more processors 412 may be configured to generate one or more control signals configured to cause the communication circuit 410 to transmit one or more measurement parameters and / or one or more determined values ​​to the remote data system 402.

[0069] In one embodiment, the remote data system 402 includes communication circuitry 404 adapted to establish a communication link between the on-substrate communication circuitry 410 and the remote data system 402. For example, the communication circuitry 404 may establish a communication link between the on-substrate communication circuitry 410 and the remote data system 402 using radio frequency (RF) signals, 3G, 4G, 4G LTE, 5G, WiFi protocols, Bluetooth protocols, and the like.

[0070] As previously discussed herein, the one or more processors 412 of the process condition measurement wafer assembly 100 can be configured to determine values ​​associated with the acquired measurement parameters. In additional and / or alternative embodiments, the values ​​associated with the acquired measurement parameters can be determined / calculated by the one or more processors 420 of the remote data system 402. For example, the communication circuit 410 can transmit the acquired measurement parameters to the remote data system 402, and the one or more processors 420 of the remote data system 402 can calculate one or more values ​​based on the acquired measurement parameters acquired by the sensor 416.

[0071] In another embodiment, the remote data system 402 may be configured to map (or correlate) one or more values ​​calculated by the processor 412 and / or the remote data system 402 based on one or more measurement parameters acquired by the sensor 416. The remote data system 402 may be configured to map (or correlate) the one or more values ​​to (or with) an acquisition location (e.g., a "measurement location") on the process condition measurement wafer assembly 100. In another embodiment, the remote data system 402 reports the mapped values ​​to a user interface. For example, the remote data system 402 may report the mapped values ​​to one or more of a desktop computer, a laptop computer, a tablet computer, a handheld device, a memory, or a server.

[0072] As previously described herein, some conventional process condition measurement wafers often suffer from temperature inaccuracies attributable to internal configuration variations. For example, for a conventional process condition measurement wafer, temperature readings (e.g., measurement parameters) may be collected at 65 discrete locations across the wafer. When these acquired temperature readings are displayed in a 2-D map, the wafer's temperature can be simply interpolated between sensor locations / measurement locations. Depending on the source and magnitude of temperature non-uniformity within the conventional process condition measurement wafer (e.g., chuck temperature, heat flux, wafer cooling), the accuracy of the interpolated temperature may vary, resulting in inaccurate temperature measurements.

[0073] Accordingly, some embodiments of the present invention relate to a process condition measurement wafer assembly 100 and techniques for improving the accuracy of temperature readings by correcting for conduction variations. Figure 5 To further understand.

[0074] Figure 5 is a simplified cross-sectional view of a process condition measurement wafer assembly 100 according to one or more embodiments of the present invention.

[0075] like Figure 5 , a first electronic component 106a (e.g., a first sensor) disposed on a first printed circuit assembly 105a can be disposed within a first cavity 107a between the top substrate 104 and the bottom substrate 102. Similarly, a second electronic component 106b (e.g., a second sensor) disposed on a second printed circuit assembly 105b can be disposed within a second cavity 107b between the top substrate 104 and the bottom substrate 102. Comparing the relative arrangement of the cavities 107a, 107b and the electronic components 106a, 106b, it can be seen that the first cavity 107a is larger than the second cavity 107b. In this regard, the first electronic component 106a is further removed from / separated from the bottom substrate 102 and, therefore, is further separated from the bottom substrate 102 by a greater thermal resistance than the second electronic component 106b.

[0076] In a perfectly isothermal environment, the first electronic component 106a (e.g., the first sensor) and the second electronic component 106a (e.g., the second sensor) would obtain the same temperature measurement (e.g., the measurement parameter). However, manufacturing processes are typically not performed in a perfectly isothermal environment. During a manufacturing process (e.g., an etching process), the bottom substrate 102 may be cooled while a heat flux 202 is applied to the top substrate 102. In this case, the first sensor's reading will be higher than the second sensor's because it is further removed from the cooled bottom substrate 102 and, therefore, more isolated from the cooling.

[0077] Thus, it can be seen that structural variations (e.g., different sizes of cavities 107a, 107b) may result in errors / differences in the acquired measurement parameters. Other structural variations that may result in differences between the acquired measurement parameters and / or calculated values ​​may include, but are not limited to, variations in the size / shape of the electronic component 106, bonding to different surfaces (e.g., coupling to the top substrate 104, coupling to the bottom substrate 102), variations in adhesive and / or conductive properties, and the like. Furthermore, as the temperature gradient and heat flux 202 become larger, these structural variations may result in increased differences between the acquired measurement parameters and / or calculated values.

[0078] Accordingly, some embodiments of the present invention relate to quantifying and correcting the effects of configuration variations on acquired measurement parameters and / or calculated values. By quantifying the effects of configuration variations on acquired measurement parameters and correcting (e.g., removing) the determined effects, the systems and methods of the present invention can achieve more efficient and accurate process monitoring.

[0079] In one embodiment, the one or more processors 420 of the remote data system 402 are configured to execute a set of program instructions stored in the memory 422, which are configured to cause the one or more processors 420 to perform various steps / functions of the present invention. For example, the one or more processors 420 may be configured to: obtain a set of temperature measurements from a set of temperature sensors distributed across the process condition measurement wafer assembly 100 and obtain a set of heat flux measurements from a set of heat flux sensors distributed across the process condition measurement wafer assembly 100 under isothermal conditions; correct the set of temperature measurements and the set of heat flux measurements obtained under isothermal conditions; apply a known heat flux to the process condition measurement wafer assembly 100; obtain an additional set of temperature measurements from the set of temperature sensors and obtain a set of heat flux measurements from the set of heat flux sensors during the application of the known heat flux; The set of heat flux sensors acquires a set of additional heat flux measurements; identifies a temperature variation observed across the set of temperature sensors during application of a known heat flux; identifies a heat flux-temperature variation relationship by correlating the known heat flux with the identified temperature variation of the set of temperature sensors; acquires a set of test temperature measurements from the set of temperature sensors and a set of test heat flux measurements from the heat flux sensors under unknown heat flux conditions; and adjusts the set of test temperature measurements based on the set of test heat flux measurements and the determined heat flux-temperature variation relationship. Each of these steps / functions is further described herein.

[0080] In one embodiment, the processor 420 may be configured to obtain a set of temperature measurements from a set of temperature sensors 416 distributed across the process condition measurement wafer assembly 100 and a set of heat flux measurements from a set of heat flux sensors 416 distributed across the process condition measurement wafer assembly 100 under isothermal conditions. For example, the process condition measurement wafer assembly 100 may be manufactured to include a plurality of temperature sensors 416 and a plurality of heat flux sensors 416 distributed at different locations throughout the process condition measurement wafer assembly 100. Under isothermal conditions, the plurality of temperature sensors 416 and the plurality of heat flux sensors 416 may be configured to obtain a set of temperature measurements and a set of heat flux measurements, respectively. The processor 420 may then be configured to receive the obtained measurements via the communication circuits 404 and 410.

[0081] In another embodiment, the processor 420 may be configured to calibrate a set of temperature measurements and a set of heat flux measurements obtained under isothermal conditions. For example, the processor 420 may be configured to set the measurements obtained under isothermal conditions as a baseline, and may involve comparing and / or adjusting subsequent measurements with the baseline.

[0082] In another embodiment, the processor 420 may be configured to generate one or more control signals configured to cause a heat source to apply a known heat flux to the process condition measurement wafer assembly 100. For example, in a processing environment, the processor 420 may be communicatively coupled to one or more heat sources (not shown). The processor 420 may be configured to generate one or more control signals configured to cause the one or more heat sources to apply a known heat flux to the process condition measurement wafer assembly 100. Parameters / characteristics associated with the known heat flux may be stored in the memory 422 and retrieved by the processor 420.

[0083] In another embodiment, the processor 420 can be configured to obtain an additional set of temperature measurements from the set of temperature sensors 416 and an additional set of heat flux measurements from the set of heat flux sensors 416 during the application of the known heat flux. For example, the plurality of temperature sensors 416 and the plurality of heat flux sensors 416 can be configured to obtain an additional set of temperature measurements and an additional set of heat flux measurements, respectively, during the application of the known heat flux. The processor 420 can then be configured to receive the obtained measurements via the communication circuits 404, 410. The processor 420 can be configured to store the obtained measurements in the memory 422.

[0084] In another embodiment, the processor 420 may be configured to identify one or more temperature variations observed across the set of temperature sensors during application of a known heat flux. Figure 5 As described, configuration variations (e.g., different sizes of the cavities 107a, 107b, variations in the size / shape of the electronic component 106, bonding to different surfaces, variations in adhesive and / or conductive properties, and the like) may cause the first temperature sensor to obtain different readings compared to additional temperature sensors. In this regard, the processor 420 may be configured to identify one or more temperature variations observed across the set of temperature sensors 416 during application of a known heat flux.

[0085] In another embodiment, the processor 420 may be configured to identify a heat flux-temperature variation relationship by correlating a known heat flux with the identified temperature variation of the set of temperature sensors 416. For example, the processor 420 may be configured to correlate the known heat flux with the identified temperature variation in order to identify the heat flux-temperature variation relationship. It is contemplated herein that the identified heat flux-temperature variation relationship may take any form known in the art, including but not limited to a relationship represented by mathematical equation(s), a list of associated heat flux values ​​and associated temperature variation values, and the like.

[0086] To more thoroughly model the heat flux-temperature variation relationship, processor 420 can be configured to collect readings under multiple isothermal conditions and during multiple varying known heat flux conditions. By collecting measurements under these different conditions, processor 420 can be configured to generate a model representing the identified heat flux-temperature variation relationship of process condition measurement wafer assembly 100.

[0087] After identifying the heat flux-temperature variation relationship, the process condition measurement wafer assembly 100 can then be used in one or more processes (e.g., a process within an epitaxial chamber, a process within a plasma etching chamber). While the conditions within the respective chambers may generally be known, the exact temperature and heat flux conditions experienced by the process condition measurement wafer assembly 100 may be unknown. Accordingly, the processor 412 can be configured to obtain a set of test temperature measurements and a set of test heat flux measurements from the sensor 416.

[0088] For example, under unknown heat flux conditions, the set of temperature sensors 416 can be configured to acquire a set of test temperature measurements, and the set of heat flux sensors 416 can be configured to acquire a set of test heat flux measurements. The processor 420 can then be configured to receive the acquired measurements via the communication circuits 404, 410. The processor 420 can be configured to store the acquired measurements in the memory 422.

[0089] In another embodiment, the processor 420 may be configured to adjust a set of test temperature measurements based on a set of test heat flux measurements and an identified heat flux-temperature variation relationship. For example, based on the heat flux-temperature variation relationship, the processor 420 may be configured to identify that a subset of the temperature sensors 416 reads higher temperatures under a particular set of heat flux conditions. In this regard, the processor 420 may be configured to adjust (e.g., lower) the temperature measurements of the set of test temperature measurements collected by the subset of the temperature sensors 416 based on the heat flux-temperature variation relationship. It should be noted herein that the processor 420 may be configured to adjust the set of test temperature measurements using any mathematical technique known in the art.

[0090] In another embodiment, the processor 420 may be configured to map the adjusted set of test temperature measurements to one or more measurement locations of the process condition measurement wafer assembly 100. For example, the location of each of the temperature sensors 416 on the process condition measurement wafer assembly 100 may be known and stored in the memory 422. These known locations of the temperature sensors 416 are locations where temperature measurements are taken by the process condition measurement wafer assembly 100 and may be referred to as measurement locations. In this regard, the processor 420 may be configured to map the adjusted set of test temperature measurements to a respective known location (e.g., a measurement location) of each temperature sensor 416.

[0091] In another embodiment, the processor 420 may be configured to interpolate a set of temperature values ​​at locations between one or more measurement locations based on the adjusted set of test temperature measurements and one or more interpolation functions. For example, the processor 420 may be configured to map a first adjusted temperature value to a first measurement location and a second adjusted temperature value to a second measurement location. In this example, the processor 420 may be configured to interpolate between the first measurement location and the second measurement location. For example, the processor 420 may be configured to assign one or more temperature values ​​to one or more locations between the first measurement location and the second measurement location.

[0092] Depending on the source and magnitude of temperature non-uniformities between the various measurement locations, the accuracy of the interpolated temperature values ​​may vary. To improve the accuracy of the interpolated temperature values ​​between the temperature sensors 416 (e.g., between the measurement locations), the processor 420 may be configured to model the effects of different types of structural variations / non-uniformities (e.g., different sizes of the cavities 107a, 107b, variations in the size / shape of the electronic components 106, bonding to different surfaces, variations in adhesive and / or conductive properties, and the like) on the acquired temperature values. For example, known structural variations / non-uniformities may be considered and included in the heat flux-temperature variation relationship discussed above. In this regard, the processor 420 may be configured to account for structural variations within the process condition measurement wafer assembly 100 when generating the heat flux-temperature variation relationship model.

[0093] After accounting for the configuration variations in the heat flux-temperature variation relationship model, the process condition measurement wafer assembly 100 can be used in the chamber to be tested. Process non-uniformities can then be identified using a number of techniques, including, but not limited to: measuring pre-plasma chuck non-uniformities, steady-state temperature data (e.g., temperature measurements from temperature sensor 416); determining the derivative of temperature measurements over time (dT / dt) to estimate heat flux and cooling non-uniformities; acquiring temperature and heat flux measurements simultaneously; and the like. In some embodiments, processor 420 can be configured to leverage known effects of configuration variations (e.g., a heat flux-temperature variation relationship model based at least in part on configuration variations) and identified process non-uniformities to more accurately predict process temperature values ​​between measurement locations (e.g., between temperature sensors 416).

[0094] In additional and / or alternative embodiments, the measurement parameters and / or values ​​obtained by the process condition measurement wafer assembly 100 can be used in a feedforward or feedback loop to adjust one or more upstream or downstream process tools. For example, when the measurement parameters are obtained in a semiconductor device process, the one or more processors 420 can be configured to receive the obtained measurement parameters and / or determined values ​​and generate one or more control signals configured to selectively adjust one or more characteristics of one or more process tools within the semiconductor device process. The process tools that can be adjusted can include, but are not limited to, photolithography tools, deposition tools, etching tools, and the like.

[0095] It should be noted herein that one or more components of the process condition measurement wafer assembly 100 and associated systems can be communicatively coupled to various other components of the process condition measurement wafer assembly 100 and associated systems in any manner known in the art. For example, the communication circuits 410, 404 can be communicatively coupled to each other and to other components via wired connections (e.g., copper wire, fiber optic cable, and the like) or wireless connections (e.g., RF coupling, IR coupling, 3G, 4G, 4G LTE, 5G, WiFi, WiMax, Bluetooth, and the like).

[0096] In one embodiment, one or more processors 412, 420 may include any one or more processing components known in the art. In this sense, one or more processors 412, 420 may include any microprocessor-type device configured to execute software algorithms and / or instructions. In one embodiment, one or more processors 412, 420 may be composed of a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, or other computer systems (e.g., network computers) configured to execute programs configured to operate the process condition measurement wafer assembly 100 and associated systems, as described throughout the present invention. It should be recognized that the steps described throughout the present invention can be implemented by a single computer system or alternatively multiple computer systems. In addition, it should be recognized that the steps described throughout the present invention can be implemented on any one or more of the one or more processors 412, 420. Generally, the term "processor" can be broadly defined as encompassing any device having one or more processing components that execute program instructions from memory 414, 422. Furthermore, the process condition measurement wafer assembly 100 and the various subsystems of the associated systems (e.g., sensor 416, remote data system 402) may include processors or logic components suitable for executing at least a portion of the steps described throughout the present invention. Therefore, the above description should not be construed as limiting the present invention, but rather merely illustrating the present invention.

[0097] The memories 414, 422 may include any storage medium known in the art suitable for storing program instructions executable by the associated one or more processors 412, 420 and data received from the process condition measurement wafer assembly 100 / sensor 416. For example, the memories 414, 422 may include non-transitory storage media. For example, the memories 414, 422 may include, but are not limited to, read-only memory (ROM), random access memory (RAM), magnetic or optical storage devices (e.g., disks), tapes, solid-state drives, and the like. It should be further noted that the memories 414, 422 may be housed in a common controller housing with the one or more processors 412, 420. In an alternative embodiment, the memories 414, 422 may be remotely located relative to the physical location of the processors 412, 420. In another embodiment, the memories 414, 422 maintain program instructions for causing the one or more processors 412, 420 to perform the various steps described herein.

[0098] Figure 6 is a flow chart of a method 600 for calculating the temperature of a wafer assembly 100 measured across process conditions, in accordance with one or more embodiments of the present invention.

[0099] In step 602, a set of temperature measurements are acquired from a set of temperature sensors distributed across a process condition measurement wafer and a set of heat flux measurements are acquired from a set of heat flux sensors distributed across the process condition measurement wafer under isothermal conditions. For example, the process condition measurement wafer assembly 100 may be fabricated to include a plurality of temperature sensors 416 and a plurality of heat flux sensors 416 distributed at different locations throughout the process condition measurement wafer assembly 100. Under isothermal conditions, the plurality of temperature sensors 416 and the plurality of heat flux sensors 416 may be configured to acquire a set of temperature measurements and a set of heat flux measurements, respectively. The processor 420 may then be configured to receive the acquired measurements via the communication circuits 404 and 410.

[0100] In step 604, the set of temperature measurements and the set of heat flux measurements acquired under isothermal conditions are corrected. For example, processor 420 may be configured to correct the set of temperature measurements by adjusting one or more of the acquired temperature measurements. As another example, processor 420 may be configured to set the measurements acquired under isothermal conditions as a baseline, which may be involved in comparing and / or adjusting subsequent measurements.

[0101] In step 606, a known heat flux is applied to the process condition measurement wafer. For example, in a processing environment, the processor 420 may be communicatively coupled to one or more heat sources (not shown). The processor 420 may be configured to generate one or more control signals configured to cause the one or more heat sources to apply the known heat flux to the process condition measurement wafer assembly 100.

[0102] In step 608, during the application of the known heat flux, an additional set of temperature measurements is acquired from the set of temperature sensors and an additional set of heat flux measurements is acquired from the set of heat flux sensors. For example, during the application of the known heat flux, the plurality of temperature sensors 416 and the plurality of heat flux sensors 416 can be configured to acquire an additional set of temperature measurements and an additional set of heat flux measurements, respectively. The processor 420 can then be configured to receive the acquired measurements via the communication circuits 404 and 410. The processor 420 can be configured to store the acquired measurements in the memory 422.

[0103] In step 610, temperature variations observed across the set of temperature sensors during application of the known heat flux are identified. For example, as previously described herein with respect to Figure 5 As described, configuration variations (e.g., different sizes of the cavities 107a, 107b, variations in the size / shape of the electronic component 106, bonding to different surfaces, variations in adhesive and / or conductive properties, and the like) may cause the first temperature sensor to obtain different readings compared to additional temperature sensors. In this regard, the processor 420 may be configured to identify one or more temperature variations observed across the set of temperature sensors 416 during application of a known heat flux.

[0104] In step 612, a heat flux-temperature variation relationship is identified by correlating the known heat flux with the identified temperature variation of the set of temperature sensors. For example, the processor 420 may be configured to correlate the known heat flux with the identified temperature variation in order to identify the heat flux-temperature variation relationship. It is contemplated herein that the identified heat flux-temperature variation relationship may take any form known in the art, including but not limited to a relationship represented by mathematical equation(s), a list of associated heat flux values ​​and associated temperature variation values, and the like.

[0105] In step 614, a set of test temperature measurements are acquired from the set of temperature sensors and a set of test heat flux measurements are acquired from the heat flux sensors under unknown heat flux conditions. For example, under unknown heat flux conditions, the set of temperature sensors 416 can be configured to acquire a set of test temperature measurements, and the set of heat flux sensors 416 can be configured to acquire a set of test heat flux measurements. The processor 420 can then be configured to receive the acquired measurements via the communication circuits 404, 410. The processor 420 can be configured to store the acquired measurements in the memory 422.

[0106] In step 616, a set of test temperature measurements is adjusted based on the set of test heat flux measurements and the identified heat flux-temperature variation relationship. For example, based on the heat flux-temperature variation relationship, the processor 420 may be configured to identify that a subset of the temperature sensors 416 reads a higher temperature under a particular set of heat flux conditions. In this regard, the processor 420 may be configured to adjust (e.g., lower) the temperature measurements of the set of test temperature measurements collected by the subset of the temperature sensors 416 based on the heat flux-temperature variation relationship. It should be noted herein that the processor 420 may be configured to adjust the set of test temperature measurements using any mathematical technique known in the art.

[0107] All methods described herein may include storing the results of one or more steps of a method embodiment in a memory. The result may include any result described herein and may be stored in any manner known in the art. The memory may include any memory described herein or any other suitable storage medium known in the art. After the result has been stored, the result may be accessed in the memory and used by any method or system embodiment described herein, formatted to display to a user, used by another software module, method or system, and the like. In addition, the result may be stored "permanently," "semi-permanently," "temporarily," or for a certain period of time. For example, the memory may be a random access memory (RAM), and the result may not necessarily remain in the memory indefinitely.

[0108] It is further contemplated that each embodiment of the method described above may include any other step(s) of any other method(s) described herein. Additionally, each embodiment of the method described above may be performed by any system described herein.

[0109] As used herein, directional terms (such as "top," "bottom," "above," "below," "up," "upward," "down," "beneath," "downward," and the like) are intended to provide relative positions for descriptive purposes and are not intended to specify an absolute reference system. Various modifications to the described embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Thus, the present invention is not intended to be limited to the specific embodiments shown and described but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0110] The target object described herein sometimes illustrates the different components contained in other components or connected with other components.It should be understood that these depicted architectures are merely exemplary, and in fact many other architectures that realize the same function can be implemented.In a conceptual sense, any component arrangement that realizes the same function is effectively "associated" so that the desired function is realized.Therefore, any two components combined to realize a specific function in this article can be considered to be "associated" with each other so that the desired function is realized, and have nothing to do with architecture or intermediate components.Similarly, any two components so associated can also be considered to be "connected" or "coupled" to realize the desired function, and any two components that can be so associated can also be considered to be "coupling" to realize the desired function.The specific instance that can be coupled includes but is not limited to physically interactive and / or physically interactive components and / or wirelessly interactive and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0111] Furthermore, it should be understood that the present invention is defined by the appended claims. Those skilled in the art will understand that, in general, the terms used herein, and especially in the appended claims (e.g., the bodies of the appended claims) are generally intended to be "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "including, but not limited to," and the like). Those skilled in the art will further understand that if a specific number of introduced claim recitations is intended, such intent will be explicitly recited in the claims, and in the absence of such recitation, such intent is not present. For example, to aid understanding, the claims appended hereafter may contain the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of these phrases should not be construed as implying that introducing a claim recitation with the indefinite article "a" or "an" limits any particular claim containing that introduced claim recitation to inventions containing only one such recitation, even if the same claim contains the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should generally be construed to mean "at least one" or "one or more"); the same applies to the use of definite articles used to introduce claim recitations. Furthermore, even if a specific number of introduced claim recitations is explicitly recited, those skilled in the art will recognize that such recitation should generally be construed to mean at least that recited number (e.g., the mere recitation of "two recitations" without other modifiers generally means at least two recitations, or two or more recitations). Furthermore, in those cases where a convention similar to “at least one of A, B, and C, and the like” is used, it is generally constructed with the expectation that one skilled in the art will understand the meaning of the convention (e.g., “a system having at least one of A, B, and C” will include, but is not limited to, systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together). In those cases where a convention similar to “at least one of A, B, or C, and the like” is used, it is generally constructed with the expectation that one skilled in the art will understand the meaning of the convention (e.g., “a system having at least one of A, B, or C” will include, but is not limited to, systems having A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together). Those skilled in the art will further understand that any antonymous conjunctions and / or phrases that actually present two or more alternative terms, whether in the detailed description, claims, or drawings, should be understood to contemplate the possibility of including one, either, or both of the terms.For example, the phrase "A or B" will be understood to include the possibilities of "A" or "B" or "A and B."

[0112] It is believed that the present invention and its many attendant advantages will be understood from the foregoing description, and it will be apparent that various changes can be made in the form, construction, and arrangement of components without departing from the disclosed object or sacrificing all of its substantial advantages. The described form is merely illustrative, and the appended claims are intended to cover and encompass such changes. Furthermore, it should be understood that the invention is defined by the appended claims.

Claims

1. A method for process condition measurement of a wafer assembly, comprising: Under isothermal conditions, obtaining a set of temperature measurements from a set of temperature sensors distributed across the process condition measurement wafer and obtaining a set of heat flux measurements from a set of heat flux sensors distributed across the process condition measurement wafer; calibrating the set of temperature measurements and the set of heat flux measurements obtained under the isothermal conditions; applying a known heat flux to the process condition measurement wafer; obtaining an additional set of temperature measurements from the set of temperature sensors and an additional set of heat flux measurements from the set of heat flux sensors during application of the known heat flux; identifying temperature variations observed across the set of temperature sensors during application of the known heat flux; identifying a heat flux-temperature variation relationship by correlating the known heat flux with the identified temperature variations of the set of temperature sensors; obtaining a set of test temperature measurements from the set of temperature sensors and a set of test heat flux measurements from the heat flux sensors under unknown heat flux conditions; and The set of test temperature measurements is adjusted based on the set of test heat flux measurements and the identified heat flux-temperature variation relationship. 2 . The method of claim 1 , wherein the set of temperature sensors measures wafer distribution across the process conditions and the set of heat flux sensors measures wafer distribution across the process conditions.

3. The method according to claim 1, further comprising: The adjusted set of test temperature measurements is mapped to one or more measurement locations on the process condition measurement wafer.

4. The method according to claim 3, further comprising: A set of temperature values ​​is interpolated at locations between the one or more measurement locations based on the adjusted set of test temperature measurements and one or more interpolation functions.

5. The method of claim 1 , wherein calibrating the set of temperature measurements and the set of heat flux measurements obtained under the isothermal conditions comprises: The set of temperature measurements and the set of heat flux measurements taken under the isothermal conditions are set as a baseline.

6. The method of claim 1 , wherein applying the known heat flux to the process condition measurement wafer comprises: A heat source is caused to apply the known heat flux to the process condition measurement wafer.

7. A system for measuring process conditions of a wafer assembly, comprising: One or more processors communicatively coupled to a set of temperature sensors and a set of heat flux sensors of a process condition measurement wafer, wherein the one or more processors are configured to execute a set of program instructions configured to cause the one or more processors to: obtaining a set of temperature measurements from the set of temperature sensors and the set of heat flux measurements under isothermal conditions; calibrating the set of temperature measurements and the set of heat flux measurements obtained under the isothermal conditions; obtaining an additional set of temperature measurements from the set of temperature sensors and an additional set of heat flux measurements from the set of heat flux sensors during application of the known heat flux; identifying temperature variations across the set of temperature sensors during application of the known heat flux; identifying a heat flux-temperature variation relationship by correlating the known heat flux with the identified temperature variations of the set of temperature sensors; obtaining a set of test temperature measurements from the set of temperature sensors and a set of test heat flux measurements from the heat flux sensors under unknown heat flux conditions; and The set of test temperature measurements is adjusted based on the set of test heat flux measurements and the identified heat flux-temperature variation relationship.

8. The system of claim 7, wherein the set of temperature sensors measures wafer distribution across the process conditions and the set of heat flux sensors measures wafer distribution across the process conditions.

9. The system of claim 7, wherein the one or more processors are configured to: The adjusted set of test temperature measurements is mapped to one or more measurement locations on the process condition measurement wafer.

10. The system of claim 9, wherein the one or more processors are configured to: A set of temperature values ​​is interpolated at locations between the one or more measurement locations based on the adjusted set of test temperature measurements and one or more interpolation functions.

11. The system of claim 7, wherein calibrating the set of temperature measurements and the set of heat flux measurements obtained under the isothermal conditions comprises: The set of temperature measurements and the set of heat flux measurements taken under the isothermal conditions are set as a baseline.

12. The system of claim 7, further comprising: A heat source is configured to apply the known heat flux to the process condition measurement wafer.

13. A system for measuring process conditions of a wafer assembly, comprising: a process condition measurement wafer, wherein the process condition measurement wafer comprises a set of temperature sensors and a set of heat flux sensors; one or more processors communicatively coupled to the set of temperature sensors and the set of heat flux sensors, wherein the one or more processors are configured to execute a set of program instructions configured to cause the one or more processors to: obtaining a set of temperature measurements from the set of temperature sensors and the set of heat flux measurements under isothermal conditions; calibrating the set of temperature measurements and the set of heat flux measurements obtained under the isothermal conditions; obtaining an additional set of temperature measurements from the set of temperature sensors and an additional set of heat flux measurements from the set of heat flux sensors during application of the known heat flux; identifying temperature variations across the set of temperature sensors during application of the known heat flux; identifying a heat flux-temperature variation relationship by correlating the known heat flux with the identified temperature variations of the set of temperature sensors; obtaining a set of test temperature measurements from the set of temperature sensors and a set of test heat flux measurements from the heat flux sensors under unknown heat flux conditions; and The set of test temperature measurements is adjusted based on the set of test heat flux measurements and the identified heat flux-temperature variation relationship.

14. The system of claim 13, wherein the set of temperature sensors measures wafer distribution across the process conditions and the set of heat flux sensors measures wafer distribution across the process conditions.

15. The system of claim 13, wherein the one or more processors are configured to: The adjusted set of test temperature measurements is mapped to one or more measurement locations on the process condition measurement wafer.

16. The system of claim 15, wherein the one or more processors are configured to: A set of temperature values ​​is interpolated at locations between the one or more measurement locations based on the adjusted set of test temperature measurements and one or more interpolation functions.

17. The system of claim 13, wherein calibrating the set of temperature measurements and the set of heat flux measurements obtained under the isothermal conditions comprises: The set of temperature measurements and the set of heat flux measurements taken under isothermal conditions are set as a baseline.

18. The system of claim 13, further comprising: A heat source is configured to apply the known heat flux to the process condition measurement wafer.

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