A satellite-based variable bit width LDPC parallel coding system and method

Abstract

The present invention discloses a satellite-based variable bit width LDPC parallel coding system and method, comprising a coding control module, a flow control shaping module, a generator matrix generation module and a coding module. The method can dynamically adjust the parallel coding bit width according to different transmission requirements in satellite-to-ground data transmission application scenarios, perform 16-bit or 32-bit parallel coding, summarize reusable operator structures in the hardware implementation structure of different parallel bit width coding methods, and generate parallel encoders of different bit widths by controlling the logical relationship between the reused operator structures through an enable signal, thereby realizing the variable bit width function of parallel coding.

Description

Technical Field

[0001] The present invention relates to the field of communication coding technology, and in particular to a satellite-based variable bit width LDPC parallel coding system and method. Background Art

[0002] In satellite communication systems, satellite-to-ground data transmission links are used to transmit valid data such as text, images, and measurement and control information generated by space exploration missions. With the continuous development of aerospace measurement and control and space exploration technology, satellite observation missions are complicated, and the amount of data transmitted in satellite communication systems has greatly increased. The demand for high-speed data transmission between satellites and the ground is extremely urgent. The communication conditions for satellite-to-ground data transmission are complex and changeable, and the hardware resources, spectrum resources, and transmission power of satellites are limited. Therefore, high-performance and high-reliability satellite-based channel coding technology should be studied to achieve high-speed satellite-to-ground data transmission. Low-density parity check code (LDPC) has excellent error correction performance, which can improve the data transmission performance under complex channel conditions; it has an error performance close to the Shannon limit, and has high coding gain and efficiency; it has a low-complexity coding structure, which is convenient for high-speed parallel coding operations on hardware. Therefore, LDPC code is a satellite-based channel coding technology widely used in satellite-to-ground data transmission systems.

[0003] At present, the Consultative Committee for Space Data Systems (CCSDS) standard recommends the use of quasi-cyclic LDPC codes, namely QC-LDPC codes, for near-Earth satellite communications. It uses a serial coding scheme with low complexity. However, the throughput of long code LDPC serial coding is low and high-speed coding cannot be achieved. A high-throughput parallel coding scheme can also be used, but its resource consumption is large and the bit width of the parallel coding cannot be adjusted according to the data transmission requirements. In summary, designing a space-based LDPC parallel pipeline coding method with variable parallel coding bit width has engineering application value. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the present invention provides a satellite-based variable bit width LDPC parallel coding method, which has the characteristics of compatibility with multiple code rates, adjustable parallel input bit width, low complexity, high speed and high efficiency. It adopts a parallel pipeline coding method to solve the problems of long LDPC code length and high resource consumption caused by iterative calculation.

[0005] In order to achieve the above-mentioned invention object, the technical solution adopted to solve the technical problem is as follows:

[0006] The present invention discloses a satellite-based variable bit width LDPC parallel coding system, comprising a coding control module, a flow control shaping module, a generator matrix generation module and a coding operation module, wherein:

[0007] The coding control module is used to generate an enable signal according to the needs of satellite-to-ground data transmission to control the coding system to work normally and orderly; output the enable signal for calibrating the coding area to the flow control shaping module, output the enable signal for calibrating the generation matrix to the generation matrix generation module, and output the enable signal for calibrating the parallel coding bit width to the coding operation module;

[0008] The flow control shaping module is used to perform flow control shaping on the data to be encoded transmitted from the satellite to the ground, so that the data to be encoded meets the CCSDS format requirements; according to the coding area enable signal generated by the coding control module, only when the enable signal is valid, that is, when the data is in the coding area, the data is filled into the data domain to be encoded, and then the data to be encoded is padded with zeros and data segmented to obtain parallel N-bit encoded data and output to the coding operation module;

[0009] The generator matrix generation module is used to generate a quasi-cyclic generator matrix operator required for a quasi-cyclic LDPC coding operation; according to the generator matrix operator enable signal generated by the coding control module, a cyclic shift operation is performed to make the generator matrix operator meet the parallel coding bit width requirement, and the generator matrix operator is output to the coding operation module;

[0010] The coding operation module is used to perform LDPC parallel pipeline coding with variable parallel coding bit width; according to the parallel coding enable signal generated by the coding control module, the corresponding hardware coding unit is configured to be effective by the variable parallel coding bit width N, an N-bit LDPC parallel encoder is generated, and the data to be encoded after flow control shaping and the quasi-cyclic generation matrix operator are operated in the encoder to generate check bits, thereby completing the variable bit width LDPC parallel pipeline coding.

[0011] Furthermore, the variable parallel coding bit width function is realized by reconstructing the hardware coding unit in the coding operation module, wherein the hardware structure for quasi-cyclic LDPC coding adopts a shift register accumulation unit; under different parallel coding bit widths N, the multiplication and accumulation calculation process adopted when the encoded data and the generating matrix operator perform coding operations are the same, and the basic substructure in the shift register accumulation unit can be shared; according to the hardware implementation structure of different parallel bit width coding processes, a reusable operator structure is summarized, and the coding control module generates an enable signal for calibrating the parallel coding bit width, configures the corresponding operator structure to be valid, and controls the logical relationship between the reconstructed valid operator structures to generate an N-bit LDPC parallel encoder, thereby reconstructing the parallel encoder in the coding operation module according to different data transmission requirements in the satellite-to-ground data transmission application scenario, and realizing variable bit width LDPC parallel pipeline coding.

[0012] The present invention also discloses a satellite-based variable bit width LDPC parallel coding method, which uses the above-mentioned satellite-based variable bit width LDPC parallel coding system for coding, and includes the following steps:

[0013] Step 1: Divide the generator matrix of the LDPC code to obtain 14×2 511×511-order quasi-circular submatrices A for generating 1022-bit check codes. i,j (i=1,2,…,14;j=1,2);

[0014] Step 2: Transmit the information bits to be encoded u = (u1, u2, ..., u 7154 ) to perform flow control shaping, and implement data segmentation and zero padding operations through two N-bit registers to obtain the information bits after flow control shaping

[0015] Step 3: Using the cyclic shift property, expand the first row of the quasi-cyclic submatrix stored in the ROM to obtain A i,j , and perform matrix partitioning through the N-bit cache register to obtain the quasi-circular matrix operator

[0016] Step 4: Perform N-bit LDPC parallel coding operation with variable bit width, perform matrix multiplication and accumulation operation on the information bits after flow control shaping and the quasi-circular matrix operator to obtain the LDPC check bits

[0017] Furthermore, the LDPC code described in step 1 adopts the CCSDS standard specification, and the near-earth satellite communication adopts a quasi-cyclic LDPC code with a code rate of 7 / 8 (8176, 7154), and its generator matrix has a quasi-cyclic characteristic. The generator matrix used to generate the 1022-bit check code is 14×2 511×511-order quasi-cyclic submatrices A i,j(i=1,2,…,14;j=1,2), the first row vector of the submatrix is ​​set to a i,j , then for a i,j A can be obtained by circular shift i,j , in hardware implementation, only the first row of the 14×2 sub-matrices needs to be stored in ROM.

[0018] Furthermore, the step 2 includes the following contents:

[0019] Step 21: After receiving the information data stream, the satellite-to-ground data transmission system fills the information bits into the data domain to be encoded according to the enable signal of the calibrated coding area. When the enable signal is valid, that is, when the data is in the coding area, the data vector to be encoded is obtained. u=(u1,u2,…,u 7154 );

[0020] Step 22: According to the parallel coding bit width N, the data to be coded u = (u1, u2, ..., u 7154 ) Each time N bits are input into the N-bit register R1, the data in R2 is output at the next clock edge, and the data in R1 is stacked into R2, and the new N-bit data is stored in R1;

[0021] Step 23: Repeat step 22 and count the output data. When the counter counts to 512 / N, it is reset to zero and the zero-filling flag is high. At this time, the last bit of R2 output becomes 0, that is, "0" is inserted after every 511 bits. i =(p i,1 ,p i,2 ,…,p i,512 )=(u (i-1)*511+1 ,u (i-1)*511+2 ,…,u i*511 ,0),i=1,2,…,14;

[0022] Step 24: When the zero padding flag is high, the register outputs N data with a length of 512 / N bits, that is, p i Divide into N sub-vectors of 512 / N bits It is transmitted to the encoding operation module for N-bit parallel encoding.

[0023] Furthermore, the step 3 includes the following contents:

[0024] Step 31: 14×2 quasi-circular submatrices A i,j The first row of a i,j Stored in ROM, each time the ROM address is incremented, the N-bit buffer register B1 reads the N-bit data in the first row of a quasi-circular submatrix from the ROM When the ROM address increments to 512 / N, it indicates that the pre-calculation operator is ready;

[0025] Step 32: Perform cyclic shift on each pre-calculated operator to obtain N 512 / N-order square matrices It is transmitted to the encoding operation module for N-bit parallel encoding.

[0026] Furthermore, the step 4 performs parallel pipeline encoding with variable bit width, and the matrix operation performed is expressed as The encoding process first obtains each generator matrix operator by cyclic shift Then it is multiplied and accumulated with the data to be encoded to finally obtain the check bit. The shift register accumulation unit SRAA is used to implement the encoding process. SRAA mainly includes an N-bit circular shift register A for generating and storing the generator matrix operator, N for calculating and AND gates for multiplication, N for calculation The XOR gate for addition and the N-bit register D that holds the result.

[0027] Furthermore, the encoding process of step 4 includes the following contents:

[0028] Step 41: Store 14×2 quasi-circular submatrices A in ROM i,j The first row of a i,j , the parallel bit width N is determined according to the enable signal generated by the encoding control module for calibrating the parallel encoding bit width, and the matrix operator is read from the ROM each time through the addressing mode To the circular shift register A;

[0029] Step 42: Data to be encoded With the generator matrix operator The multiplication is performed through N AND gates, and the multiplication result and the data stored in register D are accumulated through N XOR gates, and the accumulated result is stored in register D; the circular shift register is circularly shifted, and the above circular accumulation operation is repeated;

[0030] Step 43: perform pipeline operation, while performing the current LDPC encoding operation, synchronously calculate the generator matrix operator required for the next encoding operation, read the new generator matrix operator by incrementing the ROM address, and repeat step 42 until i=1,2,…,14, c=1,2,…,N is traversed;

[0031] Step 44: Output the result c of register D j ,j=1,2 and data splicing is performed, c=(c1,c2) ​​is the check bit, and LDPC parallel pipeline coding is completed.

[0032] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0033] 1. The present invention adopts a parallel pipeline encoding method, which reduces the number of calculation iterations, reduces hardware resource consumption, and improves data processing speed and encoding efficiency;

[0034] 2. The present invention adopts a parallel input bit width variable encoding method, which can adapt to different data transmission requirements in satellite-to-ground data transmission application scenarios and flexibly and efficiently configure hardware resources;

[0035] 3. The gating signal is set inside the encoder to adapt to the encoding requirements of various data rates. At the same time, combined with the actual needs of the AOS frame, the encoding range of the input data can be specified, and the non-coding area will not be encoded. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0037] Figure 1 This is a block diagram of the FPGA internal module structure of a satellite-based variable bit width LDPC parallel coding system of the present invention;

[0038] Figure 2 It is a schematic diagram of the structure of the shift register accumulation unit of the present invention;

[0039] Figure 3 It is a schematic diagram of the parallel encoding bit width variable function of the present invention. DETAILED DESCRIPTION

[0040] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] Embodiment 1

[0042] like Figure 1 As shown, the present invention discloses a satellite-based variable bit width LDPC parallel coding system, including a coding control module, a flow control shaping module, a generator matrix generation module and a coding operation module, wherein:

[0043] The coding control module is used to generate an enable signal according to the needs of satellite-to-ground data transmission to control the coding system to work normally and orderly; output the enable signal for calibrating the coding area to the flow control shaping module, output the enable signal for calibrating the generation matrix to the generation matrix generation module, and output the enable signal for calibrating the parallel coding bit width to the coding operation module;

[0044] The flow control shaping module is used to perform flow control shaping on the data to be encoded transmitted from the satellite to the ground, so that the data to be encoded meets the CCSDS format requirements; according to the coding area enable signal generated by the coding control module, only when the enable signal is valid, that is, when the data is in the coding area, the data is filled into the data domain to be encoded, and then the data to be encoded is padded with zeros and data segmented to obtain parallel N-bit encoded data and output to the coding operation module;

[0045] The generator matrix generation module is used to generate a quasi-cyclic generator matrix operator required for a quasi-cyclic LDPC coding operation; according to the generator matrix operator enable signal generated by the coding control module, a cyclic shift operation is performed to make the generator matrix operator meet the parallel coding bit width requirement, and the generator matrix operator is output to the coding operation module;

[0046] The coding operation module is used to perform LDPC parallel pipeline coding with variable parallel coding bit width; according to the parallel coding enable signal generated by the coding control module, the corresponding hardware coding unit is configured to be effective by the variable parallel coding bit width N, an N-bit LDPC parallel encoder is generated, and the data to be encoded after flow control shaping and the quasi-cyclic generation matrix operator are operated in the encoder to generate check bits, thereby completing the variable bit width LDPC parallel pipeline coding.

[0047] Furthermore, the variable parallel coding bit width function is realized by reconstructing the hardware coding unit in the coding operation module, wherein the hardware structure for quasi-cyclic LDPC coding adopts a shift register accumulation unit; under different parallel coding bit widths N, the multiplication and accumulation calculation process adopted when the encoded data and the generating matrix operator perform coding operations are the same, and the basic substructure in the shift register accumulation unit can be shared; according to the hardware implementation structure of different parallel bit width coding processes, a reusable operator structure is summarized, and the coding control module generates an enable signal for calibrating the parallel coding bit width, configures the corresponding operator structure to be valid, and controls the logical relationship between the reconstructed valid operator structures to generate an N-bit LDPC parallel encoder, thereby reconstructing the parallel encoder in the coding operation module according to different data transmission requirements in the satellite-to-ground data transmission application scenario, and realizing variable bit width LDPC parallel pipeline coding.

[0048] Embodiment 2

[0049] The present invention also discloses a satellite-based variable bit width LDPC parallel coding method, which uses the satellite-based variable bit width LDPC parallel coding system described in Embodiment 1 for coding, and includes the following steps:

[0050] Step 1: Divide the generator matrix of the LDPC code to obtain 14×2 511×511-order quasi-circular submatrices A for generating 1022-bit check codes. i,j (i=1,2,…,14;j=1,2);

[0051] Specifically, the LDPC code described in step 1 adopts the CCSDS standard specification, and it is recommended that near-earth satellite communications use a quasi-cyclic LDPC code with a code rate of 7 / 8 (8176, 7154), whose generator matrix has a quasi-cyclic characteristic, expressed as:

[0052]

[0053] Among them, I is the 511-order unit matrix, 0 is the 511-order zero matrix, and the 14×2 511×511-order quasi-circular submatrices A used to generate the 1022-bit check code are i,j (i=1,2,…,14;j=1,2), the first row vector of the submatrix is ​​set to a i,j , then for a i,j A can be obtained by circular shift i,j , in hardware implementation, only the first row of the 14×2 sub-matrices needs to be stored.

[0054] Step 2: Transmit the information bits to be encoded u = (u1, u2, ..., u 7154 ) to perform flow control shaping, and implement data segmentation and zero padding operations through two N-bit registers to obtain the information bits after flow control shaping

[0055] Specifically, the step 2 includes the following contents:

[0056] Step 21: After receiving the information data stream, the satellite-to-ground data transmission system fills the information bits into the data domain to be encoded according to the enable signal of the calibrated coding area. When the enable signal is valid, that is, when the data is in the coding area, the data vector to be encoded is obtained. u=(u1,u2,…,u 7154 );

[0057] Step 22: According to the parallel coding bit width N, the data to be coded u = (u1, u2, ..., u 7154 ) Each time N bits are input into the N-bit register R1, the data in R2 is output at the next clock edge, and the data in R1 is stacked into R2, and the new N-bit data is stored in R1;

[0058] Step 23: Repeat step 22 and count the output data. When the counter counts to 512 / N, it is reset to zero and the zero-filling flag is high. At this time, the last bit of R2 output becomes 0, that is, "0" is inserted after every 511 bits. i =(p i,1 ,p i,2 ,…,p i,512 )=(u (i-1)*511+1 ,u (i-1)*511+2 ,…,u i*511 ,0),i=1,2,…,14;

[0059] Step 24: When the zero padding flag is high, the register outputs N data with a length of 512 / N bits, that is, p i Divide into N sub-vectors of 512 / N bits It is transmitted to the encoding operation module for N-bit parallel encoding.

[0060] Step 3: Using the cyclic shift property, expand the first row of the quasi-cyclic submatrix stored in the ROM to obtain A i,j , and perform matrix partitioning through the N-bit cache register to obtain the quasi-circular matrix operator

[0061] Specifically, step 3 includes the following contents:

[0062] Step 31: 14×2 quasi-circular submatrices A i,j The first row of a i,j Stored in ROM, each time the ROM address is incremented, the N-bit buffer register B1 reads the N-bit data in the first row of a quasi-circular submatrix from the ROM When the ROM address increments to 512 / N, it indicates that the pre-calculation operator is ready;

[0063] Step 32: Perform cyclic shift on each pre-calculated operator to obtain N 512 / N-order square matrices It is transmitted to the encoding operation module for N-bit parallel encoding.

[0064] Step 4: Perform N-bit LDPC parallel coding operation with variable bit width, perform matrix multiplication and accumulation operation on the information bits after flow control shaping and the quasi-circular matrix operator to obtain the LDPC check bits

[0065] Furthermore, the step 4 performs parallel pipeline encoding with variable bit width, and the matrix operation performed is expressed as The encoding process first obtains each generator matrix operator by cyclic shift Then it is multiplied and accumulated with the data to be encoded to finally obtain the check bit, so the shift register adder accumulator (SRAA) can be used to implement the encoding process. SRAA mainly includes an N-bit circular shift register A for generating and storing the generator matrix operator, N for calculating and AND gates for multiplication, N for calculation The XOR gate for addition and the N-bit register D that holds the result.

[0066] Specifically, the encoding process of step 4 includes the following contents:

[0067] Step 41: Store 14×2 quasi-circular submatrices A in ROM i,j The first row of a i,j , the parallel bit width N is determined according to the enable signal generated by the encoding control module for calibrating the parallel encoding bit width, and the matrix operator is read from the ROM each time through the addressing mode To the circular shift register A;

[0068] Step 42: Data to be encoded With the generator matrix operator The multiplication is performed through N AND gates, and the multiplication result and the data stored in register D are accumulated through N XOR gates, and the accumulated result is stored in register D, such as Figure 2 ; The circular shift register performs circular shifting and repeats the above circular accumulation operation;

[0069] Step 43: perform pipeline operation, while performing the current LDPC encoding operation, synchronously calculate the generator matrix operator required for the next encoding operation, read the new generator matrix operator by incrementing the ROM address, and repeat step 42 until i=1,2,…,14, c=1,2,…,N is traversed;

[0070] Step 44: Output the result c of register D j ,j=1,2 and data splicing is performed, c=(c1,c2) ​​is the check bit, and LDPC parallel pipeline coding is completed.

[0071] like Figure 3 The embodiment of the present invention can perform two parallel encoding modes with parallel bit width N=16 and 32, and set the maximum hardware resources, that is, set 2N max (N max= 32) shift register accumulator units perform LDPC encoding with different parallel bit widths. The control module generates a parallel encoding bit width enable signal to mark the operator structure that can be reused, and controls the logical relationship between the reused operator structures, so that the 2N shift register accumulator units are effective, thereby performing parallel encoding operations. When the parallel bit width is set to N max =32, the control module generates a parallel encoding bit width enable signal to control the corresponding 2N max =64 shift register accumulation units are valid, a 32-bit LDPC parallel encoder is generated, and 32-bit parallel encoding is completed; when the parallel bit width is set to N=16, the control module generates a parallel encoding bit width enable signal to control the logical relationship between the reused operation substructures, so that 2N=32 shift register accumulation units are valid, a 16-bit LDPC parallel encoder is generated, and 16-bit parallel encoding is completed.

[0072] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A satellite-based variable bit width LDPC parallel coding system, characterized in that: It includes a coding control module, a flow control shaping module, a generator matrix generation module and a coding operation module, wherein: The coding control module is used to generate an enable signal according to the needs of satellite-to-ground data transmission to control the coding system to work normally and orderly; output the enable signal for calibrating the coding area to the flow control shaping module, output the enable signal for calibrating the generation matrix to the generation matrix generation module, and output the enable signal for calibrating the parallel coding bit width to the coding operation module; The flow control shaping module is used to perform flow control shaping on the data to be encoded transmitted from the satellite to the ground, so that the data to be encoded meets the CCSDS format requirements; according to the coding area enable signal generated by the coding control module, only when the enable signal is valid, that is, when the data is in the coding area, the data is filled into the data domain to be encoded, and then the data to be encoded is padded with zeros and data segmented to obtain parallel N-bit encoded data and output to the coding operation module; The generator matrix generation module is used to generate a quasi-cyclic generator matrix operator required for a quasi-cyclic LDPC coding operation; according to the generator matrix operator enable signal generated by the coding control module, a cyclic shift operation is performed to make the generator matrix operator meet the parallel coding bit width requirement, and the generator matrix operator is output to the coding operation module; The coding operation module is used to perform LDPC parallel pipeline coding with variable parallel coding bit width; according to the parallel coding enable signal generated by the coding control module, the corresponding hardware coding unit is configured to be effective by the variable parallel coding bit width N, an N-bit LDPC parallel encoder is generated, and the data to be encoded after flow control shaping and the quasi-cyclic generator matrix operator are operated in the encoder to generate check bits, thereby completing the variable bit width LDPC parallel pipeline coding; The variable parallel coding bit width function is realized by reconstructing the hardware coding unit in the coding operation module, wherein the hardware structure for quasi-cyclic LDPC coding adopts a shift register accumulation unit; under different parallel coding bit widths N, the multiplication and accumulation calculation process adopted when the data to be encoded and the generating matrix operator perform coding operations is the same, and the basic substructure in the shift register accumulation unit can be shared; according to the hardware implementation structure of different parallel bit width coding processes, a reusable operator structure is summarized, and the coding control module generates an enable signal for calibrating the parallel coding bit width, configures the corresponding operator structure to be effective, and controls the logical relationship between the reconstructed effective operator structures to generate an N-bit LDPC parallel encoder, thereby reconstructing the parallel encoder in the coding operation module according to different data transmission requirements in the satellite-to-ground data transmission application scenario, and realizing variable bit width LDPC parallel pipeline coding.

2. A satellite-based variable bit width LDPC parallel coding method, characterized in that: The encoding is performed using the satellite-based variable bit width LDPC parallel coding system according to claim 1, comprising the following steps: Step 1: Divide the generator matrix of the LDPC code to obtain 14×2 511×511-order quasi-circular submatrices A for generating 1022-bit check codes. i,j (i=1,2,…,14;j=1,2); Step 2: Transmit the information bits to be encoded u = (u1, u2, ..., u 7154 ) performs flow control shaping, and implements data segmentation and zero padding operations through two N-bit registers to obtain the information bit q after flow control shaping. i c (i=1,2,…,14; c=1,2,…,N); The step 2 includes the following contents: Step 21: After receiving the information data stream, the satellite-to-ground data transmission system fills the information bits into the data domain to be encoded according to the enable signal of the calibrated coding area. When the enable signal is valid, that is, when the data is in the coding area, the data vector to be encoded is obtained. u=(u1,u2,…,u 7154 ); Step 22: According to the parallel coding bit width N, the data to be coded u = (u1, u2, ..., u 7154 ) Each time N bits are input into the N-bit register R1, the data in register R2 is output at the next clock edge, and the data in register R1 is stacked into register R2, and the new N-bit data is stored in register R1; Step 23: Repeat step 22 and count the output data. When the counter counts to 512 / N, it is reset to zero and the zero-filling flag is high. At this time, the last bit of register R2 output becomes 0, that is, "0" is inserted after every 511 bits. i =(p i,1 ,p i,2 ,…,p i,512 )=(u (i-1)*511+1 ,u (i-1)*511+2 ,…,u i*511 ,0),i=1,2,…,14; Step 24: When the zero padding flag is high, register R2 outputs N data with a length of 512 / N bits, that is, p i Divide into N sub-vectors of 512 / N bits Transmit it to the encoding operation module for N-bit parallel encoding; Step 3: Using the cyclic shift property, expand the first row of the quasi-cyclic submatrix stored in the ROM to obtain A i,j , and perform matrix partitioning through the N-bit cache register to obtain the quasi-circular matrix operator Step 4: Perform N-bit LDPC parallel coding operation with variable bit width, perform matrix multiplication and accumulation operation on the information bits after flow control shaping and the quasi-circular matrix operator to obtain the LDPC check bits The step 4 performs parallel pipeline encoding with variable bit width, and the matrix operation performed is expressed as: The parallel pipeline coding first obtains each generator matrix operator by cyclic shift Then it is multiplied and accumulated with the data to be encoded to finally obtain the check bit. The shift register accumulation unit SRAA is used to implement the encoding process. SRAA mainly includes an N-bit circular shift register A for generating and storing the generator matrix operator, N for calculating and AND gates for multiplication, N for calculation An XOR gate for addition and an N-bit register D for storing the calculation result of the parallel pipeline encoding; The encoding process includes the following: Step 41: Store 14×2 quasi-circular submatrices A in ROM i,j The first row of a i,j , the parallel bit width N is determined according to the enable signal generated by the encoding control module for calibrating the parallel encoding bit width, and the matrix operator is read from the ROM each time through the addressing mode To the circular shift register A; Step 42: Data to be encoded With the generator matrix operator The multiplication is performed through N AND gates, and the multiplication result and the data stored in register D are accumulated through N XOR gates, and the accumulated result is stored in register D; the circular shift register is circularly shifted, and the above circular accumulation operation is repeated; Step 43: perform pipeline operation, while performing the current LDPC encoding operation, synchronously calculate the generator matrix operator required for the next encoding operation, read the new generator matrix operator by incrementing the ROM address, and repeat step 42 until i=1,2,…,14, c=1,2,…,N is traversed; Step 44: Output the result c of register D j ,j=1,2 and data splicing is performed, c=(c1,c2) ​​is the check bit, and LDPC parallel pipeline coding is completed.

3. The satellite-based variable bit width LDPC parallel coding method according to claim 2, characterized in that: The LDPC code described in step 1 adopts the CCSDS standard specification. The near-earth satellite communication adopts a quasi-cyclic LDPC code with a code rate of 7 / 8 (8176, 7154). Its generator matrix has a quasi-cyclic characteristic. The generator matrix used to generate a 1022-bit check code is 14×2 511×511-order quasi-cyclic submatrices A i,j (i=1,2,…,14;j=1,2), the first row vector of the submatrix is ​​set to a i,j , then for a i,j A can be obtained by circular shift i,j , in hardware implementation, only the first row of the 14×2 sub-matrices needs to be stored in ROM.

4. The satellite-based variable bit width LDPC parallel coding method according to claim 2, characterized in that: The step 3 includes the following contents: Step 31: 14×2 quasi-circular submatrices A i,j The first row of a i,j Stored in ROM, each time the ROM address is incremented, the N-bit buffer register B1 reads the N-bit data in the first row of a quasi-circular submatrix from the ROM When the ROM address increments to 512 / N, it indicates that the pre-calculation operator is ready; Step 32: Perform cyclic shift on each pre-calculated operator to obtain N 512 / N-order square matrices It is transmitted to the encoding operation module for N-bit parallel encoding.

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