A method and apparatus for testing the performance of SPI NAND Flash chips

Abstract

This invention discloses a method and apparatus for performance testing of SPI NAND Flash chips. The method includes: using a complex programmable logic device (CPL) to control a level conversion module to generate several test signals for the chip under test (SUT), wherein the test signals include the access area, test voltage, and test frequency for reading / writing operations on the SUT, and the SUT is an SPI NAND Flash chip; performing read / write operations on the SUT using the test signals; and verifying the correctness of the read / write operation results. This invention can simulate numerous usage scenarios in a short time to quickly verify the various extreme performance limits of the SPI NAND Flash chip and whether it meets product usage requirements, thus greatly improving testing efficiency.

Description

Technical Field

[0001] This invention relates to the field of performance testing technology, and in particular to a method and apparatus for testing the performance of SPI NAND Flash chips. Background Technology

[0002] SPI NAND Flash is a memory device that combines the SPI (Serial Peripheral Interface) bus and NAND Flash (Not AND Flash) memory. It is controlled and read / write via the SPI bus, possessing the high capacity and low cost advantages of NAND Flash memory, and the low power consumption and high speed advantages of SPI Flash memory. Therefore, it is widely used in various fields, including embedded systems and mobile devices, as data storage, operating system storage, and firmware storage.

[0003] Because SPI NAND Flash chips have large capacities, they may contain bad blocks and have compatibility issues with the host chip. Therefore, rigorous testing is necessary before selecting and using SPI NAND Flash chips. In recent years, the development trend of SPI NAND Flash chips has accelerated, and manufacturers of Flash chips have emerged rapidly. Due to the wide variety of chips available and their varying quality, the workload for chip testing is enormous. If testing is insufficient, problems can easily surface during mass production or engineering, thus affecting product quality.

[0004] However, there are currently no testing tools available for SPI NAND Flash chips on the market. Therefore, product testing can only be done by replacing different chips with the product for overall software read tests, a tedious and complex process. Furthermore, all available chip information comes solely from the chip manufacturer's datasheet, and subtle compatibility differences may go unnoticed by the chip manufacturer. Therefore, there is an urgent need for a technical solution that can quickly test the extreme performance of SPI NAND Flash chips under various conditions to determine whether they meet the requirements for product replacement. Summary of the Invention

[0005] To overcome the problems existing in related technologies, the present invention provides a method and apparatus for testing the performance of SPI NAND Flash chips, thereby solving the defects in related technologies.

[0006] According to a first aspect of the present invention, a method for testing the performance of an SPI NAND Flash chip is provided, characterized in that the method comprises:

[0007] A complex programmable logic device (CPL) is used to control a level shifting module to generate several test signals for a chip under test (DUT). These test signals include the access region, test voltage, and test frequency for reading / writing operations on the DUT. The DUT is an SPI NAND Flash chip. The DUT comprises several blocks, each containing several pages. The access region for each test signal is a specified page selected sequentially from each block of the DUT according to a specified rule. The test voltage is the standard voltage of the DUT, and the test frequency is the standard clock frequency of the DUT. The DUT comprises N blocks, each containing M pages, and each page is divided into s sectors. The specified rule is that the accessed region selected in the nth block is the i-th sector of the m-th page, where 1 ≤ n ≤ N, m is the remainder when n is divided by M and m = M when M divides n, and i is the remainder when m is divided by s and i = s when s divides m.

[0008] The chip under test is read / write operated using the aforementioned signals under test.

[0009] Verify the correctness of the read / write operation results.

[0010] Preferably, the access areas of the plurality of signals under test are a plurality of designated blocks of the chip under test, the test voltage is the standard voltage of the chip under test, and the test frequency is the standard clock frequency of the chip under test.

[0011] The step of using the plurality of signals under test to perform read / write operations on the chip under test includes:

[0012] The specified number of read / write operations are performed on several specified blocks of the chip under test using the specified signals under test.

[0013] Preferably, the access areas of the plurality of signals to be tested are each block selected sequentially in the chip under test, the test voltage is the standard voltage of the chip under test, and the test frequency is each frequency selected sequentially from a specified frequency range at specified frequency intervals; wherein, the specified frequency range includes the standard clock frequency of the chip under test.

[0014] Preferably, the standard clock frequency of the chip under test is 50MHz, the specified frequency range is 20MHz-100MHz, and the specified frequency interval is 5MHz.

[0015] Preferably, the access regions of the plurality of signals to be tested are each block selected sequentially in the chip under test, the test frequency is the standard clock frequency of the chip under test, and the test voltage is each voltage selected sequentially from a specified voltage range at a specified voltage interval; wherein, the specified voltage range includes the standard voltage of the chip under test.

[0016] Preferably, the standard voltage of the chip under test is 3.3V, the specified voltage range is 2.7V-3.6V, and the specified voltage interval is 0.1V.

[0017] According to a second aspect of the present invention, a performance testing apparatus for an SPI NAND Flash chip is provided, the apparatus comprising a complex programmable logic device and a level conversion module; wherein,

[0018] The complex programmable logic device is used to control the level conversion module to generate several test signals for the chip under test, so as to realize the SPI NAND Flash chip performance testing method as described in any embodiment of the present invention.

[0019] The level conversion module is used to generate the plurality of signals to be tested in order to perform read / write operations on the chip under test.

[0020] Preferably, the complex programmable logic device includes a level control module, a clock control module, a data reading module, and a data writing module; wherein,

[0021] The level control module is used to control the level conversion module to generate the plurality of signals to be tested;

[0022] The clock control module is used to generate a clock when accessing the chip under test, so as to control the test frequency of the plurality of signals under test;

[0023] The data reading module is used to read the data returned by the chip under test in order to perform a read operation on the chip under test;

[0024] The data writing module is used to write data to the chip under test in order to perform a write operation on the chip under test.

[0025] This invention discloses a method and apparatus for testing the performance of SPI NAND Flash chips. By using complex programmable logic devices to simulate the main control chip, read / write operations can be performed on the SPI NAND Flash chip. By controlling the access area, test voltage, and test frequency, tests of many usage scenarios can be simulated in a short time to quickly verify the various extreme performance limits of the SPI NAND Flash chip and whether it meets the requirements of product use, thereby greatly improving testing efficiency.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0027] Figure 1This is a flowchart illustrating a performance testing method for an SPI NAND Flash chip according to an embodiment of the present invention.

[0028] Figure 2 This is an architectural diagram of a chip under test according to an embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of the structure of an SPI NAND Flash chip performance testing device according to an embodiment of the present invention. Detailed Implementation

[0030] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the invention as detailed in the appended claims.

[0031] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms “a,” “the,” and “the” used in this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0032] It should be understood that although the terms first, second, third, etc., may be used in this invention to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first information may also be referred to as second information without departing from the scope of this invention, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "when," "when," or "in response to a determination."

[0033] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1 As shown, Figure 1 This is a flowchart illustrating a performance testing method for an SPI NAND Flash chip according to an embodiment of the present invention, including the following steps:

[0035] Step S101: Use a complex programmable logic device to control the level conversion module to generate several test signals for the chip under test. The test signals include the access area, test voltage and test frequency when performing read / write operations on the chip under test. The chip under test is an SPI NAND Flash chip.

[0036] Step S102: Use several signals under test to perform read / write operations on the chip under test;

[0037] Step S103: Verify the correctness of the read / write operation results.

[0038] Specifically, a Complex Programming Logic Device (CPLD) refers to a high-density, high-speed, and low-power programmable logic device. It consists of programmable logic functions surrounding a programmable interconnect matrix, with fixed-length metal wires used to interconnect the logic units. It also increases the number and functionality of I / O control modules. The basic structure of a CPLD can be viewed as consisting of three parts: a Logic Array Block (LAB), programmable I / O control modules, and a Programmable Interconnect Array (PIA).

[0039] Specifically, the chip under test described in this invention can be an SPI NAND Flash chip of any specification. The chip under test can include several blocks, and each block can include several pages. The CPLD can access any specified block or any specified page in the chip under test through the test signal of the specified access area.

[0040] Specifically, such as Figure 2 As shown, Figure 2 The diagram illustrates the architecture of a chip under test (DUT) according to the present invention. In some embodiments, the DUT used in the present invention includes 1024 blocks, and each block includes 64 pages. Specifically, in other embodiments, the number of blocks and pages included in the DUT can also be other specifications, which can be set according to actual needs, and the present invention does not limit this.

[0041] Specifically, in step S101, the CPLD-simulated master control chip can control the level conversion module to generate several test signals for the chip under test with different access areas, test voltages, and test frequencies, so as to perform multi-dimensional read / write operations on the SPI NAND Flash chip under test, realize the simulation of many usage scenarios in a short time, and quickly verify whether the SPI NAND Flash chip meets the requirements of product use.

[0042] Specifically, in some embodiments, since the chip under test (DUT) comprises several blocks, and each block contains several pages, the access areas of the generated DUT signals can be set to select specific pages from each block of the DUT sequentially according to a specified rule. The test voltage is set to the standard voltage of the DUT, and the test frequency is set to the standard clock frequency of the DUT. That is, during testing, the access areas can be sampled, accessing different page locations in each block while maintaining the standard voltage and frequency. This verifies whether a large number of read / write operations at various locations of the chip are normal. This method can significantly reduce the actual execution time of the test. For example, when each block of the DUT contains 64 pages, if different DUT signals only access one specific page selected from each block according to a specified rule each time, the actual execution time of the entire test only accounts for 1 / 64 of the total DUT read time.

[0043] Specifically, in this invention, the standard voltage of the chip under test can be determined according to the specific specifications of the chip. For example, the standard voltage of some chips under test can be 3.3V, and the standard voltage of some chips under test can also be other values. This invention does not limit this.

[0044] Similarly, in this invention, the standard clock frequency of the chip under test can also be determined according to the specific specifications of the chip. For example, the standard clock frequency of some chips under test can be 50MHz, and the standard clock frequency of some chips under test can also be other values. This invention does not limit this.

[0045] Specifically, in the above test mode, the rule for selecting pages to be accessed in each block can be based on the remainder of the number of pages contained in the current block number. For example, when a block contains 64 pages, Page 1 can be selected in Block 1 and Block 65, Page 2 in Block 2 and Block 66, and so on. This ensures that after all blocks have been accessed, each page location has been accessed in at least one block, so as to avoid missing the case where the chip under test has a fault in a specific page location area, and to ensure that all areas of the chip under test are fully accessed while minimizing test time.

[0046] Specifically, in some embodiments, each page of the chip under test can be divided into multiple sectors, and the signal under test can access only a sector of the page instead of the entire page. After selecting the page to be accessed, a specific sector of the page can be selected for access according to a specified rule to further reduce the actual execution time of the test.

[0047] Specifically, in some embodiments, if the chip under test includes N blocks, each block includes M pages, and each page is divided into s sectors, then the rule for selecting the access region can be: the accessed region selected in the nth block is the i-th sector of the m-th page, where 1 ≤ n ≤ N, m is the remainder of n divided by M and m = M when M divides n, and i is the remainder of m divided by s and i = s when s divides m. By using this sampling access method, when accessing each block, only a specific sector of a specific page within that block is accessed, further reducing the actual test execution time to 1 / (M*s).

[0048] For example, if the chip under test includes 1024 blocks, each block includes 64 pages, and each page includes 4 sectors, then according to the specified rules mentioned above, you can select sector1 of page1 in block1 to access, sector2 of page2 in block2 to access, sector4 of page4 in block4 to access, sector1 of page5 in block5 to access, sector4 of page64 in block64 to access, sector1 of page1 in block65 to access, and so on. In the end, the actual execution time of the entire test only accounts for 1 / 256 of the total reading time of the chip under test.

[0049] Specifically, when accessing sectors using the sampling method described above, different positions can be used to access different sectors. For example, the sampling method can be as follows: for the Sector (remainder of M / 4) of Page (N / 64) in Block N, access is performed using the corresponding M / 4 position from (0x0, 0x5, 0xA, 0xF); specifically: for Sector1 under Page 1 of Block 1, access is performed using 0x0; for Sector2 under Page 2 of Block 2, access is performed using 0x5... for Sector1 under Page 5 of Block 5, access is performed using 0x0... for Sector1 under Page 1 of Block 65, access is performed using 0x0. Finally, by adopting the above sampling method, it can be verified whether a large number of read / write operations are normal at various locations in the chip under test, and its actual execution time only accounts for 1 / 256 of the total chip read time.

[0050] Specifically, in some embodiments, pages to be accessed in each block can be selected according to other specified rules. The specific settings can be configured according to actual needs, and the present invention does not limit this.

[0051] Specifically, in addition to the extreme case of accessing a large number of locations in the chip under test, there are also cases where multiple locations in the chip are accessed multiple times.

[0052] Specifically, in step S101, the access areas of the several signals under test can be set as several designated blocks of the chip under test, and the test voltage is set to the standard voltage of the chip under test, and the test frequency is set to the standard clock frequency of the chip under test. In step S102, when using the generated signals under test to perform read / write operations on the chip under test, it can include performing a specified number of read / write operations on several designated blocks of the chip under test using the several signals under test. The designated blocks can be several blocks evenly distributed and selected from the chip under test. For example, in some embodiments, Block1, Block512, and Block1024 can be selected from a chip under test containing 1024 blocks as several designated blocks for fixed access. Specifically, in other embodiments, other numbers of other blocks can also be selected as several designated blocks for fixed access; this invention does not limit this. Specifically, the specified number of operations can be a relatively large and reasonable value, such as 100,000 times or other values, to test the performance of the chip under test under extreme conditions of frequent read / write access. Specifically, in one example, a standard voltage of 3.3V and a normal clock of 50MHz can be used. Read / write operations can be performed on fixed Block 1, Block 512, and Block 1024 to verify whether the chip under test can perform 100,000 read / write operations normally. The time of the entire read / write operation test only accounts for 3 / 1024 of the total read / write time of the chip.

[0053] Specifically, in addition to testing the performance of the chip under test at different access locations and with different access counts, it is also important to test the performance of the chip under test under different voltage conditions and different frequency conditions.

[0054] Specifically, in step S101, the access areas of several signals to be tested can be set to the blocks selected sequentially in the chip under test, the test voltage can be set to the standard voltage of the chip under test, and the test frequency can be set to the frequencies selected sequentially from the specified frequency range at specified frequency intervals; wherein, the specified frequency range may include the standard clock frequency of the chip under test.

[0055] Specifically, in some embodiments, if the standard clock frequency of the chip under test is 50MHz, then the specified frequency range can be 20MHz-100MHz, and the specified frequency interval can be 5MHz. That is, a standard voltage of 3.3V can be used, with the clock frequency ranging from 20MHz to 100MHz, in 5MHz increments, on a block-by-block basis, to sequentially perform read / write operations at different frequencies. For example, Block 0 is tested at 20MHz for read / write correctness, Block 1 at 25MHz, ... Block 17 at 100MHz, Block 18 at 20MHz, and so on, in a cyclical test to test the read / write performance of the chip under test at different frequencies.

[0056] Specifically, in step S101, the access areas of several signals to be tested can be set as blocks selected sequentially in the chip under test, the test frequency can be set as the standard clock frequency of the chip under test, and the test voltage can be set as voltages selected sequentially from a specified voltage range at specified voltage intervals; wherein, the specified voltage range may include the standard voltage of the chip under test.

[0057] Specifically, in some embodiments, if the standard voltage of the chip under test is 3.3V, then the specified voltage range can be 2.7V-3.6V, and the specified voltage interval can be 0.1V. That is, a normal clock of 50MHz can be used, with the control level between 2.7V and 3.6V. The CPLD, through a control level conversion module, performs read / write operations on the entire chip in 0.1V increments, in blocks, to verify the correctness of read / write operations under different voltages. For example, Block 0 is verified using 2.7V, Block 1 using 2.8V, ... Block 10 using 3.6V, Block 11 using 2.7V, and so on, in a cyclical test to test the read / write performance of the chip under test under different voltages.

[0058] In summary, the SPI NAND Flash chip performance testing method disclosed in this invention can use complex programmable logic devices to simulate the main control chip, perform read / write operations on the SPI NAND Flash chip, and by controlling the access area, test voltage, and test frequency, it can simulate a large number of usage scenarios in a short time, so as to quickly verify the various extreme performance limits of the SPI NAND Flash chip and whether it meets the product use requirements, thereby greatly improving the testing efficiency.

[0059] Compared to the normal process of reading and writing a complete chip using a programmer, which takes about 30 seconds and over a month to perform 100,000 operations, this invention, by controlling the clock and access area, can complete various extreme tests in a shorter time. Furthermore, by controlling signal drive capability and current level, it enables access to the SPI NAND Flash chip in various environments. Ultimately, a large number of read and write experiments in multiple scenarios can be completed within one day, saving significant testing time and ensuring more thorough testing.

[0060] Corresponding to the SPI NAND Flash chip performance testing method embodiment described above, the present invention also provides an SPI NAND Flash chip performance testing device.

[0061] like Figure 3 As shown, Figure 3 This is a schematic diagram of a performance testing device for an SPI NAND Flash chip according to an embodiment of the present invention. The device includes a complex programmable logic device (CPLD) 310 and a level conversion module 320; wherein,

[0062] The complex programmable logic device 310 is used to control the level conversion module 320 to generate several test signals for the chip under test 330, so as to realize the SPI NAND Flash chip performance testing method as described in any embodiment of the present invention.

[0063] The level conversion module 320 is used to generate several signals to be tested for reading / writing operations on the chip 330 under test.

[0064] Specifically, the complex programmable logic device 310 can be any CPLD device that can simulate the main controller, while the level conversion module 320 can be any level conversion circuit that can be used to control the level and current of the signal from the CPLD to the SPI NAND Flash chip. The present invention does not limit the specific circuits of the complex programmable logic device 310 and the level conversion module 320.

[0065] Specifically, in some embodiments, the complex programmable logic device 310 may include a level control module 311, a clock control module 312, a data reading module 313, and a data writing module 314; wherein,

[0066] Level control module 311 is used to control level conversion module 320 to generate the plurality of signals to be tested;

[0067] The clock control module 312 is used to generate a clock when accessing the chip under test 330, so as to control the test frequency of several signals under test;

[0068] The data reading module 313 is used to read the data returned by the chip under test 330 in order to perform a read operation on the chip under test 330;

[0069] The data writing module 324 is used to write data to the chip under test 330 in order to perform a write operation on the chip under test 330.

[0070] Specifically, the data reading module 313 can receive the data returned by the chip under test 330 through the clock / chip select / RX on the CPLD device; while the data writing module 314 can write data to the chip under test 330 through the clock / chip select / TX on the CPLD device; the clock control module 312 is responsible for generating various clocks required for access; and the level control module 311 is responsible for controlling the level conversion module 320 to provide the level control of the signal under test to the chip under test 330, so as to realize the test under different levels.

[0071] Specifically, the implementation process of the functions and roles of each module in the above device is detailed in the implementation process of the corresponding steps in the above method, and will not be repeated here.

[0072] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to in the description of the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected to achieve the purpose of the present invention according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0073] The various embodiments in this invention are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments. The device embodiments described above are merely illustrative. The modules described as separate components may or may not be physically separate. In implementing the present invention, the functions of each module can be implemented in one or more software and / or hardware. Alternatively, some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0074] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the implementation of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the claims of the present invention.

Claims

1. A method for testing performance of an SPI NAND Flash chip, characterized in that, The method comprises: The method comprises: The method comprises: The method comprises:

2. The method of claim 1, wherein, The method comprises: The method comprises: The method comprises:

3. The method of claim 1, wherein, The method comprises:

4. The method of claim 3, wherein, The method comprises:

5. The method of claim 1, wherein, The method comprises:

6. The method of claim 5, wherein, The method comprises:

7. An SPI NAND Flash chip performance testing device, characterized in that, The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises: The method comprises:

8. The apparatus of claim 7, wherein, The complex programmable logic device comprises a level control module, a clock control module, a data reading module and a data writing module. The level control module is configured to control the level conversion module to generate the several to-be-tested signals. The clock control module is configured to generate a clock for accessing the to-be-tested chip, so as to control a test frequency of the several to-be-tested signals. The data reading module is configured to read data returned by the to-be-tested chip, so as to perform a read operation on the to-be-tested chip. The data writing module is configured to write data to the to-be-tested chip, so as to perform a write operation on the to-be-tested chip.

Images