Circuit board pad coordinate correction method and system

Abstract

The application discloses a circuit board pad coordinate correction method and system. The method comprises the following steps: positioning a profile reference point of a to-be-tested circuit board. A target area is determined based on the profile reference point, and the target area has a plurality of pads. The target area is divided into at least two correction areas, and a pad in each correction area is selected as a reference point. A first positional relationship between reference points of two adjacent correction areas is obtained, and a second positional relationship between two pads on a standard circuit board corresponding to the reference points of the two adjacent correction areas is obtained. Based on the first positional relationship and the second positional relationship, a coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained. Based on the theoretical coordinates of the pads on the to-be-tested circuit board and the coordinate offset, actual coordinates of all the pads in the two adjacent correction areas are obtained. Thus, the coordinate positions of each pad on the to-be-tested circuit board are corrected, and accurate assembly of subsequent chips is ensured.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit board, in particular to a circuit board pad coordinate correction method and system. BACKGROUND

[0002] In the process of manufacturing circuit board, the pads on the circuit board will appear to expand and shrink. Some pads will locally expand or locally shrink, and some pads will expand or shrink as a whole, which will cause the position of the pads on the circuit board to shift to a certain extent, resulting in the phenomenon of chip fixation deviation in the subsequent process of assembling chips. SUMMARY

[0003] The present application aims to provide a circuit board pad coordinate correction method and system, which first locates the contour reference points of the to-be-tested circuit board to realize the preliminary positioning of the circuit board, and then accurately obtains the actual coordinates of each pad through coordinate correction, so as to facilitate the accurate assembly of subsequent chips.

[0004] The present application provides a circuit board pad coordinate correction method, comprising:

[0005] A. Locate the contour reference points of the to-be-tested circuit board;

[0006] B. Determine a target area based on the contour reference points, and the target area has a plurality of pads;

[0007] C. Divide the target area into at least two correction areas, and select a pad in each correction area as a reference point;

[0008] D. Obtain the first positional relationship between the reference points of the adjacent two correction areas, and obtain the second positional relationship between the two pads on the standard circuit board corresponding to the reference points of the adjacent two correction areas;

[0009] E. Based on the first positional relationship and the second positional relationship, obtain the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board;

[0010] F. Based on the theoretical coordinates of each pad of the to-be-tested circuit board and the coordinate offset, obtain the actual coordinates of all pads in the adjacent two correction areas.

[0011] In some embodiments, the locating of the contour reference points of the to-be-tested circuit board comprises:

[0012] Obtain the image information of the to-be-tested circuit board;

[0013] Compare the image information of the to-be-tested circuit board with the image information of the standard circuit board, and based on the positions of the four reference points on the standard circuit board, obtain the contour reference points of the to-be-tested circuit board.

[0014] In some embodiments, the target region is determined based on the contour reference points, comprising:

[0015] A quadrilateral region enclosed by the contour reference points is taken as the target region.

[0016] In some embodiments, the target region is divided into at least two correction regions, and a reference point is selected in each correction region, comprising:

[0017] The target region is divided into at least two correction regions based on the area of the target region and / or the distance between every two adjacent reference points in the target region, and each correction region has at least one reference point, and a reference point is selected in each correction region.

[0018] In some embodiments, the number of correction regions is positively correlated with the area of the target region, and the number of correction regions is negatively correlated with the distance between every two adjacent reference points in the target region.

[0019] In some embodiments, a first positional relationship between reference points of two adjacent correction regions is obtained, and a second positional relationship between two pads on a standard circuit board corresponding to the reference points of the two adjacent correction regions is obtained, comprising:

[0020] A first distance between reference points of the two adjacent correction regions is obtained, and a second distance between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is obtained.

[0021] In some embodiments, the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first positional relationship and the second positional relationship, comprising:

[0022] A first difference between the first distance and the second distance is obtained, and a first number of pads between the reference points of the two adjacent correction regions is identified, and a first quotient of the first difference and the first number of pads is taken as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board.

[0023] In some embodiments, the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of the pads on the to-be-tested circuit board and the coordinate offset, comprising:

[0024] The reference points in one of the correction regions are taken as a reference, and the theoretical coordinates of all the pads between the two reference points in the two adjacent correction regions are corrected in proportion to the first quotient to obtain the actual coordinates of all the pads between the two reference points in the two adjacent correction regions.

[0025] In some embodiments, the first positional relationship between the reference points of the two adjacent correction regions is obtained, and a second positional relationship between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is obtained, including:

[0026] The third distance of the reference points of the two adjacent correction regions along the X-axis direction of the target coordinate system and the fourth distance of the reference points of the two adjacent correction regions along the Y-axis direction of the target coordinate system are obtained, and the fifth distance of the two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions along the X-axis direction of the target coordinate system and the sixth distance of the two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions along the Y-axis direction of the target coordinate system are obtained.

[0027] In some embodiments, the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first positional relationship and the second positional relationship, including:

[0028] A second difference between the third distance and the fifth distance is obtained, and the second number of pads between the reference points of the two adjacent correction regions along the X-axis direction of the target coordinate system is identified. A first coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the X-axis direction of the target coordinate system is obtained by taking a second quotient of the second difference and the second number of pads as the first coordinate offset. A third difference between the fourth distance and the sixth distance is obtained, and a third number of pads between the reference points of the two adjacent correction regions along the Y-axis direction of the target coordinate system is identified. A second coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the Y-axis direction of the target coordinate system is obtained by taking a third quotient of the third difference and the third number of pads as the second coordinate offset.

[0029] In some embodiments, the actual coordinates of all the pads in the two adjacent correction regions are obtained based on the theoretical coordinates of each pad on the to-be-tested circuit board and the coordinate offset, including:

[0030] The X-axis coordinates of all pads between two reference points in the two adjacent correction regions are corrected proportionally by the second quotient value based on the reference points in one of the correction regions, and the Y-axis coordinates of all pads between the two reference points in the two adjacent correction regions are corrected proportionally by the third quotient value, to obtain the actual coordinates of all pads between the two reference points in the two adjacent correction regions.

[0031] In some embodiments, the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, including:

[0032] A first ratio between the first distance and the second distance is taken as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board.

[0033] In some embodiments, the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of the pads on the to-be-tested circuit board and the coordinate offset, including:

[0034] The theoretical coordinates of all pads in the two adjacent correction regions are corrected proportionally by the first ratio based on a reference point in one of the correction regions, to obtain the actual coordinates of all pads in the two adjacent correction regions.

[0035] In some embodiments, the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, including:

[0036] A second ratio between the third distance and the fifth distance is taken as a third coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the X-axis direction, and a third ratio between the fourth distance and the sixth distance is taken as a fourth coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the Y-axis direction.

[0037] In some embodiments, the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of the pads on the to-be-tested circuit board and the coordinate offset, including:

[0038] The X-axis coordinates of all pads in the two adjacent correction regions are corrected proportionally by the second ratio based on a reference point in one of the correction regions, and the Y-axis coordinates of all pads in the two adjacent correction regions are corrected proportionally by the third ratio, to obtain the actual coordinates of all pads in the two adjacent correction regions.

[0039] In some embodiments, the pad coordinates are corrected in the manner of steps D-F for the remaining adjacent correction regions of all the correction regions until the actual coordinates of all the pads on the circuit board under test are obtained.

[0040] In some embodiments, one of the correction regions contains a pad at the origin of the target coordinate system, and this correction region is the origin region. In the first correction of the pad coordinates, the correction starts from the origin region and the correction region adjacent to the origin region, and the coordinates of the remaining pads are corrected based on the origin in the origin region.

[0041] In some embodiments, in the process of obtaining the actual coordinates of all the pads on the circuit board under test in steps D-F, the coordinates of the pads in each of the correction regions are corrected in turn in a direction away from the origin until the actual coordinates of all the pads on the circuit board under test are obtained.

[0042] Embodiments of the present application also provide a circuit board pad coordinate correction system, comprising:

[0043] A positioning module is configured to position a contour reference point of the circuit board under test.

[0044] An identification module is configured to determine a target region based on the contour reference point.

[0045] A region division module is configured to divide the target region into at least two correction regions.

[0046] A reference point selection module is configured to select a pad in each of the correction regions as a reference point.

[0047] A position acquisition module is configured to obtain a first position relationship between the reference points of two adjacent correction regions, and obtain a second position relationship between two pads on a standard circuit board corresponding to the reference points of the two adjacent correction regions.

[0048] An offset acquisition module is configured to obtain a coordinate offset of the pads on the circuit board under test relative to the pads on the standard circuit board based on the first position relationship and the second position relationship.

[0049] A coordinate correction module is configured to obtain the actual coordinates of all the pads in the two adjacent correction regions based on the theoretical coordinates of the pads on the circuit board under test and the coordinate offset.

[0050] Embodiments of the present application also provide an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method as described above when executing the program.

[0051] The embodiment of the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the method.

[0052] The circuit board pad coordinate correction method and system provided by the embodiment of the present application preliminarily position the circuit board to be measured by positioning the contour reference point on the circuit board to be measured, divide a plurality of correction regions after determining the target region based on the contour reference point, compare the first positional relationship between the reference points of the adjacent two correction regions with the second positional relationship between the pads on the standard circuit board, thereby obtaining the coordinate offset, and obtain the actual coordinates of all pads on the circuit board to be measured by using the theoretical coordinates of the pads and the coordinate offset. Thus, the coordinate position of each pad on the circuit board to be measured can be corrected, the accurate assembly of the subsequent chip is ensured, and the phenomenon of chip fixed offset is prevented. BRIEF DESCRIPTION OF DRAWINGS

[0053] The technical solutions and other beneficial effects of the present application will be apparent through the following detailed description of the specific embodiments of the present application combined with the accompanying drawings.

[0054] Figure 1 The flowchart of the circuit board pad coordinate correction method provided by the embodiment of the present application is shown.

[0055] Figure 2 The flowchart of the positioning contour reference point provided by the embodiment of the present application is shown.

[0056] Figure 3 The flowchart of the obtaining coordinate offset provided by the embodiment of the present application is shown.

[0057] Figure 4 The flowchart of the correcting coordinate provided by the embodiment of the present application is shown.

[0058] Figure 5 The flowchart of the obtaining coordinate offset provided by the embodiment of the present application is shown.

[0059] Figure 6 The flowchart of the correcting coordinate provided by the embodiment of the present application is shown.

[0060] Figure 7 The flowchart of the correcting coordinate provided by the embodiment of the present application is shown.

[0061] Figure 8 The flowchart of the correcting coordinate provided by the embodiment of the present application is shown.

[0062] Figure 9 The structural diagram of the circuit board pad coordinate correction system provided by the embodiment of the present application is shown.

[0063] Figure 10 A structural schematic diagram of a circuit board provided by an embodiment of the present application.

[0064] Figure 11 A structural schematic diagram of an electronic device provided by an embodiment of the present application.

[0065] Reference signs:

[0066] 100 - circuit board to be measured, 110 - contour reference point, 120 - correction area, 130 - solder pad, 910 - positioning module, 920 - identification module, 930 - area division module, 940 - reference point selection module, 950 - position acquisition module, 960 - offset amount acquisition module, 970 - coordinate correction module, 1110 - processor, 1120 - communication interface, 1130 - memory, 1140 - communication bus. DETAILED DESCRIPTION

[0067] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0068] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0069] In the description of the application, it is necessary to point out that, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "linking" should be understood in a broad sense, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection or can communicate with each other; it can be directly connected, or indirectly connected through intermediate medium, or the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0070] In the present application, unless otherwise explicitly specified and limited, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above" and "above" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "under", "below" and "below" the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0071] The following disclosure provides many different embodiments or examples for implementing different structures of the application. In order to simplify the disclosure of the application, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the application. In addition, the application can repeatedly refer to numbers and / or letters in different examples. Such repetition is for the purpose of simplification and clarity, and in itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the application provides examples of various specific processes and materials, but those skilled in the art can realize the application of other processes and / or the use of other materials.

[0072] Specifically, please refer to Figures 1 to 10 The embodiment of the application provides a circuit board pad coordinate correction method, comprising:

[0073] Step A, positioning the contour reference point 110 of the circuit board to be tested 100.

[0074] Step B, determining a target area based on the contour reference point 110, the target area having a plurality of pads 130 therein.

[0075] Step C, dividing the target area into at least two correction areas 120, and selecting a pad 130 in each correction area 120 as a reference point.

[0076] Step D, obtaining a first positional relationship between the reference points of the two adjacent correction regions 120, and obtaining a second positional relationship between two pads 130 on the standard circuit board corresponding to the reference points of the two adjacent correction regions 120.

[0077] Step E, based on the first positional relationship and the second positional relationship, obtaining the coordinate offset of the pads 130 on the to-be-tested circuit board 100 relative to the pads on the standard circuit board.

[0078] Step F, based on the theoretical coordinates of each pad 130 on the to-be-tested circuit board 100 and the coordinate offset, obtaining the actual coordinates of all pads 130 in the two adjacent correction regions 120.

[0079] In the embodiment, the to-be-tested circuit board 100 is preliminarily positioned by positioning the contour reference points 110 on the to-be-tested circuit board 100, a plurality of correction regions 120 are divided based on the target region determined based on the contour reference points 110, the first positional relationship between the reference points of the two adjacent correction regions 120 is compared with the second positional relationship between the pads 130 on the standard circuit board, so as to obtain the coordinate offset, and the actual coordinates of all pads 130 on the to-be-tested circuit board 100 are obtained by the theoretical coordinates of the pads 130 and the coordinate offset. Thus, the coordinate position of each pad 130 on the to-be-tested circuit board 100 can be corrected, the accurate assembly of the subsequent chip is ensured, and the phenomenon of chip fixed offset is prevented.

[0080] The contour reference points 110 are four reference points (Mark points) on the to-be-tested circuit board 100. The four reference points are usually located at the four corners of the to-be-tested circuit board 100, so that the preliminary position of the to-be-tested circuit board 100 can be obtained to preliminarily position the to-be-tested circuit board 100.

[0081] The target region is determined based on the contour reference points 110. Since the to-be-tested circuit board 100 is usually square and the contour reference points 110 are usually located at the four corners of the to-be-tested circuit board 100, the region enclosed by the contour reference points 110 in sequence is the target region. The target region is usually a rectangular region or a square region. All pads 130 on the to-be-tested circuit board 100 are located in the target region, and the theoretical coordinates of all pads 130 can be obtained after establishing a plane rectangular coordinate system in the target region.

[0082] Based on the fact that the target region is usually a rectangular region or a square region, the at least two correction regions 120 divided in the target region are also rectangular regions or square regions. The shape and size of each correction region 120 are the same. The number of pads 130 in each correction region 120 is the same or different.

[0083] The first positional relationship between two reference points in each two adjacent correction areas 120 can be the distance between the two reference points, the ratio of the distance between the two reference points to the number of pads, or the difference between the X-axis coordinates and the difference between the Y-axis coordinates of the two reference points. The second positional relationship between two pads corresponding to the two reference points on the standard circuit board can be the distance between the two pads, the ratio of the distance between the two pads to the number of pads, or the difference between the X-axis coordinates and the difference between the Y-axis coordinates of the two pads.

[0084] By combining the first positional relationship and the second positional relationship, the coordinate offset of the pads 130 on the to-be-tested circuit board 100 relative to the pads on the standard circuit board can be calculated. By combining the theoretical coordinates of the pads 130 on the to-be-tested circuit board 100 and the coordinate offset, the actual coordinates of the pads 130 on the to-be-tested circuit board 100 can be corrected, thereby facilitating accurate assembly of subsequent chips.

[0085] The to-be-tested circuit board 100 is pre-positioned by the contour reference point 110, and the actual coordinates of the pads 130 are obtained by combining the subsequent coordinate correction of the pads 130. In the process of subsequent chip installation, the actual coordinates can be directly used for chip assembly, so that the chips can be accurately assembled to each pad 130, preventing the occurrence of chip fixation, reducing the scrap rate, and improving the yield of the product. At the same time, the product rework situation can be reduced, thereby reducing the loss of chips and solder paste, reducing the cost of consumables and labor, and preventing the waste of effective working time of the machine due to rework.

[0086] It can be understood that the to-be-tested circuit board 100 and the standard circuit board are two types of circuit boards of the same model. Based on the modification of the theoretical coordinates of the pads 130 on the to-be-tested circuit board 100, a planar rectangular coordinate system can be established on the to-be-tested circuit board 100 or on the standard circuit board. The theoretical coordinates of the pads 130 on the to-be-tested circuit board 100 are the same as the theoretical coordinates of the pads on the standard circuit board.

[0087] As shown in FIG. 1, Figure 2 In some embodiments, the contour reference point 110 for positioning the to-be-tested circuit board 100 includes:

[0088] S210, obtaining image information of the to-be-tested circuit board 100.

[0089] S220, comparing the image information of the to-be-tested circuit board 100 with the image information of the standard circuit board, and obtaining the contour reference point 110 of the to-be-tested circuit board 100 based on the positions of the four reference points on the standard circuit board.

[0090] The image information of the to-be-tested circuit board 100 can be acquired by using an image acquisition device. The image acquisition device can be a die bonder CCD (charge coupled device) camera, which can take a photo of the to-be-tested circuit board 100 to acquire the image information of the to-be-tested circuit board 100. After the image acquisition device acquires the image information of the to-be-tested circuit board 100, the image information of the to-be-tested circuit board 100 is transmitted to the central control unit. The central control unit pre-stores the image information of a standard circuit board. The central control unit compares the image information of the to-be-tested circuit board 100 with the image information of the standard circuit board, and obtains the contour reference points 110 on the to-be-tested circuit board 100 based on the four standard positions of the standard circuit board.

[0091] It can be understood that the central control unit can pre-store the image information of standard circuit boards of different models. Based on the model of the to-be-tested circuit board 100, the central control unit compares and contrasts the image information of the to-be-tested circuit board 100 with the image information of the standard circuit board of the corresponding model, so as to acquire the contour reference points 110 on the to-be-tested circuit board 100.

[0092] The image information of the standard circuit board stored in the central control unit can be a photo, a CAD drawing, a PDF drawing, or the like.

[0093] The specific manner in which the image information of the to-be-tested circuit board 100 is compared with the image information of the standard circuit board can be that the image size of the to-be-tested circuit board 100 is the same as the image size of the standard circuit board, and the images are aligned in the length direction and the width direction. At this time, the positions of the four standard points on the standard circuit board are the positions of the contour reference points 110 on the to-be-tested circuit board 100.

[0094] In some embodiments, the target region is determined based on the contour reference points 110, including:

[0095] The quadrilateral region enclosed by the contour reference points 110 is taken as the target region.

[0096] The contour reference points 110 are taken as the four vertices of the quadrilateral. The contour reference points 110 are sequentially connected, and a quadrilateral target region is enclosed.

[0097] The positions of all the pads 130 in the target region can also be acquired by using the image acquisition device, so that the theoretical coordinates of each pad 130 on the to-be-tested circuit board 100 can be known by comparing with the standard circuit board. The image acquisition device can also be a die bonder CCD camera, which can acquire the image information of the target region in a photo-taking manner and identify all the pads 130 in the target region based on the image information.

[0098] In some embodiments, a plane rectangular coordinate system can also be established in the target area with the pad 130 at the center position as the origin, and the coordinate of the pad 130 at the center position is (0, 0), and then the theoretical coordinates of the remaining pads 130 are obtained respectively. For example, the coordinates of the pads 130 in the first quadrant can be (1, 1), (2, 4), etc.

[0099] A plane rectangular coordinate system is established with the pad 130 at the center position as the origin, and then the coordinates of the remaining pads 130 can be corrected with the pad 130 at the center position as the reference.

[0100] In some embodiments, the target area is divided into at least two correction regions 120, and a pad 130 is selected as a reference point in each correction region 120, including:

[0101] Based on the area of the target area and / or the distance between every two adjacent pads 130 in the target area, the target area is divided into at least two correction regions 120, and each correction region 120 has at least one pad 130. A pad 130 is selected as a reference point in each correction region 120.

[0102] According to the area division rule, the target area is divided into at least two correction regions 120, each correction region 120 has at least one pad 130, and a pad 130 is selected as a reference point for subsequent calculation.

[0103] For example, the target area is divided into 8 correction regions 120, each correction region 120 has 20 pads 130, and the pad 130 at the center of each correction region 120 is selected as the reference point. Of course, the pads 130 at the lower left corner, the upper left corner, the lower right corner, and the upper right corner of each correction region 120 can also be selected as the reference point.

[0104] In some embodiments, the number of correction regions 120 is positively correlated with the area of the target area, and the number of correction regions 120 is negatively correlated with the distance between every two adjacent pads 130 in the target area.

[0105] It can be understood that the larger the area of the target area is, the more the number of correction regions 120 is, so as to prevent the number of correction regions 120 from being too small to cause the number of pads 130 in each correction region 120 to be too large, resulting in inaccurate correction of the coordinates of some pads 130, thereby ensuring the reliability of the correction of the coordinates of the pads 130. The smaller the area of the target area is, the smaller the number of correction regions 120 is, so as to prevent the number of correction regions 120 from being too large to cause the number of pads 130 in each correction region 120 to be too small, resulting in redundant correction steps, thereby ensuring the efficiency of the correction of the coordinates of the pads 130.

[0106] It can be understood that the greater the distance between each two adjacent pads 130, the fewer the number of correction regions 120, and the larger the area corresponding to the correction regions 120, so as to prevent the number of correction regions 120 from being too small to cause the number of pads in each correction region 120 to be too small, resulting in the coordinate correction of some pads 130 being inaccurate, thereby ensuring the reliability of the coordinate correction of the pads 130. The smaller the distance between each two adjacent pads 130, the greater the number of correction regions 120, and the smaller the area corresponding to the correction regions 120, so as to prevent the number of correction regions 120 from being too large to cause the number of pads in each correction region 120 to be too large, resulting in the coordinate correction of some pads 130 being redundant, thereby ensuring the efficiency of the coordinate correction of the pads 130.

[0107] In some embodiments, the relationship between the number of correction regions 120 and the area of the target region and the distance between each two adjacent pads 130 in the target region is n=kS / L. Wherein n is the number of correction regions 120; S is the area of the target region; L is the distance between each two adjacent pads 130 in the target region; k is an empirical constant, which is valued based on different circuit board models, for example, k=1, 2, 3, 4, ….

[0108] For example, the processor can generate the shape of the correction region 120 based on the shape of the to-be-tested circuit board 100 after scaling. The area of the correction region 120 can be set, and after identifying the area of the target region, a certain number of correction regions 120 are generated based on the set area of the correction region 120. Alternatively, the number of pads 130 in the correction region 120 can also be set, and after identifying the distance between each two adjacent pads 130 in the target region, a certain number of correction regions 120 are generated based on the set number of pads 130 in the correction region 120 combined with the distance.

[0109] In some embodiments, the first positional relationship between the reference points of the two adjacent correction regions 120 is obtained, and the second positional relationship between the two pads 130 on the standard circuit board corresponding to the reference points of the two adjacent correction regions 120 is obtained, including:

[0110] The first distance between the reference points of the two adjacent correction regions 120 is obtained.

[0111] The second distance between the two pads 130 on the standard circuit board corresponding to the reference points of the two adjacent correction regions 120 is obtained.

[0112] It can be understood that the first positional relationship is the distance relationship between the reference points of the two adjacent correction regions 120. The second positional relationship is the distance relationship between the two pads 130 on the standard circuit board corresponding to the two adjacent correction regions 120.

[0113] At the first time of coordinate correction, the first distance between the reference points in the correction region 120 corresponding to the original point and the correction region 120 adjacent to the original point can be obtained, and then the coordinates of the circuit board 100 to be measured can be corrected from the correction region 120 at the original point position, and then gradually spread to the surroundings to realize the gradual correction of the coordinates of the pads 130.

[0114] It can be understood that the number of pads, the size and the number of the correction regions 120 between the standard circuit board and the circuit board 100 to be measured are the same. Thus, the offset of the pads 130 on the standard circuit board can be directly reflected by the first position relationship and the second position relationship, so as to correct the theoretical coordinates of the pads 130.

[0115] As shown in Figure 3 In some embodiments, based on the first position relationship and the second position relationship, the coordinate offset of the pads 130 on the circuit board 100 to be measured relative to the pads on the standard circuit board includes:

[0116] S310, obtaining a first difference between the first distance and the second distance.

[0117] S320, identifying the first pad number between the reference points of the two adjacent correction regions 120.

[0118] S330, taking the first quotient value of the first difference and the first pad number as the coordinate offset of the pads 130 on the circuit board 100 to be measured relative to the pads on the standard circuit board.

[0119] Based on the numerical value of the first difference, the offset of the pads 130 on the circuit board 100 to be measured can be determined. Based on the first quotient value of the first difference and the first pad number, the correction rate of each pad 130 can be obtained to realize the coordinate correction of the pads 130.

[0120] Wherein, the first distance is P1, the second distance is P2, and the first difference is Q1. Then Q1=P1-P2. The first pad number between the reference points of the two adjacent correction regions 120 is R1, and the first quotient value is K1. Then K1=Q1 / R1. When Q1>0, the pads 130 corresponding to the correction region 120 on the circuit board 100 to be measured have "expanded". When Q1<0, the pads 130 corresponding to the correction region 120 on the circuit board 100 to be measured have "shrunk".

[0121] For example, when P1=11 and P2=10, Q1=1. At this time, if there are 10 pads 130 between the reference points of the two adjacent correction regions 120, R1=10. The corresponding coordinate offset K1=0.1.

[0122] As shown in Figure 4As shown, in some embodiments, based on the theoretical coordinates of each pad 130 of the to-be-tested circuit board 100 and the coordinate offset, the actual coordinates of the pads 130 in the adjacent two correction regions 120 are obtained, including:

[0123] S410, taking the reference point in one of the correction regions 120 as the reference.

[0124] S420, correcting the theoretical coordinates of all pads 130 located between the two reference points in the adjacent two correction regions 120 in proportion to the first quotient.

[0125] S430, obtaining the actual coordinates of all pads 130 located between the two reference points in the adjacent two correction regions 120.

[0126] It can be understood that based on the above-mentioned manner, whether the pads 130 between the two reference points have expanded or shrunk can be determined, and thus the coordinates of the pads 130 in the range are corrected to ensure the accuracy of the coordinate correction.

[0127] For example, when P1=11 and P2=10, then Q1=1. At this time, if there are 10 pads 130 between the reference points of the adjacent two correction regions 120, then R1=10. The corresponding coordinate offset K1=0.1. At this time, if the reference point with the coordinate value (0, 0) is taken as the reference, the pads 130 with the coordinate values (1, 0), (2, 0), …, (10, 0) are corrected, and the corrected actual coordinates are (1.1, 0), (2.2, 0), …, (11, 0).

[0128] For example, when P1=11 and P2=10, then Q1=1. At this time, if there are 10 pads 130 between the reference points of the adjacent two correction regions 120, then R1=10. The corresponding coordinate offset K1=0.1. At this time, if the reference point with the coordinate value (3, 3) is taken as the reference, the pads 130 with the coordinate values (4, 4), (5, 5), …, (13, 13) are corrected, and the corrected actual coordinates are (4.4, 4.4), (5.5, 5.5), …, (14, 14).

[0129] For example, when P1=9 and P2=10, then Q1=-1. At this time, if there are 5 pads 130 between the reference points of the adjacent two correction regions 120, then R1=5. The corresponding coordinate offset K1=-0.2. At this time, if the reference point with the coordinate value (0, 0) is taken as the reference, the pads 130 with the coordinate values (1, 0), (2, 0), …, (5, 0) are corrected, and the corrected actual coordinates are (0.8, 0), (1.6, 0), …, (4, 0).

[0130] In some embodiments, the first positional relationship between the reference points of the two adjacent correction regions 120 is obtained, and the second positional relationship between the two pads 130 on the standard circuit board corresponding to the reference points of the two adjacent correction regions 120 is obtained, including:

[0131] The third distance along the X-axis direction of the target coordinate system and the fourth distance along the Y-axis direction of the target coordinate system of the reference points of the two adjacent correction regions 120 are obtained, and the fifth distance along the X-axis direction of the target coordinate system and the sixth distance along the Y-axis direction of the target coordinate system of the two pads 130 on the standard circuit board corresponding to the reference points of the two adjacent correction regions 120 are obtained.

[0132] It can be understood that the first positional relationship is the third distance along the X-axis direction and the fourth distance along the Y-axis direction of the two reference points in the two adjacent correction regions 120. The second positional relationship is the fifth distance along the X-axis direction and the sixth distance along the Y-axis direction of the two pads 130 on the standard circuit board corresponding to the two reference points of the two adjacent correction regions 120.

[0133] In the process of the first coordinate correction, by obtaining the third distance along the X-axis direction and the fourth distance along the Y-axis direction of the reference points in the origin region and the adjacent correction region 120 first, the coordinates of the to-be-tested circuit board 100 can be corrected from the correction region 120 close to the origin position, and then gradually spread to the surrounding, to realize the step-by-step correction of the coordinates of the pads 130.

[0134] Based on the separate calculation along the X-axis direction and the Y-axis direction, the accuracy of the coordinate correction can be improved.

[0135] The target coordinate system can be established in the manner of taking one of the pads as the origin of the plane rectangular coordinate system.

[0136] As shown in FIG. 1, Figure 5 In some embodiments, based on the first positional relationship and the second positional relationship, the coordinate offset of the pads 130 on the to-be-tested circuit board 100 relative to the pads on the standard circuit board is obtained, including:

[0137] S510, obtaining a second difference between the third distance and the fifth distance.

[0138] S520, identifying the second pad number along the X-axis direction between the reference points of the two adjacent correction regions 120.

[0139] S530, taking the second quotient value of the second difference and the second pad number as the first coordinate offset of the pads 130 on the to-be-tested circuit board 100 relative to the pads on the standard circuit board in the X-axis direction.

[0140] S540, obtaining a third difference value between the fourth distance and the sixth distance.

[0141] S550, identifying a third number of pads between the reference points of the two adjacent correction regions 120 in the Y-axis direction.

[0142] S560, taking the third quotient value of the third difference value and the third number of pads as a second coordinate offset of the pads 130 on the to-be-tested circuit board 100 relative to the pads on the standard circuit board in the Y-axis direction.

[0143] Based on the numerical value of the second difference value, the offset of the pads 130 on the to-be-tested circuit board 100 in the X-axis direction can be determined, and based on the numerical value of the third difference value, the offset of the pads 130 on the to-be-tested circuit board 100 in the Y-axis direction can be determined. Based on the second quotient value of the second difference value and the second number of pads, the correction rate of each pad 130 in the X-axis direction can be obtained, and based on the third quotient value of the third difference value and the third number of pads, the correction rate of each pad 130 in the Y-axis direction can be obtained, so as to realize the coordinate correction of the pads 130.

[0144] Wherein, the third distance is P3, the fifth distance is P5, and the second difference value is Q2. Then Q2 = P3 - P5. The second number of pads between the reference points of the two adjacent correction regions 120 in the X-axis direction is R2, and the second quotient value is K2. Then K2 = Q2 / R2. When Q2 > 0, the pads 130 corresponding to the correction region 120 on the to-be-tested circuit board 100 have "expanded" in the X-axis direction. When Q2 < 0, the pads 130 corresponding to the correction region 120 on the to-be-tested circuit board 100 have "shrunk" in the X-axis direction.

[0145] For example, when P3 = 11 and P5 = 10, then Q2 = 1. At this time, if the reference points of the two adjacent correction regions 120 have 10 pads 130 in the X-axis direction, then R2 = 10. The corresponding first coordinate offset K2 = 0.1.

[0146] Wherein, the fourth distance is P4, the sixth distance is P6, and the third difference value is Q3. Then Q3 = P4 - P6. The third number of pads between the reference points of the two adjacent correction regions 120 in the Y-axis direction is R3, and the third quotient value is K3. Then K3 = Q3 / R3. When Q3 > 0, the pads 130 corresponding to the correction region 120 on the to-be-tested circuit board 100 have "expanded" in the Y-axis direction. When Q3 < 0, the pads 130 corresponding to the correction region 120 on the to-be-tested circuit board 100 have "shrunk" in the Y-axis direction.

[0147] For example, when P4=11 and P6=10, Q3=1. At this time, if the two adjacent correction regions 120 have 10 pads 130 between the reference points in the Y-axis direction, R3=10. The corresponding second coordinate offset K3=0.1.

[0148] In some embodiments, as shown in FIG. 6, based on the theoretical coordinates of each pad 130 of the circuit board 100 under test and the coordinate offset, the actual coordinates of all pads 130 in the two adjacent correction regions 120 are obtained, including: Figure 6

[0149] S610, taking one of the reference points in one of the correction regions 120 as the reference.

[0150] S620, correcting the X-axis coordinates of all pads 130 between the two reference points in the two adjacent correction regions 120 in proportion to the second quotient.

[0151] S630, correcting the Y-axis coordinates of all pads 130 between the two reference points in the two adjacent correction regions 120 in proportion to the third quotient.

[0152] S640, obtaining the actual coordinates of all pads 130 between the two reference points in the two adjacent correction regions 120.

[0153] It can be understood that based on the above method, it can be determined whether the pads 130 between the two reference points have expanded or shrunk in the X-axis direction and the Y-axis direction, and thus the X-axis coordinates and the Y-axis coordinates of the pads 130 in the range are corrected respectively to ensure the accuracy of the coordinate correction.

[0154] For example, when P3=11 and P5=10, Q2=1. At this time, if the two adjacent correction regions 120 have 10 pads 130 between the reference points in the X-axis direction, R2=10. The corresponding first coordinate offset K2=0.1. For example, when P4=11 and P6=10, Q3=1. At this time, if the two adjacent correction regions 120 have 10 pads 130 between the reference points in the Y-axis direction, R3=10. The corresponding second coordinate offset K3=0.1. At this time, if the reference point with a coordinate value of (0, 0) is taken as the reference, the pads 130 with coordinate values of (1, 0), (0, 1), (2, 0), (2, 1), (2, 2) …, (10, 10) are corrected, and the corrected actual coordinates are (1.1, 0), (0, 1.1), (2.2, 0), (2.2, 1.1), (2.2, 2.2) …, (11, 11).

[0155] ​For example, when P3=11 and P5=10, Q2=1. At this time, if there are 10 pads 130 between the reference points of the two adjacent correction areas 120 in the X-axis direction, R2=10. The corresponding first coordinate offset K2=0.1. For example, when P4=10 and P6=10, Q3=0. At this time, if there are 10 pads 130 between the reference points of the two adjacent correction areas 120 in the Y-axis direction, R3=10. The corresponding second coordinate offset K3=0. At this time, if the pads 130 with coordinate values of (1, 0), (0, 1), (2, 0), (2, 1), (2, 2), …, (10, 10) are corrected in coordinates with the reference point with a coordinate value of (0, 0) as the reference, the corrected actual coordinates are (1.1, 0), (0, 1), (2.2, 0), (2.2, 1), (2.2, 2), …, (11, 10).

[0156] For example, when P3=9 and P5=10, Q2=-1. At this time, if there are 10 pads 130 between the reference points of the two adjacent correction areas 120 in the X-axis direction, R2=10. The corresponding first coordinate offset K2=-0.1. For example, when P4=11 and P6=10, Q3=1. At this time, if there are 10 pads 130 between the reference points of the two adjacent correction areas 120 in the Y-axis direction, R3=10. The corresponding second coordinate offset K3=0.1. At this time, if the pads 130 with coordinate values of (1, 0), (0, 1), (2, 0), (2, 1), (2, 2), …, (10, 10) are corrected in coordinates with the reference point with a coordinate value of (0, 0) as the reference, the corrected actual coordinates are (0.9, 0), (0, 1.1), (1.8, 0), (1.8, 1.1), (1.8, 2.2), …, (9, 11).

[0157] In some embodiments, based on the first position relationship and the second position relationship, the coordinate offset of the pads 130 on the to-be-tested circuit board 100 relative to the pads on the standard circuit board is obtained, including:

[0158] The first ratio between the first interval and the second interval is taken as the coordinate offset of the pads 130 on the to-be-tested circuit board 100 relative to the pads on the standard circuit board.

[0159] The coordinate offset is calculated in the first ratio manner, facilitating quick calculation of the coordinate offset. Specifically, the relationship formula of the first interval, the second interval, and the coordinate offset is: m=L2 / L1. Wherein, m is the coordinate offset, L1 is the first interval, and L2 is the second interval. For example, when L1=1 and L2=1.2, m=1.2. For example, when L1=1 and L2=1, m=1.

[0160] AsFigure 7 As shown in some embodiments, based on the theoretical coordinates of each pad 130 of the to-be-tested circuit board 100 and the coordinate offset, the actual coordinates of all pads 130 in the adjacent two correction regions 120 are obtained, including:

[0161] S710, taking the reference point in one of the correction regions 120 as a reference.

[0162] S720, correcting the theoretical coordinates of all pads 130 in the adjacent two correction regions 120 in a first ratio.

[0163] S730, obtaining the actual coordinates of all pads 130 in the adjacent two correction regions 120.

[0164] Based on the calculated first ratio and the theoretical coordinates of all pads 130 in the two correction regions 120, the correction coordinates of all pads 130 in the two correction regions 120 can be obtained. For example, when L1 = 1 and L2 = 1.2, then m = 1.2. At this time, if the theoretical coordinates of the pad 130 on the to-be-tested circuit board 100 are (1, 1), then it is corrected to (1.2, 1.2). For example, when L1 = 1 and L2 = 1, then m = 1. At this time, no coordinate correction is needed for the pad 130 on the to-be-tested circuit board 100.

[0165] In some embodiments, based on the first position relationship and the second position relationship, the coordinate offset of the pad 130 on the to-be-tested circuit board 100 relative to the pad on the standard circuit board is obtained, including:

[0166] The second ratio between the third distance and the fifth distance is taken as the third coordinate offset of the pad 130 on the to-be-tested circuit board 100 relative to the pad on the standard circuit board in the X-axis direction, and the third ratio between the fourth distance and the sixth distance is taken as the fourth coordinate offset of the pad 130 on the to-be-tested circuit board 100 relative to the pad on the standard circuit board in the Y-axis direction.

[0167] The first coordinate offset in the X-axis direction is calculated in the form of the second ratio, which facilitates the rapid calculation of the coordinate offset. Specifically, the third distance, the fifth distance, and the first coordinate offset relationship are: Mx = L5 / L3. Wherein, Mx is the first coordinate offset, L3 is the third distance, and L5 is the fifth distance. For example, when L3 = 1 and L5 = 1.1, then Mx = 1.1. For example, when L3 = 1 and L5 = 1, then Mx = 1.

[0168] The second coordinate offset in the Y-axis direction is calculated using the third ratio, facilitating rapid calculation of the coordinate offset. Specifically, the relationship between the fourth and sixth spacings and the second coordinate offset is: My = L6 / L4. Where My is the second coordinate offset, L4 is the fourth spacing, and L6 is the sixth spacing. For example, when L4 = 1 and L6 = 1.1, then My = 1.1.

[0169] like Figure 8 As shown, in some embodiments, based on the theoretical coordinates and coordinate offsets of each pad 130 of the circuit board under test 100, the actual coordinates of all pads 130 within two adjacent correction regions 120 are obtained, including:

[0170] S810, using a reference point within one of the correction regions 120 as a reference.

[0171] S820, proportionally correct the X-axis coordinates of all pads 130 within the two adjacent correction regions 120 using the second ratio.

[0172] S830, proportionally correct the Y-axis coordinates of all pads 130 within the two adjacent correction regions 120 using the third ratio.

[0173] S840, to obtain the actual coordinates of all pads 130 within two adjacent correction regions 120.

[0174] Based on the calculated second and third ratios combined with the theoretical coordinates of all pads 130 within the two correction regions 120, the corrected coordinates of all pads 130 within the two correction regions 120 can be obtained. For example, when Mx = 1.1 and My = 1, if the theoretical coordinates of pad 130 on the circuit board under test 100 are (1,1), then they are corrected to (1.1,1). For example, when Mx = 1 and My = 1.2, if the theoretical coordinates of pad 130 on the circuit board under test 100 are (1,1), then they are corrected to (1,1.2). For example, when Mx = 1 and My = 1, then no coordinate correction is needed for pad 130 on the circuit board under test 100.

[0175] By calculating the coordinate offsets in the X-axis and Y-axis directions respectively, the coordinates of the pads 130 on the circuit board under test 100 can be accurately corrected.

[0176] In the coordinate correction with the first ratio, the second ratio and the third ratio, if the coordinates of all pads 130 are corrected with reference to the origin, the actual coordinates are obtained by multiplying the direct theoretical coordinate values by the ratios. If the coordinates of the remaining pads 130 are corrected with reference to the coordinates of the reference points in one of the correction regions 120, subtraction calculation is required. For example, the coordinates of the reference points in one of the correction regions 120 are kept unchanged, and then the coordinates of all pads 130 in the adjacent two correction regions 120 are corrected based on the coordinate offset. For example, when Mx = 1.1 and My = 1.2, if the coordinates of one of the reference points are (1, 2) and the coordinates of the other reference point are (5, 5). When (5, 5) is corrected with reference to (1, 2), the X-axis coordinate correction process is X = (5-1)*1.1+1 = 5.4, and the Y-axis coordinate correction process is Y = (5-2)*1.2+2 = 5.6. The coordinates can be corrected to (5.4, 5.6).

[0177] In some embodiments, the coordinates of the pads 130 are corrected in the manner of steps D-F for the remaining adjacent correction regions 120 of all the correction regions 120, until the actual coordinates of all the pads 130 on the circuit board 100 under test are obtained.

[0178] In the foregoing steps, the coordinates of all pads 130 between the two reference points in the adjacent two correction regions 120 can be corrected. By repeating the process of steps D-F several times, the coordinates of all pads 130 on the circuit board 100 under test can be gradually corrected, so that the actual coordinates of all pads 130 on the circuit board 100 under test are obtained. This ensures that the subsequent chip can be accurately assembled to each pad 130, prevents the chip from being fixed, reduces the scrap rate, and improves the yield of the product. At the same time, the product rework situation can be reduced, which can reduce the loss of chips and solder paste, reduce the cost of consumables and labor, and prevent the machine from wasting effective working time due to rework.

[0179] In some embodiments, one of the correction regions 120 contains the pad 130 with the origin of the target coordinate system, and this correction region 120 is the origin region. When the coordinates of the pads 130 are corrected for the first time, the correction is started from the origin region and the correction region 120 adjacent to the origin region, and during the correction process, the coordinates of the remaining pads 130 are corrected with reference to the origin in the origin region.

[0180] Understandably, when initially correcting the coordinates of pad 130, the origin is assumed to be the correct coordinate. The origin region is selected as one of the correction regions 120, and an adjacent correction region 120 is chosen for the first correction. This corrects the coordinates of all pads 130 within the origin region and adjacent correction regions 120 located between two reference points. Since the origin region has four adjacent correction regions 120, the first four coordinate corrections can all use the origin as a reference to correct the coordinates of the pads 130 within the four adjacent correction regions 120. Then, using the reference points within the corrected correction region 120 as references, the coordinates of the pads 130 in the regions adjacent to the corrected correction region 120 are corrected. This process is repeated sequentially to correct the coordinates of each pad 130.

[0181] In some embodiments, during the process of obtaining the actual coordinates of all pads 130 on the circuit board 100 under test using steps D-F, the coordinates of all pads 130 in each correction area 120 are sequentially corrected in a direction away from the origin until the actual coordinates of all pads 130 on the circuit board 100 under test are obtained.

[0182] It is understandable that by sequentially correcting the coordinates of all pads 130 within each correction region 120 in a direction away from the origin, the coordinates of all pads 130 on the circuit board 100 under test can be gradually corrected in an outward diffusion manner.

[0183] On the other hand, such as Figure 9 As shown in the figure, this application embodiment also provides a system for correcting the coordinates of pads on a circuit board. The system includes a positioning module 910, an identification module 920, a region division module 930, a reference point selection module 940, a position acquisition module 950, an offset acquisition module 960, and a coordinate correction module 970. The positioning module 910 is used to locate the contour reference point 110 of the circuit board 100 under test. The identification module 920 is used to determine a target area based on the contour reference point 110, where the target area has multiple pads 130. The region division module 930 is used to divide the target area into at least two correction areas 120. The reference point selection module 940 is used to select a pad 130 as a reference point within each correction area 120. The position acquisition module 950 is used to acquire a first positional relationship between the reference points of two adjacent correction areas 120, and to acquire a second positional relationship between two pads 130 on a standard circuit board corresponding to the reference points of the two adjacent correction areas 120. The offset acquisition module 960 is used to acquire the coordinate offset of the pads 130 on the circuit board under test 100 relative to the pads on the standard circuit board based on the first positional relationship and the second positional relationship. The coordinate correction module 970 is used to acquire the actual coordinates of all pads 130 within two adjacent correction areas 120 based on the theoretical coordinates and coordinate offsets of each pad 130 on the circuit board under test 100.

[0184] In the embodiment, the to-be-tested circuit board 100 is preliminarily positioned by positioning the contour reference point 110 on the to-be-tested circuit board 100, a plurality of correction regions 120 are divided based on the target region determined based on the contour reference point 110, the first positional relationship between the reference points of two adjacent correction regions 120 is compared with the second positional relationship between the pads 130 on the standard circuit board, so as to obtain the coordinate offset, and the actual coordinates of all the pads 130 on the to-be-tested circuit board 100 are obtained by the theoretical coordinates of the pads 130 and the coordinate offset. Thus, the coordinate position of each pad 130 on the to-be-tested circuit board 100 can be corrected, the accurate assembly of the subsequent chip is ensured, and the phenomenon of chip fixed offset is prevented.

[0185] In some embodiments, the positioning module 910, the identification module 920, the region division module 930, the reference point selection module 940, the position acquisition module 950, the offset acquisition module 960 and the coordinate correction module 970 are integrated in a processing system. The image information of different types of standard circuit boards can be pre-stored in the processing system. Based on the type of the to-be-tested circuit board 100, the image information of the corresponding type of standard circuit board is compared with the image information of the to-be-tested circuit board 100 by the control unit, so as to obtain the contour reference point 110 on the to-be-tested circuit board 100.

[0186] Figure 11 An example of a schematic diagram of the physical structure of an electronic device is shown in FIG. 1. Figure 11As shown, the electronic device includes a processor 1110, a communications interface 1120, a memory 1130, and a communications bus 1140, wherein the processor 1110, the communications interface 1120, and the memory 1130 complete mutual communication through the communications bus 1140. The processor 1110 can invoke a logical instruction in the memory 1130 to execute a correction method for the pad 130 coordinates on the circuit board, and the method includes positioning a contour reference point 110 of a to-be-tested circuit board 100. A target area is determined based on the contour reference point 110, and the target area has a plurality of pads 130 therein. The target area is divided into at least two correction areas 120, and a pad 130 is selected as a reference point in each correction area 120. A first positional relationship between reference points of two adjacent correction areas 120 is obtained, and a second positional relationship between two pads 130 corresponding to the reference points of the two adjacent correction areas 120 on a standard circuit board is obtained. Based on the first positional relationship and the second positional relationship, a coordinate offset of the pad 130 on the to-be-tested circuit board 100 relative to the pad on the standard circuit board is obtained. Based on the theoretical coordinates of each pad 130 of the to-be-tested circuit board 100 and the coordinate offset, actual coordinates of all pads 130 in the two adjacent correction areas 120 are obtained.

[0187] In addition, the logical instruction in the memory 1130 described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0188] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the method for correcting the coordinates of pads 130 on a circuit board as described above, which includes locating a profile reference point 110 of a circuit board 100 to be measured. A target area is determined based on the profile reference point 110, and the target area has a plurality of pads 130 therein. The target area is divided into at least two correction areas 120, and a pad 130 in each correction area 120 is selected as a reference point. A first positional relationship between reference points of two adjacent correction areas 120 is obtained, and a second positional relationship between two pads 130 on a standard circuit board corresponding to the reference points of the two adjacent correction areas 120 is obtained. Based on the first positional relationship and the second positional relationship, a coordinate offset of the pads 130 on the circuit board 100 to be measured relative to the pads on the standard circuit board is obtained. Based on the theoretical coordinates of each pad 130 on the circuit board 100 to be measured and the coordinate offset, actual coordinates of all pads 130 in the two adjacent correction areas 120 are obtained.

[0189] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e., can be located in one place, or can be distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0190] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be implemented by means of software and necessary universal hardware platforms, and of course can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in terms of contribution to the prior art, can be embodied in the form of a software product. The computer software product can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0191] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features thereof; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method of correcting a circuit board pad coordinate, characterized by, The method comprises the following steps: A. locating a profile reference point of the to-be-tested circuit board; B. determining a target area based on the profile reference point, the target area having a plurality of pads therein; C. dividing the target area into at least two correction areas, and selecting one pad in each correction area as a reference point; D. obtaining a first positional relationship between the reference points of two adjacent correction areas, and obtaining a second positional relationship between two pads on a standard circuit board corresponding to the reference points of the two adjacent correction areas; E. obtaining a coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board based on the first positional relationship and the second positional relationship; F. obtaining actual coordinates of all pads in the two adjacent correction areas based on the theoretical coordinates of the pads on the to-be-tested circuit board and the coordinate offset; For the remaining adjacent correction areas of all correction areas, the pads are corrected in the manner of steps D-F until the actual coordinates of all pads on the to-be-tested circuit board are obtained; one of the correction areas contains a pad with a target coordinate system origin point, and this correction area is the origin area; when the pad coordinates are corrected for the first time, the correction starts from the origin area and the correction area adjacent to the origin area, and during the correction, the coordinates of the remaining pads are corrected based on the origin point in the origin area; during the process of obtaining the actual coordinates of all pads on the to-be-tested circuit board by steps D-F, the coordinates of the pads in each correction area are corrected in turn in the direction away from the origin point until the actual coordinates of all pads on the to-be-tested circuit board are obtained.

2. The method of claim 1, wherein, The method for locating the profile reference point of the to-be-tested circuit board comprises the following steps: obtaining image information of the to-be-tested circuit board; comparing the image information of the to-be-tested circuit board with the image information of the standard circuit board, and obtaining the profile reference point of the to-be-tested circuit board based on the positions of four reference points on the standard circuit board.

3. The method of claim 1, wherein, The method for determining the target area based on the profile reference point comprises the following steps: taking a quadrilateral area enclosed by the profile reference point as the target area.

4. The method of claim 1, wherein, The method for dividing the target area into at least two correction areas and selecting one pad in each correction area as a reference point comprises the following steps: dividing the target area into at least two correction areas based on the area of the target area and / or the distance between every two adjacent pads in the target area, and ensuring that each correction area has at least one pad, and selecting one pad in each correction area as a reference point.

5. The method of claim 4, wherein, The number of correction areas is positively correlated with the area of the target area, and the number of correction areas is negatively correlated with the distance between every two adjacent pads in the target area.

6. The method of claim 1, wherein, The method for obtaining the first positional relationship between the reference points of two adjacent correction areas and the second positional relationship between two pads on a standard circuit board corresponding to the reference points of the two adjacent correction areas comprises the following steps: acquire a first distance between the reference points of the two adjacent correction regions, and acquire a second distance between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions.

7. The method of claim 6, wherein, The first position relationship between the reference points of the two adjacent correction regions is acquired, and a second position relationship between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is acquired. The first distance between the reference points of the two adjacent correction regions is acquired, and the second distance between the two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is acquired.

8. The method of claim 7, wherein, The first difference between the first distance and the second distance is acquired, and the first pad quantity between the reference points of the two adjacent correction regions is identified, and a first quotient value of the first difference and the first pad quantity is taken as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board. The first position relationship between the reference points of the two adjacent correction regions is acquired, and a second position relationship between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is acquired.

9. The method of claim 6, wherein, The first distance between the reference points of the two adjacent correction regions is acquired, and the second distance between the two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is acquired. The first position relationship between the reference points of the two adjacent correction regions is acquired, and a second position relationship between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is acquired.

10. The method of claim 9, wherein, The third distance and the fifth distance are acquired, and the second pad quantity between the reference points of the two adjacent correction regions in the X-axis direction of the target coordinate system is identified, and a second quotient value of the second difference and the second pad quantity is taken as the first coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the X-axis direction of the target coordinate system, and the fourth distance and the sixth distance are acquired, and the third pad quantity between the reference points of the two adjacent correction regions in the Y-axis direction of the target coordinate system is identified, and a third quotient value of the third difference and the third pad quantity is taken as the second coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the Y-axis direction of the target coordinate system. The first position relationship between the reference points of the two adjacent correction regions is acquired, and a second position relationship between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is acquired.

11. The method of claim 10, wherein, The third distance and the fifth distance are acquired, and the second pad quantity between the reference points of the two adjacent correction regions in the X-axis direction of the target coordinate system is identified, and a second quotient value of the second difference and the second pad quantity is taken as the first coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the X-axis direction of the target coordinate system, and the fourth distance and the sixth distance are acquired, and the third pad quantity between the reference points of the two adjacent correction regions in the Y-axis direction of the target coordinate system is identified, and a third quotient value of the third difference and the third pad quantity is taken as the second coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the Y-axis direction of the target coordinate system. The first position relationship between the reference points of the two adjacent correction regions is acquired, and a second position relationship between two pads on the standard circuit board corresponding to the reference points of the two adjacent correction regions is acquired. The X-axis coordinates of all pads between the two reference points in the two adjacent correction regions are corrected in proportion to the second quotient value, and the Y-axis coordinates of all pads between the two reference points in the two adjacent correction regions are corrected in proportion to the third quotient value, to obtain the actual coordinates of all pads between the two reference points in the two adjacent correction regions.

12. The method of claim 6, wherein, The coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of each pad on the to-be-tested circuit board and the coordinate offset, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on one of the reference points in the correction region as a reference, and the first ratio between the first distance and the second distance is used as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board. The X-axis coordinates of all pads between the two reference points in the two adjacent correction regions are corrected in proportion to the second quotient value, and the Y-axis coordinates of all pads between the two reference points in the two adjacent correction regions are corrected in proportion to the third quotient value, to obtain the actual coordinates of all pads between the two reference points in the two adjacent correction regions.

13. The method of claim 12, wherein, The coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of each pad on the to-be-tested circuit board and the coordinate offset, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on one of the reference points in the correction region as a reference, and the first ratio between the first distance and the second distance is used as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board. The third coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the X-axis direction is obtained based on the second ratio between the third distance and the fifth distance, and the fourth coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board in the Y-axis direction is obtained based on the third ratio between the fourth distance and the sixth distance.

14. The method of claim 9, wherein, The X-axis coordinates of all pads between the two reference points in the two adjacent correction regions are corrected in proportion to the second quotient value, and the Y-axis coordinates of all pads between the two reference points in the two adjacent correction regions are corrected in proportion to the third quotient value, to obtain the actual coordinates of all pads between the two reference points in the two adjacent correction regions. The coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of each pad on the to-be-tested circuit board and the coordinate offset, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on one of the reference points in the correction region as a reference, and the first ratio between the first distance and the second distance is used as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board.

15. The method of claim 14, wherein, The coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of each pad on the to-be-tested circuit board and the coordinate offset, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on one of the reference points in the correction region as a reference, and the first ratio between the first distance and the second distance is used as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board. The coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of each pad on the to-be-tested circuit board and the coordinate offset, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on one of the reference points in the correction region as a reference, and the first ratio between the first distance and the second distance is used as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board.

16. A circuit board pad coordinate correction system that implements the circuit board pad coordinate correction method according to any one of claims 1 to 15, characterized by, The coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board is obtained based on the first position relationship and the second position relationship, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on the theoretical coordinates of each pad on the to-be-tested circuit board and the coordinate offset, and the actual coordinates of all pads in the two adjacent correction regions are obtained based on one of the reference points in the correction region as a reference, and the first ratio between the first distance and the second distance is used as the coordinate offset of the pads on the to-be-tested circuit board relative to the pads on the standard circuit board. ​ ​ ​ ​ ​ ​ A coordinate correction module is configured to obtain actual coordinates of all pads in the two adjacent correction regions based on the theoretical coordinates of the pads of the to-be-tested circuit board and the coordinate offset.

17. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein, The processor implements the method of any one of claims 1-15 when executing the program.

18. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the method of any one of claims 1-15 when executed by a processor.

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