A miniaturized dual-channel signal processor with ultra-high isolation

Abstract

The present invention discloses an ultra-high isolation miniaturized dual-channel signal processor, which relates to the technical field of signal processors, and includes a ceramic body, a circuit layer inside the ceramic body, and an external electrode outside the ceramic body, wherein the external electrode includes a common port (N1), a low-frequency channel output port (N2), a high-frequency channel output port (N3), a first ground port (G1), a second ground port (G2), and a third ground port (G3), wherein the first ground port (G1), the common port (N1), and the second ground port (G2) are located on one side outside the ceramic body, and the low-frequency channel output port (N2), the high-frequency channel output port (N3), and the third ground port (G3) are located on the other side outside the ceramic body, wherein the external electrode is connected to the circuit layer inside the ceramic body via a side metal. The present invention solves the problems of large circuit volume, high cost, and easy signal distortion of existing processors.

Description

Technical Field

[0001] The present invention relates to the technical field of signal processors, and in particular to an ultra-high isolation miniaturized dual-channel signal processor. Background Art

[0002] With the widespread application of wireless communication technology, the demand for wireless communication technology and wireless network systems is getting higher and higher. With a common dual-band operating system, such as a wireless local area network (WLAN), it generally has two operating frequency bands, 2.4 GHz and 5 GHz. However, the signal transmission process is often accompanied by noise interference. In order to avoid the noise that may be introduced in the dual-band operating system, the existing practice is to connect a low-pass signal processor and a high-pass signal processor in parallel before the input of the two passband processors to filter out the noise intensity in the two operating frequency bands respectively.

[0003] However, increasing the size of the two circuits will increase the volume of the entire circuit, which is not conducive to the miniaturization of the circuit and will also increase the cost of the signal processor. In addition, the two signal processors with communication bands will also be coupled with each other, resulting in signal distortion problems. Summary of the invention

[0004] In view of the above-mentioned deficiencies in the prior art, the present invention provides an ultra-high isolation miniaturized dual-channel signal processor that solves the problems of large circuit size, high cost, and easy signal distortion of the prior processor.

[0005] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention is: an ultra-high isolation miniaturized dual-channel signal processor, including a ceramic body, a circuit layer inside the ceramic body and an external electrode outside the ceramic body, the external electrode includes a common port, a low-frequency channel output port, a high-frequency channel output port, a first ground port, a second ground port and a third ground port, the first ground port, the common port and the second ground port are located on one side of the outside of the ceramic body, the low-frequency channel output port, the high-frequency channel output port and the third ground port are located on the other side of the outside of the ceramic body, and the external electrode is connected to the circuit layer inside the ceramic body via side metal.

[0006] The beneficial effect of the above scheme is: the present invention provides an ultra-high isolation miniaturized dual-channel signal processor with a multi-layer circuit structure, which realizes a dual-channel signal processing function with high isolation in an extremely miniature packaging volume. The use of a multi-layer structure can achieve the effect of reducing the circuit structure, solving the problems of large circuit size, high cost, and easy signal distortion of existing processors.

[0007] Furthermore, the circuit layer includes a low-frequency channel signal processor and a high-frequency channel signal processor, and the low-frequency channel signal processor and the high-frequency channel signal processor are both connected to the common port.

[0008] The beneficial effect of the above further scheme is: the present invention has a signal processor with three signal ends capable of bidirectional transmission, which is used in wireless communication systems and is an important microwave circuit component. Because it is a single signal processor component, the manufacturing cost will be lower than the manufacturing cost of combining two signal processors. Therefore, the present invention can effectively improve the signal quality.

[0009] Furthermore, the low-frequency channel signal processor includes a first equivalent inductor L1, a second equivalent inductor L2, a first equivalent capacitor C1, a second equivalent capacitor C2 and a third equivalent capacitor C3, one end of the first equivalent inductor L1 is connected to the common port, and the other end thereof is respectively connected to one end of the second equivalent inductor L2, one end of the first equivalent capacitor C1 and one end of the second equivalent capacitor C2, the other end of the second equivalent inductor L2 and the other end of the first equivalent capacitor C1 are both connected to one end of the third equivalent capacitor C3, the other end of the second equivalent capacitor C2 is connected to the second ground port, the other end of the third equivalent capacitor C3 is connected to the second ground port, and one end of the third equivalent capacitor C3 is also connected to the low-frequency channel output port.

[0010] Further, the high-frequency channel signal processor includes a third equivalent inductor L3, a fourth equivalent inductor L4, a fifth equivalent inductor L5, a fourth equivalent capacitor C4, a fifth equivalent capacitor C5, a sixth equivalent capacitor C6, a seventh equivalent capacitor C7, an eighth equivalent capacitor C8 and a ninth equivalent capacitor C9, one end of the fourth equivalent capacitor C4 is respectively connected to the common port and one end of the sixth equivalent capacitor C6, and the other end thereof is respectively connected to one end of the third equivalent inductor L3 and one end of the fifth equivalent capacitor C5, the other end of the third equivalent inductor L3 is connected to the first ground port, and the other end of the fifth equivalent capacitor C5 is connected to the first ground port. One end is respectively connected to one end of the fourth equivalent inductor L4 and the other end of the sixth equivalent capacitor C6, the other end of the fourth equivalent inductor L4 is respectively connected to one end of the eighth equivalent capacitor C8, one end of the seventh equivalent capacitor C7 and one end of the fifth equivalent inductor L5, the other end of the seventh equivalent capacitor C7 and the other end of the fifth equivalent inductor L5 are both connected to the high-frequency channel output port, the high-frequency channel output port is also connected to one end of the ninth equivalent capacitor C9, the other end of the eighth equivalent capacitor C8 is connected to the first ground port, and the other end of the ninth equivalent capacitor C9 is connected to the first ground port.

[0011] The beneficial effect of the above further solution is that the present invention respectively embeds the above inductor and capacitor components into eleven circuit layers in the ceramic body, and has microwave characteristics of high isolation, reduced volume and low loss.

[0012] Furthermore, the circuit layer also includes an isolation improving unit LG, one end of the isolation improving unit LG is respectively connected to the other end of the second equivalent capacitor C2 and the other end of the third equivalent capacitor C3, and the other end is respectively connected to the other end of the third equivalent inductor L3, the other end of the eighth equivalent capacitor C8 and the other end of the ninth equivalent capacitor C9.

[0013] The beneficial effect of the above further scheme is: by connecting an inductor element LG in series between the two channel ground terminals to improve the isolation, the isolation between the two passbands is improved, solving the problem of mutual interference between lumped components that is easily caused by traditional frequency dividers, and because no additional circuit is added, the overall low-loss capability is improved.

[0014] Further, the circuit layer includes, from top to bottom, a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, an eighth circuit layer, a ninth circuit layer, a tenth circuit layer and an eleventh circuit layer;

[0015] The first circuit layer includes a first electrode plate, a second electrode plate, a third electrode plate, a fourth electrode plate, a first via hole, a fifth via hole, a ninth via hole, a tenth via hole, a fourteenth via hole and a sixteenth via hole;

[0016] The second circuit layer includes a fifth electrode plate, a sixth electrode plate, a second via hole, a fifth via hole, a ninth via hole, an eleventh via hole, a fourteenth via hole and a sixteenth via hole;

[0017] The third circuit layer includes a seventh electrode plate, an eighth electrode plate, a ninth electrode plate, a third via hole, a sixth via hole, a ninth via hole, a twelfth via hole, a fourteenth via hole and a sixteenth via hole;

[0018] The fourth circuit layer includes a tenth electrode plate, an eleventh electrode plate, a twelfth electrode plate, a thirteenth electrode plate, a fourteenth electrode plate, a fourth via hole, a seventh via hole, a ninth via hole, a thirteenth via hole, a fifteenth via hole and a sixteenth via hole;

[0019] The fifth circuit layer includes a fifteenth electrode plate, a sixteenth electrode plate, a seventeenth electrode plate, an eighteenth electrode plate, an eighth via hole and a seventeenth via hole;

[0020] The sixth circuit layer includes a nineteenth electrode plate, an eighth via hole, a seventeenth via hole, and an eighteenth via hole;

[0021] The seventh circuit layer includes a twentieth electrode plate, a twenty-first electrode plate, a twenty-second electrode plate, an eighth via hole, a seventeenth via hole, and a nineteenth via hole;

[0022] The eighth circuit layer includes a twenty-third electrode plate, a twenty-fourth electrode plate, a twenty-fifth electrode plate, a twenty-sixth electrode plate, an eighth via hole, a seventeenth via hole, and a twentieth via hole;

[0023] The ninth circuit layer includes a twenty-seventh electrode plate, a twenty-eighth electrode plate, a twenty-ninth electrode plate, an eighth via hole, a seventeenth via hole, and a twenty-first via hole;

[0024] The tenth circuit layer includes a 30th electrode plate, a 31st electrode plate, a 32nd electrode plate, a 33rd electrode plate and a 21st via hole;

[0025] The eleventh circuit layer includes a thirty-fourth electrode plate, a thirty-fifth electrode plate and a thirty-sixth electrode plate;

[0026] The 20th electrode plate and the 25th electrode plate are connected in sequence via the eighth via hole, and are coupled with the 24th electrode plate and the 31st electrode plate through interlayer coupling to form the first equivalent capacitor C1;

[0027] The 20th electrode plate, the 27th electrode plate and the 30th electrode plate are connected in sequence via the eighth via hole, and are coupled with the 23rd electrode plate and the 34th electrode plate through interlayers to form the second equivalent capacitor C2;

[0028] The thirty-first electrode plate and the thirty-fifth electrode plate form the third equivalent capacitor C3 through interlayer coupling;

[0029] The sixteenth electrode plate and the nineteenth electrode plate form the fourth equivalent capacitor C4 through interlayer coupling;

[0030] The seventeenth electrode plate and the nineteenth electrode plate form the fifth equivalent capacitor C5 through interlayer coupling;

[0031] The fourteenth electrode plate and the seventeenth electrode plate form the sixth equivalent capacitor C6 through interlayer coupling;

[0032] The twenty-second electrode plate and the twenty-ninth electrode plate are connected via the seventh via hole and are coupled with the twenty-sixth electrode plate through interlayer coupling to form the seventh equivalent capacitor C7;

[0033] The thirty-second electrode plate and the thirty-fourth electrode plate form the eighth equivalent capacitor C8 through interlayer coupling;

[0034] The thirty-third electrode plate and the thirty-fourth electrode plate form the ninth equivalent capacitor C9 through interlayer coupling;

[0035] The first electrode plate, the fifth electrode plate, the seventh electrode plate, the tenth electrode plate and the fifteenth electrode plate are connected end to end in sequence via the second via hole, the third via hole and the fourth via hole to form the first equivalent inductor L1;

[0036] The second electrode plate, the eighth electrode plate, the eleventh electrode plate and the fifteenth electrode plate are connected end to end in sequence via the fifth via hole, the sixth via hole and the seventh via hole to form the second equivalent inductor L2;

[0037] The 21st electrode plate, the 25th electrode plate and the 28th electrode plate are connected end to end via the 19th via hole, the 20th via hole and the 21st via hole in sequence to form the third equivalent inductor L3;

[0038] The third electrode plate, the sixth electrode plate, the ninth electrode plate, the twelfth electrode plate and the eighteenth electrode plate are connected end to end in sequence via the tenth via hole, the eleventh via hole, the twelfth via hole and the thirteenth via hole to form the fourth equivalent inductor L4;

[0039] The fourth electrode plate, the thirteenth electrode plate and the eighteenth electrode plate are connected end to end in sequence via the fourteenth via hole and the fifteenth via hole to form the fifth equivalent inductor L5.

[0040] The beneficial effect of the above further scheme is: by reasonably selecting the equivalent component values ​​of the signal processor and optimizing the coupling relationship of its equivalent components in the vertical space, two equivalent inductors and three equivalent capacitors of the low-frequency channel signal processor and three equivalent inductors and six equivalent capacitors of the high-frequency channel signal processor are formed, providing a miniaturized dual-channel signal processor for ultra-high isolation, which can layout multiple inductor and capacitor components in an extremely small volume and achieve low loss and high isolation effects at the same time.

[0041] Furthermore, the ultra-high isolation miniaturized dual-channel signal processor also includes a mark, and the mark and the external electrode are located on the opposite side of the ceramic body.

[0042] Furthermore, the circuit layer is built into the ceramic body by using a low temperature co-fired ceramic process.

[0043] The beneficial effect of the above further scheme is that the present invention embeds the multi-layer circuit of the frequency divider into the ceramic body based on the low-temperature co-fired ceramic process, realizes the integration of various equivalent components on the three-dimensional circuit substrate, and realizes the miniaturization and high density of the circuit.

[0044] Furthermore, the circuit layer adopts an embedded metal material, and the embedded metal material includes copper or silver.

[0045] The beneficial effect of the above further solution is that the use of the above high conductivity metal material is conducive to improving the quality factor of the circuit system. For example, copper and silver can be used as embedded metal materials, which will not oxidize during the sintering process and do not require electroplating protection. In addition, there is a simple circuit isolation enhancement unit, which can achieve the effect of increasing isolation without increasing the volume of the external circuit and reduce the complexity of circuit design. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 FIG. 4 is a schematic diagram of the appearance of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0047] Figure 2 This is an equivalent schematic diagram of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0048] Figure 3 Schematic diagram of the internal structure of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0049] Figure 4 It is a schematic diagram of the first circuit layer of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0050] Figure 5 It is a schematic diagram of the second layer circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0051] Figure 6 It is a schematic diagram of the third layer circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0052] Figure 7 It is a schematic diagram of the fourth circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0053] Figure 8 It is a schematic diagram of the fifth circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0054] Fig. 9 It is a schematic diagram of the sixth circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0055] Fig.10 It is a schematic diagram of the seventh circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0056] Fig.11 It is a schematic diagram of the eighth circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0057] Fig.12 It is a schematic diagram of the ninth circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0058] Fig.13 It is a schematic diagram of the tenth circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0059] Fig.14 It is a schematic diagram of the eleventh circuit of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0060] Fig.15It is a low-frequency channel response curve diagram of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0061] Fig.16 It is a high frequency channel response curve diagram of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0062] Fig.17 It is an isolation response curve diagram of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0063] Fig.18 It is a return loss response curve diagram of the ultra-high isolation miniaturized dual-channel signal processor of the present invention.

[0064] Wherein: N1, common port; N2, low frequency channel output port; N3, high frequency channel output port; G1, first ground port; G2, second ground port; G3, third ground port; M, mark; 101, first electrode plate; 102, second electrode plate; 103, third electrode plate; 104, fourth electrode plate; 201, fifth electrode plate; 202, sixth electrode plate; 301, seventh electrode plate; 302, eighth electrode plate; 303, ninth electrode plate; 401, tenth electrode plate electrode plate; 402, the eleventh electrode plate; 403, the twelfth electrode plate; 404, the thirteenth electrode plate; 405, the fourteenth electrode plate; 501, the fifteenth electrode plate; 502, the sixteenth electrode plate; 503, the seventeenth electrode plate; 504, the eighteenth electrode plate; 601, the nineteenth electrode plate; 701, the twentieth electrode plate; 702, the twenty-first electrode plate; 703, the twenty-second electrode plate; 801, the twenty-third electrode plate; 802, the twenty-fourth electrode plate; 803, the twenty-third electrode plate The fifth electrode plate; 804, the twenty-sixth electrode plate; 901, the twenty-seventh electrode plate; 902, the twenty-eighth electrode plate; 903, the twenty-ninth electrode plate; 1001, the thirtieth electrode plate; 1002, the thirty-first electrode plate; 1003, the thirty-second electrode plate; 1004, the thirty-third electrode plate; 1101, the thirty-fourth electrode plate; 1102, the thirty-fifth electrode plate; 1103, the thirty-sixth electrode plate; P1, the first via hole; P2, the second via hole; P3, the third via hole; P4, the fourth via hole; P5, the fifth via hole; P6, the sixth via hole; P7, the seventh via hole; P8, the eighth via hole; P9, the ninth via hole; P10, the tenth via hole; P11, the eleventh via hole; P12, the twelfth via hole; P13, the thirteenth via hole; P14, the fourteenth via hole; P15, the fifteenth via hole; P16, the sixteenth via hole; P17, the seventeenth via hole; P18, the eighteenth via hole; P19, the nineteenth via hole; P20, the twentieth via hole; P21, the twenty-first via hole. DETAILED DESCRIPTION

[0065] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0066] like Figure 1 As shown, an ultra-high isolation miniaturized dual-channel signal processor includes a ceramic body, a circuit layer inside the ceramic body and an external electrode outside the ceramic body, the external electrode includes a common port N1, a low-frequency channel output port N2, a high-frequency channel output port N3, a first ground port G1, a second ground port G2 and a third ground port G3, the first ground port G1, the common port N1 and the second ground port G2 are located on one side of the outside of the ceramic body, the low-frequency channel output port N2, the high-frequency channel output port N3 and the third ground port G3 are located on the other side of the outside of the ceramic body, and the external electrode is connected to the circuit layer inside the ceramic body via side metal.

[0067] The ultra-high isolation miniaturized dual-channel signal processor proposed in the present invention has excellent isolation and low differential loss. The present invention uses a multi-layer substrate stack to form a base body. The multi-layer structure design can achieve the effect of circuit miniaturization. In addition to being constructed by a low-frequency passband processor and a high-frequency passband processor, an isolation inductor is set between the two passband grounding ends to further improve the isolation between the low-frequency passband port and the high-frequency passband port without increasing any circuit volume and contributing the advantage of low differential loss.

[0068] like Figure 2 As shown, the circuit layer includes a low-frequency channel signal processor and a high-frequency channel signal processor, and both the low-frequency channel signal processor and the high-frequency channel signal processor are connected to a common port N1.

[0069] The low-frequency channel signal processor includes a first equivalent inductor L1, a second equivalent inductor L2, a first equivalent capacitor C1, a second equivalent capacitor C2 and a third equivalent capacitor C3. One end of the first equivalent inductor L1 is connected to the common port N1, and the other end thereof is respectively connected to one end of the second equivalent inductor L2, one end of the first equivalent capacitor C1 and one end of the second equivalent capacitor C2. The other end of the second equivalent inductor L2 and the other end of the first equivalent capacitor C1 are both connected to one end of the third equivalent capacitor C3. The other end of the second equivalent capacitor C2 is connected to the second ground port G2. The other end of the third equivalent capacitor C3 is connected to the second ground port G2. One end of the third equivalent capacitor C3 is also connected to the low-frequency channel output port N2.

[0070] The high-frequency channel signal processor includes a third equivalent inductor L3, a fourth equivalent inductor L4, a fifth equivalent inductor L5, a fourth equivalent capacitor C4, a fifth equivalent capacitor C5, a sixth equivalent capacitor C6, a seventh equivalent capacitor C7, an eighth equivalent capacitor C8 and a ninth equivalent capacitor C9, one end of the fourth equivalent capacitor C4 is respectively connected to the common port N1 and one end of the sixth equivalent capacitor C6, and the other end thereof is respectively connected to one end of the third equivalent inductor L3 and one end of the fifth equivalent capacitor C5, the other end of the third equivalent inductor L3 is connected to the first ground port G1, and the other end of the fifth equivalent capacitor C5 is respectively connected to the common port N1 and the sixth equivalent capacitor C6. One end of the fourth equivalent inductor L4 is connected to the other end of the sixth equivalent capacitor C6, the other end of the fourth equivalent inductor L4 is respectively connected to one end of the eighth equivalent capacitor C8, one end of the seventh equivalent capacitor C7 and one end of the fifth equivalent inductor L5, the other end of the seventh equivalent capacitor C7 and the other end of the fifth equivalent inductor L5 are both connected to the high-frequency channel output port N3, the high-frequency channel output port N3 is also connected to one end of the ninth equivalent capacitor C9, the other end of the eighth equivalent capacitor C8 is connected to the first ground port G1, and the other end of the ninth equivalent capacitor C9 is connected to the first ground port G1.

[0071] The circuit layer also includes an isolation improving unit LG, one end of the isolation improving unit LG is respectively connected to the other end of the second equivalent capacitor C2 and the other end of the third equivalent capacitor C3, and the other end is respectively connected to the other end of the third equivalent inductor L3, the other end of the eighth equivalent capacitor C8 and the other end of the ninth equivalent capacitor C9.

[0072] like Figure 3 As shown, the circuit layers include, from top to bottom, a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, an eighth circuit layer, a ninth circuit layer, a tenth circuit layer and an eleventh circuit layer;

[0073] like Figure 4 As shown, the first circuit layer includes a first electrode plate 101, a second electrode plate 102, a third electrode plate 103, a fourth electrode plate 104, a first via hole P1, a fifth via hole P5, a ninth via hole P9, a tenth via hole P10, a fourteenth via hole P14 and a sixteenth via hole P16;

[0074] like Figure 5 As shown, the second circuit layer includes a fifth electrode plate 201, a sixth electrode plate 202, a second via hole P2, a fifth via hole P5, a ninth via hole P9, an eleventh via hole P11, a fourteenth via hole P14 and a sixteenth via hole P16;

[0075] like Figure 6As shown, the third circuit layer includes a seventh electrode plate 301, an eighth electrode plate (302), a ninth electrode plate 303, a third via hole P3, a sixth via hole P6, a ninth via hole P9, a twelfth via hole P12, a fourteenth via hole P14 and a sixteenth via hole P16;

[0076] like Figure 7 As shown, the fourth circuit layer includes a tenth electrode plate 401, an eleventh electrode plate 402, a twelfth electrode plate 403, a thirteenth electrode plate 404, a fourteenth electrode plate 405, a fourth via hole P4, a seventh via hole P7, a ninth via hole P9, a thirteenth via hole P13, a fifteenth via hole P15 and a sixteenth via hole P16;

[0077] like Figure 8 As shown, the fifth circuit layer includes a fifteenth electrode plate 501, a sixteenth electrode plate 502, a seventeenth electrode plate 503, an eighteenth electrode plate 504, an eighth via hole P8 and a seventeenth via hole P17;

[0078] like Fig. 9 As shown, the sixth circuit layer includes a nineteenth electrode plate 601, an eighth via hole P8, a seventeenth via hole P17, and an eighteenth via hole P18;

[0079] like Fig.10 As shown, the seventh circuit layer includes a twentieth electrode plate 701, a twenty-first electrode plate 702, a twenty-second electrode plate 703, an eighth via hole P8, a seventeenth via hole P17 and a nineteenth via hole P19;

[0080] like Fig.11 As shown, the eighth circuit layer includes a twenty-third electrode plate 801, a twenty-fourth electrode plate 802, a twenty-fifth electrode plate 803, a twenty-sixth electrode plate 804, an eighth via hole P8, a seventeenth via hole P17 and a twentieth via hole P20;

[0081] like Fig.12 As shown, the ninth circuit layer includes a twenty-seventh electrode plate 901, a twenty-eighth electrode plate 902, a twenty-ninth electrode plate 903, an eighth via hole P8, a seventeenth via hole P17 and a twenty-first via hole P21;

[0082] like Fig.13 As shown, the tenth circuit layer includes a 30th electrode plate 1001, a 31st electrode plate 1002, a 32nd electrode plate 1003, a 33rd electrode plate 1004 and a 21st via hole P21;

[0083] like Fig.14 As shown, the eleventh circuit layer includes a thirty-fourth electrode plate 1101, a thirty-fifth electrode plate 1102 and a thirty-sixth electrode plate 1103;

[0084] The 20th electrode plate 701 and the 25th electrode plate 901 are connected in sequence via the eighth via hole P8, and are coupled with the 24th electrode plate 802 and the 31st electrode plate 1002 through interlayer coupling to form the first equivalent capacitor C1;

[0085] The 20th electrode plate 701, the 27th electrode plate 901 and the 30th electrode plate 1001 are connected in sequence via the eighth via hole P8, and are coupled with the 23rd electrode plate 801 and the 34th electrode plate 1101 through interlayer coupling to form the second equivalent capacitor C2;

[0086] The thirty-first electrode plate 1002 and the thirty-fifth electrode plate 1102 form the third equivalent capacitor C3 through interlayer coupling;

[0087] The sixteenth electrode plate 502 and the nineteenth electrode plate 601 form the fourth equivalent capacitor C4 through interlayer coupling;

[0088] The seventeenth electrode plate 503 and the nineteenth electrode plate 601 form the fifth equivalent capacitor C5 through interlayer coupling;

[0089] The fourteenth electrode plate 405 and the seventeenth electrode plate 503 form the sixth equivalent capacitor C6 through interlayer coupling;

[0090] The twenty-second electrode plate 703 and the twenty-ninth electrode plate 903 are connected via the seventh via hole P7 and are coupled with the twenty-sixth electrode plate 804 through interlayer coupling to form the seventh equivalent capacitor C7;

[0091] The thirty-second electrode plate 1003 and the thirty-fourth electrode plate 1101 form the eighth equivalent capacitor C8 through interlayer coupling;

[0092] The thirty-third electrode plate 1004 and the thirty-fourth electrode plate 1101 form the ninth equivalent capacitor C9 through interlayer coupling;

[0093] The first electrode plate 101, the fifth electrode plate 201, the seventh electrode plate 301, the tenth electrode plate 401 and the fifteenth electrode plate 501 are connected end to end in sequence via the second via hole P2, the third via hole P3 and the fourth via hole P4 to form the first equivalent inductor L1;

[0094] The second electrode plate 102, the eighth electrode plate 302, the eleventh electrode plate 402 and the fifteenth electrode plate 501 are connected end to end in sequence via the fifth via hole P5, the sixth via hole P6 and the seventh via hole P7 to form the second equivalent inductance L2;

[0095] The 21st electrode plate 702, the 25th electrode plate 803 and the 28th electrode plate 902 are connected end to end in sequence via the 19th via hole P19, the 20th via hole P20 and the 21st via hole P21 to form the third equivalent inductor L3;

[0096] The third electrode plate 103, the sixth electrode plate 202, the ninth electrode plate 303, the twelfth electrode plate 403 and the eighteenth electrode plate 504 are connected end to end in sequence via the tenth via hole P10, the eleventh via hole P11, the twelfth via hole P12 and the thirteenth via hole P13 to form the fourth equivalent inductor L4;

[0097] The fourth electrode plate 104 , the thirteenth electrode plate 404 , and the eighteenth electrode plate 504 are connected end to end in sequence via the fourteenth via hole P14 and the fifteenth via hole P15 to form the fifth equivalent inductor L5 .

[0098] In one embodiment of the present invention, the low-frequency channel signal processor comprises a first equivalent inductor L1 via Figures 4 to 8 Connect to Figure 1 The common port N1 in the embodiment is connected, and the other end thereof is connected to one end of the first equivalent capacitor C1 and one end of the second equivalent inductor L2 via Figures 9 to 13 The other end of the first equivalent capacitor C1 is connected to the other end of the second equivalent circuit L2 by Figures 4 to 9 The eighth via P8 in the circuit is connected to form a parallel connection, and the other end of the second equivalent inductor L2 is connected to the Figure 1 The low-frequency channel output port N2 is connected to the low-frequency channel output port, the low-frequency channel output port is connected to one end of the third equivalent capacitor C3, and the other end of the third equivalent capacitor C3 is connected to Figure 1 and Fig.14 The ground terminal G2 in.

[0099] The high frequency channel signal processor is connected to the Figure 1 The common port N1 in the embodiment is connected to one end of the sixth equivalent capacitor C6, and the other end of the fourth equivalent capacitor C4 is connected to one end of the fifth equivalent capacitor C5 by Figures 4 to 9 The other end of the fifth equivalent capacitor C5 is connected to the other end of the sixth equivalent capacitor C6 by Figures 4 to 9 The connecting end of the fourth equivalent capacitor C4 and the fifth equivalent capacitor C5 is connected to the third equivalent inductor L3 by Figure 9 to Figure 10 The third equivalent inductor L3 is connected to the other end by the nineteenth via P19 in Figure 13 to Figure 14 The eleventh via P21 is connected to the low passband ground terminal G1, the other end of the fifth equivalent capacitor C5 and the other end of the sixth equivalent capacitor C6 are connected to one end of the fourth equivalent inductor L4 by Figures 4 to 9The other end of the fourth equivalent inductor L4 and one end of the eighth equivalent capacitor C8 are connected by 8 to the sixteenth via P16 in the Fig.12 The other end of the eighth equivalent capacitor C8 is connected to the ground, the fourth equivalent inductor L4 and one end of the eighth equivalent capacitor C8 are connected to one end of the seventh equivalent capacitor C7 and one end of the fifth equivalent capacitor L5, the other end of the seventh equivalent capacitor C7 is connected to the other end of the fifth equivalent capacitor L5, and the connection end of the seventh equivalent capacitor C7 and the fifth equivalent capacitor L5 is connected to one end of the ninth equivalent capacitor C9, Figure 1 The side conductor N3 in the circuit is connected to the high-frequency channel output port connection N3, and the other end of the ninth equivalent capacitor C9 is connected to the ground end.

[0100] The ultra-high isolation miniaturized dual-channel signal processor further includes a mark M, wherein the mark M and the external electrode are located on the opposite side of the ceramic body.

[0101] The circuit layer is built into the ceramic body by adopting a low temperature co-fired ceramic process.

[0102] The circuit layer adopts an embedded metal material, and the embedded metal material includes copper or silver.

[0103] In one embodiment of the present invention, the multi-layer circuit of the frequency divider is built into a ceramic body of 1.6 mm×0.8 mm×0.6 mm and sintered at a temperature of 890° C.±20° C.

[0104] Fig.15 , Fig.16 , Fig.17 and Fig.18 FIG. 1 is a schematic frequency response characteristic curve diagram of an ultra-high isolation miniaturized signal processor in an embodiment of the present invention. The low-frequency passband loss and echo response of the present invention are shown in FIG. Fig.15 As shown in the figure, the insertion loss of the low-frequency channel signal processor in the working frequency band of 2400-2500MHz is only 0.50dB, and the out-of-band suppression of 4800-7500MHz reaches 40dB. The return loss response of the high-frequency channel signal processor is shown in the figure. Fig.16 As shown in the figure, the insertion loss of the working frequency band of 4900-5950MHz is only 0.6dB, and the out-of-band suppression of low frequency from 824-2500MHz reaches 26dB, of which 2400-2500MHz is as high as 37dB, and the high frequency reaches more than 27dB at 10300-11900MHz. Fig.17 The isolation characteristic curve is shown in Figure 2. The operating frequency bands of 2400-2500MHz and 4900-5950MHz reach more than 38dB. Fig.18The common end echo of the signal processor of the present invention has an echo loss of nearly 15 dB for both channels. The above indicators reflect the good transmission characteristics of the frequency divider and the high mutual isolation between channels.

[0105] The present invention provides an ultra-high isolation miniaturized dual-channel signal processor based on multi-layer interconnection technology, which has excellent performances such as high isolation, small size, and low insertion loss. At the same time, under the premise of ensuring that the volume is not affected, the isolation unit is applied to the ground loop of the two passbands, which improves the isolation and realizes the function of easy integration with other circuit modules, and has broad application prospects in the field of new generation wireless communications.

[0106] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those skilled in the art can make various other specific variations and combinations that do not deviate from the essence of the present invention based on the technical revelations disclosed by the present invention, and these variations and combinations are still within the protection scope of the invention.

Claims

1. An ultra-high isolation miniaturized dual-channel signal processor, characterized in that: The invention comprises a ceramic body, a circuit layer inside the ceramic body and an external electrode outside the ceramic body, wherein the external electrode comprises a common port (N1), a low-frequency channel output port (N2), a high-frequency channel output port (N3), a first ground port (G1), a second ground port (G2) and a third ground port (G3), wherein the first ground port (G1), the common port (N1) and the second ground port (G2) are located on one side outside the ceramic body, and the low-frequency channel output port (N2), the high-frequency channel output port (N3) and the third ground port (G3) are located on the other side outside the ceramic body, and the external electrode is connected to the circuit layer inside the ceramic body via a side metal. The circuit layer includes a low-frequency channel signal processor and a high-frequency channel signal processor, and the low-frequency channel signal processor and the high-frequency channel signal processor are both connected to a common port (N1); The low-frequency channel signal processor comprises a first equivalent inductor L1, a second equivalent inductor L2, a first equivalent capacitor C1, a second equivalent capacitor C2 and a third equivalent capacitor C3, one end of the first equivalent inductor L1 is connected to a common port (N1), and the other end thereof is respectively connected to one end of the second equivalent inductor L2, one end of the first equivalent capacitor C1 and one end of the second equivalent capacitor C2, the other end of the second equivalent inductor L2 and the other end of the first equivalent capacitor C1 are both connected to one end of the third equivalent capacitor C3, the other end of the second equivalent capacitor C2 is connected to a second ground port (G2), the other end of the third equivalent capacitor C3 is connected to the second ground port (G2), and one end of the third equivalent capacitor C3 is also connected to a low-frequency channel output port (N2); The high-frequency channel signal processor includes a third equivalent inductor L3, a fourth equivalent inductor L4, a fifth equivalent inductor L5, a fourth equivalent capacitor C4, a fifth equivalent capacitor C5, a sixth equivalent capacitor C6, a seventh equivalent capacitor C7, an eighth equivalent capacitor C8 and a ninth equivalent capacitor C9, one end of the fourth equivalent capacitor C4 is respectively connected to the common port (N1) and one end of the sixth equivalent capacitor C6, and the other end thereof is respectively connected to one end of the third equivalent inductor L3 and one end of the fifth equivalent capacitor C5, the other end of the third equivalent inductor L3 is connected to the first ground port (G1), the other end of the fifth equivalent capacitor C5 is respectively connected to one end of the fourth equivalent inductor L4 and the other end of the sixth equivalent capacitor C6 The other end of the fourth equivalent inductor L4 is respectively connected to one end of the eighth equivalent capacitor C8, one end of the seventh equivalent capacitor C7 and one end of the fifth equivalent inductor L5, the other end of the seventh equivalent capacitor C7 and the other end of the fifth equivalent inductor L5 are both connected to the high-frequency channel output port (N3), the high-frequency channel output port (N3) is also connected to one end of the ninth equivalent capacitor C9, the other end of the eighth equivalent capacitor C8 is connected to the first ground port (G1), and the other end of the ninth equivalent capacitor C9 is connected to the first ground port (G1); The circuit layer further includes an isolation improving unit LG, one end of the isolation improving unit LG is respectively connected to the other end of the second equivalent capacitor C2 and the other end of the third equivalent capacitor C3, and the other end thereof is respectively connected to the other end of the third equivalent inductor L3, the other end of the eighth equivalent capacitor C8 and the other end of the ninth equivalent capacitor C9; The circuit layers include, from top to bottom, a first circuit layer, a second circuit layer, a third circuit layer, a fourth circuit layer, a fifth circuit layer, a sixth circuit layer, a seventh circuit layer, an eighth circuit layer, a ninth circuit layer, a tenth circuit layer and an eleventh circuit layer; The first circuit layer comprises a first electrode plate (101), a second electrode plate (102), a third electrode plate (103), a fourth electrode plate (104), a first via hole (P1), a fifth via hole (P5), a ninth via hole (P9), a tenth via hole (P10), a fourteenth via hole (P14) and a sixteenth via hole (P16); The second circuit layer comprises a fifth electrode plate (201), a sixth electrode plate (202), a second via hole (P2), a fifth via hole (P5), a ninth via hole (P9), an eleventh via hole (P11), a fourteenth via hole (P14) and a sixteenth via hole (P16); The third circuit layer comprises a seventh electrode plate (301), an eighth electrode plate (302), a ninth electrode plate (303), a third via hole (P3), a sixth via hole (P6), a ninth via hole (P9), a twelfth via hole (P12), a fourteenth via hole (P14) and a sixteenth via hole (P16); The fourth circuit layer comprises a tenth electrode plate (401), an eleventh electrode plate (402), a twelfth electrode plate (403), a thirteenth electrode plate (404), a fourteenth electrode plate (405), a fourth via hole (P4), a seventh via hole (P7), a ninth via hole (P9), a thirteenth via hole (P13), a fifteenth via hole (P15) and a sixteenth via hole (P16); The fifth circuit layer comprises a fifteenth electrode plate (501), a sixteenth electrode plate (502), a seventeenth electrode plate (503), an eighteenth electrode plate (504), an eighth via hole (P8) and a seventeenth via hole (P17); The sixth circuit layer includes a nineteenth electrode plate (601), an eighth via hole (P8), a seventeenth via hole (P17), and an eighteenth via hole (P18); The seventh circuit layer comprises a twentieth electrode plate (701), a twenty-first electrode plate (702), a twenty-second electrode plate (703), an eighth via hole (P8), a seventeenth via hole (P17) and a nineteenth via hole (P19); The eighth circuit layer includes a twenty-third electrode plate (801), a twenty-fourth electrode plate (802), a twenty-fifth electrode plate (803), a twenty-sixth electrode plate (804), an eighth via hole (P8), a seventeenth via hole (P17) and a twentieth via hole (P20); The ninth circuit layer includes a twenty-seventh electrode plate (901), a twenty-eighth electrode plate (902), a twenty-ninth electrode plate (903), an eighth via hole (P8), a seventeenth via hole (P17) and a twenty-first via hole (P21); The tenth circuit layer comprises a thirtieth electrode plate (1001), a thirty-first electrode plate (1002), a thirty-second electrode plate (1003), a thirty-third electrode plate (1004) and a twenty-first via hole (P21); The eleventh circuit layer includes a thirty-fourth electrode plate (1101), a thirty-fifth electrode plate (1102) and a thirty-sixth electrode plate (1103); The 20th electrode plate (701) and the 25th electrode plate (901) are connected in sequence via the eighth via hole (P8), and are coupled with the 24th electrode plate (802) and the 31st electrode plate (1002) through interlayer coupling to form the first equivalent capacitor C1; The twentieth electrode plate (701), the twenty-seventh electrode plate (901) and the thirtieth electrode plate (1001) are connected in sequence via the eighth via hole (P8), and are coupled with the twenty-third electrode plate (801) and the thirty-fourth electrode plate (1101) through interlayer coupling to form the second equivalent capacitor C2; The thirty-first electrode plate (1002) and the thirty-fifth electrode plate (1102) form the third equivalent capacitor C3 through interlayer coupling; The sixteenth electrode plate (502) and the nineteenth electrode plate (601) form the fourth equivalent capacitor C4 through interlayer coupling; The seventeenth electrode plate (503) and the nineteenth electrode plate (601) form the fifth equivalent capacitor C5 through interlayer coupling; The fourteenth electrode plate (405) and the seventeenth electrode plate (503) form the sixth equivalent capacitor C6 through interlayer coupling; The twenty-second electrode plate (703) and the twenty-ninth electrode plate (903) are connected via the seventh via hole (P7), and are coupled with the twenty-sixth electrode plate (804) through interlayer coupling to form the seventh equivalent capacitor C7; The thirty-second electrode plate (1003) and the thirty-fourth electrode plate (1101) form the eighth equivalent capacitor C8 through interlayer coupling; The thirty-third electrode plate (1004) and the thirty-fourth electrode plate (1101) form the ninth equivalent capacitor C9 through interlayer coupling; The first electrode plate (101), the fifth electrode plate (201), the seventh electrode plate (301), the tenth electrode plate (401) and the fifteenth electrode plate (501) are connected end to end in sequence via the second via hole (P2), the third via hole (P3) and the fourth via hole (P4) to form the first equivalent inductance L1; The second electrode plate (102), the eighth electrode plate (302), the eleventh electrode plate (402) and the fifteenth electrode plate (501) are connected end to end in sequence via a fifth via hole (P5), a sixth via hole (P6) and a seventh via hole (P7) to form the second equivalent inductance L2; The twenty-first electrode plate (702), the twenty-fifth electrode plate (803) and the twenty-eighth electrode plate (902) are connected end to end in sequence via the nineteenth via hole (P19), the twentieth via hole (P20) and the twenty-first via hole (P21) to form the third equivalent inductance L3; The third electrode plate (103), the sixth electrode plate (202), the ninth electrode plate (303), the twelfth electrode plate (403) and the eighteenth electrode plate (504) are connected end to end in sequence via the tenth via hole (P10), the eleventh via hole (P11), the twelfth via hole (P12) and the thirteenth via hole (P13) to form the fourth equivalent inductance L4; The fourth electrode plate (104), the thirteenth electrode plate (404) and the eighteenth electrode plate (504) are connected end to end in sequence via the fourteenth via hole (P14) and the fifteenth via hole (P15) to form the fifth equivalent inductor L5.

2. The ultra-high isolation miniaturized dual-channel signal processor according to claim 1, characterized in that: The ultra-high isolation miniaturized dual-channel signal processor also includes a mark, and the mark and the external electrode are located on the opposite side of the ceramic body.

3. The ultra-high isolation miniaturized dual-channel signal processor according to claim 1, characterized in that: The circuit layer is built into the ceramic body by adopting a low temperature co-fired ceramic process.

4. The ultra-high isolation miniaturized dual-channel signal processor according to claim 1, characterized in that: The circuit layer is made of embedded metal material, and the embedded metal material includes copper or silver.

Images