A fully digital laser frequency stabilization method based on system-on-chip

Abstract

The present invention provides a fully digital laser frequency stabilization system based on a system on chip, which includes a board-level power supply module, a signal generation module, a data acquisition module, a digital signal processing module, a peak search module, a PID module, a data output module, a data cache module and a data communication module; the digital signal processing module and the signal generation module use the FPGA chip of the system on chip; the digital signal processing module is used to demodulate and low-pass filter the reflected signal of the frequency stabilization optical system; the signal generation module is used to generate a swept frequency sawtooth wave signal, a modulated sine signal, and an IQ demodulated sine and cosine signal; the PID module is based on the ARM processor of the system on chip, and the PDH error signal is subjected to a PID algorithm to obtain a PZT feedback control signal and a temperature feedback control signal. The present invention uses the system on chip as the control core, the FPGA chip is responsible for data acquisition, digital signal processing, and data output, and the ARM processor is responsible for the PID control algorithm and inverse tangent calculation, and can stabilize the output optical frequency of the laser.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technology, and in particular to a full digital laser frequency stabilization method based on a system on a chip. Background Art

[0002] In gravitational wave detection, high-stability laser interferometers are the key core parts, among which frequency-stable lasers are one of the most important components. The frequency of a free-running laser fluctuates over time and is easily affected by external factors, so certain measures need to be taken to stabilize the frequency of the laser. Laser frequency stabilization methods are divided into passive frequency stabilization and active frequency stabilization. Passive frequency stabilization generally adopts sealing, constant temperature, and seismic isolation, and the resulting laser frequency stability is low. Active frequency stabilization often uses atomic and molecular transition lines or high-quality optical reference cavities as reference frequency benchmarks, and uses frequency stabilization control circuits as the control core. Frequency stabilization control circuits with high-speed data acquisition, output, and communication functions can be built, and ultra-stable lasers with high stability and extremely narrow linewidth can be obtained.

[0003] The PDH active frequency stabilization based on a high-precision reference cavity is a high-precision and high-stability frequency stabilization solution. The basic principle is to stabilize the laser frequency to the optical reference cavity. The PDH frequency stabilization technology is first used to apply a sinusoidal signal to the electro-optical phase modulator EOM. The laser modulated by the EOM will produce a pair of first-order modulation sidebands with equal amplitude and opposite phase on both sides of the original carrier frequency. After being incident on the FP cavity, a reflected signal for frequency stabilization is generated. Secondly, the electronic system demodulates and low-pass filters the reflected signal to obtain the PDH error signal for frequency stabilization. Finally, the PDH error signal is fed back to the laser PZT and the temperature actuator after PID calculation to achieve laser frequency stabilization.

[0004] The existing PDH frequency stabilization control circuit adopts a full analog solution or an analog + digital circuit solution, that is, the required signal generator, mixer, and low-pass filter are all or partially implemented with analog devices. The disadvantages of using an analog frequency stabilization solution are: analog signals are easily interfered by the outside world, and if discrete analog devices are used to build a frequency stabilization circuit, it also has the disadvantages of distributed spurious and large volume, which is not conducive to the miniaturization and intelligence of PDH frequency stabilization lasers.

[0005] The existing digital frequency stabilization solution uses a single FPGA chip to implement the signal generator, mixer, and low-pass filter required for frequency stabilization. At the same time, the PID module is also completed by the FPGA chip. The PID parameter adjustment implemented by the FPGA chip often uses shifting instead of division to approximate decimal calculations, which has the disadvantages of large errors and low precision. If the accuracy of PID parameter adjustment is improved by expanding the bit width, it will also cause problems such as increased resource consumption and difficulty in bit truncation. If floating-point numbers are used for PID parameter adjustment, higher control accuracy can be obtained, but FPGA chips are not good at floating-point calculations. Therefore, FPGA chips have limitations in floating-point operations and are not as good as conventional microcontrollers in processing floating-point numbers. Using FPGA chips to implement PID calculations makes it difficult to achieve the best control effect for the frequency stabilization system through precise parameter adjustment.

[0006] In the existing frequency stabilization technology, a synchronous detection method is used to obtain the PDH error signal, that is, to ensure the synchronization of the phase of the demodulated sine signal and the reflected signal. If the phase is not synchronized, the amplitude of the demodulated error signal will be reduced and asymmetric. The existing frequency stabilization technology often achieves phase synchronization of the demodulated sine signal and the reflected signal before frequency stabilization by manually adjusting the phase. This method can ensure phase synchronization in the short term, but the phase difference is not always constant in long-term frequency stabilization. The use of manual phase adjustment will cause the problem that the strict synchronization of the phase cannot always be maintained in long-term frequency stabilization. The common method of actively calculating the phase difference is to use IQ demodulation to automatically calculate the phase difference, by multiplying the reflected signal by the sine signal and the cosine signal to obtain two signals, and then calculating the inverse tangent of the two signals to obtain the phase difference. In the existing frequency stabilization technology, IQ demodulation calculates the inverse tangent through the host computer, and then transmits the data to the FPGA chip through the host computer. This implementation method depends on the host computer (PC), and the data calculation, data reception, and data transmission of the host computer will consume time, slowing down the response speed of the frequency stabilization system.

[0007] The performance of low-pass filters is very important in frequency stabilization. The filtering effect directly affects the frequency stabilization effect. However, the existing frequency stabilization technology does not clearly describe the design method of digital filters, nor does it fully compare the advantages and disadvantages of I IR and FIR digital filters in frequency stabilization.

[0008] The existing digital frequency stabilization technology often uses commercial high-speed data acquisition cards to collect reflected signals. For different frequency stabilization systems, the amplitude of the reflected signal is often different. When the amplitude of the reflected signal is greater than the acquisition voltage range, the reflected signal cannot be correctly collected. When the amplitude of the reflected signal is much smaller than the acquisition voltage range, there is a problem of low signal-to-noise ratio of the collected reflected signal. If the acquisition voltage range of the circuit board used for frequency stabilization is fixed, there will be problems such as insufficient acquisition range and the acquisition signal-to-noise ratio cannot reach the highest level for different frequency stabilization systems.

[0009] To sum up, it is necessary to make further innovations on existing technologies. Summary of the invention

[0010] In view of the technical problems existing in the above-mentioned background technology, the present invention proposes a fully digital laser frequency stabilization system based on a system on chip, which uses the system on chip as the control core. The FPGA chip of the system on chip is responsible for data acquisition, digital signal processing, and data output, and the ARM processor of the system on chip is responsible for PID control algorithm and inverse tangent calculation. The two work together to achieve the purpose of stabilizing the output optical frequency of the laser.

[0011] In order to solve the above technical problems, the present invention provides a fully digital laser frequency stabilization system based on a system on chip, which includes a board-level power supply module, a signal generation module, a data acquisition module, a digital signal processing module, a peak search module, a PID module, a data output module, a data cache module, a data communication module, a system on chip and a host computer;

[0012] The main control chip of the system on chip includes an FPGA chip and an ARM processor;

[0013] The board-level power supply module uses a power supply chip to generate various voltage values ​​required by each circuit module in the frequency stabilization system, and realizes sequential power-on of the system on chip;

[0014] The signal generation module uses the DDS ip core in the FPGA chip of the system on chip to generate two sinusoidal signals for modulation and demodulation, a sine and cosine signal for IQ demodulation, and a sawtooth wave signal for frequency sweeping; the modulated sine signal is output to the EOM to modulate the laser frequency, the demodulated sine signal is used for frequency mixing of the digital signal processing module, the IQ demodulated sine and cosine signals are used for phase matching in the digital signal processing module, and the sawtooth wave signal is output to the PZT actuator of the laser to sweep the laser frequency;

[0015] The data acquisition module uses a high-speed analog-to-digital converter, which is connected to the FPGA chip side of the system on chip and is used to collect the reflection signal of the FP cavity in the frequency-stabilizing optical system into the system on chip;

[0016] The digital signal processing module uses the FPGA chip of the system on chip to demodulate and low-pass filter the reflection signal of the FP cavity in the frequency stabilization optical system to obtain a PDH error signal for frequency stabilization;

[0017] The peak-finding module is used to find the zero-crossing point of the PDH error signal;

[0018] The PID module is based on the ARM processor of the system on chip, and is used to perform an incremental digital PID algorithm operation on the PDH error signal to obtain a PZT feedback control signal of the laser and a temperature actuator feedback control signal;

[0019] The data output module uses a high-speed digital-to-analog converter to convert the digital signal into an analog voltage signal; the analog voltage signal includes a modulated sine signal, a swept sawtooth signal and a feedback control signal; the modulated sine signal is output to the EOM to modulate the laser frequency; the swept sawtooth signal is output to the PZT actuator of the laser for frequency sweeping; the feedback control signal is output to the PZT actuator and temperature actuator of the laser;

[0020] The data cache module uses a DDR3 chip to form a cache space of the system on chip, which is used to cache the signals in the frequency stabilization process in real time;

[0021] The data communication module uses a USB3.0 chip to read the signal cached in the DDR3 chip in real time and send it to the host computer for display, and adjust the parameters in the PID module in real time and send control commands to the on-chip system.

[0022] The all-digital laser frequency stabilization system based on a system on chip, wherein: the board-level power supply module is electrically connected to the system on chip, and includes a system on chip power supply module, a high-speed digital-to-analog converter power supply module, a high-speed analog-to-digital converter power supply module, an operational amplifier power supply module and a data communication power supply module; the system on chip power supply module adopts a sequential power-on method to power the system on chip; the sequential power-on method is: using a power chip with a PG pin and an EN pin, and connecting the PG pin to the EN pin of the next-level power chip to realize the sequential power-on of the system on chip; the high-speed digital-to-analog converter power supply module, the high-speed analog-to-digital converter power supply module and the operational amplifier power supply module all select LDO chips to generate the voltage required by the corresponding device; the data communication power supply module selects a DC-DC chip whose output meets the device requirements to generate the voltage required by the corresponding device.

[0023] The all-digital laser frequency stabilization system based on the system on chip, wherein the sequential power-on method can also be: sequential power-on is achieved by adjusting the capacitance of the external capacitor of the soft-start pin of the power chip to control the voltage rise time of each level of the power chip; the power-on sequence of the system on chip is core power, auxiliary power and BANK power.

[0024] The all-digital laser frequency stabilization system based on the system on chip, wherein: the signal input end of the data acquisition module is electrically connected to the signal output end of the external frequency stabilization optical system, and the signal output end of the data acquisition module is electrically connected to another signal input end of the digital signal processing module; the data acquisition module includes a high-speed analog-to-digital converter and a front-end analog signal link; the high-speed analog-to-digital converter is powered by the high-speed analog-to-digital converter power module, which adopts a high-speed analog-to-digital conversion chip with 16-bit resolution, 125M sampling rate and dual channels; the front-end analog signal link is used to condition the analog signal output by the frequency stabilization optical system to convert it into a differential signal and conform to the acquisition range of the high-speed analog-to-digital conversion chip.

[0025] The all-digital laser frequency stabilization system based on the system on chip, wherein: the front-end analog signal link includes an AC coupling module, an impedance matching network, a filtering module, a voltage follower module and a single-ended to differential module; the AC coupling module uses a capacitor C1 with a capacitance of 100nF to filter out the DC component of the reflected signal of the FP cavity in the frequency stabilization optical system; the impedance matching network uses four high-precision thin-film resistors R1-R4 to build a π-type resistor network, which can achieve 50Ω impedance matching and can determine whether to attenuate the signal according to the size of the reflected signal of the FP cavity in the frequency stabilization optical system; the filtering module uses a passive low-pass filter with a cutoff frequency of 30MHZ to filter out high-frequency noise in the reflected signal of the FP cavity in the frequency stabilization optical system, so as to improve the reflection of the FP cavity in the frequency stabilization optical system. The signal-to-noise ratio of the RF signal is improved; the voltage follower module is powered by the operational amplifier power module, which is constructed using the first high-speed operational amplifier OPA1. By outputting the signal passing through the filtering module to the positive end of the first high-speed operational amplifier OPA1, the reverse end of the first high-speed operational amplifier OPA1 is connected to the output end, so as to realize the voltage following function, so as to increase the driving capability of the analog input signal; the single-ended to differential module is powered by the operational amplifier power module, which is constructed using the second high-speed operational amplifier OPA2, and is used to convert the single-ended output signal of the voltage follower module into a differential signal, and increase the DC bias of the high-speed analog-to-digital converter output, so that the input single-ended analog signal is finally converted into a differential signal that meets the acquisition range of the high-speed analog-to-digital converter.

[0026] The all-digital laser frequency stabilization system based on the system on chip, wherein: the signal generator module is electrically connected to one of the signal input ends of the digital signal processing module through one of the signal output ends, and is electrically connected to one of the signal input ends of the data output module through another signal output end; the signal generator module includes a modulation and demodulation sine signal generation module, an IQ demodulation sine and cosine signal generation module and a swept sawtooth wave signal generation module; the signal generation modules all use a DDS signal generator ip core to generate the required signal.

[0027] The all-digital laser frequency stabilization system based on a system on a chip, wherein: the digital signal processing module includes a phase matching module, a frequency mixing module and a low-pass filtering module;

[0028] The phase matching module is used to obtain the phase difference between the reflected signal of the FP cavity in the frequency stabilization optical system and the demodulated sine signal generated by the modulation and demodulation sine signal generation module, and the demodulated sine signal generated by the signal generation module is added with the phase difference to obtain the demodulated sine signal that is phase-aligned with the reflected signal in the frequency stabilization; the calculation method of the phase difference is based on IQ demodulation, that is, in the FPGA chip, the reflected signal of the FP cavity in the frequency stabilization optical system is numerically multiplied by the IQ demodulated sine signal generated by the signal generation module and the IQ demodulated cosine signal generated by the signal generation module to obtain two output signals, and the obtained two output signals are passed through two low-pass filters to obtain two filtered signals, and finally the two filtered signals are sent to the ARM processor of the system on chip to calculate the inverse tangent to obtain the phase difference between the reflected signal of the FP cavity in the frequency stabilization optical system and the demodulated sine signal, so as to achieve the phase alignment of the demodulated sine signal and the reflected signal of the FP cavity in the frequency stabilization optical system; and the data interaction between the FPGA chip and the ARM processor is based on the AXI protocol;

[0029] The frequency mixing module numerically multiplies the demodulated sinusoidal signal and the reflected signal of the FP cavity of the frequency stabilizing optical system collected by the data collection module through a multiplier;

[0030] The low-pass filtering module is used to pass the output of the mixing module through a digital low-pass filter to obtain a PDH error signal for frequency stabilization after filtering.

[0031] The all-digital laser frequency stabilization system based on a system on a chip, wherein: the low-pass filtering module uses a limited impulse response filter.

[0032] The all-digital laser frequency stabilization system based on the system on chip, wherein: the signal input end of the peak-finding module is electrically connected to the signal output end of the digital signal processing module, and the signal output end of the peak-finding module is electrically connected to the signal input end of the PID module; the peak-finding module transmits the PDH error signal for frequency stabilization obtained by the digital signal processing module to the ARM processor of the system on chip through the AXI protocol for peak-finding algorithm operation to calculate the zero-crossing point of the PDH error signal.

[0033] The all-digital laser frequency stabilization system based on the system on chip, wherein: the peak finding algorithm uses a threshold judgment method to find the peak point of the PDH error signal, then finds the position of the zero crossing point of the PDH error signal, and records the magnitude of the sawtooth wave signal voltage value at the zero crossing point.

[0034] The all-digital laser frequency stabilization system based on the system on chip, wherein: the signal output end of the PID module is electrically connected to the signal input end of the data output module; the PID module includes a first-level PID and a second-level PID, which inputs the PDH error signal to the first-level PID operation, adds the first-level PID operation result and the sawtooth wave voltage value at the zero-crossing point of the PDH error signal to obtain a PZT feedback control signal, and switches to a laser frequency stabilization mode after obtaining the PZT feedback control signal, and switches the swept frequency sawtooth wave signal applied to the PZT actuator of the laser to a PZT feedback control signal to achieve rapid modulation of the laser frequency; at the same time, the first-level PID operation result is sent to the second-level PID operation, and the second-level PID operation result is output to the temperature actuator of the laser to slowly modulate the laser frequency.

[0035] The all-digital laser frequency stabilization system based on the system on chip, wherein: the feedback control signal size of the PZT actuator of the laser is the sum of the first-level PID operation result of the PID module and the sawtooth wave signal voltage value at the zero crossing point of the PDH error signal; the feedback control signal size of the temperature actuator of the laser is the second-level PID calculation result of the PID module.

[0036] The all-digital laser frequency stabilization system based on the system on chip, wherein: the signal output end of the data output module is electrically connected to the signal input end of the frequency stabilization optical system; the data output module includes the high-speed digital-to-analog converter, the current-to-voltage module, the differential-to-single-ended module and the voltage amplification module; the high-speed digital-to-analog converter is powered by the high-speed digital-to-analog converter power supply module, which adopts a high-speed digital-to-analog conversion chip with 16-bit resolution, 125M sampling rate and dual channels; the current-to-voltage module uses two independent high-precision thin-film resistors with a resistance of 50Ω, one end of which is connected to the differential output end of the high-speed digital-to-analog converter and the other end is grounded; the high-speed digital-to-analog converter The two differential output pins are each connected to a 50Ω high-precision resistor to ground, so as to convert the current output signal of the high-speed digital-to-analog converter into a voltage signal. The current output signal of the high-speed digital-to-analog converter is ±20mA, which is converted into a ±1V voltage signal through a 50Ω high-precision resistor to ground; the differential-to-single-ended module uses a high-speed operational amplifier and is powered by the operational amplifier power supply module to convert the differential voltage signal into a single-ended signal; the voltage amplification module uses a high-speed operational amplifier and is powered by the operational amplifier power supply module to amplify the single-ended signal generated by the differential-to-single-ended module, and amplifies the ±1V voltage signal into ±3V.

[0037] The all-digital laser frequency stabilization system based on the system on chip, wherein: the data communication module is also bidirectionally electrically connected to the host computer; the data communication module is powered by the data communication power supply module, and includes a data reading module, a data sending module and a data receiving module; the data reading module is used to read the important signal cache data in the data cache module in real time; the data sending module is used to send the read cache data to the host computer through the USB interface in real time; the data receiving module is used to receive instructions from the host computer in real time, and adjust the frequency and amplitude of the signal generated in the signal generating module, adjust the threshold value in the peak finding module, and adjust the PID parameters in the PID module in real time.

[0038] The all-digital laser frequency stabilization system based on the system on chip, wherein: one end of the data cache module is bidirectionally electrically connected to the system on chip, and the other end is bidirectionally electrically connected to the data communication module; the data cache module uses four DDR3 chips, and the FPGA chip side and ARM processor side of the system on chip each mount two DDR3 chips, each DDR3 chip has a storage capacity of 2Gb, forming a total of 8Gb of data cache space.

[0039] By adopting the above technical solution, the present invention has the following beneficial effects:

[0040] The all-digital laser frequency stabilization system based on the system on chip of the present invention is reasonably conceived, and uses the FPGA chip in the system on chip to digitize the analog devices in the existing PDH frequency stabilization solution, realizes the functions of high-speed data acquisition and digital signal processing, uses the advantage of the ARM processor in floating-point number calculation to perform more accurate parameter adjustment on the PID algorithm in the frequency stabilization, and calculates the inverse tangent in the IQ demodulation link. The ARM and FPGA chips of the system on chip work together to realize high-performance all-digital laser frequency stabilization.

[0041] Compared with the prior art, the main advantages of the present invention are embodied in the following aspects:

[0042] ① The existing frequency stabilization technology adopts a full analog or analog plus digital method. The present invention uses the FPGA chip of the system on chip to realize the full digitization of analog devices. Compared with the analog solution, the circuit volume is smaller and the frequency stabilization system has a higher degree of integration. In terms of the anti-interference ability of the frequency stabilization system, digital signals have stronger anti-interference ability than analog signals.

[0043] ② The system on chip of the present invention is equipped with an ARM processor, and its advantages are reflected in the PID calculation and phase matching of frequency stabilization; the PID module in frequency stabilization involves PID parameter adjustment, and the PID module is implemented by the ARM processor in the system on chip. The ARM processor can easily implement floating-point calculation, and can more accurately adjust the PID parameters to achieve the best effect of frequency stabilization control. The existing frequency stabilization circuit uses a pure FPGA chip. The common method of using the FPGA chip to implement PID calculation is: the PID parameters are first expanded by integer multiples, and after obtaining the calculation results, fixed-point shift is used instead of division to approximate floating-point calculation. This calculation method has the disadvantage of large error and has limitations in floating-point calculation. The PID parameter adjustment has the disadvantage of large error, and it is not easy to achieve more precise parameter adjustment to achieve the best effect of frequency stabilization control. If the parameter adjustment accuracy is improved by expanding the bit width, it will cause the FPGA chip to consume more resources and data truncation difficulties. The present invention uses an ARM processor for PID control, and the parameter adjustment uses floating-point calculation. It is simple to implement and has higher accuracy under the premise of meeting real-time performance. After rounding the calculation results, the data is transmitted to the FPGA chip at high speed through the AXI protocol.

[0044] ③ The existing frequency stabilization technology uses synchronous detection to demodulate, and it is necessary to manually adjust the phase to achieve the alignment of the reflected signal and the demodulated sinusoidal signal phase. The existing method of automatically calculating the phase difference is to use IQ demodulation. The arctangent calculation in IQ demodulation relies on the host computer to achieve it, and it is necessary to send the data to the host computer for calculation, and then send the calculation result from the host computer to the FPGA chip. The present invention uses the ARM processor of the system on chip to complete the arctangent calculation, and the phase difference can be conveniently and accurately calculated using the mature mathematical library of ARM, and high-speed data interaction is performed inside the chip and with the FPGA chip through the AXI protocol. Its advantage is that the IQ demodulation to obtain the phase difference is implemented in the system on chip, and the arctangent is partially calculated using the ARM processor of the system on chip, which does not rely on the host computer. At the same time, the ARM processor supports the operating system, which is convenient for the development of later upper-layer applications for the frequency stabilization system.

[0045] ④ The design of digital filter is the key to frequency stabilization. The quality of error signal filtering directly affects the quality of frequency stabilization. The existing frequency stabilization technology is not clear enough in the design method of digital filter. The present invention uses finite impulse response digital filter (IIR filter for short) to achieve the same filtering effect in the frequency stabilization system while consuming less resources than infinite impulse response digital filter (FIR filter for short).

[0046] ⑤Although it is very convenient to design a digital filter using the FIR filter ip core, the performance of the designed filter is fixed, that is, the order and cutoff frequency cannot be modified. When facing lasers with different bandwidths, the FIR filter needs to be redesigned. The present invention saves the pre-calculated parameters of the IIR filter with different performances by adding a 64KB EEPROM on the frequency stabilization circuit board. The order and cutoff frequency of the filter can be easily modified by reading the pre-saved parameters in the EEPROM through the host computer control, and filters with different performances can be flexibly called in the frequency stabilization. Compared with the design method of the FIR filter, the digital filter design method of the present invention has good filtering effect when facing lasers with different bandwidths in different frequency stabilization systems, uses IIR filters, occupies less resources, and has strong flexibility.

[0047] ⑥ In the digital frequency stabilization system, it is very important to collect the reflected signal with a high signal-to-noise ratio. The effective information amplitude of the reflected signal is often different in different frequency stabilization systems. Most of the existing frequency stabilization technologies use commercial data acquisition cards, and their acquisition ranges are mostly fixed. When the amplitude of the reflected signal is greater than the acquisition voltage range, the reflected signal cannot be correctly collected. When the amplitude of the reflected signal is much smaller than the acquisition voltage range, there is a problem of low signal-to-noise ratio of the collected reflected signal. In order to solve the problem that the reflected signal voltage amplitude exceeds the acquisition range and the reflected signal cannot be correctly collected, the present invention adds an impedance matching network, namely a π-type resistor network, to the front-end analog signal chain of the high-speed analog-to-digital converter. While achieving 50Ω impedance matching, it can determine whether to attenuate the amplitude of the reflected signal in the frequency stabilization system by adjusting the resistance value of the resistor in the network. By adding this impedance matching network, the problem that the amplitude of the reflected signal in the frequency stabilization system exceeds the acquisition range of the analog-to-digital converter is effectively solved. In order to solve the problem that the reflected signal amplitude is much smaller than the acquisition voltage range, resulting in a low signal-to-noise ratio, the present invention selects to use a high-speed differential operational amplifier with a high gain-bandwidth product, and adjusts the resistance of the feedback resistors at both ends to achieve high-gain amplification without losing the accuracy of the signal. When the reflected signal amplitude is much smaller than the acquisition range of the analog-to-digital converter, the signal-to-noise ratio of the collected reflected signal will be reduced. By adjusting the resistance of the feedback resistor of the high-speed differential operational amplifier, the signal can be amplified without losing the accuracy of the original signal. At the same time, the present invention adds a passive low-pass filter to the frequency stabilization circuit to filter the reflected signal to improve the signal-to-noise ratio of the reflected signal. When facing different frequency stabilization systems, the design of the present invention can flexibly choose to amplify or attenuate the amplitude of the reflected signal in hardware, so that it meets the full-scale acquisition range of the high-speed analog-to-digital converter while improving the signal-to-noise ratio of the collected reflected signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0049] Figure 1 It is a schematic diagram of the overall structure of the all-digital laser frequency stabilization system based on the system-on-chip of the present invention;

[0050] Figure 2 It is a schematic diagram for describing the functions of the system on chip of the all-digital laser frequency stabilization system based on the system on chip of the present invention;

[0051] Figure 3 It is a schematic diagram of the interaction between the ARM processor and the FPGA chip of the system-on-chip of the all-digital laser frequency stabilization system based on the system-on-chip of the present invention;

[0052] Figure 4 A network diagram of a board-level power supply module of a full digital laser frequency stabilization system based on a system on a chip according to the present invention;

[0053] Figure 5 It is a design flow chart of an IIR digital filter of the all-digital laser frequency stabilization system based on a system on a chip of the present invention;

[0054] Figure 6 The circuit diagram of the data acquisition module of the all-digital laser frequency stabilization system based on the system-on-chip of the present invention. DETAILED DESCRIPTION

[0055] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0056] The present invention is further explained below in conjunction with specific implementation modes.

[0057] like Figure 1-2 As shown, the present embodiment provides a fully digital laser frequency stabilization system based on a system on a chip, including a board-level power supply module 1, a signal generating module 2, a data acquisition module 3, a digital signal processing module 4, a peak finding module 5, a PID module 6, a data output module 7, a data cache module 8, a data communication module 9 and a system on a chip 100.

[0058] The system on chip 100 integrates multiple functional modules on a single chip, wherein the main control chip of the system on chip 100 includes an FPGA chip and an ARM processor, which cooperate with each other to achieve the function of high-performance laser frequency stabilization.

[0059] like Figure 4 As shown, the board-level power supply module 1 is implemented using a DC-DC chip and an LDO chip, and its power input terminal uses a 12V DC voltage input. The board-level power supply module 1 is electrically connected to the system on chip 100, and includes a system on chip power supply module, a high-speed analog-to-digital converter power supply module, a high-speed digital-to-analog converter power supply module, and a data communication power supply module.

[0060] The system-on-chip power supply module is electrically connected to the system-on-chip 100 and is used to power the system-on-chip 100, and includes a DC-DC1 chip with a PG pin and an EN pin and LDO1~LD04 chips. The power input end of the DC-DC1 chip is connected to a 12V DC voltage, and the power output end is electrically connected to the EN pin of the power input end of the LDO1~LD04 chips through the PG pin; the power output end of the LDO1~LD04 chips is electrically connected to the system-on-chip 100. Among them, the system-on-chip power supply module needs to realize sequential power-on, and the implementation method of the sequential power-on is to first realize the voltage reduction from 12V to 5V through the DC-DC1 chip, and then realize the voltage reduction from 5V to 1V, 1.8V, 1.5V, and 3.3V through the LDO1~LD04 chips; the LDO1~LD04 chips are connected to the PG pin and the EN pin to realize the power-on sequence of the system-on-chip 100, first realize the power-on of the 1.0V core power supply, followed by the 1.8V auxiliary power supply, and finally the 1.8V, 1.5V, and 3.3V BANK power supplies. At the same time, the system-on-chip power supply module can also realize the sequential power-on method of the system-on-chip 100: by adjusting the capacitance of the external capacitor of the power chip soft start pin to control the voltage rise time of each level of the power chip to realize sequential power-on; the power-on sequence of the system-on-chip 100 is the core power supply, the auxiliary power supply, and the BANK power supply.

[0061] The high-speed analog-to-digital converter power module and the high-speed analog-to-digital converter power module are respectively electrically connected to the high-speed digital-to-analog converter of the data output module 7 and the high-speed analog-to-digital converter of the data acquisition module 3, and are used to power the high-speed analog-to-digital converter of the data acquisition module 3 and the high-speed digital-to-analog converter of the data output module 7. Among them, the high-speed analog-to-digital converter power module and the high-speed analog-to-digital converter power module require small power supply current and small power supply voltage ripple, and both include a DC-DC2 chip and an LDO5~LD08 chip; the power input end of the DC-DC2 chip is connected to a 12V DC voltage, and the power output end is respectively electrically connected to the power input end of the LDO5~LD08 chip; the power output end of the LDO5~LD08 chip is electrically connected to the power input end of the high-speed digital-to-analog converter and the high-speed analog-to-digital converter, and supplies power to the high-speed digital-to-analog converter and the high-speed analog-to-digital converter. Among them, the digital power supply and analog power supply of the high-speed digital-to-analog converter and the high-speed analog-to-digital converter need to be powered separately.

[0062] The operational amplifier power supply module 14 is used to provide dual power supply for the voltage follower module and the single-ended to differential module of the data acquisition module 3, as well as the differential to single-ended module of the data output module 7 and the high-speed operational amplifier in the voltage amplifier module. It requires a small power supply current and a small power supply voltage ripple and includes a DC-DC3 chip and an LDO9~LD011 chip. Among them, the power input end of the DC-DC3 chip is connected to a 12V DC voltage, and the power output end is electrically connected to the LDO9~LD010 chips respectively; the power output end of the LDO9 chip is electrically connected to the positive power input end of the operational amplifier; the LD010 chip is a negative voltage conversion chip, and its power output end is electrically connected to the power input end of the LD011 chip; the power output end of the LD011 chip is electrically connected to the negative power input end of the operational amplifier. The operational amplifier power supply module 14 adopts a two-stage step-down method to obtain positive and negative 5V power supplies. The first stage uses a DC-DC3 chip to convert the 12V DC voltage into a 5.5V voltage output, and uses an LD010 chip to convert 5.5V into -5.5V; the second stage uses an LDO9 chip and an LD011 chip to convert 5.5V into 5V and -5.5V into -5V respectively, providing ±5V dual power supply for the operational amplifier.

[0063] The data communication power supply module is used to power the data communication module 9, and includes a DC-DC4 chip whose output meets the device requirements; the power input end of the DC-DC4 chip is connected to a 12V DC voltage, and the power output end outputs the 3.3V voltage value required by the data communication module 9.

[0064] The signal generating module 2 uses the DDS ip core in the FPGA chip of the system on chip 100 to generate two sinusoidal signals for modulation and demodulation, a sine and cosine signal for IQ demodulation, and a sawtooth wave signal for frequency sweeping; wherein, the modulated sine signal is output to the EOM to modulate the laser frequency, the demodulated sine signal is used for mixing of the digital signal processing module, the IQ demodulated sine and cosine signals are used for phase matching of the digital signal processing module 4, and the sawtooth wave signal is output to the PZT actuator of the laser to sweep the laser. One of the signal output ends of the signal generating module 2 is electrically connected to one of the signal input ends of the digital signal processing module 4, and the other signal output end of the signal generating module 2 is electrically connected to one of the signal input ends of the data output module 7; the signal generating module 2 includes a modulation and demodulation sinusoidal signal generating module, an IQ demodulation sine and cosine signal generating module, and a frequency sweeping sawtooth wave signal generating module; wherein, the modulation and demodulation sinusoidal signal generating module, the phase matching sine and cosine signal generating module, and the frequency sweeping sawtooth wave signal generating module use the DDS signal generator ip core to generate the required signal. The signal generating module 2 uses the ip core DDS Compiler provided in VIVADO, and the output signal frequency formula is:

[0065]

[0066] Wherein, θ is the frequency control word, and N is the number of bits; the values ​​of θ and N are configured in the IP core to control the frequency of the output signal, wherein the higher the N, the higher the frequency resolution; the frequency of the modulation and demodulation sinusoidal signal used in the frequency stabilization system of the present invention is 1.3 MHz, and the frequency of the swept sawtooth wave signal is 10 Hz (the frequencies of the modulation and demodulation sinusoidal signal and the swept sawtooth wave are not fixed and can be changed according to the actual frequency stabilization system).

[0067] The signal input end of the data acquisition module 3 is electrically connected to the signal output end of the frequency stabilization optical system 300, and the signal output end of the data acquisition module 3 is electrically connected to another signal input end of the digital signal processing module 4; the data acquisition module 3 includes a high-speed analog-to-digital converter and a front-end analog signal link. Figure 6As shown, the data acquisition module 3 is connected to the FPGA chip side of the system on chip 100 through a high-speed analog-to-digital converter, converts the reflection signal of the FP cavity in the frequency-stabilizing optical system 300 from an analog signal to a digital signal, and transmits it to the FPGA chip for subsequent digital signal processing; the high-speed analog-to-digital converter adopts a 16-bit resolution, 125M sampling rate, dual-channel high-speed analog-to-digital conversion chip, and uses a built-in 1.0V reference voltage. The front-end analog signal link conditions the analog reflection signal output by the frequency-stabilizing optical system 300 to convert it into a differential signal and conform to the acquisition range of the high-speed analog-to-digital conversion chip; the front-end analog signal link includes an AC coupling module, an impedance matching network, a filtering module, a voltage follower module, and a single-ended to differential module. Among them, the AC coupling module uses a 100nF capacitor C1 to filter out the DC component of the reflection signal of the FP cavity in the frequency-stabilizing optical system 300. The impedance matching network uses resistors R1 to R4, and a total of four high-precision thin-film resistors R1 to R4 are used to build a π-type resistor network. While achieving 50Ω impedance matching, it can determine whether to attenuate the reflected signal voltage amplitude of the FP cavity in the frequency-stabilizing optical system 300, and the attenuation multiple can be controlled by modifying the resistance value. The filter module uses a passive low-pass filter with a cutoff frequency of 30MHz to filter out high-frequency noise in the reflected signal of the FP cavity in the frequency-stabilizing optical system 300, so as to improve the signal-to-noise ratio of the reflected signal of the FP cavity in the frequency-stabilizing optical system 300. The voltage follower is built using the first high-speed operational amplifier OPA1, and the signal passing through the filter module is output to the positive end of the first high-speed operational amplifier OPA1, and the inverting end of the first high-speed operational amplifier OPA1 is connected to the output end to realize the voltage following function and increase the driving capability of the analog input signal. The single-ended to differential module uses the second high-speed operational amplifier OPA2. This second high-speed operational amplifier OPA2 uses a high-speed differential operational amplifier to convert the single-ended output signal of the voltage follower module into a differential signal, and increase the DC bias of the high-speed analog-to-digital converter output through the VCM pin, so that the input single-ended analog signal is finally converted into a differential signal that meets the acquisition range of the high-speed analog-to-digital converter. When selecting the high-speed differential operational amplifier, a high gain-bandwidth product should be selected to ensure that the single-ended to differential module has a large amplification factor and a high bandwidth; the amplification factor can be controlled by adjusting the resistance ratio of resistors R5, R6, R7, and R8.

[0068] The digital signal processing module 4 uses the FPGA chip in the system on chip 100, and the demodulated sinusoidal signal is mixed with the reflected signal of the FP cavity in the frequency stabilization optical system 300 after phase matching, and the mixed signal is passed through a low-pass filter to obtain a PDH error signal for frequency stabilization; wherein, the digital signal processing module 4 includes a phase matching module, a mixing module and a low-pass filtering module.

[0069] The phase matching module is used to obtain the phase difference between the reflected signal of the FP cavity in the frequency stabilization optical system 300 and the demodulated sine signal generated by the modulation and demodulation sine signal generating module of the signal generating module 2. The demodulated sine signal generated by the signal generating module 2 is increased by the phase difference to obtain a demodulated sine signal that is phase-aligned with the reflected signal in the frequency stabilization. The method for calculating the phase difference is based on IQ demodulation. The specific implementation method is to multiply the reflected signal of the FP cavity in the frequency stabilization optical system 300 by the IQ demodulated sine signal generated by the signal generating module 2 and the IQ demodulated cosine signal generated by the signal generating module 2 in the FPGA chip to obtain two output signals. Finally, the two filtered signals are sent to the ARM processor to calculate the inverse tangent to obtain the phase difference between the reflected signal and the demodulated sine signal of the FP cavity in the frequency stabilization optical system 300, so as to achieve the phase alignment of the demodulated sine signal and the reflected signal of the FP cavity in the frequency stabilization optical system 300. The data interaction between the FPGA chip and the ARM processor is based on the AXI protocol.

[0070] The mixing module numerically multiplies the phase-aligned demodulated sinusoidal signal and the reflected signal of the FP cavity of the frequency stabilization optical system 300 collected by the data acquisition module 3 through a multiplier; the low-pass filtering module passes the output of the mixing module through the low-pass filtering module, and obtains the PDH error signal used for frequency stabilization after filtering.

[0071] The low-pass filter module uses an infinite impulse response filter (IIR filter for short). The IIR digital filter implemented in the FPGA chip has a lower order than the infinite impulse response filter (FIR filter for short). The IIR filter has a higher benefit in the frequency stabilization system. In terms of filtering performance, the IIR digital filter is better than the FIR filter. In terms of implementation order, the order used by the IIR filter is much smaller than that of the FIR filter, which can save more FPGA chip resources. In terms of flexibility, the designed IIR parameters can be saved in the EEPROM and the IIR parameters can be modified by reading the EEPROM through the IIC protocol to implement filters with different performances. However, due to the high order of FIR, it is difficult to adjust the filter performance by changing the parameters of the designed FIR filter, and it consumes a lot of FPGA chip resources. Figure 5As shown, the IIR digital filter design method in the present invention is: first call the filterDesigner tool in Matlab; then set the parameters, select the Butterworth function as the filter design function, set the sampling frequency to 125MHz, the passband cutoff frequency to 100KHz, the order to 2, and the stopband attenuation to 60dB, and obtain the zero-pole parameters of the IIR digital filter; the obtained zero-pole parameters are decimals, which are not convenient to process in the FPGA chip, so it is necessary to quantize the zero-pole parameters to obtain the integer zero-pole parameters that can be finally used in the FPGA chip; then according to the configured zero-pole parameters, use Verilog to program the FPGA chip to realize the IIR digital filter. The frequency stabilization circuit board is equipped with a 64KB EEPROM to save the pre-designed IIR filter parameters. The parameters pre-saved in the EEPROM are read through the IIC interface, and digital filters of different orders and different cutoff frequencies can be realized. This design method has greater flexibility than using FIR filters.

[0072] The reflected signal of the FP cavity collected by the data collection module 3 passes through the mixing module and the low-pass filtering module of the digital signal processing module 4, and is mixed and low-pass filtered to obtain a PDH error signal that can be used for frequency stabilization.

[0073] The signal input end of the peak-finding module 5 is electrically connected to the signal output end of the digital signal processing module 4, and the signal output end of the peak-finding module 5 is electrically connected to the signal input end of the PID module 6. The peak-finding module 5 is implemented in the ARM processor of the on-chip system 100, and is used to transmit the PDH error signal for frequency stabilization obtained by the digital signal processing module 4 to the ARM processor of the on-chip system 100 through the AXI protocol for peak-finding algorithm operation to calculate the zero-crossing point of the PDH error signal; the peak-finding algorithm uses a threshold judgment method to find the peak point of the PDH error signal, then finds the position of the zero-crossing point of the PDH error signal, and records the magnitude of the sawtooth wave signal voltage value at the zero-crossing point; the peak-finding algorithm uses a threshold judgment method, specifically setting upper and lower thresholds, when it is detected that the PDH error signal value exceeds the threshold, it can be considered to be close to the peak point of the PDH error signal, and the zero-crossing point of the PDH error signal is found at this time; when the zero-crossing point is detected, the voltage value of the frequency sweep sawtooth wave signal at this moment is recorded, and the PDH error signal is connected to the PID module 6.

[0074] The PID module 6 is based on the ARM processor of the system on chip 100, and is used to perform incremental digital PID algorithm operation on the PDH error signal to obtain the PZT feedback control signal of the laser and the temperature actuator feedback control signal, and its signal output end is electrically connected to another signal input end of the data output module 7. The PID module 6 is implemented in the ARM processor of the system on chip 100; the PID module 6 includes a first-level PID and a second-level PID; after the PID module 6 performs the first-level PID operation, the first-level PID operation result and the sawtooth wave voltage value at the zero-crossing point of the PDH error signal are added to obtain the PZT feedback control signal, and after obtaining the PZT feedback control signal, the PZT feedback control signal is switched to switch the frequency sweeping sawtooth wave signal applied to the PZT actuator of the laser to the PZT feedback control signal, so as to realize rapid modulation of the laser frequency. The output of the first-level PID operation is connected to the second-level PID, and the calculation result obtained is output to the temperature actuator of the laser, and the laser frequency is slowly modulated to achieve long-term stability of the laser frequency. The two-level PID parameters are adjusted in real time on the host computer 20010 through the data communication module 9 to achieve the best control effect. The PID module 6 is implemented in the ARM processor of the system on chip 100, and double-precision floating-point numbers are used to adjust the parameters of the two-level PID. When the peak-seeking module 5 detects the moment of the zero-crossing point of the PDH error signal, it switches to the PID control mode to obtain the PZT feedback control signal and the temperature actuator feedback control signal, wherein the PZT feedback control signal is the sum of the first-level PID calculation result and the sawtooth wave voltage value at the zero-crossing point of the PDH error signal, and the temperature actuator feedback control signal of the laser is the second-level PID calculation result. The PID module 6 uses double-precision floating-point numbers in the ARM processor for parameter adjustment, which can achieve more accurate calculation results compared to FPGA chips. The PID module 6 obtains the two-stage PID calculation result, rounds it, and sends it to the FPGA chip through the AXI protocol. The FPGA chip controls the data output module 7 to output data.

[0075] The signal output end of the data output module 7 is electrically connected to the signal input end of the frequency stabilizing optical system 300; the data output module 7 converts the digital signal into an analog signal through a high-speed digital-to-analog converter, and outputs a modulated sine signal, a swept sawtooth wave signal and a feedback control signal; the modulated sine signal is output to the EOM to modulate the laser frequency, the swept sawtooth wave signal is output to the PZT actuator to sweep the laser, and the feedback control signal is output to the PZT actuator and the temperature actuator of the laser to feedback control the laser frequency. The data output module 7 includes a high-speed digital-to-analog converter, a current-to-voltage module, a differential-to-single-ended module and a voltage amplifier module; the high-speed digital-to-analog converter adopts a 16-bit resolution, 125M sampling rate, dual-channel high-speed digital-to-analog conversion chip, and the reference voltage uses an internal 1.0V reference voltage; the current-to-voltage module outputs a differential current, using two independent high-precision thin-film resistors with a resistance of 50Ω, one end of which is connected to the differential output end of the high-speed digital-to-analog converter, and the other end is connected to the ground; the two differential output pins of the high-speed digital-to-analog converter are each connected to a 50Ω high-precision resistor to the ground, so as to realize the conversion of the differential current output signal of the high-speed digital-to-analog converter into a differential voltage signal, the current output signal range of the high-speed digital-to-analog converter is ±20mA, and is converted into a ±1V voltage signal through a 50Ω high-precision resistor grounded; the differential-to-single-ended module uses a third high-speed operational amplifier to convert the differential voltage signal into a single-ended voltage signal; the voltage amplifier module uses a third high-speed operational amplifier to amplify the single-ended voltage signal generated by the differential-to-single-ended module, and the output voltage range is positive and negative 5V. The data output module 7 uses three high-speed digital-to-analog converters, each with two outputs, for a total of six outputs.

[0076] One end of the data cache module 8 is bidirectionally electrically connected to the system on chip 100, and the other end is bidirectionally electrically connected to the data communication module 9. Among them, the data cache module 8 uses four DDR3 chips, which together constitute the 8Gb cache space of the system on chip 100; two DDR3 chips are mounted on the FPGA chip side of the system on chip 100, and two are mounted on the ARM processor side of the system on chip 100, real-time cache reflection signals, error signals, feedback control signals, etc. Theoretically, the communication rate between the DDR3 chip and the FPGA chip is up to 1600Mb per second, and the storage capacity can meet the cache of various important signals in the frequency stabilization process. When allocating pins to the two DDR3 chips mounted on the FPGA chip side, HP BANK needs to be selected. Each of the four groups of data signal lines corresponds to a group of pins of the FPGA chip. The DQS differential signal line cannot be changed within the group. The remaining data signal lines can be changed at will for the convenience of PCB routing. The DDR3 chip mounted on the ARM processor side can be docked according to the special pins reserved by the system on chip 100. When drawing the PCB, the two DDR3 chips on the FPGA chip side and the ARM processor side both use the FLY-BY architecture, with data lines in the same group and layer, controlling the single-ended signal impedance to 50Ω and the differential signal impedance to 100 ohms to achieve impedance matching.

[0077] The data communication module 9 is also bidirectionally electrically connected to the host computer 200; wherein, the data communication module 9 uses the USB3.0 chip to read the data in the data cache module 8 in real time and transmit it to the host computer 200 for display, and adjusts the parameters in the PID module 6 in real time and sends control commands to the on-chip system 100. During the frequency stabilization process, the USB3.0 chip reads the signal data cached in the DDR3 chip of the data cache module 8, sends it to the host computer 200 for display in real time through the USB interface, and receives the control command from the host computer 200, which can adjust the parameters in the PID module 6 in real time, adjust the frequency control word of the signal generator, and generate a modulation signal and a frequency sweep signal of any frequency. The data communication module 9 includes a data reading module, a data sending module and a data receiving module; the data reading module is used to read the important signal cache data in the data cache module 8 in real time; the data sending module is used to send the read cache data to the host computer 200 through the USB interface in real time; the data receiving module is used to receive instructions from the host computer 200 in real time, and adjust the frequency and amplitude of the signal generated in the signal sending module 2, adjust the IIR filter parameters in the digital signal processing module 4, adjust the threshold size in the peak search module 5, and adjust the PID parameters in the PID module 6 in real time.

[0078] The present invention uses a system on chip as the control core. The FPGA chip is responsible for data acquisition, digital signal processing, and data output. The ARM processor is responsible for the peak-finding algorithm and the PID control algorithm. The two work together to achieve the purpose of stabilizing the output optical frequency of the laser. Compared with the existing implementation scheme, the use of the system on chip has stronger computing power, smaller circuit size, and stronger system anti-interference ability.

[0079] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A fully digital laser frequency stabilization system based on a system on a chip, characterized by: The frequency stabilization system comprises a board-level power supply module (1), a signal generation module (2), a data acquisition module (3), a digital signal processing module (4), a peak search module (5), a PID module (6), a data output module (7), a data cache module (8), a data communication module (9), a system on chip (100) and a host computer (200); The main control chip of the system on chip (100) comprises an FPGA chip and an ARM processor; the ARM processor of the system on chip is responsible for the PID control algorithm and the inverse tangent calculation; The board-level power supply module (1) uses a power supply chip to generate various voltage values ​​required by various circuit modules in the frequency stabilization system, and realizes sequential power-on of the system on chip (100); The signal generating module (2) uses the DDS ip core in the FPGA chip of the system on chip (100) to generate two sinusoidal signals for modulation and demodulation, a sinusoidal and cosine signal for IQ demodulation, and a sawtooth wave signal for frequency sweeping; the modulated sinusoidal signal is output to the EOM to modulate the laser frequency, the demodulated sinusoidal signal is used for frequency mixing of the digital signal processing module (4), the IQ demodulated sinusoidal and cosine signals are used for phase matching in the digital signal processing module (4), and the sawtooth wave signal is output to the PZT actuator of the laser to sweep the laser frequency; The data acquisition module (3) uses a high-speed analog-to-digital converter, is connected to the FPGA chip side of the system on chip (100), and is used to collect the reflection signal of the FP cavity in the frequency stabilization optical system (300) into the system on chip (100); The digital signal processing module (4) uses the FPGA chip of the system on chip (100) to demodulate and low-pass filter the reflection signal of the FP cavity in the frequency stabilization optical system (300) to obtain a PDH error signal for frequency stabilization; The digital signal processing module (4) comprises a phase matching module, a frequency mixing module and a low-pass filtering module; The phase matching module is used to obtain the phase difference between the reflected signal of the FP cavity in the frequency stabilization optical system (300) and the demodulated sinusoidal signal generated by the modulation and demodulation sinusoidal signal generation module, and the demodulated sinusoidal signal generated by the signal generation module (2) is added with the phase difference to obtain a demodulated sinusoidal signal that is phase-aligned with the reflected signal in the frequency stabilization. The calculation method of the phase difference is based on IQ demodulation, which is to multiply the reflected signal of the FP cavity in the frequency stabilization optical system (300) by the IQ demodulated sinusoidal signal generated by the signal generation module (2) and the signal generation module (2) in numerical value. The IQ demodulated cosine signal generated by the signal generation module (2) is used to obtain two output signals, and the two output signals are passed through two low-pass filters to obtain two filtered signals, and finally the two filtered signals are sent to the ARM processor of the on-chip system (100) to calculate the inverse tangent to obtain the phase difference between the reflected signal of the FP cavity in the frequency-stabilizing optical system (300) and the demodulated sine signal, so as to achieve phase alignment between the demodulated sine signal and the reflected signal of the FP cavity in the frequency-stabilizing optical system (300); and the data interaction between the FPGA chip and the ARM processor is based on the AXI protocol; The frequency mixing module numerically multiplies the demodulated sinusoidal signal and the reflected signal of the FP cavity of the frequency stabilizing optical system (300) collected by the data collection module (3) through a multiplier; The low-pass filtering module is used to pass the output of the mixing module through a digital low-pass filter to obtain a PDH error signal for frequency stabilization after filtering; The peak-finding module (5) is used to find the zero-crossing point of the PDH error signal; The PID module (6) is based on the ARM processor of the system on chip (100), and is used to perform an incremental digital PID algorithm operation on the PDH error signal to obtain a PZT feedback control signal of the laser and a temperature actuator feedback control signal; The data output module (7) uses a high-speed digital-to-analog converter to convert the digital signal into an analog voltage signal; the analog voltage signal includes a modulated sine signal, a swept frequency sawtooth wave signal and a feedback control signal; The modulated sine signal is output to the EOM to modulate the laser frequency; the swept sawtooth signal is output to the PZT actuator of the laser to sweep the frequency; the feedback control signal is output to the PZT actuator and temperature actuator of the laser; The data cache module (8) uses a DDR3 chip to form a cache space of the system on chip (100) and is used to cache signals in a frequency stabilization process in real time; The data communication module (9) uses a USB3.0 chip to read the signal cached in the DDR3 chip in real time and send it to the host computer (200) for display, and to adjust the parameters in the PID module (6) in real time and send control commands to the on-chip system (100).

2. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 1, characterized in that: The board-level power supply module (1) is electrically connected to the system on chip (100), and comprises a system on chip power supply module, a high-speed digital-to-analog converter power supply module, a high-speed analog-to-digital converter power supply module, an operational amplifier power supply module and a data communication power supply module; The system-on-chip power supply module supplies power to the system-on-chip (100) in a sequential power-on manner; The high-speed digital-to-analog converter power module, the high-speed analog-to-digital converter power module and the operational amplifier power module all select LDO chips to generate the voltages required by the corresponding devices; The data communication power supply module selects a DC-DC chip that outputs the DC-DC chip that meets the device requirements to generate the voltage required by the corresponding device.

3. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 2, characterized in that: The signal input end of the data acquisition module (3) is electrically connected to the signal output end of the external frequency stabilization optical system (300), the signal generation module (2) is electrically connected to one of the signal input ends of the digital signal processing module (4) via one of the signal output ends, and the signal output end of the data acquisition module (3) is electrically connected to another signal input end of the digital signal processing module (4); The data acquisition module (3) comprises a high-speed analog-to-digital converter and a front-end analog signal link; the high-speed analog-to-digital converter is powered by the high-speed analog-to-digital converter power module, and adopts a high-speed analog-to-digital conversion chip with 16-bit resolution, 125M sampling rate and dual channels; the front-end analog signal link is used to condition the analog signal output by the frequency stabilization optical system (300) so as to convert it into a differential signal and conform to the acquisition range of the high-speed analog-to-digital conversion chip.

4. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 3, characterized in that: The front-end analog signal link includes an AC coupling module, an impedance matching network, a filtering module, a voltage follower module and a single-ended to differential module; The AC coupling module uses a capacitor C1 with a capacitance of 100 nF to filter out the DC component of the reflected signal of the FP cavity in the frequency stabilization optical system (300); The impedance matching network uses four high-precision thin-film resistors R1-R4 to build a π-type resistor network, which can achieve 50Ω impedance matching and can determine whether to attenuate the signal according to the size of the reflected signal of the FP cavity in the frequency-stabilizing optical system (300); The filtering module uses a passive low-pass filter with a cut-off frequency of 30 MHz to filter out high-frequency noise in the reflection signal of the FP cavity in the frequency stabilizing optical system (300), so as to improve the signal-to-noise ratio of the reflection signal of the FP cavity in the frequency stabilizing optical system (300); The voltage follower module is powered by the operational amplifier power supply module and is constructed using the first high-speed operational amplifier OPA1. By outputting the signal passing through the filter module to the positive end of the first high-speed operational amplifier OPA1 and connecting the negative end of the first high-speed operational amplifier OPA1 to the output end, a voltage follower function is realized to increase the driving capability of the analog input signal. The single-ended to differential module is powered by the operational amplifier power supply module and is constructed using a second high-speed operational amplifier OPA2 to convert the single-ended output signal of the voltage follower module into a differential signal and increase the DC bias output by the high-speed analog-to-digital converter so that the input single-ended analog signal is ultimately converted into a differential signal that conforms to the acquisition range of the high-speed analog-to-digital converter.

5. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 1, characterized in that: The signal generating module (2) is electrically connected to one of the signal input terminals of the digital signal processing module (4) via one of the signal output terminals, and is electrically connected to one of the signal input terminals of the data output module (7) via another signal output terminal; The signal generating module (2) comprises a modulation and demodulation sine signal generating module, an IQ demodulation sine and cosine signal generating module and a frequency sweeping sawtooth wave signal generating module; the signal generating modules all use a DDS signal generator ip core to generate the required signal.

6. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 1, characterized in that: The low-pass filtering module uses a limited impulse response filter.

7. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 1, characterized in that: The signal input end of the peak-finding module (5) is electrically connected to the signal output end of the digital signal processing module (4), and the signal output end of the peak-finding module (5) is electrically connected to the signal input end of the PID module (6); The peak-finding module (5) transmits the PDH error signal for frequency stabilization obtained by the digital signal processing module (4) to the ARM processor of the on-chip system (100) via the AXI protocol for peak-finding algorithm operation to calculate the zero-crossing point of the PDH error signal.

8. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 7, characterized in that: The peak finding algorithm uses a threshold value judgment method to find the peak point of the PDH error signal, then finds the position of the zero-crossing point of the PDH error signal, and records the magnitude of the sawtooth wave signal voltage value at the zero-crossing point.

9. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 1, characterized in that: The signal output end of the PID module (6) is electrically connected to the signal input end of the data output module (7); the PID module (6) comprises a first-level PID and a second-level PID, and after inputting the PDH error signal into the first-level PID operation, adds the first-level PID operation result and the sawtooth wave voltage value at the zero-crossing point of the PDH error signal to obtain a PZT feedback control signal, and after obtaining the PZT feedback control signal, switches to a laser frequency stabilization mode, switches the frequency sweeping sawtooth wave signal applied to the PZT actuator of the laser to the PZT feedback control signal, and realizes rapid modulation of the laser frequency; at the same time, the first-level PID operation result is sent to the second-level PID operation, and the second-level PID operation result is output to the temperature actuator of the laser, so as to perform slow modulation on the laser frequency.

10. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 9, characterized in that: The feedback control signal size of the PZT actuator of the laser is the sum of the first-level PID calculation result of the PID module (6) and the voltage value of the sawtooth wave signal at the zero-crossing point of the PDH error signal; the feedback control signal size of the temperature actuator of the laser is the second-level PID calculation result of the PID module (6).

11. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 2, characterized in that: The signal output end of the data output module (7) is electrically connected to the signal input end of the frequency stabilization optical system (300); the data output module (7) comprises the high-speed digital-to-analog converter, the current-to-voltage module, the differential-to-single-ended module and the voltage amplification module; The high-speed digital-to-analog converter is powered by the high-speed digital-to-analog converter power module, which adopts a high-speed digital-to-analog conversion chip with 16-bit resolution, 125M sampling rate and dual channels; The current-to-voltage module uses two independent high-precision thin-film resistors with a resistance of 50Ω, one end of which is connected to the differential output end of the high-speed digital-to-analog converter and the other end is grounded; The two differential output pins of the high-speed digital-to-analog converter are each connected to a 50Ω high-precision resistor to the ground, so as to convert the current output signal of the high-speed digital-to-analog converter into a voltage signal. The current output signal of the high-speed digital-to-analog converter is ±20mA, which is converted into a ±1V voltage signal through a 50Ω high-precision resistor to the ground; The differential-to-single-ended module uses a high-speed operational amplifier and is powered by the operational amplifier power module, and is used to convert the differential voltage signal into a single-ended signal; The voltage amplification module uses a high-speed operational amplifier and is powered by the operational amplifier power supply module, and is used to amplify the single-ended signal generated by the differential to single-ended module, and amplify the ±1V voltage signal to ±3V.

12. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 2, characterized in that: The data communication module (9) is also bidirectionally electrically connected to the host computer (200); the data communication module (9) is powered by the data communication power supply module, and comprises a data reading module, a data sending module and a data receiving module; The data reading module is used to read the important signal buffer data in the data buffer module in real time; The data sending module is used for sending the read cache data to the host computer (200) in real time via a USB interface; The data receiving module is used to receive instructions from the host computer (200) in real time, and to adjust the frequency and amplitude of the signal generated in the signal generating module (2), the threshold value in the peak finding module (5), and the PID parameters in the PID module (6) in real time.

13. The all-digital laser frequency stabilization system based on a system on a chip as claimed in claim 1, characterized in that: One end of the data cache module (8) is bidirectionally electrically connected to the system on chip (100), and the other end is bidirectionally electrically connected to the data communication module (9); The data cache module (8) uses four DDR3 chips, and the FPGA chip side and the ARM processor side of the system on chip (100) each mount two DDR3 chips, each DDR3 chip has a storage capacity of 2Gb, forming a total of 8Gb of data cache space.

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