A large full-well TDI-CMOS pixel structure

Abstract

The invention relates to a large full-well TDI-CMOS pixel structure, belonging to the field of CMOS image sensors; the structure comprises 6 CCD electrodes, 4 column isolations and 3 CCD channels; wherein the 4 column isolations and the 3 CCD channels are all rectangular parallelepiped structures; the 4 column isolations and the 3 CCD channels are arranged adjacently and staggered to form a rectangular parallelepiped base; the 6 CCD electrodes are evenly arranged at equal intervals on the upper surface of the rectangular parallelepiped base, and the axial direction of the CCD electrodes is perpendicular to the axial direction of the column isolations and the CCD channels; the invention is suitable for a CCD-CMOS fusion type TDI image sensor, and in particular can increase the full-well capacity performance without affecting the voltage swing, the charge transfer efficiency and the anti-dispersion capability.

Description

Technical Field

[0001] The invention belongs to the field of CMOS image sensors and relates to a large full-well TDI-CMOS pixel structure. Background Art

[0002] Time Delay Integration (TDI) CMOS image sensors can be divided into digital accumulation TDI, analog accumulation TDI, CCD-CMOS fusion TDI (CCD, Charge Coupled Device) or multiple architecture fusions according to the type of pixels. Among them, CCD-CMOS fusion TDI takes into account the advantages of traditional CCD image sensor signal noise-free accumulation and traditional CMOS image sensor high integration, and has unparalleled line frequency performance, so it is the TDI CMOS image sensor with the most performance advantages.

[0003] For CCD-CMOS fusion TDI image sensors, their full well capacity is naturally limited by gate oxide thickness, CCD electrode voltage swing, and multi-phase control architecture. The upper limit of full well capacity per unit area is gate oxide capacitance. However, in order to improve charge transfer efficiency and increase the number of accumulation levels, its pixel structure usually adopts a buried trench design. Affected by design factors such as anti-dispersion capability and buried trench depth, its full well capacity is at least 50% lower than that of surface channel devices. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and propose a large full-well TDI-CMOS pixel structure, which is suitable for CCD-CMOS fusion TDI image sensors, and in particular can increase the full-well capacity performance without affecting the voltage swing, charge transfer efficiency and anti-dispersion ability.

[0005] The solution of the present invention is:

[0006] A large full-well TDI-CMOS pixel structure includes six CCD electrodes, four column isolations and three CCD channels;

[0007] Among them, the four inter-column isolations and the three CCD channels are all rectangular structures; the four inter-column isolations and the three CCD channels are arranged adjacent to each other in an alternating manner to form a rectangular base; the six CCD electrodes are evenly arranged at equal intervals on the upper surface of the rectangular base, and the axial direction of the CCD electrodes is perpendicular to the axial direction of the inter-column isolations and the CCD channels.

[0008] In the above-mentioned large full-well TDI-CMOS pixel structure, the upper surface of the rectangular base is provided with layer; the lower surface of the 6 CCD electrodes and Layer contact.

[0009] In the above-mentioned large full-well TDI-CMOS pixel structure, the inter-column isolation is a single structure, using dielectric isolation or ion implantation isolation.

[0010] In the above-mentioned large full-well TDI-CMOS pixel structure, the CCD channel includes an n-type buried channel, substrate and 6 deep n-type ion implants;

[0011] in, The substrate is placed horizontally; the n-type buried channel is placed horizontally The top of the substrate; 6 deep n-type ion implants are vertically set on the n-type buried channel and The upper part of the deep n-type ion implantation is located in the n-type buried trench, and the lower part of the deep n-type ion implantation is located in the substrate. In the substrate.

[0012] In the above-mentioned large full-well TDI-CMOS pixel structure, the six deep n-type ion implantations correspond one to one to the positions of the six CCD electrodes, and each deep n-type ion implantation is located directly below the corresponding CCD electrode.

[0013] In the above-mentioned large full-well TDI-CMOS pixel structure, when the pixel structure is to improve the dark current, the CCD channel includes an n-type buried channel, substrate, 6 deep n-type ion implants and 7 p-type barrier implants;

[0014] in, The substrate is placed horizontally; the n-type buried channel is placed horizontally The top of the substrate; 6 deep n-type ion implants are vertically set on the n-type buried channel and The upper part of the deep n-type ion implantation is located in the n-type buried trench, and the lower part of the deep n-type ion implantation is located in the substrate. In the substrate, 7 p-type potential barriers are implanted and uniformly arranged at the inner top of the n-type buried trench.

[0015] In the above-mentioned large full-well TDI-CMOS pixel structure, the six deep n-type ion implantations correspond one-to-one to the positions of the six CCD electrodes, and each deep n-type ion implantation is located directly below the corresponding CCD electrode; one p-type barrier implantation is correspondingly arranged between two adjacent CCD electrodes, and the remaining two p-type barrier implantations are respectively located at the two top corners of the n-type buried trench.

[0016] In the above-mentioned large full-well TDI-CMOS pixel structure, the n-type buried trench is implanted by As or P ions; the energy range of the n-type buried trench is 50keV~150keV; the depth of the n-type buried trench is 0.3 ~1 .

[0017] In the above-mentioned large full-well TDI-CMOS pixel structure, the CCD electrode is made of polysilicon material; the CCD electrode is implanted with B, P or As ions; and the energy range of the CCD electrode is 3keV~20keV.

[0018] In the above-mentioned large full-well TDI-CMOS pixel structure, the p-type barrier implantation adopts B or Ion implantation: the energy range of p-type barrier implantation is 5keV~30keV; deep n-type ion implantation uses P ion implantation; the energy range of deep n-type ion implantation is 200keV~2MeV; the depth of deep n-type ion implantation is 1 ~5 ; The distance between two adjacent deep n-type ion implantations is 0.4 ~3 .

[0019] The beneficial effects of the present invention compared with the prior art are:

[0020] (1) The present invention proposes a large full-well TDI-CMOS pixel structure, which is suitable for CCD-CMOS fusion TDI image sensors, and can increase the full-well capacity performance without affecting the voltage swing, charge transfer efficiency, and anti-dispersion capability;

[0021] (2) The present invention provides a novel buried channel CCD structure, including a CCD electrode, an n-type buried channel, and additional distributed deep n-type ion implantation. There is a certain distance between each deep n-type ion implantation, which effectively enhances the charge full well capacity;

[0022] (3) The present invention adds deep n-type ion implantation and p-type barrier implantation, and effectively utilizes the space deep from the surface for storage and charge transfer under the spatial scale constraint of a fixed charge field. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A top view of the large full-well TDI-CMOS pixel structure of the present invention;

[0024] Figure 2 This is a front view of the large full-well TDI-CMOS pixel structure of the present invention;

[0025] Figure 3 It is a side view of the CCD channel of the present invention;

[0026] Figure 4 A side view of a CCD channel of a pixel structure for improving dark current of the present invention;

[0027] Figure 5Schematic diagram of the CCD potential distribution of the large full-well TDI-CMOS pixel structure of the present invention. DETAILED DESCRIPTION

[0028] The present invention will be further described below in conjunction with the embodiments.

[0029] The present invention provides a large full-well TDI-CMOS pixel structure, which is suitable for a CCD-CMOS fusion TDI image sensor, and can especially increase the full-well capacity performance without affecting the voltage swing, charge transfer efficiency and anti-dispersion capability.

[0030] Large full-well TDI-CMOS pixel structure, such as Figure 1 , Figure 2 As shown, it specifically includes 6 CCD electrodes 1, 4 inter-column isolations 2 and 3 CCD channels 3. Among them, the 4 inter-column isolations 2 and the 3 CCD channels 3 are all rectangular parallelepiped structures; the 4 inter-column isolations 2 and the 3 CCD channels 3 are arranged alternately and adjacently to form a rectangular parallelepiped base; the 6 CCD electrodes 1 are evenly arranged on the upper surface of the rectangular parallelepiped base at equal intervals, and the axial direction of the CCD electrode 1 is perpendicular to the axial direction of the inter-column isolation 2 and the CCD channel 3.

[0031] The upper surface of the rectangular base is provided with layer; the lower surface of the 6 CCD electrodes 1 and The inter-column isolation 2 is a single structure, using dielectric isolation or ion implantation isolation.

[0032] like Figure 3 As shown, the CCD channel 3 includes an n-type buried channel 31, Substrate 32 and 6 deep n-type ion implants 33. Among them, The substrate 32 is placed horizontally; the n-type buried trench 31 is placed horizontally The top of the substrate 32; 6 deep n-type ion implants 33 are vertically arranged on the n-type buried trench 31 and The upper part of the deep n-type ion implantation 33 is located in the n-type buried trench 31, and the lower part of the deep n-type ion implantation 33 is located in the substrate 32; In the substrate 32 , the six deep n-type ion implants 33 correspond to the six CCD electrodes 1 one by one, and each deep n-type ion implant 33 is located directly below the corresponding CCD electrode 1 .

[0033] like Figure 4 As shown in FIG. 1 , when the pixel structure is used to improve the dark current, the CCD channel 3 includes an n-type buried channel 31, Substrate 32, 6 deep n-type ion implants 33 and 7 p-type barrier implants 34. The substrate 32 is placed horizontally; the n-type buried trench 31 is placed horizontally The top of the substrate 32; 6 deep n-type ion implants 33 are vertically arranged on the n-type buried trench 31 and The upper part of the deep n-type ion implantation 33 is located in the n-type buried trench 31, and the lower part of the deep n-type ion implantation 33 is located in the substrate 32; In the substrate 32 , seven p-type barrier implants 34 are evenly arranged at the inner top of the n-type buried trench 31 .

[0034] The six deep n-type ion implantations 33 correspond one to one with the positions of the six CCD electrodes 1 , and each deep n-type ion implantation 33 is located directly below the corresponding CCD electrode 1 ; one p-type barrier implantation 34 is correspondingly arranged between two adjacent CCD electrodes 1 , and the remaining two p-type barrier implantations 34 are respectively located at the two top corners of the n-type buried trench 31 .

[0035] Figure 4 A cross-sectional view of a novel buried-channel CCD structure with p-type barrier injection between electrodes along the charge transfer direction is given. The structure includes CCD electrodes, n-type buried channel, p-type barrier injection, and additional distributed deep n-type ion injection. There is a certain distance space between each deep n-type ion injection.

[0036] In the present invention, the n-type buried trench 31 is implanted with As or P ions; the energy range of the n-type buried trench 31 is 50keV to 150keV; the depth of the n-type buried trench 31 is 0.3 ~1 The CCD electrode 1 is made of polysilicon material; the CCD electrode 1 is implanted with B, P or As ions; and the energy range of the CCD electrode 1 is 3keV to 20keV.

[0037] The p-type barrier implant 34 uses B or Ion implantation, the energy range of p-type barrier implantation 34 is 5keV~30keV; deep n-type ion implantation 33 uses P ion implantation; the energy range of deep n-type ion implantation 33 is 200keV~2MeV; the depth of deep n-type ion implantation 33 is 1 ~5 ; The distance between two adjacent deep n-type ion implantations 33 is 0.4 ~3 .

[0038] like Figure 5As shown in the figure, the moment when electrode 1 and electrode 4 are set to a low level and electrode 2, electrode 3, electrode 5 and electrode 6 are set to a high level is taken as an example. Along the C2-D2 tangent line in the n-type buried channel region, corresponding to the spatial position of the deep n-type ion implantation region, a smaller potential well is generated regardless of the high or low level, and the local depth of the potential well is much less than 0.5eV; along the E2-F2 tangent line in the substrate region, corresponding to the spatial position of the deep n-type ion implantation region, a larger potential well (>0.5eV) is generated when the electrode is at a high level. The deep n-type ion implantation does not significantly change the maximum depletion potential of the overall n-type region, but significantly increases the spatial scale range of the potential well in the overall n-type region, so it can effectively improve the full well capacity of the buried channel CCD structure.

[0039] The present invention proposes a large full-well TDI-CMOS pixel structure, which is suitable for a CCD-CMOS fusion TDI image sensor, and in particular can increase the full-well capacity performance without affecting the voltage swing, charge transfer efficiency and anti-dispersion capability.

[0040] The present invention proposes a large full-well TDI-CMOS pixel structure, which is suitable for a CCD-CMOS fusion TDI image sensor, and in particular can increase the full-well capacity performance without affecting the voltage swing, charge transfer efficiency and anti-dispersion capability.

[0041] The present invention provides a novel buried channel CCD structure, including a CCD electrode, an n-type buried channel, and additionally adds distributed deep n-type ion implantation, with a certain distance space between each deep n-type ion implantation, which effectively enhances the charge full well capacity;

[0042] The present invention adds deep n-type ion implantation and p-type barrier implantation, and effectively utilizes the space deeper than the surface for storage and charge transmission under the condition of the spatial scale constraint of the fixed charge field.

[0043] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A large full-well TDI-CMOS pixel structure, characterized in that: It includes 6 CCD electrodes (1), 4 column isolations (2) and 3 CCD channels (3); The four inter-column isolations (2) and the three CCD channels (3) are all rectangular parallelepiped structures; the four inter-column isolations (2) and the three CCD channels (3) are arranged in an alternating manner adjacent to each other to form a rectangular parallelepiped base; the six CCD electrodes (1) are evenly arranged at equal intervals on the upper surface of the rectangular parallelepiped base, and the axial direction of the CCD electrodes (1) is perpendicular to the axial direction of the inter-column isolations (2) and the CCD channels (3); The upper surface of the rectangular base is provided with layer; the lower surface of the 6 CCD electrodes (1) and Layer contact; The inter-column isolation (2) is a single structure, using dielectric isolation or ion implantation isolation; The CCD channel (3) comprises an n-type buried channel (31), substrate (32) and 6 deep n-type ion implants (33); in, The substrate (32) is placed horizontally; the n-type buried channel (31) is arranged horizontally The top of the substrate (32); 6 deep n-type ion implants (33) are vertically arranged between the n-type buried trench (31) and The upper part of the deep n-type ion implantation (33) is located in the n-type buried trench (31), and the lower part of the deep n-type ion implantation (33) is located in the substrate (32); in the substrate (32); The six deep n-type ion implantations (33) correspond one to one to the positions of the six CCD electrodes (1), and each deep n-type ion implantation (33) is located directly below the corresponding CCD electrode (1).

2. A large full-well TDI-CMOS pixel structure according to claim 1, characterized in that: When the pixel structure is used to improve dark current, the CCD channel (3) further includes 7 p-type barrier implants (34); Seven p-type potential barrier implants (34) are evenly arranged on the inner top of the n-type buried trench (31).

3. A large full-well TDI-CMOS pixel structure according to claim 2, characterized in that: The six deep n-type ion implants (33) correspond to the positions of the six CCD electrodes (1) one by one, and each deep n-type ion implant (33) is located directly below the corresponding CCD electrode (1); one p-type barrier implant (34) is correspondingly arranged between two adjacent CCD electrodes (1), and the remaining two p-type barrier implants (34) are respectively located at two vertex corners of the n-type buried trench (31).

4. The large full-well TDI-CMOS pixel structure according to claim 3, characterized in that: The n-type buried trench (31) is implanted with As or P ions; the energy range of the n-type buried trench (31) is 50keV to 150keV; the depth of the n-type buried trench (31) is 0.3 ~1 .

5. The large full-well TDI-CMOS pixel structure according to claim 4, characterized in that: The CCD electrode (1) is made of polysilicon material; the CCD electrode (1) is implanted with B, P or As ions; and the energy range of the CCD electrode (1) is 3keV to 20keV.

6. The large full-well TDI-CMOS pixel structure according to claim 5, characterized in that: The p-type barrier implant (34) is provided by B or Ion implantation, the energy range of p-type barrier implantation (34) is 5keV~30keV; deep n-type ion implantation (33) uses P ion implantation; The energy range of deep n-type ion implantation (33) is 200keV~2MeV; the depth of deep n-type ion implantation (33) is 1 ~5 ; The distance between two adjacent deep n-type ion implants (33) is 0.4 ~3 .

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