2.5D micro-bump packaging structure and method for preparing the 2.5D micro-bump packaging structure

Abstract

The present application relates to a 2.5D micro-bump packaging structure and a method for preparing the 2.5D micro-bump packaging structure, and relates to the field of semiconductor technology. The 2.5D micro-bump packaging structure comprises a substrate, a first dielectric layer, a first reflective layer, a second dielectric layer, a second reflective layer, a first wiring assembly layer, a second wiring assembly layer and a conductive bump. The first dielectric layer, the first reflective layer, the second dielectric layer and the second reflective layer are sequentially arranged on the substrate, and a first wiring assembly layer and a second wiring assembly layer are prepared after a notch is formed by grooving. Finally, a conductive bump is formed. Since the first reflective layer and the second reflective layer are both made of shading materials, light can be blocked. During the grooving process, the reflection and diffraction of light in the dielectric layer can be slowed down, thereby improving the opening accuracy. At the same time, the problem of pits on the surface of the dielectric layer due to reflection or diffraction is avoided, thereby improving the bonding strength of subsequent wiring layers.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a 2.5D micro-bump packaging structure and a method for preparing the 2.5D micro-bump packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, the photolithography process in the wafer manufacturing process is used to form line width openings on the dielectric layer. As the aspect ratio of the line width becomes smaller and smaller (for example: line width / depth 2um / 2um-20um / 5um, etc.), the required photolithography machine has become more and more capable, evolving from I-line high-pressure mercury lamp (wavelength 356nm) to DUV deep ultraviolet lamp (DeepUltra Violet), including: krf laser (wavelength 248nm), Arf laser (wavelength 193nm), F2 laser (wavelength 157nm), to meet the requirements of opening accuracy and size reduction.

[0003] However, during the photolithography process, the light propagates in the medium and is subject to reflection and diffraction, resulting in low opening accuracy. At the same time, the medium layer is affected by the reflection wavelength or diffraction wavelength, causing pits on the surface of the medium layer, leading to problems such as poor bonding of subsequent wiring layers. Summary of the invention

[0004] The purpose of this application is to provide a 2.5D micro-bump packaging structure and a method for preparing a 2.5D micro-bump packaging structure, which can slow down the reflection and diffraction of light in the dielectric layer, improve the opening accuracy, and avoid pits on the surface of the dielectric layer, thereby improving the bonding strength of subsequent wiring layers.

[0005] In order to achieve the above object, the present invention adopts the following scheme:

[0006] In a first aspect, the present invention provides a 2.5D micro-bump packaging structure, comprising:

[0007] A substrate, wherein a welding pad is disposed on one side surface of the substrate;

[0008] A first dielectric layer, the first dielectric layer is disposed on a surface of a side of the substrate where the solder pad is disposed;

[0009] a first reflective layer, wherein the first reflective layer is disposed on the first dielectric layer;

[0010] a second dielectric layer, the second dielectric layer being disposed on the first reflective layer;

[0011] a second reflective layer, wherein the second reflective layer is disposed on the second dielectric layer;

[0012] a first wiring assembly layer, the first wiring assembly layer being disposed on the second reflective layer and electrically connected to the pad;

[0013] a second wiring combination layer, the second wiring combination layer being disposed on the first wiring combination layer and electrically connected to the first wiring combination layer;

[0014] A conductive bump, the conductive bump being disposed on the second wiring assembly layer and electrically connected to the second wiring assembly layer;

[0015] The first reflective layer and the second reflective layer are both made of light-shielding materials, and the first wiring assembly layer sequentially passes through the second reflective layer, the second dielectric layer, the first reflective layer and the first dielectric layer, and is in electrical contact with the pad.

[0016] In an optional embodiment, a first opening and a second opening having the same opening width are provided on the second reflective layer, the first opening corresponds to the second wiring combination layer and penetrates the second reflective layer so that the second dielectric layer is exposed at the first opening, the first wiring combination layer is filled to the first opening, the second opening corresponds to the soldering pad and penetrates the second reflective layer and the second dielectric layer so that the first reflective layer is exposed to the second opening, a third opening corresponding to the second opening and connected to the third opening is further provided on the first reflective layer in the second opening, the opening width of the third opening is smaller than the opening width of the second opening, the third opening penetrates the first reflective layer and the first dielectric layer so that the soldering pad is exposed to the third opening, and the first wiring combination layer is filled to the second opening and the third opening.

[0017] In an optional embodiment, the first wiring combination layer includes a buffer dielectric layer, a first circuit layer and a first dielectric layer, the buffer dielectric layer is arranged on the second reflective layer and fills the first opening, and a fourth opening having an opening width the same as that of the second opening is arranged on the buffer dielectric layer, and the fourth opening is correspondingly connected to the second opening, the first circuit layer is arranged on the buffer dielectric layer, and extends to the fourth opening, the second opening and the third opening in sequence, and the first circuit layer is electrically contacted with the pad, and the first dielectric layer is arranged on the buffer dielectric layer and covers the first circuit layer.

[0018] In an optional embodiment, the first wiring combination layer includes a first circuit layer and a first dielectric layer, the first circuit layer is arranged on the second reflective layer and fills the first opening, and the first circuit layer extends to the second opening and the third opening in sequence and is in electrical contact with the welding, and the first dielectric layer is arranged on the second reflective layer and covers the first circuit layer.

[0019] In an optional embodiment, the second wiring combination layer includes a second dielectric layer, a second line layer and a third dielectric layer, the second dielectric layer is arranged on the first dielectric layer, the second line layer is arranged on the second dielectric layer, the third dielectric layer is arranged on the second dielectric layer and covers the second line layer, the second line layer is electrically connected to the first line layer, and the conductive bump is embedded in the second dielectric layer and electrically contacted with the second line layer.

[0020] In an optional embodiment, a third reflective layer is further disposed between the second dielectric layer and the first dielectric layer, and the third reflective layer is made of a light-shielding material.

[0021] In an optional embodiment, a fifth opening having an opening width the same as that of the first opening is provided on the second dielectric layer, the fifth opening penetrates the second dielectric layer so that the third reflective layer is exposed at the fifth opening, a sixth opening is provided on the third reflective layer within the fifth opening, the sixth opening penetrates the third reflective layer and the first dielectric layer and corresponds to the first circuit layer so that the first circuit layer is exposed at the sixth opening, and an opening width of the sixth opening is smaller than an opening width of the fifth opening, and the second circuit layer extends to the fifth opening and the sixth opening in sequence and is in electrical contact with the first circuit layer.

[0022] In an optional implementation, the first reflective layer is provided with a bump, and the bump sequentially passes through the second dielectric layer and the second reflective layer and is connected to the first wiring assembly layer.

[0023] In an optional embodiment, a heat dissipation protrusion is further provided on the substrate, and the heat dissipation protrusion passes through the first dielectric layer, the first reflective layer, the second dielectric layer, the second reflective layer, the first wiring combination layer and the second wiring combination layer in sequence, wherein an end of the heat dissipation protrusion away from the substrate is flush with an end of the second wiring combination layer away from the substrate.

[0024] In an optional embodiment, the 2.5D micro-bump packaging structure also includes a packaging chip and a plastic packaging layer, the packaging chip is arranged on the side of the second wiring assembly layer away from the substrate and is welded to the conductive bump, and the plastic packaging layer is arranged on the second wiring assembly layer and covers the outside of the packaging chip.

[0025] In an optional embodiment, the substrate includes a metal layer and a third dielectric layer, the metal layer is connected to the solder pad, the third dielectric layer is coated outside the metal layer, and solder balls are also arranged on the third dielectric layer, and the solder balls are connected to the metal layer.

[0026] In a second aspect, the present invention provides a method for preparing a 2.5D micro-bump packaging structure, which is used to prepare the 2.5D micro-bump packaging structure as described in the above embodiment, and the preparation method comprises:

[0027] Providing a substrate, wherein a welding pad is disposed on one side surface of the substrate;

[0028] Forming a first dielectric layer covering the pad on one side surface of the substrate;

[0029] forming a first reflective layer on the first dielectric layer;

[0030] forming a second dielectric layer on the first reflective layer;

[0031] forming a second reflective layer on the second dielectric layer;

[0032] cutting grooves in the second reflective layer;

[0033] forming a first wiring assembly layer electrically connected to the pad on the second reflective layer;

[0034] forming a second wiring combination layer on the first wiring combination layer and electrically connected to the first wiring combination layer;

[0035] forming a conductive bump electrically connected to the second wiring combination layer on the second wiring combination layer;

[0036] The first reflective layer and the second reflective layer are both made of light-shielding materials, and the first wiring assembly layer sequentially passes through the second reflective layer, the second dielectric layer, the first reflective layer and the first dielectric layer, and is in electrical contact with the pad.

[0037] In an optional embodiment, the step of forming grooves on the second reflective layer includes:

[0038] forming a first opening on the second reflective layer at a position corresponding to the second wiring assembly layer, wherein the first opening penetrates the second reflective layer so that the second dielectric layer is exposed at the first opening;

[0039] A second opening having the same opening width as the first opening is formed at a position corresponding to the pad on the second reflective layer, wherein the second opening penetrates the second reflective layer and the second dielectric layer so that the first reflective layer is exposed at the second opening;

[0040] A third opening is formed on the first reflective layer in the second opening and is connected to the second opening. The third opening penetrates the first reflective layer and the first dielectric layer, so that the pad is exposed at the third opening.

[0041] In an optional embodiment, after the step of forming a first wiring assembly layer electrically connected to the pad on the second reflective layer, the preparation method further comprises:

[0042] A third reflective layer is formed on the first wiring combination layer.

[0043] The 2.5D micro-bump packaging structure and the preparation method thereof provided by the embodiment of the present invention are as follows: a first dielectric layer, a first reflective layer, a second dielectric layer and a second reflective layer are sequentially arranged on a substrate; a first wiring assembly layer and a second wiring assembly layer are prepared after a notch is formed by grooving; and finally a conductive bump is formed; since the first reflective layer and the second reflective layer both adopt light-shielding materials, and the first wiring assembly layer sequentially passes through the second reflective layer, the second dielectric layer, the first reflective layer and the first dielectric layer and is in electrical contact with the pad, during the grooving process of the first dielectric layer and the second dielectric layer, since the first reflective layer and the second reflective layer both adopt light-shielding materials, light can be shielded; during the grooving process, the reflection and diffraction of light in the dielectric layer can be slowed down, the opening accuracy can be improved, and at the same time, the problem of pits on the surface of the dielectric layer due to reflection or diffraction can be avoided, thereby improving the bonding strength of subsequent wiring layers.

[0044] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A schematic structural diagram of a 2.5D micro-bump packaging structure provided in the first embodiment of the present application;

[0047] Figure 2 for Figure 1 A local enlarged schematic diagram of the middle A;

[0048] Figure 3 for Figure 1 A partial enlarged schematic diagram of point B in the middle;

[0049] Figures 4 to 13 A process flow chart of a method for preparing a 2.5D micro-bump packaging structure provided in the first embodiment of the present application;

[0050] Fig.14 A schematic structural diagram of a 2.5D micro-bump packaging structure provided in the second embodiment of the present application;

[0051] Fig.15 A schematic structural diagram of a 2.5D micro-bump packaging structure provided in the third embodiment of the present application;

[0052] Fig.16 A schematic structural diagram of a 2.5D micro-bump packaging structure provided in a fourth embodiment of the present application;

[0053] Fig.17 A top view of a 2.5D micro-bump packaging structure provided in a fourth embodiment of the present application;

[0054] Fig.18 A schematic diagram of the upper plate structure of a 2.5D micro-bump packaging structure provided in the fourth embodiment of the present application;

[0055] Fig.19 A structural schematic diagram of a 2.5D micro-bump packaging structure is provided for the fifth embodiment of the present application;

[0056] Fig. 20 A top view of a 2.5D micro-bump package structure is provided for a fifth embodiment of the present application;

[0057] Fig.21 for Fig.19 A partial enlarged schematic diagram of point C in the middle;

[0058] Figure 22 to Figure 24 A process flow chart of a method for preparing a 2.5D micro-bump packaging structure is provided for the fifth embodiment of the present application.

[0059] icon:

[0060] 100-2.5D micro-bump packaging structure; 110-substrate; 111-solder pad; 112-heat dissipation protrusion; 113-heat dissipation block; 114-metal layer; 115-third dielectric layer; 120-first dielectric layer; 130-first reflective layer; 131-third opening; 132-bump; 140-second dielectric layer; 150-second reflective layer; 151-first opening; 152-second opening; 160-first wiring assembly layer; 161-buffer dielectric layer; 162-first circuit layer ;163-first dielectric layer;164-fourth opening;170-second wiring combination layer;171-second dielectric layer;172-second line layer;173-third dielectric layer;174-third reflective layer;175-fifth opening;176-sixth opening;180-conductive bump;181-UBM layer;182-copper pillar;183-tin cap;190-packaged chip;191-plastic layer;192-solder ball;200-substrate;210-solder pad;230-bottom filling glue layer. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0062] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0063] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0064] As disclosed in the background technology, most of the current 5G / 6G electronic products (for example, wifi modules, communication modules, etc.) require high-speed transmission and low loss, and often shorten the line width and line spacing to improve the transmission efficiency of their products. However, in the existing photolithography process, the light propagates in the medium and there are reflection and diffraction phenomena, resulting in low opening accuracy. At the same time, the medium layer is affected by the reflection wavelength or the diffraction wavelength, and it is easy to form spots on the surface near the opening when propagating in the medium layer, which leads to unevenness such as pits on the surface of the medium layer, resulting in problems such as poor bonding of subsequent wiring layers.

[0065] In addition, the thermal expansion coefficients of various packaging materials used in existing wafer-level chip structures (such as bumps, fan-out / fan-in packaged chips, 2.5D and 3D packaging, etc.) are inconsistent, which can easily lead to material stratification (for example, stratification of wiring layer and dielectric layer materials), affecting the performance of the product.

[0066] In order to solve the above problems, an embodiment of the present invention provides a 2.5D micro-bump packaging structure and a method for preparing the 2.5D micro-bump packaging structure. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0067] First embodiment

[0068] See also Figures 1 to 3 This embodiment provides a 2.5D micro-bump packaging structure 100, which can slow down the reflection and diffraction of light in the dielectric layer, improve the opening accuracy, and avoid pits on the surface of the dielectric layer, thereby improving the bonding strength of the subsequent wiring layer. In addition, it can reduce the delamination problem, slow down the deformation of the circuit layer, and improve the bonding strength of the circuit layer.

[0069] The 2.5D micro-bump package structure 100 provided in this embodiment includes a substrate 110, a first dielectric layer 120, a first reflective layer 130, a second dielectric layer 140, a second reflective layer 150, a first wiring assembly layer 160, a second wiring assembly layer 170 and a conductive bump 180. A pad 111 is provided on one side surface of the substrate 110; the first dielectric layer 120 is provided on the side surface of the substrate 110 provided with the pad 111; the first reflective layer 130 is provided on the first dielectric layer 120; the second dielectric layer 140 is provided on the first reflective layer 130; the second reflective layer 150 is provided on the second dielectric layer 140; the first wiring combination layer is arranged on the second reflective layer 150 and is electrically connected to the pad 111; the second wiring combination layer 170 is arranged on the first wiring combination layer 160 and is electrically connected to the first wiring combination layer 160; the conductive bump 180 is arranged on the second wiring combination layer 170 and is electrically connected to the second wiring combination layer 170; wherein the first reflective layer 130 and the second reflective layer 150 are both made of shading material, and the first wiring combination layer 160 passes through the second reflective layer 150, the second dielectric layer 140, the first reflective layer 130 and the first dielectric layer 120 in sequence, and is electrically in contact with the pad 111.

[0070] In this embodiment, since both the first reflective layer 130 and the second reflective layer 150 are made of shading materials, they can be black light absorbing materials, carbon nanotube black bodies, black epoxy polyurethane, black colloids, high molecular polymers, etc. The first dielectric layer 120 and the second dielectric layer 140 can be made of dielectric materials, such as epoxide, polyimide, benzocyclobutene, etc. The first wiring assembly layer 160 passes through the second reflective layer 150, the second dielectric layer 140, the first reflective layer 130 and the first dielectric layer 120 in sequence, and is in electrical contact with the pad 111. Therefore, in the process of slotting the first dielectric layer 120 and the second dielectric layer 140, since both the first reflective layer 130 and the second reflective layer 150 are made of shading materials, light can be blocked, and the reflection and diffraction of light in the dielectric layer can be slowed down during the slotting process, thereby improving the opening accuracy, and at the same time avoiding the problem of pits on the surface of the dielectric layer due to reflection or diffraction, thereby improving the bonding force of the subsequent wiring layer.

[0071] In this embodiment, the second reflective layer 150 is provided with a first opening 151 and a second opening 152 having the same opening width. The first opening 151 corresponds to the second wiring assembly layer 170 and penetrates the second reflective layer 150 so that the second dielectric layer 140 is exposed at the first opening 151. The first wiring assembly layer 160 is filled to the first opening 151. The second opening 152 corresponds to the pad 111 and penetrates the second reflective layer 150 and the second dielectric layer 140 so that the first reflective layer 130 is exposed at the second opening 152. A third opening 131 corresponding to the second opening 152 and connected to the third opening 131 is further provided on the first reflective layer 130 in the second opening 152. The third opening 131 penetrates the first reflective layer 130 and the first dielectric layer 120 so that the pad 111 is exposed at the third opening 131. The first wiring assembly layer 160 is filled to the second opening 152 and the third opening 131. Specifically, the opening width of the third opening 131 is smaller than that of the second opening 152, so that a step structure is formed at the junction of the third opening 131 and the second opening 152, thereby increasing the contact area and improving the bonding force of the first wiring assembly layer 160. In addition, by continuously slotting the second opening 152 to form the third opening 131, the second opening 152 can also be used to achieve opening positioning and ensure the opening accuracy of the third opening 131.

[0072] Among them, the opening widths of the first opening 151 and the second opening 152 are the same, and the first opening 151 can be used as a subsequent opening width standard. When actually slotting, the first opening 151 of slot size A can be formed on the second reflective layer 150 through an exposure and development process, and then the line width measurement machine is used to measure and control the opening width of the first opening 151, and the slotting action of the second opening 152 is performed when the opening size is accurate (fine-tuning can be performed when the opening width does not meet the standard). This method can avoid the problem of accuracy being uncontrollable due to direct slotting on the second dielectric layer 140, and avoid the inability to correct the opening size error. Moreover, the opening size of the first opening 151 here can be used as a reference point for subsequent measurement of the circuit layer opening, simplifying the wiring process. Moreover, in conjunction with the arrangement of the first reflective layer 130 and the second reflective layer 150, the reflection and diffraction of the light source in the exposure and development process can be slowed down, thereby making the absorption rate of the photolithography energy to the dielectric layer, further improving the opening accuracy.

[0073] In this embodiment, the first wiring combination layer 160 includes a buffer dielectric layer 161, a first circuit layer 162 and a first dielectric layer 163. The buffer dielectric layer 161 is arranged on the second reflective layer 150 and fills the first opening 151. A fourth opening 164 having the same opening width as the second opening 152 is arranged on the buffer dielectric layer 161. The fourth opening 164 is correspondingly connected to the second opening 152. The first circuit layer 162 is arranged on the buffer dielectric layer and extends to the fourth opening 164, the second opening 152 and the third opening 131 in sequence. The first circuit layer 162 is electrically contacted with the pad 111. The first dielectric layer 163 is arranged on the buffer dielectric layer 161 and covers the first circuit layer 162. Specifically, the buffer dielectric layer 161 is filled into the first opening 151, thereby forming a buffer structure. Since the first opening 151 corresponds to the bottom layer of the wiring structure of the first wiring combination layer 160 and the second wiring combination layer 170, the buffer structure can be designed below the overlap of the wiring layer over layer to play a buffering role, prevent the wiring from deforming, and thereby slow down the internal delamination phenomenon, thereby ensuring product performance.

[0074] It should be noted that the buffer dielectric layer 161 and the first dielectric layer 163 are also made of dielectric materials, such as epoxy, polyimide, benzocyclobutene, etc. The first wiring layer 162 can be made of a copper layer and is manufactured through a conventional wiring process.

[0075] Further, the second wiring combination layer 170 includes a second dielectric layer 171, a second line layer 172 and a third dielectric layer 173, the second dielectric layer 171 is arranged on the first dielectric layer 163, the second line layer 172 is arranged on the second dielectric layer 171, the third dielectric layer 173 is arranged on the second dielectric layer 171 and covers the second line layer 172, the second line layer 172 is electrically connected to the first line layer 162, and the conductive bump 180 is embedded in the second dielectric layer 171 and is in electrical contact with the second line layer 172. Specifically, the second dielectric layer 171 and the third dielectric layer 173 are both made of dielectric materials, such as epoxy, polyimide, benzocyclobutene, etc. The second line layer 172 can be made of a copper layer and is manufactured by a conventional wiring process.

[0076] In this embodiment, a third reflective layer 174 is further provided between the second dielectric layer 171 and the first dielectric layer 163. The third reflective layer 174 is made of a light shielding material, and its specific material may be the same as that of the first reflective layer 130 and the second reflective layer 150. By providing the third reflective layer 174, light shielding can be achieved in the process of forming the second wiring layer 172, thereby ensuring the groove accuracy of the second wiring assembly layer 170.

[0077] In this embodiment, a fifth opening 175 having the same opening width as the first opening 151 is provided on the second dielectric layer 171, and the fifth opening 175 penetrates the second dielectric layer 171 so that the third reflective layer 174 is exposed at the fifth opening 175. A sixth opening 176 is provided on the third reflective layer 174 in the fifth opening 175, and the sixth opening 176 penetrates the third reflective layer 174 and the first dielectric layer 163 and corresponds to the first circuit layer 162 so that the first circuit layer 162 is exposed at the sixth opening 176. The second circuit layer 172 extends to the fifth opening 175 and the sixth opening 176 in sequence and is in electrical contact with the first circuit layer 162. Specifically, the opening width of the sixth opening 176 is smaller than the opening width of the fifth opening 175, so that a step structure is formed at the junction of the sixth opening 176 and the fifth opening 175, which can increase the contact area with the wiring layer and improve the bonding force. Here, the first opening 151 is used as a reference opening to calibrate the subsequent second opening 152 , the fourth opening 164 , and the fifth opening 175 , thereby further improving the opening accuracy.

[0078] In this embodiment, the conductive bump 180 includes a UBM layer 181, a copper pillar 182 and a tin cap 183, wherein the UBM layer 181 is embedded in the third dielectric layer 173 and electrically contacts the second circuit layer 172, the copper pillar 182 is disposed on the UBM layer 181, and the tin cap 183 is disposed on the copper pillar 182. The specific structure of the conductive bump 180 may refer to the existing bump 132 structure.

[0079] This embodiment also provides a method for preparing a 2.5D micro-bump package structure 100, which is used to prepare the aforementioned 2.5D micro-bump package structure 100, and the preparation method comprises the following steps:

[0080] S1: providing a substrate 110 , wherein a solder pad 111 is disposed on one side surface of the substrate 110 .

[0081] See also Figure 4 Specifically, the substrate 110 may be a silicon wafer, and the pad 111 may be pre-prepared and formed on the front side of the substrate 110 .

[0082] S2 : forming a first dielectric layer 120 covering the pad 111 on one surface of the substrate 110 .

[0083] See also Figure 5 Specifically, a liquid dielectric layer (polymer layer) is evenly coated on the wafer by a coating machine in a spin coating manner, and then soft-baked on a hot plate to form a film. The dielectric layer (polymer layer) material can be composed of dielectric materials, such as epoxide, polyimide, benzocyclobutene, etc.

[0084] S3 : forming a first reflective layer 130 on the first dielectric layer 120 .

[0085] See also Figure 6 Specifically, the liquid reflective layer is evenly coated on the first dielectric layer 120 by spin coating using a coating machine, and then soft-baked on a hot plate to form a film. The material of the first reflective layer 130 can be a light-shielding material, such as a black light-absorbing material, a carbon nanotube black body, a black epoxy polyurethane, and a black colloid.

[0086] S4 : forming a second dielectric layer 140 on the first reflective layer 130 .

[0087] See also Figure 7 Specifically, the liquid medium layer (polymer layer) is evenly coated on the first reflective layer 130 by spin coating using a coater again, and then soft-baked on a hot plate to form a film to form the second medium layer 140 . The material of the second medium layer 140 can be the same as that of the first medium layer 120 .

[0088] S5 : forming a second reflective layer 150 on the second dielectric layer 140 .

[0089] See also Figure 8 Specifically, the liquid reflective layer is evenly coated on the second dielectric layer 140 by spin coating using a coating machine, and then soft-baked on a hot plate to form a film. The material of the second reflective layer 150 can be the same as that of the first reflective layer 130. The first reflective layer 130 and the second reflective layer 150 are both made of light-shielding materials.

[0090] S6: Grooving the second reflective layer 150 .

[0091] See also Fig. 9 and Fig.10Specifically, when the groove is formed, first, a first opening 151 is formed on the second reflective layer 150 at a position corresponding to the second wiring assembly layer 170, and the first opening 151 penetrates the second reflective layer 150, so that the second dielectric layer 140 is exposed at the first opening 151; then, a second opening 152 with the same opening width as the first opening 151 is formed on the second reflective layer 150 at a position corresponding to the pad 111, and the second opening 152 penetrates the second reflective layer 150 and the second dielectric layer 140, so that the first reflective layer 130 is exposed at the second opening 152; finally, a third opening 131 is formed on the first reflective layer 130 in the second opening 152, which is connected to the second opening 152, and the third opening 131 penetrates the first reflective layer 130 and the first dielectric layer 120, so that the pad 111 is exposed at the third opening 131.

[0092] In actual preparation, firstly, an exposure machine is used, which uses the second reflective layer 150 (reflective layer) to cover the position of the first opening 151 in a proximity method and not be exposed to light. Then, the developer is sprayed to remove the unexposed area by the developer. The slot size A (CD: critical dimension) of the first opening 151 is consistent with the opening size above the subsequent pad 111. After the first opening 151 is formed on the second reflective layer 150, the line width measuring machine is used to measure and control the opening width of the first opening 151 to ensure that the opening size is accurate before proceeding to the next process. If the opening width does not meet the standard, it can be fine-tuned. Here, the first opening 151 is opened first to avoid the problem of uncontrollable accuracy caused by opening the dielectric layer directly above the pad 111 (that is, avoiding the problem of opening size errors that cannot be repaired). At the same time, the first opening 151 of the second reflective layer 150 is used as a reference point for subsequent measurement of the circuit layer opening to improve the wiring process. At the same time, the second reflective layer 150 can prevent the reflection and diffraction of the light source in the exposure and development photolithography process, thereby improving the accuracy of the circuit opening, and solving the problem of the increasing capability of the photolithography machine required.

[0093] In traditional wiring processes, most circuit layers overlap with each other. The accuracy of overlapping circuit wiring can be improved by opening the reflective layer. In addition, during the traditional photolithography process, the wavelength is reflected and diffracted when propagating in the medium, resulting in low opening accuracy and size accuracy. In addition, when light propagates in the dielectric layer, it is easy to form spots on the surface near the opening, which makes the dielectric layer uneven, thereby affecting the bonding strength of the metal circuit layer.

[0094] After forming the first opening 151, the exposure machine is used again, and its function is to use the second reflective layer 150 (reflective layer) to cover the opening position above the predetermined solder joint in a proximity method so that it is not exposed to light. The developer is sprayed by the developer again by the development method to remove the unexposed area, thereby forming the second opening 152. The second opening 152 is located above the solder pad 111, and the opening width is consistent with the first opening 151. Here, the size accuracy is improved by the calibration of the first opening 151 and the second reflective layer 150. In addition, the second opening 152 can penetrate the second dielectric layer 140 downward, thereby exposing the first reflective layer 130. The oven is used again to heat and accelerate the curing of the material to a fully matured stable state, and finally the plasma descum is used to remove the organic pollutants on the surface of the material or the residues of the opening.

[0095] After forming the second opening 152 , the first reflective layer 130 in the second opening 152 can be grooved by using the exposure and development process to form a third opening 131 . The third opening 131 is smaller than the second opening 152 and exposes the pad 111 .

[0096] S7 : forming a first wiring combination layer 160 electrically connected to the pad 111 on the second reflective layer 150 .

[0097] See also Fig.11 Specifically, the first wiring assembly layer 160 sequentially passes through the second reflective layer 150, the second dielectric layer 140, the first reflective layer 130 and the first dielectric layer 120, and is in electrical contact with the pad 111. The first wiring assembly layer 160 includes a buffer dielectric layer 161, a first circuit layer 162 and a first dielectric layer 163. In actual preparation, a liquid dielectric layer (polymer layer) can be evenly coated on the second reflective layer 150 by a coating machine by spin coating, and then soft-baked to form a film. The buffer dielectric layer 161 can cover and fill the first opening 151, thereby improving the bonding force of the buffer dielectric layer 161 and forming a buffer structure at the first opening 151. Then, an oven is used to heat the material again to accelerate the curing to a fully matured stable state, and then a plasma descum is used to remove organic pollutants on the surface of the material or residues in the opening.

[0098] After the buffer dielectric layer 161 is prepared and formed, the buffer dielectric layer 161 can cover the second opening 152 and the third opening 131. Then, through the aforementioned exposure and development method, a fourth opening 164 is grooved on the buffer dielectric layer 161, wherein the opening width of the fourth opening 164 is consistent with the first opening 151, which can greatly improve the opening accuracy and expose the second opening 152 and the third opening 131 again.

[0099] After the fourth opening 164 is slotted, a conventional wiring process can be performed to form the first wiring layer 162, which can extend above the first opening 151, and the buffer dielectric layer 161 in the first opening 151 plays a buffering role to prevent the first wiring layer 162 from deforming. Then, a first dielectric layer 163 is formed to complete the preparation of the first wiring assembly layer 160.

[0100] S8 : forming a second wiring combination layer 170 electrically connected to the first wiring combination layer 160 on the first wiring combination layer 160 .

[0101] See also Fig.12 Specifically, the second wiring assembly layer 170 includes a second dielectric layer 171, a second line layer 172, and a third dielectric layer 173. After the first wiring assembly layer 160 is completed, a liquid reflective layer can be evenly coated on the wafer by a coating machine by spin coating on the first dielectric layer 163, and then soft-baked by a hot plate to form a film, thereby forming a third reflective layer 174. The material of the third reflective layer 174 is consistent with that of the second reflective layer 150 and the first reflective layer 130.

[0102] After forming the third reflective layer 174, the second dielectric layer 171 can be formed on the third reflective layer 174 again by a spin coating process, and then a groove operation is performed. The opening process can be the preparation process of the second opening 152 and the third opening 131, and the fifth opening 175 is formed on the second dielectric layer 171 by an exposure and development process, and the opening width of the fifth opening 175 is the same as that of the first opening 151, and then the sixth opening 176 is formed in the fifth opening 175 by an exposure and development process again, and the sixth opening 176 penetrates the third reflective layer 174 and the first dielectric layer 163, so as to expose the first wiring layer 162, and the opening width of the sixth opening 176 is smaller than the opening width of the fifth opening 175, so that the junction of the sixth opening 176 and the fifth opening 175 forms a step structure, which can increase the contact area with the wiring layer and improve the bonding force, and then the second wiring layer 172 and the third dielectric layer 173 are formed by a conventional wiring process.

[0103] S9 : forming a conductive bump 180 electrically connected to the second wiring combination layer 170 on the second wiring combination layer 170 .

[0104] See also Fig.13 Specifically, the conductive bump 180 includes a UBM layer 181, a copper pillar 182 and a tin cap 183. During preparation, an opening can be opened on the third dielectric layer 173, and metal is sputtered in the opening to form a UBM layer 181 (UBM: under bump metalization). Then, photoresist is coated and an opening is formed again, and then metal is sputtered to form a copper pillar 182. Finally, tin is brushed to form a tin cap 183. The preparation process of the conductive bump 180 can refer to the existing bump 132 process.

[0105] After the conductive bumps 180 are formed, they can be cut according to preset cutting paths to obtain single products.

[0106] In summary, the 2.5D micro-bump package structure 100 and the preparation method thereof provided in the embodiment of the present invention are as follows: a first dielectric layer 120, a first reflective layer 130, a second dielectric layer 140 and a second reflective layer 150 are sequentially arranged on a substrate 110, a first wiring assembly layer 160 and a second wiring assembly layer 170 are prepared after a notch is formed by grooving, and finally a conductive bump 180 is prepared. Since the first reflective layer 130 and the second reflective layer 150 are both made of shading materials, and the first wiring assembly layer 160 passes through the second reflective layer 150 in sequence, , the second dielectric layer 140, the first reflective layer 130 and the first dielectric layer 120, and are in electrical contact with the pad 111. Therefore, during the slotting process of the first dielectric layer 120 and the second dielectric layer 140, since the first reflective layer 130 and the second reflective layer 150 are both made of shading materials, they can block light, and during the slotting process, the reflection and diffraction of light in the dielectric layer can be slowed down, the opening accuracy can be improved, and the problem of pits on the surface of the dielectric layer due to reflection or diffraction can be avoided, thereby improving the bonding force of the subsequent wiring layer. And the first opening 151 is used as a reference opening to conveniently and accurately limit the width of the subsequent opening, further improving the opening accuracy and precision.

[0107] Second embodiment

[0108] See also Fig.14 This embodiment provides a 2.5D micro-bump package structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment. Compared with the first embodiment, this embodiment omits the buffer dielectric layer.

[0109] In this embodiment, the first wiring combination layer 160 includes a first circuit layer 162 and a first dielectric layer 163. The first circuit layer 162 is arranged on the second reflective layer 150 and fills the first opening 151. The first circuit layer 162 extends to the second opening 152 and the third opening 131 in sequence and is electrically contacted with the welding. The first dielectric layer 120 is arranged on the second reflective layer 150 and covers the first circuit layer 162.

[0110] It should be noted that, in actual preparation, the first circuit layer 162 can be formed first, and the first circuit layer 162 can be filled into the first opening 151 to improve its bonding and avoid delamination with the dielectric layer. At the same time, the thickness and metal content of the first circuit layer 162 can be increased, thereby improving the signal transmission efficiency of the circuit layer.

[0111] Third embodiment

[0112] See also Fig.15 This embodiment provides a 2.5D micro-bump package structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment. Compared with the first embodiment, the first reflective layer 130 in this embodiment is different.

[0113] In this embodiment, the first reflective layer 130 is provided with a bump 132, and the bump 132 sequentially passes through the second dielectric layer 140 and the second reflective layer 150, and is connected to the first wiring assembly layer 160. Specifically, the bump 132 is integrally provided with the first reflective layer 130, which can achieve a light shielding effect, and can connect the upper and lower reflective layers. At the same time, the bump 132 can at least partially correspond to different regions of the first wiring layer 162 (the first wiring layer 162 can be divided into multiple regions, and a line width gap is formed), which can prevent the diffraction and reflection of waves caused by the lithography process when the wiring process forms the first wiring assembly layer, and reduce the line width gap between the wiring layers.

[0114] Different from the first embodiment, the bump 132 in this embodiment is arranged in a raised manner. When preparing the second dielectric layer 140 and the second reflective layer 150, it is necessary to coat around the bump 132 so that the bump 132 can pass through the second dielectric layer 140 and the second reflective layer 150 in sequence, which can greatly improve the bonding force between the first reflective layer 130 and the second reflective layer 150, thereby improving the buffering performance of the bump 132 and further improving the bonding force of the dielectric layer.

[0115] Fourth embodiment

[0116] See also Figures 16 to 18This embodiment provides a 2.5D micro-bump package structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment or the third embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment or the third embodiment. Compared with the first embodiment, this embodiment adds a heat dissipation protrusion 112.

[0117] In this embodiment, a heat dissipation protrusion 112 is further provided on the substrate 110, and the heat dissipation protrusion 112 sequentially passes through the first dielectric layer 120, the first reflective layer 130, the second dielectric layer 140, the second reflective layer 150, the first wiring assembly layer 160, and the second wiring assembly layer 170, wherein an end of the heat dissipation protrusion 112 away from the substrate 110 is flush with an end of the second wiring assembly layer 170 away from the substrate 110. Specifically, the heat dissipation protrusion 112 is spaced from the second wiring layer 172, and can be made of a high thermal conductivity material, such as a metal material or a thermally conductive ACF glue, and there can be a plurality of heat dissipation protrusions 112, which are arranged around the conductive bump 180.

[0118] It should be noted that the heat dissipation protrusion 112 here can be columnar, and its cross-sectional shape can be circular, diamond or rectangular, etc., which is not specifically limited here. In some other preferred embodiments, the heat dissipation protrusion 112 can also be distributed around the conductive bump 180 in the shape of a wall. In this embodiment, by providing the heat dissipation protrusion 112, a structure that penetrates the surface of the chip can be formed to achieve a heat dissipation effect. At the same time, the heat dissipation protrusion 112 can be a buffer column and can play the role of an isolation wall between the first circuit layer 162, slowing down the reflection and diffraction of the wave, increasing the spacing between the circuits, and improving the wiring accuracy.

[0119] Preferably, the heat dissipation protrusion 112 may be partially embedded in the substrate 110 , thereby greatly improving the bonding force between the substrate 110 and the first dielectric layer 120 and preventing the wiring layer and the dielectric layer from being delaminated.

[0120] In actual board, Fig.18 As shown, the 2.5D micro-bump package structure 100 substrate 110 is welded upward, and a heat sink 113 is designed on the end face of the heat dissipation protrusion 112. The heat sink 113 can be metal or ACF glue. At the same time, the bottom filler layer 230 is used at the bottom, and the ACF glue is used to release static electricity. The interface layer of the bottom filler layer 230 is affected by the electron migration phenomenon. When the current and temperature gradient are large, the electron migration effect will be triggered, resulting in defects such as dissolution of the interface layer compound and fracture of the glue layer, which in turn causes the integrity of the glue layer welding structure to be damaged and the mechanical properties to be degraded. At the same time, an additional pad 210 can be designed on the substrate 200 and docked with the heat sink 113 to achieve a better heat dissipation effect.

[0121] Fifth embodiment

[0122] See also Figures 19 to 21 This embodiment provides a 2.5D micro-bump packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0123] In this embodiment, the 2.5D micro-bump package structure 100 further includes a package chip 190 and a plastic encapsulation layer 191. The package chip 190 is disposed on a side of the second wiring assembly layer 170 away from the substrate 110 and is welded to the conductive bump 180. The plastic encapsulation layer 191 is disposed on the second wiring assembly layer 170 and is coated on the outside of the package chip 190. Specifically, there may be multiple package chips 190, and the multiple package chips 190 may be a combination of a logic chip and a memory chip. The pins of the package chip 190 are welded to the conductive bump 180 and are encapsulated by the plastic encapsulation layer 191.

[0124] In this embodiment, the substrate 110 includes a metal layer 114 and a third dielectric layer 115, the metal layer 114 is connected to the pad 111, the third dielectric layer 115 is coated outside the metal layer 114, and a solder ball 192 is also arranged on the third dielectric layer 115, and the solder ball 192 is connected to the metal layer 114. Specifically, in actual preparation, the silicon wafer in the above-mentioned embodiment can be removed first, for example, by grinding to expose the pad 111, and then the substrate is reconstructed to form the metal layer 114 and the third dielectric layer 115, the metal layer 114 is connected to the pad 111, the third dielectric layer 115 is coated outside the metal layer 114, and the solder ball 192 is designed on the metal layer 114.

[0125] The metal layer 114 may be a wiring structure or a pad structure.

[0126] This embodiment provides a method for preparing a 2.5D micro-bump package structure 100 , and its basic steps and principles are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0127] Steps S1 to S9 of the preparation method can all refer to the first embodiment. On this basis, the preparation method further includes the following steps:

[0128] S10 : mounting the packaged chip 190 on the conductive bump 180 .

[0129] See also Fig. 22 Specifically, the micro bumps of the inverted chip can be welded to the conductive bumps 180 to complete the mounting of the packaged chip 190. The packaged chip 190 can be a separate memory chip or a logic chip, or a combination of a logic chip and a memory chip.

[0130] S11: forming a plastic sealing layer 191 .

[0131] See also Fig.23 Specifically, after the packaging chip 190 is mounted, a plastic packaging layer 191 may be formed through a plastic packaging process, and the plastic packaging layer 191 covers the packaging chip 190 .

[0132] S12: Grinding and removing the substrate 110.

[0133] See also Fig.24 Specifically, the substrate 110 can be removed through a grinding process to expose the pad 111.

[0134] S13 : Reconstructing the substrate 110 .

[0135] Please continue to see Fig.19 and Fig. 20 Specifically, a metal layer 114 can be formed by a wiring process, and the metal layer 114 can contact the pad 111 to achieve electrical connection. Then, the third dielectric layer 115 is spin-coated so that the third dielectric layer 115 can be coated outside the metal layer 114.

[0136] S14: Ball planting.

[0137] Please continue to see Fig.19 and Fig. 20 Specifically, through the ball planting process, an opening is formed on the third dielectric layer 115 and a solder ball 192 is planted, and the solder ball 192 is connected to the metal layer 114, thereby realizing signal output.

[0138] After the ball planting is completed, it can be cut to obtain single products.

[0139] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A 2.5D micro-bump packaging structure, characterized in that: include: A substrate, wherein a welding pad is disposed on one side surface of the substrate; A first dielectric layer, the first dielectric layer is disposed on a surface of a side of the substrate where the solder pad is disposed; a first reflective layer, wherein the first reflective layer is disposed on the first dielectric layer; a second dielectric layer, the second dielectric layer being disposed on the first reflective layer; a second reflective layer, wherein the second reflective layer is disposed on the second dielectric layer; a first wiring assembly layer, the first wiring assembly layer being disposed on the second reflective layer and electrically connected to the pad; a second wiring combination layer, the second wiring combination layer being disposed on the first wiring combination layer and electrically connected to the first wiring combination layer; A conductive bump, the conductive bump being disposed on the second wiring assembly layer and electrically connected to the second wiring assembly layer; Among them, the first reflective layer and the second reflective layer are both made of shading materials, and the first reflective layer and the second reflective layer are configured to shield light during the process of grooving by exposure and development to slow down the reflection and diffraction of light. The first wiring combination layer passes through the second reflective layer, the second dielectric layer, the first reflective layer and the first dielectric layer in sequence, and is in electrical contact with the pad.

2. The 2.5D micro-bump packaging structure according to claim 1, characterized in that: The second reflective layer is provided with a first opening and a second opening having the same opening width, the first opening corresponds to the second wiring combination layer and penetrates the second reflective layer so that the second dielectric layer is exposed at the first opening, the first wiring combination layer is filled to the first opening, the second opening corresponds to the soldering pad and penetrates the second reflective layer and the second dielectric layer so that the first reflective layer is exposed to the second opening, and the first reflective layer in the second opening is further provided with a third opening corresponding to the second opening and conductive, the opening width of the third opening is smaller than the opening width of the second opening, and penetrates the first reflective layer and the first dielectric layer so that the soldering pad is exposed to the third opening, and the first wiring combination layer is filled to the second opening and the third opening.

3. The 2.5D micro-bump packaging structure according to claim 2, characterized in that: The first wiring combination layer includes a buffer dielectric layer, a first circuit layer and a first dielectric layer. The buffer dielectric layer is arranged on the second reflective layer and fills the first opening. A fourth opening having an opening width the same as that of the second opening is arranged on the buffer dielectric layer. The fourth opening is correspondingly connected to the second opening. The first circuit layer is arranged on the buffer dielectric layer and extends to the fourth opening, the second opening and the third opening in sequence. The first circuit layer is electrically contacted with the pad. The first dielectric layer is arranged on the buffer dielectric layer and covers the first circuit layer.

4. The 2.5D micro-bump packaging structure according to claim 2, characterized in that: The first wiring combination layer includes a first circuit layer and a first dielectric layer, the first circuit layer is arranged on the second reflective layer and fills the first opening, and the first circuit layer extends to the second opening and the third opening in sequence and is electrically contacted with the pad, the first dielectric layer is arranged on the second reflective layer and covers the first circuit layer.

5. The 2.5D micro-bump packaging structure according to claim 3 or 4, characterized in that: The second wiring combination layer includes a second dielectric layer, a second line layer and a third dielectric layer, the second dielectric layer is arranged on the first dielectric layer, the second line layer is arranged on the second dielectric layer, the third dielectric layer is arranged on the second dielectric layer and covers the second line layer, the second line layer is electrically connected to the first line layer, and the conductive bump is embedded in the second dielectric layer and electrically contacted with the second line layer.

6. The 2.5D micro-bump packaging structure according to claim 5, characterized in that: A third reflective layer is further arranged between the second dielectric layer and the first dielectric layer, and the third reflective layer is made of a light-shielding material.

7. The 2.5D micro-bump packaging structure according to claim 6, characterized in that: A fifth opening having the same opening width as that of the first opening is provided on the second dielectric layer, the fifth opening penetrates the second dielectric layer so that the third reflective layer is exposed at the fifth opening, a sixth opening is provided on the third reflective layer in the fifth opening, the sixth opening penetrates the third reflective layer and the first dielectric layer and corresponds to the first circuit layer so that the first circuit layer is exposed at the sixth opening, and an opening width of the sixth opening is smaller than an opening width of the fifth opening, the second circuit layer extends to the fifth opening and the sixth opening in sequence, and is in electrical contact with the first circuit layer.

8. The 2.5D micro-bump packaging structure according to claim 1, characterized in that: The first reflective layer is provided with a bump, and the bump passes through the second dielectric layer and the second reflective layer in sequence and is connected to the first wiring assembly layer.

9. The 2.5D micro-bump packaging structure according to claim 1, characterized in that: A heat dissipation protrusion is also arranged on the substrate, and one end of the heat dissipation protrusion away from the substrate is flush with one end of the second wiring assembly layer away from the substrate.

10. The 2.5D micro-bump packaging structure according to claim 1, characterized in that: The 2.5D micro-bump packaging structure also includes a packaging chip and a plastic packaging layer. The packaging chip is arranged on a side of the second wiring assembly layer away from the substrate and is welded to the conductive bumps. The plastic packaging layer is arranged on the second wiring assembly layer and covers the outside of the packaging chip.

11. The 2.5D micro-bump packaging structure according to claim 10, characterized in that: The substrate comprises a metal layer and a third dielectric layer, the metal layer is connected to the pad, the third dielectric layer is coated outside the metal layer, and solder balls are also arranged on the third dielectric layer, and the solder balls are connected to the metal layer.

12. A method for preparing a 2.5D micro-bump packaging structure, used for preparing the 2.5D micro-bump packaging structure as claimed in claim 1, characterized in that: The preparation method comprises: Providing a substrate, wherein a welding pad is disposed on one side surface of the substrate; Forming a first dielectric layer covering the pad on one side surface of the substrate; forming a first reflective layer on the first dielectric layer; forming a second dielectric layer on the first reflective layer; forming a second reflective layer on the second dielectric layer; Forming grooves on the second reflective layer by exposure and development; forming a first wiring assembly layer electrically connected to the pad on the second reflective layer; forming a second wiring combination layer on the first wiring combination layer and electrically connected to the first wiring combination layer; forming a conductive bump electrically connected to the second wiring combination layer on the second wiring combination layer; Among them, the first reflective layer and the second reflective layer are both made of shading materials, and the first reflective layer and the second reflective layer are configured to shield light during the process of grooving by exposure and development to slow down the reflection and diffraction of light. The first wiring combination layer passes through the second reflective layer, the second dielectric layer, the first reflective layer and the first dielectric layer in sequence, and is in electrical contact with the pad.

13. The method for preparing the 2.5D micro-bump packaging structure according to claim 12, characterized in that: The step of cutting grooves on the second reflective layer comprises: forming a first opening on the second reflective layer at a position corresponding to the second wiring assembly layer, wherein the first opening penetrates the second reflective layer so that the second dielectric layer is exposed at the first opening; forming a second opening having the same opening width as the first opening at a position corresponding to the pad on the second reflective layer, wherein the second opening penetrates the second reflective layer and the second dielectric layer, so that the first reflective layer is exposed at the second opening; A third opening is formed on the first reflective layer in the second opening and is connected to the second opening. The third opening penetrates the first reflective layer and the first dielectric layer, so that the pad is exposed at the third opening.

14. The method for preparing the 2.5D micro-bump packaging structure according to claim 12, characterized in that: After the step of forming a first wiring assembly layer electrically connected to the pad on the second reflective layer, the preparation method further comprises: A third reflective layer is formed on the first wiring combination layer.

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