Semiconductor processing method

Abstract

The invention provides a semiconductor processing method. The semiconductor processing method comprises the following steps: providing a wafer comprising a silicon layer, a dielectric layer and a bonding layer; metal layers are arranged in at least part of the cutting channels; manufacturing a metal protection layer on the surface of the bonding layer; sequentially etching the metal protection layer, the bonding layer and the dielectric layer along the cutting channel by adopting dry etching until the metal layer is etched, and forming a first etching groove section; the bottom of the first etching groove section is etched through laser etching until the metal layer is removed, and a second etching groove section is formed; etching downwards according to the width of the first etching groove section along the direction of the cutting channel until a preset depth in the silicon layer is reached; thinning the surface, deviating from the dielectric layer, of the silicon layer until the cutting channel is completely separated; and removing the metal protection layer to form an independent chip. The metal protection layer is added on the surface of the bonding layer, and the laser etching position is arranged below the bonding interface, so that the interface protection capability of the bonding layer is remarkably improved, warping is reduced, and the flatness and cleanliness of the bonding layer are ensured.

Description

Technical Field

[0001] The present application relates to the field of semiconductor processing technology, and in particular, to a semiconductor processing method. Background Art

[0002] In the field of semiconductor packaging technology, C2W (Chip to Wafer) technology has attracted much attention because of its ability to achieve high-density integration and improve electrical performance. C2W technology makes it possible to miniaturize and improve the performance of semiconductor devices by directly packaging chips onto wafers. In this process, Hybrid Bonding technology is a key step in achieving stable and efficient electrical connection between chips and wafers. The development of hybrid bonding technology is of great significance to improving the overall performance and reliability of semiconductor devices.

[0003] Currently, wafers need to be cut into individual chips through a cutting process before hybrid bonding. For wafers with metal layers in the cutting path, the existing cutting processes mainly include Laser Grove and Bladesaw. In the laser etching process, the laser is used to etch the metal structure on the cutting path until it stops above the silicon layer to form a cutting path. Subsequently, the wafer is cut into individual chips using a knife cutting method.

[0004] Although the existing cutting process meets the needs of the C2W hybrid bonding process to a certain extent, there are still some significant problems. First, during the laser etching process, due to the high temperature generated by the laser, the junction between the side wall of the cutting path and the surface of the bonding layer is prone to large warping. This warping phenomenon not only affects the cutting accuracy, but may also cause damage to the bonding layer. Secondly, if the by-product Debris (slag) produced during the laser etching process is not effectively removed, it will form an obstacle in the subsequent hybrid bonding process and reduce the quality and stability of the bonding. In addition, damage to the bonding interface during laser etching is also a problem that cannot be ignored. This damage will directly affect the yield of C2W hybrid bonding, and then affect the performance and reliability of the final product. Summary of the invention

[0005] The purpose of the embodiment of the present application is to provide a semiconductor processing method, which significantly improves the protection capability of the bonding layer interface and reduces the warping problem of the bonding layer by adding a metal protective layer on the surface of the bonding layer and setting the laser etching position below the bonding interface, thereby ensuring the flatness and cleanliness of the bonding layer surface and improving the processing quality.

[0006] The present application provides a semiconductor processing method, comprising:

[0007] S0. providing a wafer, which at least comprises a silicon layer, a dielectric layer disposed on a surface of the silicon layer, and a bonding layer disposed on a surface of the dielectric layer; the dielectric layer corresponding to at least part of the cutting paths of the wafer has a metal layer;

[0008] S1. Making a metal protective layer on the surface of the bonding layer;

[0009] S2, using a dry etching process to sequentially etch the metal protection layer, the bonding layer and the dielectric layer along the cutting path until the etching stops at the metal layer, thereby forming a first etched groove segment;

[0010] S3, etching the bottom of the first etched groove segment using a laser etching process until the metal layer is removed to form a second etched groove segment;

[0011] S4, etching downwards along the cutting path direction and according to the width of the first etching groove segment until stopping at a predetermined depth in the silicon layer;

[0012] S5, thinning the side of the silicon layer of the wafer facing away from the dielectric layer until the cutting path is completely separated;

[0013] S6. Remove the metal protective layer on the surface of the bonding layer to form an independent chip.

[0014] In an practicable solution, the overall width of the metal layer in the dielectric layer corresponding to the cutting street does not exceed the width of the first etched groove segment;

[0015] The width of the first etching groove segment is a, and the overall width of the metal layer in the cutting path is m, wherein a≥m.

[0016] In an implementable solution, the width of the second etched groove segment is b, wherein m≤b≤a.

[0017] In an implementable scheme, when the width of the first etched groove segment is greater than the overall width of the metal layer, that is, a>m, the width b of the second etched groove segment satisfies m≤b<a, so as to form a step structure at the junction of the bottom of the first etched groove segment and the second etched groove segment.

[0018] In an practicable solution, the overall width of the metal layer in the dielectric layer corresponding to the cutting street exceeds the width of the first etched groove segment;

[0019] The width of the first etching groove segment is a, and the overall width of the metal layer in the cutting path is m, wherein a<m.

[0020] In one feasible solution, the width of the second etched groove segment is b, wherein b=a.

[0021] In one feasible solution, step S4 includes:

[0022] S41, using a first plasma cutting technology, etching downwards along the cutting path direction and according to the width of the first etching groove segment until the etching stops at the surface of the silicon layer;

[0023] S42, using a second plasma cutting technology to cut the silicon layer until the cutting stops at a predetermined depth in the silicon layer.

[0024] In an implementable solution, the first plasma cutting technology is an inductively coupled plasma cutting technology; and the second plasma cutting technology is a capacitively coupled plasma cutting technology.

[0025] In an practicable solution, before step S2, the method includes: exposing the surface of the metal protective layer to reveal the cutting path area.

[0026] In an practicable solution, in step S5, the metal protection layer on the surface of the bonding layer is removed by wet etching.

[0027] Compared with the prior art, the beneficial effects of this application include at least:

[0028] This application adopts a method combining dry etching and laser etching. Dry etching accurately removes the dielectric layer above the metal layer in the cutting path, and at the same time, the dry etching process maintains a low process temperature, reducing the risk of thermal stress and thermal damage to the bonding layer, and reducing the probability of warping problems at the junction of the cutting path and the bonding layer.

[0029] At the same time, when removing the metal layer in the cutting path, the laser etching does not start directly from the surface of the bonding layer, but starts from the bottom of the first etching groove segment formed by dry etching. In this way, the warping and slag generated by high temperature are below the bonding interface of the bonding layer, which is equivalent to making the high temperature of laser etching and the generated slag relatively far away from the bonding layer, greatly reducing the warping problem caused by high temperature, optimizing the flatness of the bonding layer surface, and ensuring the cleanliness of the bonding layer.

[0030] In addition, by making a metal protective layer on the surface of the bonding layer, it not only effectively resists the bombardment of etching gas during the etching process and protects the bonding layer from damage, but also avoids the influence of subsequent possible chemical corrosion on the interface, ensuring the integrity and performance of the bonding layer. At the same time, the existence of the metal protective layer further prevents the contamination of the bonding layer by slag and maintains the cleanliness of the interface.

[0031] To sum up, in the semiconductor processing method of the present application, by adding a metal protective layer on the surface of the bonding layer and setting the laser etching position below the bonding interface, the protection capability of the bonding layer interface is significantly improved, the warping problem of the bonding layer surface is reduced or even eliminated, and the flatness and cleanliness of the bonding layer surface can be ensured, the overall processing quality is improved, the yield of the subsequent C2W hybrid bonding process is ensured, and the stability and reliability of the final product are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 A flowchart of a semiconductor processing method according to an embodiment of the present application is shown;

[0034] Figure 2 A cross-sectional view of a wafer according to an embodiment of the present application is shown;

[0035] Figure 3 For Figure 2 A cross-sectional view of the bonding layer surface of the wafer shown in FIG. 1 after a metal protective layer is provided;

[0036] Figure 4 For Figure 2 A cross-sectional view after the first etched groove segment is made on the basis of the wafer shown in ;

[0037] Figure 5 , Figure 6 and Figure 7 For Figure 4 A cross-sectional view after a second etched groove segment is made on the wafer shown in ;

[0038] Figure 8 Another cross-sectional view of a wafer according to an embodiment of the present application;

[0039] Fig. 9 For Figure 8 A cross-sectional view after the first etched groove segment is made on the basis of the wafer shown in ;

[0040] Fig.10 For Fig. 9 A cross-sectional view after a second etched groove segment is made on the wafer shown in ;

[0041] Fig.11 For Figure 5 , Figure 6 , Figure 7 or Fig.10 A cross-sectional view of the wafer after etching to the silicon layer shown in FIG.

[0042] Fig.12 For the general Fig.11 Cross-section diagram after transfer;

[0043] Fig.13 For the general Fig.12 Cross-sectional view of the wafer after backside thinning;

[0044] Fig.14 For the general Fig.13 Cross-sectional view of the wafer after transfer;

[0045] Fig.15 Schematic diagram of using wet etching to remove the metal protective layer on the surface of the bonding layer.

[0046] In the figure: 01, cutting road; 1, wafer; 11, silicon layer; 12, dielectric layer; 13, bonding layer; 14, metal layer; 15, metal protection layer; 16, photoresist layer; 17, protective glue layer; 101, first etching groove section; 102, second etching groove section. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0048] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0049] The present application provides a semiconductor processing method for Figure 2 The wafer 1 shown is processed, and the wafer 1 at least includes a silicon layer 11, a dielectric layer 12 arranged on the surface of the silicon layer 11, and a bonding layer 13 arranged on the surface of the dielectric layer 12; the dielectric layer 12 corresponding to at least part of the cutting lanes 01 of the wafer 1 has a metal layer 14.

[0050] like Figure 1 As shown, the semiconductor processing method includes:

[0051] S1, such as Figure 3 As shown, a metal protective layer 15 is formed on the surface of the bonding layer 13;

[0052] S2, such as Figure 4 As shown, the metal protection layer 15, the bonding layer 13 and the dielectric layer 12 are etched in sequence along the cutting path 01 by a dry etching process until the etching stops at the metal layer 14, thereby forming a first etched groove segment 101;

[0053] S3, such as Figure 5 As shown, a laser etching process is used to etch the bottom of the first etched groove segment 101 until the metal layer 14 is removed to form a second etched groove segment 102;

[0054] S4, such as Fig.11 As shown, etching is performed downward along the direction of the cutting path 01 and according to the width of the first etching groove segment 101 until it stops at a predetermined depth in the silicon layer 11;

[0055] S5, such as Fig.12 and Fig.13 As shown, the side of the silicon layer 11 of the wafer 1 facing away from the dielectric layer 12 is thinned until the cutting path 01 is completely separated;

[0056] S6, such as Fig.14 and Fig.15 As shown, the metal protection layer 15 on the surface of the bonding layer 13 is removed to form an independent chip.

[0057] In step S1, a metal protective layer 15 can be formed on the surface of the bonding layer 13 by physical vapor deposition, and the metal protective layer 15 can be made of Ti. In the subsequent etching process, the metal protective layer 15 can resist the bombardment of the etching gas and protect the bonding interface of the bonding layer 13.

[0058] In the present embodiment, before step S2, the process includes: exposing the surface of the metal protective layer 15 to reveal the area of ​​the cutting path 01. Specifically, a layer of light-sensitive photoresist layer 16 is evenly coated on the surface of the wafer 1, and soft baking can be performed to enhance the adhesion of the photoresist layer 16. After ensuring that the wafer 1 is accurately aligned with the design pattern using an alignment device, a photolithography machine is used for exposure, and light of a specific wavelength is projected onto the wafer 1 through a mask to trigger a chemical reaction of the photoresist layer 16. After exposure, post-baking is performed to cure the reaction, and then a developer is used to dissolve the photoresist layer 16 in the exposed area. After development, the accuracy of the pattern is checked and any residues are removed. Finally, the remaining photoresist is further cured by hard baking to prepare for the subsequent cutting or etching process at the cutting path 01. At the end of step S4, the photoresist layer 16 on the surface of the bonding layer 13 is also consumed.

[0059] In step S2, dry etching is a commonly used etching technique in semiconductor manufacturing, which selectively removes surface materials by using gas plasma. Dry etching is usually performed using a plasma etcher (Plasma Etch System), which can generate high-density plasma for chemically reacting with the material on the surface of the wafer to achieve etching. The etching gas has high chemical activity in the plasma state and can react with the dielectric material on the surface of the wafer to generate volatile byproducts, thereby achieving etching. The temperature during dry etching is relatively low, usually between room temperature and several hundred degrees Celsius. This is because plasma etching mainly relies on chemical reactions, not thermal effects. Low-temperature operation helps to reduce thermal stress and thermal damage at the bonding layer 13, greatly reduces the probability of warping problems at the junction of the bonding layer 13 and the cutting path 01, and maintains the integrity and performance of the bonding layer 13.

[0060] In step S3, the laser etching process is a technology that uses a high-energy laser beam to locally heat the surface of a material, thereby melting, evaporating or chemically changing the material to form a desired pattern or text. This process has important applications in semiconductor manufacturing processes, especially for etching of metal copper layers.

[0061] Laser etching usually uses a laser etcher, which consists of a laser source (such as a fiber laser or UV laser), a focusing system, and a precision optical scanning system. The laser source generates a high-energy laser beam, which forms a high-power density laser spot through the focusing system, and the optical scanning system controls the movement of the laser beam on the surface of the material to form the desired pattern. When the laser beam contacts the material, it will generate extremely high temperatures, causing the material to melt or evaporate rapidly.

[0062] In the prior art, for a wafer with a metal layer 14 in the cutting path 01, a laser is directly used to etch from the surface of the bonding layer to the silicon layer. On the one hand, due to the high temperature generated by the laser, the junction between the side wall of the cutting path and the surface of the bonding layer is prone to large warping, which not only affects the cutting accuracy, but may also cause damage to the bonding layer. On the other hand, the high temperature of the laser melts the metal layer in the cutting path to produce slag, which will contaminate the surface of the bonding layer, affect the cleanliness of the surface of the bonding layer, and reduce the quality and stability of subsequent bonding.

[0063] In the embodiment of the present application, it can be seen from step S3 that the laser etching process does not directly etch downward from the surface of the bonding layer 13, but etches downward from the bottom of the first etching groove segment 101. Therefore, the etching position of the laser is relatively far away from the position of the bonding layer 13. Therefore, the high temperature generated by the laser can be relatively far away from the position of the bonding layer 13, which greatly reduces the warping problem of the surface of the bonding layer 13 and the side wall of the bonding layer 13 and the cutting path 01, and optimizes and ensures the flatness of the surface of the bonding layer 13.

[0064] In addition, since the metal protective layer 15 protects the bonding layer 13 , the surface of the bonding layer 13 can be protected from being contaminated by laser high-temperature slag, thereby ensuring the cleanliness of the surface of the bonding layer 13 .

[0065] It should be noted that in step S3, the purpose of the laser etching process is mainly to remove the metal layer 14 in the cutting path 01. Figure 5 As shown, the laser etching can stop at the surface of the silicon layer 11. Figure 6 As shown, the laser etching can stop when the etching reaches a certain distance inside the silicon layer 11. Figure 7 As shown, after the laser etching removes the metal layer 14, the etching can be stopped at a predetermined distance above the surface of the silicon layer 11. In a preferred solution, the laser etching can be stopped at the surface of the silicon layer 11.

[0066] In this embodiment, if Figure 2 and Figure 3 As shown, the overall width of the metal layer 14 in the dielectric layer 12 corresponding to the cutting path 01 does not exceed the width of the first etched groove segment 101. Specifically, as Figure 4 As shown, when dry etching is performed in step S2, the width a of the first etched groove segment 101 is greater than or equal to the overall width m of the metal layer 14 in the cutting street 01, that is, a≥m.

[0067] In this embodiment, if Figure 5 , Figure 6 and Figure 7 As shown, the width of the second etched groove segment 102 is b, where m≤b≤a, to ensure that the metal layer 14 at the bottom of the second etched groove segment 102 can be completely removed by the pipe etching process.

[0068] In this embodiment, if Figure 5 , Figure 6 and Figure 7 As shown, when the width of the first etched groove segment 101 is greater than the overall width of the metal layer 14, that is, when a>m, the width b of the second etched groove segment 102 can satisfy m≤b<a, so as to form a step structure at the junction of the bottom of the first etched groove segment 101 and the second etched groove segment 102. The step structure can make the etching position of the laser etching process relatively far away from the side wall of the first etched groove segment 101, reducing the degree of warping caused to the side wall.

[0069] In this embodiment, if Figure 8 As shown, the overall width of the metal layer 14 in the dielectric layer 12 corresponding to the cutting path 01 exceeds the width of the first etched groove segment 101. Figure 4 As shown, when dry etching is performed in step S2, the width a of the first etched groove segment 101 is smaller than the overall width m of the metal layer 14 in the cutting street 01, that is, a<m.

[0070] In this embodiment, if Fig. 9 As shown, in order to completely remove the metal layer 14 at the bottom of the first etched groove segment 101 , the width b of the second etched groove segment 102 needs to satisfy b=a.

[0071] In this embodiment, step S4 includes:

[0072] S41, using inductively coupled plasma cutting technology, etching is performed downward along the direction of the cutting path 01 and according to the width of the first etching groove segment 101 until the surface of the silicon layer 11 is stopped;

[0073] S42 , cutting the silicon layer 11 using capacitively coupled plasma cutting technology until the silicon layer 11 stops at a predetermined depth.

[0074] for Figure 5 , Figure 6 and Figure 7 The step structure is formed at the junction of the bottom of the first etched groove segment 101 and the second etched groove segment 102 . The cutting in step S41 can remove the step structure and play a certain role in repairing the warping of the side wall of the first etched groove segment 101 .

[0075] for Fig.10 In the structure shown, there is no step structure at the junction of the bottom of the first etched groove segment 101 and the second etched groove segment 102, but there may be some warping problems on the side walls of the first etched groove segment 101 and the second etched groove segment 102. The cutting in step S41 can also play a certain role in repairing the warping of the side walls.

[0076] In this embodiment, if Fig.11 As shown, at the end of step S4, the photoresist layer 16 on the surface of the metal protection layer 15 is also completely consumed.

[0077] After step S4 is completed and before step S5 is started, a protective adhesive layer 17 is applied to the surface of the metal protective layer 15, and then the wafer 1 is turned over (eg, Fig.12 The protective adhesive layer 17 protects the front side of the wafer 1 during the back side grinding process to prevent the wafer 1 from being physically damaged during the back side grinding. At the same time, the protective adhesive layer 17 can also prevent the wafer 1 from shifting during the grinding process.

[0078] Back grinding is completed (such as Fig.13 After that, a protective adhesive layer 17 may be applied to the back of the ground silicon layer 11, and then the wafer 1 may be flipped over to face up (as shown in FIG. Fig.14 As shown), one side of the silicon layer 11 is attached to a base surface, and the protective adhesive layer 17 on the surface of the metal protective layer 15 of the wafer 1 can be removed by ultraviolet heating, solvent cleaning, etc.

[0079] In this embodiment, if Fig.15 As shown, in step S6, the metal protection layer 15 can be removed by a wet cleaning process to expose the surface of the bonding layer 13. Afterwards, the protective glue layer 17 on the surface of the silicon layer 11 on the back side of the wafer 1 can be removed.

[0080] This solution uses a combination of dry etching and laser etching. Dry etching uses the high chemical activity of plasma to accurately remove the dielectric layer 12 above the metal layer 14 in the cutting path 01. At the same time, the dry etching process maintains a low process temperature, reducing the risk of thermal stress and thermal damage to the bonding layer 13, and reducing the probability of warping at the junction of the cutting path 01 and the bonding layer 13.

[0081] At the same time, when removing the metal layer 14 in the cutting path 01, the laser etching does not start directly from the surface of the bonding layer 13, but starts from the bottom of the first etching groove segment 101 formed by dry etching. In this way, the warping and slag generated by high temperature are below the bonding interface of the bonding layer 13, which is equivalent to making the high temperature of laser etching and the generated slag relatively far away from the bonding layer 13, greatly reducing the warping problem caused by high temperature, optimizing the flatness of the bonding layer surface, and ensuring the cleanliness of the bonding layer 13.

[0082] In addition, by forming a metal protective layer 15 on the surface of the bonding layer 13, not only can the bombardment of the etching gas be effectively resisted during the etching process, protecting the bonding layer 13 from damage, but also the influence of subsequent possible chemical corrosion on the interface is avoided, thereby ensuring the integrity and performance of the bonding layer 13. At the same time, the presence of the metal protective layer 15 further prevents the contamination of the bonding layer by the slag and maintains the cleanliness of the interface.

[0083] To sum up, in the semiconductor processing method of the embodiment of the present application, by adding a metal protective layer on the surface of the bonding layer and setting the laser etching position below the bonding interface, the protection of the bonding layer interface is significantly improved, the warping problem of the bonding layer surface is reduced or even eliminated, the flatness and cleanliness of the bonding layer surface can be ensured, the overall processing quality is improved, the yield of the subsequent C2W hybrid bonding process is guaranteed, and the stability and reliability of the final product are improved.

[0084] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A semiconductor processing method, characterized in that: include: S0. providing a wafer, which at least comprises a silicon layer, a dielectric layer disposed on a surface of the silicon layer, and a bonding layer disposed on a surface of the dielectric layer; The dielectric layer corresponding to at least part of the cutting paths of the wafer has a metal layer; S1. Making a metal protective layer on the surface of the bonding layer; S2, using a dry etching process to sequentially etch the metal protection layer, the bonding layer and the dielectric layer along the cutting path until the etching stops at the metal layer, thereby forming a first etched groove segment; S3, etching the bottom of the first etched groove segment using a laser etching process until the metal layer is removed to form a second etched groove segment; S4, etching downwards along the cutting path direction and according to the width of the first etching groove segment until stopping at a predetermined depth in the silicon layer; S5, thinning the side of the silicon layer of the wafer facing away from the dielectric layer until the cutting path is completely separated; S6. Remove the metal protective layer on the surface of the bonding layer to form an independent chip.

2. The semiconductor processing method according to claim 1, characterized in that: The overall width of the metal layer in the dielectric layer corresponding to the cutting street does not exceed the width of the first etching groove segment; The width of the first etching groove segment is a, and the overall width of the metal layer in the cutting path is m, wherein a≥m.

3. The semiconductor processing method according to claim 2, characterized in that: The width of the second etched groove segment is b, wherein m≤b≤a.

4. The semiconductor processing method according to claim 3, characterized in that: When the width of the first etched groove segment is greater than the overall width of the metal layer, that is, a>m, the width b of the second etched groove segment satisfies m≤b<a, so as to form a step structure at the junction of the bottom of the first etched groove segment and the second etched groove segment.

5. The semiconductor processing method according to claim 1, characterized in that: The overall width of the metal layer in the dielectric layer corresponding to the cutting street exceeds the width of the first etching groove segment; The width of the first etching groove segment is a, and the overall width of the metal layer in the cutting path is m, wherein a<m.

6. The semiconductor processing method according to claim 5, characterized in that: The width of the second etched groove segment is b, wherein b=a.

7. The semiconductor processing method according to any one of claims 1 to 6, characterized in that: The step S4 comprises: S41, using a first plasma cutting technology, etching downwards along the cutting path direction and according to the width of the first etching groove segment until the etching stops at the surface of the silicon layer; S42, using a second plasma cutting technology to cut the silicon layer until the silicon layer stops at a predetermined depth.

8. The semiconductor processing method according to claim 7, characterized in that: The first plasma cutting technology is an inductively coupled plasma cutting technology; the second plasma cutting technology is a capacitively coupled plasma cutting technology.

9. The semiconductor processing method according to any one of claims 1 to 6, characterized in that: Before the step S2, the method includes: exposing the surface of the metal protective layer to reveal the cutting path area.

10. The semiconductor processing method according to any one of claims 1 to 6, characterized in that: In step S5, the metal protection layer on the surface of the bonding layer is removed by wet etching.

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