High-voltage silicon capacitor and electronic equipment
By setting up a multi-layer structure and TiN barrier layer in a high-voltage silicon capacitor unit, the bottom problem during deep trench etching is solved, the withstand voltage and capacitance density of silicon capacitor devices is improved, and the capacity and reliability of silicon capacitor devices is achieved. sex.
Patent Information
- Application Number
- CN202411195868.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2024-12-06
AI Technical Summary
During deep trench etching, problems such as lateral drilling at the bottom, residual bottom defects, rough and burrs on the side wall surface are prone to occur, resulting in poor voltage withstand performance and small capacity of high-voltage silicon capacitor devices, which affects the product yield and reliability.
By etching the deep through holes in the silicon capacitance unit and setting the TiN barrier layer between the tungsten conductive layer and the dielectric layer, another TiN barrier layer is set between the dielectric layer and the inner wall, along the deep through hole radius The SiN and SiO2 sub-layers are set in the direction, and the NON dielectric layer with a thickness of more than 2 μm is achieved. The stacked interconnection of silicon capacitor cells is achieved by thinning the bottom of the trench and grinding the arc corners.
The voltage withstandability and reliability of silicon capacitor devices are improved, the capacitance density is enhanced, and the adhesion problem of SiN sub-layer and silicon substrate is solved through the TiN barrier layer, achieving higher capacitance and anti-interference.
Smart Images
Figure CN119095479A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a high-voltage silicon capacitor and an electronic device. Background Art
[0002] Silicon capacitors are capacitors made of silicon as the main body and thin film materials such as silicon dioxide / silicon nitride as dielectrics, using semiconductor chip manufacturing technology. With the advantages of ultra-small size, higher Q value, low insertion loss, stability, reliability, temperature resistance, aging resistance and lower leakage current, they have been widely used in data centers, aerospace, national defense, energy, communications, automobiles, automation and medical fields, and are expected to completely replace traditional ceramic capacitors in many fields.
[0003] To increase the capacitance density of silicon capacitors, semiconductor deep trench technology can be used to realize 3D silicon capacitors. The deep trenches can be used to increase the area (S) of the capacitor to increase the capacitance density. The withstand voltage of silicon capacitors is proportional to the thickness of the dielectric layer, V BR =E m *e, where V BR is the withstand voltage of silicon capacitor, E m is the avalanche threshold electric field, and e is the thickness of the dielectric layer.
[0004] Capacitance (C) and withstand voltage (V BR ) is inversely proportional. The thicker the dielectric layer, the higher the withstand voltage (V BR ) is higher, but the capacitance (C) is smaller. In order to improve the capacitance density of high-voltage silicon capacitor devices, 3D deep trench technology must be used. However, during the deep trench etching process, lateral drilling, residual bottom defects, rough sidewall surface and burrs are prone to occur at the bottom, which brings challenges to the subsequent dielectric filling. As a result, the bottom of the trench is the weakest position of the device's withstand voltage, which seriously affects the withstand voltage performance, product yield and reliability of high-voltage silicon capacitor devices. Summary of the invention
[0005] The technical problem to be solved by the present disclosure is to overcome the defects of the prior art that multiple problems are likely to occur at the bottom during deep trench etching, resulting in poor voltage resistance and small capacitance, and to provide a high-voltage silicon capacitor and an electronic device.
[0006] The present invention solves the above technical problems through the following technical solutions:
[0007] The present disclosure provides a high-voltage silicon capacitor, the high-voltage silicon capacitor comprising: a plurality of silicon capacitor units;
[0008] The silicon capacitor units are interconnected by stacking;
[0009] Each of the silicon capacitor units includes a plurality of deep through holes etched on the same silicon substrate;
[0010] For each of the deep through holes, a tungsten conductive layer and a dielectric layer are sequentially provided from the central axis to the inner wall;
[0011] The deep through hole is obtained by etching a deep trench using a semiconductor deep trench process, and then thinning the back side of the wafer to remove the bottom of the deep trench.
[0012] Optionally, for each of the deep through holes, a TiN barrier layer is provided between the tungsten conductive layer and the dielectric layer, and another TiN (titanium nitride) barrier layer is provided between the dielectric layer and the inner wall.
[0013] Optionally, the dielectric layer is a NON dielectric layer;
[0014] Along the radial direction of the deep through hole, the NON dielectric layer sequentially includes a SiN (silicon nitride) sublayer, a SiO2 (silicon dioxide) sublayer and another SiN sublayer.
[0015] Optionally, the NON dielectric layer has a thickness of more than 2 μm (micrometer).
[0016] Optionally, the silicon capacitor unit is divided into an upper electrode region and a lower electrode region;
[0017] The upper electrode regions of all the silicon capacitor units overlap up and down, and the lower electrode regions of all the silicon capacitor units overlap up and down;
[0018] An upper electrode plate is provided at the top of each of the deep through holes in the upper electrode region, a lower electrode plate is provided at the top of each of the deep through holes in the lower electrode region, and a lower electrode plate connected to the silicon substrate is provided in each of the lower electrode regions;
[0019] For the silicon capacitor unit at the top layer, an upper electrode is provided to be connected to each of the upper plates, and a lower electrode is provided to be connected to each of the lower plates;
[0020] Two adjacent deep through holes are connected via a metal bump, and each lower electrode connected to the silicon substrate is connected to the bottom of a deep through hole at a corresponding position in the upper silicon capacitor unit via a metal bump.
[0021] Optionally, the number of deep through holes in each of the upper electrode regions is the same, and the projections of the deep through holes in each of the upper electrode regions on the wafer reference plane overlap with each other.
[0022] Optionally, the number of deep through holes in each of the lower electrode regions is the same, and the projections of the deep through holes in two upper and lower adjacent layers of lower electrode regions on the wafer reference plane overlap.
[0023] Optionally, the number of deep through holes in each of the lower electrode regions is the same, and the projections of the deep through holes in two adjacent layers of lower electrode regions do not overlap on the wafer reference plane.
[0024] Optionally, the number of deep through holes in the lower electrode region decreases from top to bottom, and the projection of the deep through holes in the upper lower electrode region in two adjacent layers on the wafer reference plane covers the projection of the deep through holes in the lower lower electrode region on the wafer reference plane.
[0025] The present disclosure also provides an electronic device, which includes the aforementioned high-voltage silicon capacitor.
[0026] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.
[0027] The positive progress effect disclosed in the present invention is that: the silicon capacitor unit achieves the goal of ultra-high voltage by grinding away the arc corners at the bottom of the groove to eliminate the electric field gathering at the bottom arc, thereby improving the voltage resistance and reliability of the silicon capacitor device; at the same time, the NON dielectric layer in the silicon capacitor unit has a higher avalanche threshold electric field and dielectric constant than a single SiO2 dielectric, which can further improve the voltage resistance and capacitance density of the silicon capacitor device, and overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate through the TiN barrier layer; the silicon capacitor units are interconnected by stacking, which greatly improves the capacitance. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 A schematic structural diagram of an example of a high-voltage silicon capacitor provided in Embodiment 1 of the present disclosure;
[0029] Figure 2 A schematic diagram of the structure of a single silicon capacitor unit of a high-voltage silicon capacitor provided in Embodiment 1 of the present disclosure;
[0030] Figure 3 A schematic structural diagram of another example of a high-voltage silicon capacitor provided in Embodiment 1 of the present disclosure;
[0031] Figure 4 A schematic diagram of the structure of another example of a high-voltage silicon capacitor provided in Embodiment 1 of the present disclosure. DETAILED DESCRIPTION
[0032] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.
[0033] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.
[0034] Example 1
[0035] The present invention discloses a high voltage silicon capacitor, referring to Figure 1 , the high voltage silicon capacitor includes: a plurality of silicon capacitor units 10.
[0036] The silicon capacitor units 10 are interconnected by stacking.
[0037] The structural diagram of a single silicon capacitor unit 10 is shown in FIG. Figure 2 As shown, each silicon capacitor unit 10 includes a plurality of deep through holes etched on the same silicon substrate 1 .
[0038] For each deep through hole, a tungsten conductive layer 2 and a dielectric layer 3 are sequentially arranged from the central axis to the inner wall.
[0039] The deep through hole is obtained by etching a deep trench using a semiconductor deep trench process and then thinning the back side of the wafer to remove the bottom of the deep trench.
[0040] Among them, the silicon capacitor in this embodiment can achieve the superposition of no less than 6 silicon capacitor units, and can maximize the capacity of the stacked silicon capacitor units.
[0041] The silicon capacitor unit can be made by the following steps:
[0042] S11. Etching deep trenches on the silicon substrate.
[0043] S12, depositing a dielectric layer, and performing surface planarization processing using a CMP process to remove the dielectric layer on the surface of the wafer.
[0044] S13, depositing a tungsten conductive layer, and performing surface planarization processing using a CMP process to remove the tungsten conductive layer on the surface of the wafer.
[0045] S14, depositing to generate an IMD layer.
[0046] S15, opening a hole in the IMD layer, depositing a tungsten electrode contact layer, and performing surface planarization by a CMP process to remove the tungsten electrode contact layer on the surface of the wafer. The tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate.
[0047] S16, depositing and generating an aluminum / copper conductive layer, wherein a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer.
[0048] S17, thinning the back side of the wafer so that the thickness of the thinned wafer is smaller than the depth of the deep trench.
[0049] In this embodiment, the silicon capacitor unit achieves the goal of ultra-high voltage by grinding away the arc corners at the bottom of the groove to eliminate the electric field gathering at the bottom arc, thereby improving the voltage resistance and reliability of the silicon capacitor device; at the same time, the NON dielectric layer in the silicon capacitor unit has a higher avalanche threshold electric field and dielectric constant than a single SiO2 dielectric, which can further improve the voltage resistance and capacitance density of the silicon capacitor device, and overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate through the TiN barrier layer; the silicon capacitor units are interconnected by stacking, which greatly improves the capacitance.
[0050] In one embodiment, referring to Figure 2 For each deep through hole, a TiN barrier layer 4 is provided between the tungsten conductive layer 2 and the dielectric layer 3, and another TiN barrier layer is provided between the dielectric layer 3 and the inner wall.
[0051] In one embodiment, referring to Figure 2 , dielectric layer 3 is a NON dielectric layer.
[0052] Along the radial direction of the deep through hole, the NON dielectric layer includes a SiN sub-layer 31 , a SiO 2 sub-layer 32 and another SiN sub-layer 31 in sequence.
[0053] In one embodiment, the thickness of the NON dielectric layer is greater than 2 μm.
[0054] The silicon capacitor unit can be made by the following steps:
[0055] S21. Etch a plurality of deep trenches on a silicon substrate using a semiconductor deep trench process.
[0056] S22, depositing a TiN barrier layer on the silicon substrate.
[0057] S23, depositing a SiN sublayer, a SiO2 sublayer and a SiN sublayer in sequence on the TiN barrier layer deposited on the silicon substrate to form a NON dielectric layer; and performing surface planarization treatment using a CMP process to remove the dielectric layer on the wafer surface.
[0058] S24, depositing a TiN barrier layer on the NON dielectric layer.
[0059] S25, depositing a tungsten conductive layer, and performing surface planarization processing using a CMP process to remove the tungsten conductive layer on the surface of the wafer.
[0060] S26, depositing to generate an IMD layer.
[0061] S27, opening a hole in the IMD layer, depositing a tungsten electrode contact layer, and performing surface planarization by a CMP process to remove the tungsten electrode contact layer on the surface of the wafer. The tungsten electrode contact layer includes: a first tungsten electrode contact layer connected to the dielectric layer, and a second tungsten electrode contact layer connected to the silicon substrate.
[0062] S28, depositing and generating an aluminum / copper conductive layer, wherein a section of the aluminum / copper conductive layer is connected to the first tungsten electrode contact layer, and another section of the aluminum / copper conductive layer is connected to the second tungsten electrode contact layer.
[0063] S29, thinning the back side of the wafer so that the thickness of the wafer after thinning is smaller than the depth of the deep trench.
[0064] In one embodiment, the silicon capacitor unit 10 is divided into an upper electrode region and a lower electrode region. Figure 1 , Figure 3 and Figure 4 Three examples of the structure of a silicon capacitor are shown, with the upper electrode region to the left of the dotted line and the lower electrode region to the right of the dotted line.
[0065] The upper electrode regions of all silicon capacitor units 10 overlap each other vertically, and the lower electrode regions of all silicon capacitor units 10 overlap each other vertically.
[0066] An upper electrode plate 20 is provided at the top of each deep through hole in the upper electrode region, a lower electrode plate 30 is provided at the top of each deep through hole in the lower electrode region, and a lower electrode plate 30 connected to the silicon substrate 1 is provided in each lower electrode region.
[0067] For the uppermost silicon capacitor unit, an upper electrode 50 is provided to connect with each upper electrode plate 20 , and a lower electrode 60 is provided to connect with each lower electrode plate 30 .
[0068] Two adjacent deep through holes are connected via a metal bump 40 , and each lower electrode plate 30 connected to the silicon substrate 1 is connected to the bottom of a deep through hole at a corresponding position in the upper silicon capacitor unit via a metal bump 40 .
[0069] In one embodiment, referring to Figure 1 , Figure 3 and Figure 4 The number of deep through holes in each upper electrode region is the same, and the projections of the deep through holes in each upper electrode region on the wafer reference plane overlap with each other.
[0070] In one embodiment, referring to Figure 3 The number of deep through holes in each lower electrode region is the same, and the projections of the deep through holes in the upper and lower adjacent lower electrode regions on the wafer reference plane overlap.
[0071] In one embodiment, referring to Figure 1 The number of deep through holes in each lower electrode region is the same, and the projections of the deep through holes in the upper and lower adjacent lower electrode regions on the wafer reference plane do not overlap.
[0072] Among them, compared with Figure 3 The silicon capacitor in this embodiment has better anti-interference performance, and the capacity of the stacked silicon capacitor unit is maximized.
[0073] In one embodiment, referring to Figure 4 , the number of deep through holes in the lower electrode region decreases from top to bottom, and the projection of the deep through holes in the upper lower electrode region in the two adjacent layers on the wafer reference plane covers the projection of the deep through holes in the lower lower electrode region on the wafer reference plane.
[0074] Among them, compared with Figure 1 and Figure 3 The silicon capacitor in this embodiment has a lower difficulty in stacking the silicon capacitor, but the capacitance of the device is smaller.
[0075] Example 2
[0076] This embodiment provides an electronic device, and the electronic device includes the high-voltage silicon capacitor in Embodiment 1.
[0077] In this embodiment, the silicon capacitor unit achieves the goal of ultra-high voltage by grinding away the arc corners at the bottom of the groove to eliminate the electric field gathering at the bottom arc, thereby improving the voltage resistance and reliability of the silicon capacitor device; at the same time, the NON dielectric layer in the silicon capacitor unit has a higher avalanche threshold electric field and dielectric constant than a single SiO2 dielectric, which can further improve the voltage resistance and capacitance density of the silicon capacitor device, and overcomes the device reliability problem that the SiN sublayer in the NON dielectric layer cannot be attached to the silicon substrate through the TiN barrier layer; the silicon capacitor units are interconnected by stacking, which greatly improves the capacitance.
[0078] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.
Claims
1. A high voltage silicon capacitor, characterized in that: The high-voltage silicon capacitor comprises: a plurality of silicon capacitor units; The silicon capacitor units are interconnected by stacking; Each of the silicon capacitor units includes a plurality of deep through holes etched on the same silicon substrate; For each of the deep through holes, a tungsten conductive layer and a dielectric layer are sequentially provided from the central axis to the inner wall; The deep through hole is obtained by etching a deep trench using a semiconductor deep trench process, and then thinning the back side of the wafer to remove the bottom of the deep trench.
2. The high voltage silicon capacitor according to claim 1, characterized in that: For each of the deep through holes, a TiN barrier layer is disposed between the tungsten conductive layer and the dielectric layer, and another TiN barrier layer is disposed between the dielectric layer and the inner wall.
3. The high voltage silicon capacitor according to claim 1, characterized in that: The dielectric layer is a NON dielectric layer; Along the radial direction of the deep through hole, the NON dielectric layer includes a SiN sublayer, a SiO2 sublayer and another SiN sublayer in sequence.
4. The high voltage silicon capacitor according to claim 3, characterized in that: The thickness of the NON dielectric layer is greater than 2 μm.
5. The high voltage silicon capacitor according to claim 1, characterized in that: The silicon capacitor unit is divided into an upper electrode region and a lower electrode region; The upper electrode regions of all the silicon capacitor units overlap up and down, and the lower electrode regions of all the silicon capacitor units overlap up and down; An upper electrode plate is provided at the top of each of the deep through holes in the upper electrode region, a lower electrode plate is provided at the top of each of the deep through holes in the lower electrode region, and a lower electrode plate connected to the silicon substrate is provided in each of the lower electrode regions; For the silicon capacitor unit at the top layer, an upper electrode is provided to be connected to each of the upper plates, and a lower electrode is provided to be connected to each of the lower plates; Two adjacent deep through holes are connected via a metal bump, and each lower electrode connected to the silicon substrate is connected to the bottom of a deep through hole at a corresponding position in the upper silicon capacitor unit via a metal bump.
6. The high voltage silicon capacitor according to claim 5, characterized in that: The number of the deep through holes in each of the upper electrode regions is the same, and the projections of the deep through holes in each of the upper electrode regions on the wafer reference plane overlap with each other.
7. The high voltage silicon capacitor according to claim 6, characterized in that: The number of deep through holes in each of the lower electrode regions is the same, and the projections of the deep through holes in the upper and lower adjacent layers of lower electrode regions on the wafer reference plane overlap.
8. The high voltage silicon capacitor according to claim 6, characterized in that: The number of deep through holes in each of the lower electrode regions is the same, and the projections of the deep through holes in the upper and lower adjacent layers of lower electrode regions on the wafer reference plane do not overlap.
9. The high voltage silicon capacitor according to claim 6, characterized in that: The number of deep through holes in the lower electrode region decreases from top to bottom, and the projection of the deep through holes in the upper lower electrode region in two adjacent layers on the wafer reference plane covers the projection of the deep through holes in the lower lower electrode region on the wafer reference plane.
10. An electronic device, characterized in that: The electronic device comprises the high-voltage silicon capacitor according to any one of claims 1 to 9.
Citation Information
Cited By
Silicon capacitor and preparation method thereof
CN121013355A