Micro-LED display-oriented driving method and chip

Abstract

The invention discloses a Micro-LED display-oriented driving method and chip, and belongs to the technical field of LED display, and the method comprises the steps: obtaining the total number of pixel points of a to-be-displayed image; according to the total number of the pixel points, the image to be displayed is divided into a plurality of sub-areas, and each sub-area comprises a pixel array composed of a plurality of driving units; transmitting the gray data of each pixel point to the driving unit of the corresponding sub-region through a preset protocol; the driving unit receives a row signal, gray data, reference current and a clock signal as input signals; when a row signal is received, the driving unit converts gray data into a PWM signal, and the duty ratio of the PWM signal is determined by the gray data; and controlling the output time of the reference current according to the PWM signal so as to generate a driving current corresponding to the gray data to drive the pixel point to emit light. Aiming at the problem that a Micro-LED display driving chip in the prior art is high in power consumption, the display uniformity is improved while the power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of LED display technology, and more specifically, to a driving method and chip for Micro-LED display. Background Art

[0002] With the rapid development of information technology, people have higher and higher requirements for the performance of display devices. As a new display technology, Micro-LED is attracting widespread attention in the industry due to its advantages such as high resolution, low power consumption and fast response speed. Micro-LED technology is derived from traditional LED display, but by combining with advanced semiconductor technology, hundreds or thousands of display units are integrated in a unit area, greatly improving its display resolution and fineness.

[0003] However, Micro-LED's high-density pixel array poses a severe challenge to its driving circuit. Traditional LED driver chips are limited by their low integration and are difficult to be directly applied to Micro-LED displays. In order to give full play to the advantages of Micro-LED technology, it is urgent to develop a new type of driver chip that is highly integrated, low-power, and highly reliable. The existing LED driver chips have the following main shortcomings: First, the power consumption is high, which makes it difficult to meet the low power consumption requirements of portable devices; second, the display uniformity is poor, which is prone to problems such as inconsistent brightness and color deviation.

[0004] The Chinese patent application, application number CN202210042636.7, published on April 15, 2022, discloses a highly integrated LED display driver chip with rows and columns, integrating row drive and column drive inside the chip; the chip includes a current reference unit, an image parameter writing unit, an SRAM unit, a configurable register unit, a row switch output array unit, and a column constant current output array unit; the input signal is sent to the current reference unit and the image parameter writing unit, passes through the SRAM unit and the configurable register unit, and is output under the control of the row switch output array unit and the column constant current output array unit. However, this scheme mainly adopts a global constant current driving method, that is, the same driving current is provided to all pixels through the column constant current output array unit, ignoring the differences in electrical characteristics between different pixels, resulting in the need to further improve the uniformity of pixel brightness. Summary of the invention

[0005] 1. Technical problems to be solved

[0006] In response to the problem of high power consumption of Micro-LED display driver chips in the prior art, the present application provides a driving method and chip for Micro-LED display. By dividing the pixel unit and the driving unit into multiple sub-areas and configuring an independent protocol interface for each sub-area, parallel transmission of grayscale data is achieved, thereby reducing power consumption. At the same time, by collecting temperature signals at different positions on the chip and dynamically adjusting the brightness of the pixel unit according to the temperature difference, the display uniformity is improved. A two-stage trigger is used to generate a PWM signal to accurately control the conduction time of the driving transistor, thereby reducing power consumption and improving display uniformity.

[0007] 2. Technical solution

[0008] The purpose of this application is achieved through the following technical solutions.

[0009] One aspect of the present application provides a driving method for Micro-LED display, including: obtaining the total number of pixels of an image to be displayed; dividing the image to be displayed into multiple sub-areas according to the total number of pixels, each sub-area comprising a pixel array composed of multiple driving units; transmitting the grayscale data of each pixel to the driving unit of the corresponding sub-area through a preset protocol; the driving unit receives a row signal, grayscale data, a reference current and a clock signal as input signals; when receiving the row signal, the driving unit converts the grayscale data into a PWM signal, and the duty cycle of the PWM signal is determined by the grayscale data; controlling the output time of the reference current according to the PWM signal, thereby generating a driving current corresponding to the grayscale data, and driving the pixel to emit light.

[0010] Furthermore, generating a driving current also includes: detecting whether a row signal is received: if a row signal is not received, setting a control signal SELB to a high level, writing grayscale data into a first register and a second register, and setting an output end of the register to a high level or a low level according to the grayscale data; wherein the first register and the second register are used to temporarily store grayscale data; if a row signal is received, setting a control signal SEL to a high level, and setting a SET signal to a low level at the same time, controlling the first switch tube PM1 and the second switch tube PM2 to be disconnected, and the third switch tube PM3 to be turned on; and causing the reference current to be output to the driving current end via the third switch tube PM3.

[0011] Among them, SELB is a control signal used to control the working state of the driving unit. When the driving unit does not receive the row signal, the SELB signal is set to a high level, and the driving unit enters the data writing state, and the grayscale data transmitted externally is written into the first register and the second register, and the data output end of the register is set to a corresponding high level or low level according to the value of the grayscale data. SEL is also a control signal, which has the opposite function to SELB. When the driving unit receives the row signal, the SEL signal is set to a high level, and the driving unit enters the working state, the first switch tube PM1 and the second switch tube PM2 are controlled to be disconnected, and the third switch tube PM3 is turned on, so that the reference current is output to the driving current end via PM3, and the pixel point is driven to emit light. The SET signal is used to control the conduction state of the switch tube in the driving unit. When the driving unit receives the row signal, the SET signal is set to a low level, and cooperates with the SEL signal to control PM1 and PM2 to be disconnected and PM3 to be turned on.

[0012] PM1 is a switch tube in the drive unit, which is connected in series with the second switch tube PM2 on the output path of the reference current. PM1 is controlled by the SEL signal and the SET signal. When SEL is at a low level, PM1 is turned on, and when SEL is at a high level and SET is at a low level, PM1 is turned off. The cooperation of PM1 and PM2 is used to control whether the reference current is output to the drive current end. PM2 is connected in series with PM1, and its control method is the same as PM1. When both PM1 and PM2 are disconnected, the reference current is blocked and cannot be output to the drive current end. PM3 is another switch tube in the drive unit, which is connected in parallel with PM1 and PM2. When SEL is at a high level and SET is at a low level, PM3 is turned on, so that the reference current is output to the drive current end through PM3. When the CLK_PWM signal coincides with the rising edge of the clock CLK, PM3 is turned off and the output of the drive current is stopped.

[0013] Furthermore, if the driving unit receives a row signal, before setting the SEL signal to a high level, the method further includes: counting the number of cycles of the clock signal CLK by a counter; and when the count value is greater than 2, setting the control signal SEL to a high level.

[0014] Among them, CLK is a clock signal in the driving unit, which is used to control the working rhythm and timing of each sub-unit in the driving unit. It is a periodic square wave signal, which plays a role in synchronization and timing during the working process of the driving unit. When the driving unit receives the row signal, the counter starts to count the number of cycles of CLK. Every time CLK completes a complete cycle, the count value of the counter will increase by 1. This process continues until the count value reaches a preset threshold (2 in the scheme). When the count value of the counter is greater than the preset threshold (2), the control signal SEL is set to a high level, and the driving unit officially enters the working state. The purpose of this is to give the driving unit a certain response time after receiving the row signal, and wait until its internal circuit state is stable before starting to work, so as to improve the reliability of the work. The clock signal CLK is also used to generate a PWM control clock signal CLK_PWM. When CLK_PWM coincides with the rising edge of CLK, it means that a PWM cycle ends, the output end of the D flip-flop is set to a low level, PM3 is turned off, and the output of the driving current stops. In this way, the control of the driving current pulse width using the PWM signal is realized. The CLK signal is also used to generate a clock signal CLK1 synchronized with it. When the control signal SELB is set to a low level, CLK1 is synchronized with CLK to provide a working clock for the series-connected D flip-flops, so that the grayscale data stored in the register can be read in sequence, shifted, and finally output a PWM signal.

[0015] Furthermore, it also includes: the driving unit determines the rising edge of the clock CLK through the CLK_PWM signal; when the CLK_PWM signal coincides with the rising edge of the clock CLK, a preset low level is written into the data input terminal of the D flip-flop, and a low level is output at the output terminal Q of the D flip-flop, thereby turning off the third switch PM3 and stopping the output of the driving current; the control signal SELB is set to a low level, so that the clock signal CLK1 is synchronized with the input clock CLK, and the output terminals of the first register and the second register are set to a high level; through a plurality of series-connected D flip-flops, according to the clock signal CLK1, the grayscale data stored in the first register and the second register are read in sequence, and the grayscale data is converted into a PWM signal output by shifting.

[0016] Among them, CLK_PWM is a PWM control clock signal, which is used to determine the rising edge of the clock signal CLK. When the CLK_PWM signal coincides with the rising edge of CLK, it means that a PWM cycle ends. At this time, a preset low level needs to be written into the data input of the D flip-flop, so that its output Q outputs a low level, thereby turning off the third switch tube PM3 and stopping the output of the drive current. The period of the CLK_PWM signal determines the period of the PWM signal, and then determines the pulse width of the drive current. The D flip-flop is a common sequential logic circuit, which is used to generate a PWM signal in this scheme. It has a data input terminal D and a clock input terminal. When the rising edge of the clock signal arrives, the level state of the D terminal is transmitted to the output terminal Q. By connecting multiple D flip-flops in series and connecting the output terminal of the upper-level D flip-flop to the input terminal of the next-level D flip-flop in turn when each clock rising edge arrives, data shifting can be achieved, and finally a PWM signal is output. The duty cycle of the PWM signal depends on the data (grayscale data) written into the D flip-flop.

[0017] CLK1 is a clock signal synchronized with the clock signal CLK, and provides a working clock for the serially connected D flip-flops. When the control signal SELB is set to a low level, CLK1 is synchronized with CLK, so that the D flip-flop can read the grayscale data stored in the first register and the second register in turn at each rising edge of CLK, and convert it into a PWM signal output through a shift operation. The frequency of CLK1 determines the resolution of the PWM signal. The first register and the second register are memories in the drive unit for temporarily storing grayscale data. When the SELB signal is at a high level, the input grayscale data is written into these two registers. When the SELB signal is at a low level, the output end of the register is set to a high level, so that the stored grayscale data can be read by the serially connected D flip-flops. By alternating the two registers, it is possible to receive the grayscale data of the next frame in advance without affecting the current display, thereby improving the display efficiency.

[0018] In this scheme, when the CLK_PWM signal coincides with the rising edge of CLK, the preset low level is written into the D flip-flop, the output terminal Q becomes low level, PM3 is turned off, the output drive current stops, and a PWM cycle ends. At the same time, the SELB signal is set to a low level, CLK1 is synchronized with CLK, and the output terminals of the first and second registers are set to a high level, so that the stored grayscale data can be read out and shifted in sequence through the series-connected D flip-flops, and finally a new PWM signal is output to start a new display cycle.

[0019] Furthermore, a PWM signal is generated according to the clock signal CLK1, including: a driving unit sets the control signal SELB to a low level to synchronize the clock signal CLK1 with CLK; and at the same time, the data output terminals of the first register and the second register are set to a high level; starting from the first D flip-flop, at the rising edge of each clock signal CLK1: the output terminal Q of the previous level D flip-flop is used as the data input terminal of the current level D flip-flop, and the level state of the input terminal of the current level D flip-flop is transferred to the output terminal Q as the data input terminal of the next level D flip-flop; and so on, until the last level D flip-flop, the PWM signal is output through the output terminal Q of the last level D flip-flop.

[0020] Among them, in the D flip-flop, the Q terminal is the output terminal of the flip-flop. When the rising edge of the clock signal arrives, the D flip-flop transfers the level state of the data input terminal D to the output terminal Q, and maintains this state until the next clock rising edge arrives. In this scheme, multiple D flip-flops are connected in series to form a shift register, which is used to convert parallel grayscale data into a serial PWM signal. The specific working process is as follows: when the control signal SELB is set to a low level, the clock signal CLK1 is synchronized with CLK to provide a working clock for the D flip-flop; at the same time, the data output terminals of the first register and the second register are set to a high level, so that the stored grayscale data can be read by the D flip-flop. When the rising edge of the first clock CLK1 arrives, the first D flip-flop reads the output of the first register (the first grayscale data) into the data input terminal D, and transfers it to the output terminal Q when the next CLK1 rising edge arrives. The output terminal Q of the first D flip-flop is connected to the data input terminal D of the second D flip-flop. When the next CLK1 rising edge arrives, the second D flip-flop reads the state of Q (the first grayscale data) and transfers it to its own output terminal Q when the next CLK1 rising edge arrives. Similarly, when each rising edge of CLK1 arrives, the grayscale data shifts in the D flip-flop chain in sequence until the last D flip-flop. The output terminal Q of the last D flip-flop outputs the PWM signal. The duty cycle of the PWM signal depends on the grayscale data written into the D flip-flop. If the grayscale data is high, the PWM signal is high during the clock cycle; otherwise, it is low. By controlling the proportion of high levels in the grayscale data, the duty cycle of the PWM signal can be adjusted, and then the brightness of the pixel can be adjusted.

[0021] Furthermore, the preset protocol is the QSPI protocol. Among them, QSPI (Quad Serial Peripheral Interface) is a high-speed serial communication protocol, which is commonly used for data transmission between processors and peripherals. It is an extension of the SPI (Serial Peripheral Interface) protocol, and can achieve a higher data transmission rate by using four data lines (SPI only uses one).

[0022] Furthermore, the number of triggers connected in series corresponds one-to-one to the number of bits of the grayscale data.

[0023] Furthermore, in each driving unit, the row signal, grayscale data, reference current, and clock signal are received through independent input ports.

[0024] Furthermore, the driving method also includes: setting a temperature sensor on the Micro-LED to collect the temperature of different areas, and adjusting the grayscale data of different areas of the Micro-LED according to the temperature.

[0025] Another aspect of the embodiment of the present application further provides a driver chip for Micro-LED display, including: multiple parallel driving units, each driving unit corresponds to a pixel point, and generates a driving current according to the grayscale data of the pixel point to drive the pixel point to emit light; wherein the multiple driving units form a pixel array, the multiple pixel arrays form a sub-area, and the multiple sub-areas form a display area; a row signal generating unit, generating a row signal and transmitting the row signal to the driving unit of each row; a data transmission unit, transmitting the grayscale data of each pixel point to the corresponding driving unit through the QSPI protocol; a clock generating unit, generating a clock signal CLK, a PWM control clock signal CLK_PWM and a clock signal synchronized with CLK signal CLK1, and transmit the clock signal to the driving unit respectively; a reference current generating unit, generates a constant reference current, and transmits the reference current to the driving unit; a temperature correction unit, collects the temperature data of the Micro-LED display area, and corrects the grayscale data of different areas according to the temperature data; wherein each driving unit includes: a first register and a second register, temporarily storing grayscale data; a first switch tube PM1, a second switch tube PM2 and a third switch tube PM3, controlling the output of the reference current; a counter, counting the clock signal CLK; a plurality of D flip-flops connected in series, the number of the D flip-flops is the same as the number of bits of the grayscale data, and the plurality of D flip-flops connected in series convert the grayscale data into a PWM signal.

[0026] 3. Beneficial effects

[0027] Compared with the prior art, the advantages of this application are:

[0028] Existing Micro-LED driver chips usually adopt a centralized data transmission and processing architecture, and the grayscale data of all pixel units need to be transmitted serially through a single interface, resulting in long transmission time and high power consumption. This application divides the display area into multiple sub-areas, and each sub-area is configured with an independent QSPI interface, which can realize the parallel transmission of grayscale data between multiple sub-areas. This distributed data transmission architecture greatly shortens the data transmission time of a single pixel and reduces the power consumption during the transmission process. At the same time, multiple drive units in each sub-area can also work in parallel, further reducing the workload and power consumption per unit time.

[0029] Due to the tiny pixel size, Micro-LED is more sensitive to factors such as chip technology and material properties, and is prone to uneven display problems. This application integrates a temperature sensor array on the chip, which can collect temperature data from different areas in real time. Since temperature will affect the luminous efficiency of Micro-LED, the pixel grayscale values ​​in different areas can be dynamically compensated according to the temperature difference between areas, thereby improving the display uniformity between areas. At the same time, this application also proposes an improved PWM signal generation method. Traditional PWM signals are directly generated by counters, and have limitations in resolution and linearity. This application uses a two-stage D flip-flop to first convert the grayscale data into a bit string of high and low levels, and then output the PWM waveform through a shift register. This method can achieve higher PWM resolution, and the linearity between each grayscale level is better, which helps to improve display uniformity.

[0030] Increasing the display refresh rate and reducing power consumption are often contradictory. A higher refresh rate means that more data needs to be transmitted per unit time, and power consumption will increase accordingly. The present application sets up dual registers in each driver unit, which can receive the grayscale data of the next subframe in advance when the current subframe is displayed. By using the subframe gap to complete data transmission and storage in advance, the transmission time within the unit subframe can be shortened, and low instantaneous power consumption can still be maintained without reducing the refresh rate. In addition, the present application further reduces power consumption by optimizing the QSPI protocol, adopting dual-channel transmission, and increasing the clock frequency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is an exemplary flow chart of a driving method for Micro-LED display of the present application;

[0032] Figure 2 This is a schematic diagram of the driver chip driving array of the present application;

[0033] Figure 3 It is a schematic diagram of the framework of a single drive unit;

[0034] Figure 4It is a schematic diagram of the circuit implementation of a single drive unit;

[0035] Figure 5 This is the working timing diagram of a single drive unit;

[0036] Figure 6 It is a schematic diagram of the row and column integrated driver chip;

[0037] Figure 7 This is the structural block diagram of the temperature sensor. DETAILED DESCRIPTION

[0038] The present application is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0039] Example 1

[0040] Figure 1 This is an exemplary flow chart of a driving method for Micro-LED display of the present application, including: obtaining the total number of pixels of an image to be displayed; dividing the image to be displayed into multiple sub-areas according to the total number of pixels, each sub-area comprising a pixel array composed of multiple driving units; transmitting the grayscale data of each pixel to the driving unit of the corresponding sub-area through a preset protocol; the driving unit receives a row signal, grayscale data, a reference current and a clock signal as input signals; when receiving the row signal, the driving unit converts the grayscale data into a PWM signal, and the duty cycle of the PWM signal is determined by the grayscale data; controlling the output time of the reference current according to the PWM signal, thereby generating a driving current corresponding to the grayscale data, and driving the pixel to emit light.

[0041] A driver chip for Micro-LED display, the total number of dots in the chip is 12960, and it is divided into 16 sub-areas to achieve efficient parallel transmission. Each sub-area corresponds to a pixel array, which contains 12960 driver units. The chip uses the QSPI (Quad Serial Peripheral Interface) protocol to transmit data independently to each sub-area, that is, the brightness data of the pixel is transmitted in parallel through 16 data lines, which improves the data throughput and transmission rate; Figure 2 The overall architecture diagram of the chip is given. The 16 sub-areas are marked as area 1 to area 16, and each sub-area is equipped with an independent QSPI interface, which can receive data instructions from the external MCU (Micro Control Unit) separately. This sub-area parallel transmission design can give full play to the potential of the Micro-LED high-density array, while ensuring the refresh rate and reducing the transmission power consumption.

[0042] Figure 3The structural diagram of a single driving unit is shown. Each driving unit corresponds to a pixel, including a row selection circuit, a storage circuit, a PWM generation circuit, a driving circuit, and a temperature compensation circuit. Among them, the row selection circuit is used to receive the row signal, and when the row signal is valid, all the driving units of the row are started; the storage circuit is used to temporarily store the grayscale data from the QSPI interface; the PWM generation circuit generates a PWM waveform with a specific duty cycle according to the grayscale data and the clock signal; the driving circuit further converts the PWM signal into a constant current driving current with adjustable amplitude and applies it to the corresponding Micro-LED device; the temperature compensation circuit can adjust the driving current bias in real time according to the value of the temperature sensor.

[0043] The driver chip of this embodiment uses 8-bit grayscale data, that is, each pixel has 256 levels of adjustable brightness. This is achieved through fine control of the PWM duty cycle. In theory, 2^8=256 PWM waveforms with different duty cycles can be generated, corresponding to 256 different brightness levels. The higher the grayscale level, the greater the PWM duty cycle, the greater the average value of the drive current, and the higher the pixel brightness. In addition, each drive unit introduces a reference current input to provide an initial bias for the drive current. The reference current can be configured through an external circuit during the chip initialization phase to adapt to different process conditions and display applications. The size of the reference current affects the basic brightness of the pixel point and is generally set to a smaller value to reduce power consumption. The clock signal provides synchronization timing for the entire chip and controls the working timing of each drive unit. In practical applications, the clock frequency can be adjusted according to the dynamic range and refresh rate requirements of the display content to balance power consumption and display quality.

[0044] This driving method takes a four-bit grayscale data as an example. Figure 4 As shown, the driving unit is mainly composed of a trigger circuit, a bias circuit and a driving circuit. Among them, the first-level trigger circuit includes a D trigger and a NAND gate, which are used to control the start and stop of the driving circuit; the second-level trigger circuit includes 4 D triggers, which are used to generate PWM signals according to grayscale data and modulate the pulse width of the driving current.

[0045] Before the row signal arrives, the SELB signal is high. At this time, the input terminals S<3:0> and R<3:0> of the second-stage flip-flop circuit are set to the high and low level combination corresponding to the grayscale data. Taking 4-bit grayscale as an example, the grayscale data "0000" corresponds to no brightness, "1111" corresponds to the brightest, and other values ​​correspond to 16 grayscale levels in sequence. S<3:0> and R<3:0> pass the grayscale data to the reset and set terminals of the corresponding D flip-flop, and control its Q terminal to output high or low level.

[0046] When the row signal arrives, after two clock cycles, the SEL signal is pulled high, and the SET signal is briefly set low. This negative pulse signal sets the Q end of the D flip-flop to "1" and the Qn end to "0". At the same time, CLK1 controlled by the SEL signal begins to synchronize with the system clock CLK as the working clock of the series flip-flop; S<3:0> and R<3:0> controlled by the SELB signal are all set to high level "1", so that the second-stage flip-flop works in normal mode. Make EN high and ENB low. In this way, PM1 is turned off and PM2 is turned on, so that the bias signal Vbias is connected to the driving transistor PM3. Vbias provides a constant bias voltage, and PM3 enters the saturation region to work, thereby outputting a constant drive current at the Iout port to light up the Micro-LED device.

[0047] When the next CLK_PWM clock rising edge arrives, the input "0" of the first-stage D flip-flop is sampled to the Q terminal, EN becomes low and ENB becomes high, PM3 is turned off, and the drive current stops outputting.

[0048] Next, at each rising edge of CLK1, the second-level trigger circuit starts shifting and reading the grayscale data stored in the D flip-flop, generating a PWM waveform bit by bit. For example, for the grayscale data "1110", Q<3:0> are all high at the beginning. At the first rising edge of CLK1, the highest bit "1" is shifted and output, and PWM remains high; at the second and third rising edges of CLK1, "1" continues to shift and output, and PWM continues to be high; until the fourth rising edge of CLK1, the lowest bit "0" is shifted and output, and PWM becomes low. It can be seen that the duration of the high level of PWM is proportional to the number of "1" in the grayscale data. The PWM signal controls the on-time of PM3, thereby adjusting the lighting duration of the Micro-LED to achieve brightness modulation.

[0049] like Figure 5 As shown in the figure, assuming that the input 4-bit grayscale data is "1111", it means that full brightness display is required. Before the rising edge of CLK1 arrives, the PWM signal and CLK2, CLK3, and CLK4 are all preset to high level "1". This means that the driving transistor PM3 is in the on state and the Micro-LED is initially lit.

[0050] When the first CLK1 rising edge arrives, the input terminal D of the first-stage D flip-flop receives the highest-bit grayscale data "1", and transmits it to the Q terminal at the next CLK1 rising edge, so that CLK2 changes from "1" to "0". The falling edge of CLK2 triggers the second-stage D flip-flop, so that its input terminal D receives the second-highest-bit grayscale data "1".

[0051] Similarly, when the next rising edge of CLK1 arrives, the second-stage D flip-flop transfers "1" to the Q terminal, changing CLK3 from "1" to "0". The falling edge of CLK3 triggers the third-stage D flip-flop, causing its input terminal D to receive the second lowest grayscale data "1".

[0052] By analogy, each rising edge of CLK1 will trigger the shift and transfer of one grayscale data level, and the corresponding CLKx signal (x=2, 3, 4) will also generate a falling edge. The PWM signal will not become "0" until the last grayscale data "1" is transferred to CLK5.

[0053] During the whole process, the PWM signal remains high for 4 CLK1 cycles, corresponding to the maximum brightness. If the grayscale data is "1110", the PWM signal will become "0" in the 4th CLK1 cycle, corresponding to the second highest brightness. It can be seen that the number of "1" in the grayscale data determines the high-level duration of the PWM signal, thereby adjusting the lighting duration of the Micro-LED.

[0054] When the rising edge of CLK5 arrives, the ENB signal is pulled high, PM1 is turned on and PM2 is turned off, cutting off the bias of the bias signal Bias on PM3 and turning it off. At this time, the drive current stops outputting, the drive unit goes out, and the display cycle ends. Figure 5 Only the special case of 1111 full brightness is shown. For other grayscale data, the high level duration of PWM will be different, but the control principle and timing process are similar. In addition, the timing circuit is completely composed of D flip-flops, which use their clock synchronization and shift characteristics to achieve automatic conversion and transmission of grayscale data, avoid complex control logic, and simplify circuit design.

[0055] Example 2

[0056] This embodiment proposes an on-chip temperature compensation solution, which integrates temperature sensors at the four corners of the chip to monitor the temperature distribution of the chip in real time and adjust the LED drive current according to the temperature change, thereby improving the display quality. The specific implementation is as follows: Figure 6 As shown in the figure, an on-chip temperature sensor is placed at each of the four corners of the driver chip. This distributed sensor layout can comprehensively monitor the temperature distribution of the chip and promptly detect temperature anomalies in local areas. When the temperature of different areas of the chip changes, the corresponding sensor will convert the temperature information into an electrical signal and output it to the control system.

[0057] Based on the received temperature data, the control system calculates the temperature distribution of the LED array and the brightness compensation value required for each area. Then, the control system converts the compensation value into the corresponding bias voltage or current, and dynamically changes the driving current of the LED by adjusting the V bias signal of each driving unit, thereby offsetting the brightness deviation caused by temperature changes and ensuring display uniformity.

[0058] Figure 7 The detailed structure of the temperature sensor is given. It mainly consists of three parts: temperature sensing circuit, amplifier module and ADC. Among them, the temperature sensing circuit is a temperature-dependent resistor network, and its output voltage changes with temperature; the amplifier module is responsible for amplifying the tiny temperature signal to a suitable amplitude range; the ADC quantizes the analog temperature signal into a digital value for easy control system processing.

[0059] Temperature sensing circuits usually use silicon-based integrated resistors, using the temperature coefficient effect of silicon materials to build a voltage divider circuit that changes with temperature. When the temperature rises, the silicon resistance value decreases, and the output voltage of the temperature sensing circuit decreases; when the temperature decreases, the opposite is true.

[0060] The amplifier module is generally composed of a multi-stage operational amplifier, which uses appropriate resistor negative feedback to amplify the millivolt-level temperature signal to the volt level. In order to reduce the impact of offset and noise, the amplifier circuit needs to use modulation techniques such as chopping or chopping to modulate the DC signal to a higher frequency, and then obtain the amplified temperature DC signal through demodulation and filtering.

[0061] The ADC uses a successive approximation architecture, which determines the digital quantization value of the input signal bit by bit through a series of comparison and approximation operations. SAR ADC has the advantages of fast conversion speed, low power consumption, and moderate accuracy, and is particularly suitable for on-chip temperature sensing applications. This embodiment uses an 8-bit SAR ADC, which can provide 256 levels of temperature resolution, meeting the requirements of most applications.

[0062] The specific implementation is as follows: The temperature sensing circuit adopts a PTAT (Proportional To Absolute Temperature) structure based on a PNP transistor. Figure 6 As shown in the figure, two currents with integer current proportional coefficients flow through two identical PNP transistors, generating two voltage signals at their emitters. According to the transistor's volt-ampere characteristic equation, the difference between the two voltage signals is linearly related to the absolute temperature, and its slope is determined by the current ratio and the physical parameters of the transistor. Therefore, by detecting this differential voltage, a voltage signal proportional to the temperature can be obtained. Compared with the conventional PN junction temperature sensing method, this circuit has good linearity and consistency, and is easy to integrate.

[0063] In order to facilitate the quantization processing of the subsequent ADC, it is necessary to amplify the tiny signal output by the temperature sensing circuit. This design uses a fully differential switched capacitor operational amplifier to perform 20 times differential amplification of the input signal under the control of two-phase non-overlapping clocks. Compared with single-ended amplification, the fully differential structure has a stronger ability to suppress common-mode noise and power supply noise, which helps to improve the signal-to-noise ratio. At the same time, the reasonable design of the capacitor ratio and clock phase can make the amplified signal amplitude just correspond to the quantization range of the ADC, simplifying the interface circuit. The simulation results show that the amplifier module can amplify the temperature sensing signal corresponding to 1°C to the same value as 1LSB (Least Significant Bit) of the ADC, thereby achieving the best match between temperature detection accuracy and ADC resolution.

[0064] The ADC part uses an 8-bit successive approximation architecture. It completes the digital conversion of analog signals within 8 clock cycles by binary search. Considering that the temperature changes slowly and the conversion rate is not required, synchronous SAR logic is used to reduce circuit complexity and power consumption. The 8-bit resolution can quantize the temperature range of -40℃ to 125℃ into 256 levels, and the corresponding temperature resolution is better than 0.5℃, which fully meets the design indicators.

[0065] The invention of the present application and its implementation methods are described schematically above. The description is not restrictive. Without departing from the spirit or basic features of the present application, the present application can be implemented in other specific forms. What is shown in the accompanying drawings is only one of the implementation methods of the invention of the present application. The actual structure is not limited to this. Any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by it, without departing from the purpose of the present invention, a structural method and an embodiment similar to the technical solution are designed without creativity, which should all fall within the scope of protection of this patent. In addition, the word "including" does not exclude other elements or steps, and the word "one" before the element does not exclude the inclusion of "multiple" elements. The multiple elements stated in the product claim can also be implemented by one element through software or hardware. The words first, second, etc. are used to indicate names, and do not indicate any specific order.

Claims

1. A driving method for Micro-LED display, characterized in that: include: Get the total number of pixels of the image to be displayed; According to the total number of pixels, the image to be displayed is divided into a plurality of sub-areas, each of which includes a pixel array composed of a plurality of driving units; Transmitting the grayscale data of each pixel to the driving unit of the corresponding sub-area through a preset protocol; The driving unit receives a row signal, grayscale data, a reference current and a clock signal as input signals; When receiving the row signal, the driving unit converts the grayscale data into a PWM signal, and the duty cycle of the PWM signal is determined by the grayscale data; the output time of the reference current is controlled according to the PWM signal, thereby generating a driving current corresponding to the grayscale data to drive the pixel to emit light.

2. The driving method for Micro-LED display according to claim 1, characterized in that: Generating a driving current corresponding to the grayscale data, further comprising: Check whether the line signal is received: If the row signal is not received, the control signal SELB is set to a high level, the grayscale data is written into the first register and the second register, and the output end of the register is set to a high level or a low level according to the grayscale data; wherein the first register and the second register are used to sample the grayscale data and send it to the set end and the reset end of the second-stage trigger; If a row signal is received, the control signal SEL is set to a high level, and the SET signal is briefly set to a low level, so that the first switch tube PM1 is controlled to be disconnected and the second switch tube PM2 is turned on, so that the bias signal is connected to the gate of the third switch tube PM3; the reference current is output to the driving current terminal through the third switch tube PM3.

3. The driving method for Micro-LED display according to claim 2, characterized in that: If the driving unit receives a row signal, before setting the SEL signal to a high level, it also includes: The number of cycles of the clock signal CLK is counted by a counter; when the count value is greater than 2, the control signal SEL is set to a high level.

4. The driving method for Micro-LED display according to claim 3, characterized in that: Also includes: The drive unit synchronizes the rising edge of the clock CLK through the CLK_PWM signal; When the rising edge of the CLK_PWM signal synchronization clock CLK coincides, the preset low level is transmitted to the D flip-flop, and a low level is output at the output terminal Q of the D flip-flop, thereby turning off the third switch PM3 and stopping the output of the driving current; The control signal SELB is set to a low level, so that the clock signal CLK1 is synchronized with the input clock CLK, and the output terminals of the first register and the second register are set to a high level; Through a plurality of serially connected D flip-flops, the grayscale data stored in the grayscale data stored in the second-stage flip-flop is read and transmitted in sequence according to the clock signal CLK, and the grayscale data is converted into a PWM signal output through a counter.

5. The driving method for Micro-LED display according to claim 4, characterized in that: Generate PWM signal according to grayscale data, including: The driving unit sets the control signal SEL to a high level and SELB to a low level to synchronize the clock signal CLK1 with CLK; at the same time, the data output terminals of the first register and the second register are set to a high level; Starting from the first D flip-flop, at each rising edge of the clock signal CLK1: The output terminal Q of the previous stage D flip-flop is used as the data input terminal of the current stage D flip-flop, and the level state of the input terminal of the current stage D flip-flop is transferred to the output terminal Q as the data input terminal of the next stage D flip-flop; And so on until the last stage of D flip-flop, the PWM signal is output through the output terminal Q of the last stage of D flip-flop.

6. The driving method for Micro-LED display according to claim 5, characterized in that: The default protocol is QSPI protocol.

7. The driving method for Micro-LED display according to claim 6, characterized in that: The number of flip-flops connected in series corresponds one-to-one to the number of bits of the grayscale data.

8. The driving method for Micro-LED display according to claim 7, characterized in that: In each driving unit, the row signal, grayscale data, reference current, and clock signal are received through independent input ports.

9. The driving method for Micro-LED display according to claim 8, characterized in that: The driving method further includes: By setting a temperature sensor on the Micro-LED, the temperature of different areas is collected, and the grayscale data of different areas of the Micro-LED is adjusted according to the temperature.

10. A driver chip for Micro-LED display, characterized in that: include: A plurality of parallel driving units, each driving unit corresponds to a pixel point, and generates a driving current according to the grayscale data of the pixel point to drive the pixel point to emit light; wherein the plurality of driving units form a pixel array, the plurality of pixel arrays form a sub-area, and the plurality of sub-areas form a display area; A row signal generating unit, generating a row signal and transmitting the row signal to a driving unit of each row; The data transmission unit transmits the grayscale data of each pixel to the corresponding driving unit through the QSPI protocol; A clock generating unit, generating a clock signal CLK, a PWM control clock signal CLK_PWM and a clock signal CLK1 synchronized with CLK, and transmitting the clock signals to the driving unit respectively; A reference current generating unit generates a constant reference current and transmits the reference current to the driving unit; The temperature correction unit collects the temperature data of the Micro-LED display area and corrects the grayscale data of different areas based on the temperature data; Each drive unit includes: The first register and the second register temporarily store grayscale data; The first switch tube PM1, the second switch tube PM2 and the third switch tube PM3 control the output of the reference current; A counter for counting the clock signal CLK; A plurality of D flip-flops connected in series, the number of which is the same as the number of bits of the grayscale data, convert the grayscale data into a PWM signal.

Images