Bandgap reference circuit, reference voltage source, and reference voltage generation method

Abstract

The embodiments of the present invention disclose a bandgap reference circuit, a reference voltage source, and a reference voltage generation method. The circuit includes a current module, a differential input module, a limit module, a feedback module, and a voltage divider module. The differential input module generates a first conduction current and a second conduction current in response to a first voltage signal and a second voltage signal of the voltage divider module, respectively, and further outputs a first output current and a second output current, respectively. The limit module outputs a drive signal in response to the first output current and the second output current to control the feedback module to adjust the first voltage signal and the second voltage signal so that the first output current and the second output current are equal, so that the differential input module outputs a reference voltage with a zero temperature coefficient. The limit module includes a matching resistor or a low transconductance switch tube to reduce the offset voltage. The present invention reduces the offset voltage of the limit module and improves the accuracy of the reference voltage by setting a matching resistor or a low transconductance switch tube in the limit module.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of integrated circuits, and in particular to a bandgap reference circuit, a reference voltage source, and a reference voltage generating method. Background Art

[0002] Bandgap reference circuits, as fundamental building blocks, play an extremely important role in analog and hybrid analog circuits. They generate a reference voltage that remains stable despite variations in temperature, power supply voltage, process technology, and other parameters. The accuracy of a bandgap reference circuit directly impacts many parameters of the chip in which it resides. Therefore, the design of a bandgap reference circuit is crucial for any chip.

[0003] However, most existing technologies use a single operational amplifier to control the bandgap reference circuit loop, which complicates the circuit structure of the bandgap reference circuit. Furthermore, the offset voltage of the operational amplifier reduces the accuracy of the reference voltage output by the bandgap reference circuit. Summary of the Invention

[0004] The main technical problem solved by the embodiments of the present invention is to provide a bandgap reference circuit, a reference voltage source and a reference voltage generation method, which can reduce the influence of the offset voltage on the accuracy of the reference voltage.

[0005] In order to solve the above technical problems, a technical solution adopted in an embodiment of the present invention is: to provide a bandgap reference circuit, comprising: a current module, a differential input module, a limit module, a feedback module and a voltage divider module, wherein the current module is connected to an input power supply and the differential input module, and the current module is used to provide current to the differential input module; the limit module is connected to the feedback module and the differential input module, and the feedback module is connected to the input power supply; the differential input module is configured to generate a first conduction current and a second conduction current respectively in response to a first voltage signal and a second voltage signal of the voltage divider module, and to conduct and output the first output current and the second output current respectively; the limit module outputs a drive signal to the feedback module in response to the first output current and the second output current to adjust the output current of the feedback module, and the output current enables the voltage divider module to generate the first voltage signal and the second voltage signal; when the first output current and the second output current are equal, the differential input module outputs a reference voltage with a zero temperature coefficient; the limit module includes a matching resistor or a low transconductance switch tube to reduce the offset voltage, and the transconductance of the low transconductance switch tube is smaller than the transconductance of the transistor of the differential input module.

[0006] In some embodiments, the limit module includes a switch tube M1, a switch tube M2, a switch tube M3 and a switch tube M5, the drain of the switch tube M1 is connected to the gate of the switch tube M3 and the first output end of the differential input module, the gate of the switch tube M1 is connected to the gate of the switch tube M2, the drain of the switch tube M2 and the second output end of the differential input module, the source of the switch tube M1, the source of the switch tube M2 and the source of the switch tube M3 are grounded; the gate of the switch tube M3 is connected to the drain of the switch tube M5, the gate of the switch tube M5 and the controlled end of the feedback module, and the source of the switch tube M5 is connected to the input power supply.

[0007] In some embodiments, the limit module also includes a resistor R6, a resistor R7 and a resistor R8, the first end of the resistor R6 is connected to the source of the switch tube M1, the first end of the resistor R7 is connected to the source of the switch tube M2, the first end of the resistor R8 is connected to the source of the switch tube M3, and the second end of the resistor R6, the second end of the resistor R7 and the second end of the resistor R8 are grounded.

[0008] In some embodiments, the current module includes a constant current source I1 , a positive electrode of the constant current source I1 is connected to the input power supply, and a negative electrode of the constant current source I1 is connected to the input end of the differential input module.

[0009] In some embodiments, the current module includes a switch tube M6, a source of the switch tube M6 is connected to the input power supply, a gate of the switch tube M6 is connected to a bias voltage source, and a drain of the switch tube M6 is connected to the input end of the differential input module.

[0010] In some embodiments, the current module includes a switch tube M6, the gate of the switch tube M6 is connected to the controlled end of the feedback module, the source of the switch tube M6 is connected to the input power supply, and the drain of the switch tube M6 is connected to the input end of the differential input module.

[0011] In some embodiments, the limit module includes an operational amplifier U1, a resistor R4 and a resistor R5, the non-inverting input terminal of the operational amplifier U1 is connected to the first output terminal of the differential input module and the first end of the resistor R4, the inverting input terminal of the operational amplifier U1 is connected to the second output terminal of the differential input module and the first end of the resistor R5, the output terminal of the operational amplifier U1 is connected to the controlled end of the feedback module, and the second end of the resistor R4 and the second end of the resistor R5 are grounded.

[0012] In some embodiments, the feedback module includes a switch tube M4, the gate of the switch tube M4 is connected to the output end of the limit module, the source of the switch tube M4 is connected to the input power supply, and the drain of the switch tube M4 is connected to the first end of the voltage divider module and the third output end of the differential input unit.

[0013] In some embodiments, the differential input module includes a transistor Q1, a transistor Q2 and a resistor R3, the emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the output end of the current module, the base of the transistor Q1 is connected to the first end of the resistor R3, the collector of the transistor Q1 is connected to the first input end of the limit module, and the collector of the transistor Q2 is connected to the second input end of the limit module; the voltage divider module includes a resistor R1 and a resistor R2, the first end of the resistor R1 is connected to the second end of the resistor R3 and the output end of the feedback module, the second end of the resistor R1 is connected to the first end of the resistor R2 and the base of the transistor Q2, and the second end of the resistor R2 is grounded; the resistance of the resistor R3 is equal to the resistance of the resistor R1.

[0014] In order to solve the above technical problem, another technical solution adopted in the embodiment of the present invention is: providing a reference voltage source, including: a bandgap reference circuit as described above.

[0015] In order to solve the above technical problems, another technical solution adopted in the embodiment of the present invention is: providing a reference voltage generation method, which is applied to a bandgap reference circuit as described above, including: under the action of the first voltage signal and the second voltage signal provided by the voltage divider module, controlling the differential input module to generate the first on-current and the second on-current respectively, and then outputting the first output current and the second output current; under the action of the first output current and the second output current, controlling the limit module to output a drive signal; under the action of the drive signal, controlling the feedback module to adjust the first voltage signal and the second voltage signal so that the first on-current and the second on-current are equal, and then making the first output current and the second output current equal; when the first output current and the second output current are equal, controlling the differential input module to output a reference voltage with a zero temperature coefficient; making the limit module provide a matching resistor or a low transconductance switch tube with a transistor transconductance less than the differential input module to reduce the offset voltage.

[0016] The beneficial effects of the embodiments of the present invention are: different from the existing technology, the embodiments of the present invention use an isolation structure formed by a PNP transistor, and by setting a matching resistor in the limit module to reduce the offset, or setting a low transconductance switch tube whose transconductance is much lower than the transconductance of the transistor, the injection of minority carriers is avoided, the influence of the offset voltage of the limit module is reduced, and the accuracy of the reference voltage is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a circuit structure diagram of an existing bandgap reference circuit;

[0018] Figure 2 1 is a schematic structural diagram of a bandgap reference circuit provided by an embodiment of the present invention;

[0019] Figure 3 1 is a circuit structure diagram of a first bandgap reference circuit provided by an embodiment of the present invention;

[0020] Figure 4 1 is a circuit structure diagram of a second bandgap reference circuit provided by an embodiment of the present invention;

[0021] Figure 5 1 is a circuit structure diagram of a third bandgap reference circuit provided by an embodiment of the present invention;

[0022] Figure 6 1 is a circuit structure diagram of a fourth bandgap reference circuit provided by an embodiment of the present invention;

[0023] Figure 7 1 is a circuit structure diagram of a fifth bandgap reference circuit provided by an embodiment of the present invention;

[0024] Figure 8 1 is a circuit structure diagram of a sixth bandgap reference circuit provided by an embodiment of the present invention;

[0025] Figure 9 It is a flow chart of a reference voltage generating method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or there can be one or more centered elements therebetween. When an element is described as being "connected to" another element, it can be directly connected to the other element, or there can be one or more centered elements therebetween. The terms "upper", "lower", "inner", "outer", "bottom" and the like used in this specification indicate an orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0027] Unless otherwise defined, all technical and scientific terms used in this specification have the same meanings as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification and in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the relevant listed items.

[0028] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0029] The technical solution in this application will be described below with reference to the accompanying drawings.

[0030] Figure 1 The circuit structure of an existing bandgap reference circuit is shown. The bandgap reference circuit includes an operational amplifier U1, a resistor R1, a resistor R2, a transistor Q1 and a transistor Q2.

[0031] The non-inverting input terminal of operational amplifier U1 is connected to the second end of resistor R2 and the emitter of transistor Q2. The inverting input terminal of operational amplifier U1 is connected to the second end of resistor R1 and the first end of resistor R0. The output terminal of operational amplifier U1 is connected to the first end of resistor R2 and the first end of resistor R1. The second end of resistor R0 is connected to the emitter of transistor Q1. The base of transistor Q1, the collector of transistor Q1, the base of transistor Q2, and the collector of transistor Q2 are grounded.

[0032] The resistance value of the resistor R1 is equal to the resistance value of the resistor R2 , the transistor Q1 and the transistor Q2 are both PNP transistors, and the ratio between the size of the transistor Q1 and the size of the transistor Q2 is m:1.

[0033] Because operational amplifier U1 forms negative feedback with resistors R1 and R2, the operational amplifier's virtual short characteristic can be used to clamp the voltage at the second terminal of resistor R1 and the voltage at the second terminal of resistor R2, making the voltage at the second terminal of resistor R1 equal to the voltage at the second terminal of resistor R2. Furthermore, because the resistance values ​​of resistors R1 and R2 are equal, the current I1 flowing through resistor R1 and the current I2 flowing through resistor R2 are equal.

[0034] Since the ratio between the size of transistor Q1 and the size of Q2 is m:1, the voltage across resistor R0 can be expressed by the following formula:

[0035] ΔVBE=VBE1- VBE2=k*T*lnm / q, (1)

[0036] Wherein, k represents the Boltzmann constant, q represents the electron charge constant, T represents the temperature, m represents the ratio between the size of the transistor Q1 and the size of the transistor Q2, VBE1 represents the voltage difference between the base of the transistor Q1 and the emitter of the transistor Q1, and VBE2 represents the voltage difference between the base of the transistor Q2 and the emitter of the transistor Q2.

[0037] From formula (1), we can see that only temperature T is a variable, and other physical quantities are constants. Therefore, it is not difficult to understand that the voltage across the resistor R0 is a voltage that is positively correlated with temperature, that is, a positive temperature coefficient voltage.

[0038] It's known that the voltage difference VBE between the base and emitter of a transistor is negatively correlated with temperature, known as a negative temperature coefficient voltage. Therefore, by selecting appropriate resistors R1 and R0 and controlling the resistance ratio of R1 to R0, we can ensure that the positive temperature coefficient corresponding to ΔVBE is equal to the negative temperature coefficient corresponding to VBE1. This results in a reference voltage with zero temperature coefficient—a voltage that is unaffected by temperature.

[0039] Among them, the reference voltage with zero temperature coefficient can be expressed by the following formula:

[0040] VREF= VBE1+(R0+R) / R0*ΔVBE,

[0041] Wherein, VBE1 represents the voltage difference between the base of the transistor Q1 and the emitter of the transistor Q1 , R represents the resistance value of the resistor R1 and / or the resistance value of the resistor R2 , and ΔVBE represents the voltage across the resistor R0 .

[0042] However, the above bandgap reference circuit is affected by the offset voltage of the operational amplifier. The actual reference voltage is as shown in the following formula:

[0043] VREF= VBE1+(R0+R) / R0*(ΔVBE+Vos),

[0044] Among them, Vos is the offset voltage. It is not difficult to see that the offset voltage is amplified, and the amplified offset voltage will cause a higher temperature drift, which in turn leads to a decrease in the accuracy of the reference voltage output by the bandgap reference circuit.

[0045] In order to solve the above problems, an embodiment of the present invention provides a bandgap reference circuit, the structural diagram of which is shown in FIG. Figure 2 As shown, the bandgap reference circuit includes a current module 110 , a differential input module 120 , a limit module 130 , a voltage divider module 140 and a feedback module 150 .

[0046] The input end of the current module 110 is connected to the input power supply 20, the output end of the current module 110 is connected to the input end of the differential input module 120, the first output end of the differential input module 120 is connected to the first input end of the limit module 130, the second output end of the differential input module 120 is connected to the second input end of the limit module 130, the third output end of the differential input module 120 is connected to the first input end of the voltage divider module 140, and the fourth output end of the differential input module 120 is connected to the second input end of the voltage divider module 140.

[0047] The output of limit module 130 is connected to the controlled terminal of feedback module 150. The input of feedback module 150 is connected to input power supply 20. The output of feedback module 150 is connected to the first input of voltage divider module 140. Current module 110, feedback module 150, differential input module 120, voltage divider module 140, and limit module 130 form a negative feedback loop.

[0048] The current module 110 is configured to provide current to the differential input module 120. When the feedback module 150 is turned on, the input power supply 20 supplies power to the voltage divider module 140, causing the voltage divider module 140 to output a first voltage signal and a second voltage signal. The differential input module 120 is configured to generate a first conduction current and a second conduction current, respectively, in response to the first and second voltage signals from the voltage divider module 140, and thereby output a first output current and a second output current, respectively.

[0049] The limit module 130 outputs a driving signal to the feedback module 150 in response to the first output current and the second output current to adjust the output current of the feedback module 150, thereby adjusting the first voltage signal and the second voltage signal to make the first conduction current and the second conduction current equal.

[0050] In the embodiment of the present application, the transistor used in the differential input module 120 is a PNP transistor.

[0051] It should be noted that a matching resistor or a low transconductance switch is provided in the limit module 130 to reduce the offset voltage. The transconductance of the low transconductance switch is smaller than the transconductance of the transistor of the differential input module 120 .

[0052] Different from the prior art, the embodiment of the present invention uses an isolation structure formed by a PNP transistor. By setting a matching resistor in the limit module to reduce the offset, or setting a low transconductance switch tube whose transconductance is much lower than the transconductance of the transistor, the injection of minority carriers is avoided, the influence of the offset voltage of the limit module is reduced, and the accuracy of the reference voltage is improved.

[0053] In some embodiments of the present application, a circuit structure diagram of a first bandgap reference circuit is provided, such as Figure 3 shown.

[0054] The current module 110 includes a constant current source I1 , a positive electrode of the constant current source I1 is connected to the input power supply VDD, and a negative electrode of the constant current source I1 is connected to the input end of the differential input module 120 .

[0055] The differential input module 120 includes a transistor Q1, a transistor Q2 and a resistor R3. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the negative electrode of the constant current source I1. The base of the transistor Q1 is connected to the first end of the resistor R3. The collector of the transistor Q1 is connected to the first input end of the limit module 140. The collector of the transistor Q2 is connected to the second input end of the limit module 140.

[0056] The limit module includes switch tube M1, switch tube M2, switch tube M3 and switch tube M5. The drain of switch tube M1 is connected to the gate of switch tube M3 and the collector of transistor Q1. The gate of switch tube M1 is connected to the gate of switch tube M2, the drain of switch tube M2 and the collector of transistor Q2. The source of switch tube M1, the source of switch tube M2 and the source of switch tube M3 are grounded; the gate of switch tube M3 is connected to the drain of switch tube M5, the gate of switch tube M5 and the controlled end of feedback module 150, and the source of switch tube M5 is connected to the input power supply VDD.

[0057] In the embodiment of the present application, the switch tube M1 , the switch tube M2 , and the switch tube M3 are N-channel MOS tubes, and the switch tube M5 is a P-channel MOS tube.

[0058] The voltage divider module includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the second end of the resistor R3 and the output end of the feedback module 140. The second end of the resistor R1 is connected to the first end of the resistor R2 and the base of the transistor Q2. The second end of the resistor R2 is grounded.

[0059] In the embodiment of the present application, the resistance value of the resistor R1 is equal to the resistance value of the resistor R3.

[0060] The feedback module includes a switch tube M4, the gate of the switch tube M4 is connected to the gate of the switch tube M5 and the drain of the switch tube M5, the source of the switch tube M4 is connected to the input power supply VDD, and the drain of the switch tube M4 is connected to the first end of the resistor R1 and the second end of the resistor R3.

[0061] In the embodiment of the present application, the switch tube M4 is a P-channel MOS tube.

[0062] The emitter of transistor Q2 outputs a reference power supply VREF.

[0063] Specifically, the constant current source I1 provides a stable current for the transistor Q1 and the transistor Q2. The source of the switch tube M1 is connected to the source of the switch tube M2, and the gate of the switch tube M1 is connected to the gate of the switch tube M2, so that the switch tube M1 and the switch tube M2 form a current mirror, so that the switch tube M1 can mirror the current of the switch tube M2.

[0064] Transistor Q1 generates a first conduction current in response to a first voltage signal provided at the first terminal of resistor R1, and transistor Q2 generates a second conduction current in response to a second voltage signal provided at the second terminal of resistor R1, thereby outputting a first output current and a second output current, respectively. The currents of switch M1 and switch M2 maintain a fixed proportional relationship, regulating the current amplification factors of transistors Q1 and Q2.

[0065] In some embodiments of the present application, the size ratio of switch M1 to switch M2 is 1:1, that is, the first output current is equal to the second output current. Under the action of the current mirror formed by switch M1 and switch M2, the first output current and the second output current are compared. Switch M3 and switch M5 generate a drive signal based on the comparison result and output it to switch M4 to control the gate voltage of switch M4, thereby adjusting the on-state current of switch M4, and adjusting the voltage across resistor R1, that is, the first voltage signal and the second voltage signal, so that the base current of transistor Q1 is equal to the base current of transistor Q2, that is, the first on-state current is equal to the second on-state current.

[0066] When the base currents of transistors Q1 and Q2 are equal, the voltage difference between the voltage at the first terminal of resistor R3 and the voltage at the first terminal of resistor R2 is ΔVBE. ΔVBE is a positive temperature coefficient voltage. ΔVBE is equal to the voltage across resistor R1 plus the voltage across resistor R3: ΔVBE = I1 * R1 + I3 * R3.

[0067] I3 is the current flowing through the resistor R3, that is, the base current of the transistor Q1, and I1 is the current flowing through the resistor R1.

[0068] It can be obtained that I1=(ΔVBE- I3* R3) / R1,

[0069] It is not difficult to understand that I1 is a positive temperature coefficient current.

[0070] Since the current flowing through the resistor R2 is the sum of I1 and the base current of the transistor Q2 , it can be understood that the voltage across the resistor R2 is a positive temperature coefficient voltage.

[0071] Because the voltage difference VBE2 between the base and emitter of transistor Q2 is a negative temperature coefficient voltage, the negative temperature coefficient voltage and the positive temperature coefficient voltage can be combined through the electrical connection between resistor R2 and transistor Q2, thereby obtaining a reference voltage VREF with a zero temperature coefficient. In other words, the reference voltage VREF does not change with changes in temperature.

[0072] According to the above, we can get

[0073] VREF=I2*R2+VBE2,

[0074] I2 is the current flowing through the resistor R2, that is, I2=I1+I3.

[0075] Therefore, we can get

[0076] VREF=((ΔVBE- I3*R3) / R1+I3)*R2+VBE2,

[0077] Assuming R3=R1, VREF=ΔVBE / R1*R2+VBE2.

[0078] However, due to the influence of offset voltage, the actual reference voltage is

[0079] VREF=(ΔVBE+Vos*gm1 / gm2) / R1*R2+VBE2,

[0080] Among them, Vos is the offset voltage, gm1 is the transconductance of the switch tube M1, and gm2 is the transconductance of the transistor Q1.

[0081] Therefore, the offset voltage Vos can be made close to 0 by setting a switch tube M1 whose transconductance is much smaller than the transconductance of the transistor Q1, thereby reducing the influence of the offset voltage Vos.

[0082] In other embodiments of the present application, a circuit structure diagram of a second bandgap reference circuit is provided, such as Figure 4 shown.

[0083] The current module 110 includes a switch tube M6 , a source of the switch tube M6 is connected to the input power supply VDD, a gate of the switch tube M6 is connected to the bias voltage source VEP, and a drain of the switch tube M6 is connected to the input end of the differential input module 120 .

[0084] In the embodiment of the present application, the switch tube M6 is a P-channel MOS tube.

[0085] The differential input module 120 includes a transistor Q1, a transistor Q2 and a resistor R3. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the drain of the switch tube M6. The base of the transistor Q1 is connected to the first end of the resistor R3. The collector of the transistor Q1 is connected to the first input end of the limit module 140. The collector of the transistor Q2 is connected to the second input end of the limit module 140.

[0086] The limit module includes switch tube M1, switch tube M2, switch tube M3 and switch tube M5. The drain of switch tube M1 is connected to the gate of switch tube M3 and the collector of transistor Q1. The gate of switch tube M1 is connected to the gate of switch tube M2, the drain of switch tube M2 and the collector of transistor Q2. The source of switch tube M1, the source of switch tube M2 and the source of switch tube M3 are grounded; the gate of switch tube M3 is connected to the drain of switch tube M5, the gate of switch tube M5 and the controlled end of feedback module 150, and the source of switch tube M5 is connected to the input power supply VDD.

[0087] In the embodiment of the present application, the switch tube M1 , the switch tube M2 , and the switch tube M3 are N-channel MOS tubes, and the switch tube M5 is a P-channel MOS tube.

[0088] The voltage divider module includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the second end of the resistor R3 and the output end of the feedback module 140. The second end of the resistor R1 is connected to the first end of the resistor R2 and the base of the transistor Q2. The second end of the resistor R2 is grounded.

[0089] In the embodiment of the present application, the resistance value of the resistor R1 is equal to the resistance value of the resistor R3.

[0090] The feedback module includes a switch tube M4, the gate of the switch tube M4 is connected to the gate of the switch tube M5 and the drain of the switch tube M5, the source of the switch tube M4 is connected to the input power supply VDD, and the drain of the switch tube M4 is connected to the first end of the resistor R1 and the second end of the resistor R3.

[0091] In the embodiment of the present application, the switch tube M4 is a P-channel MOS tube.

[0092] The emitter of transistor Q2 outputs a reference power supply VREF.

[0093] The specific working principle is the same as Figure 3The difference of the bandgap reference circuit shown is that, in this embodiment, the transistors Q1 and Q2 are supplied with current by the input power supply VDD.

[0094] In other embodiments of the present application, a circuit structure diagram of a third bandgap reference circuit is provided, such as Figure 5 shown.

[0095] The current module 110 includes a switch tube M6 , a source of the switch tube M6 connected to the input power supply VDD, a gate of the switch tube M6 connected to the gate of the switch tube M5 in the limit module 130 , and a drain of the switch tube M6 connected to the input end of the differential input module 120 .

[0096] In the embodiment of the present application, the switch tube M6 is a P-channel MOS tube.

[0097] The differential input module 120 includes a transistor Q1, a transistor Q2 and a resistor R3. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the drain of the switch tube M6. The base of the transistor Q1 is connected to the first end of the resistor R3. The collector of the transistor Q1 is connected to the first input end of the limit module 140. The collector of the transistor Q2 is connected to the second input end of the limit module 140.

[0098] The limit module includes switch tube M1, switch tube M2, switch tube M3 and switch tube M5. The drain of switch tube M1 is connected to the gate of switch tube M3 and the collector of transistor Q1. The gate of switch tube M1 is connected to the gate of switch tube M2, the drain of switch tube M2 and the collector of transistor Q2. The source of switch tube M1, the source of switch tube M2 and the source of switch tube M3 are grounded; the gate of switch tube M3 is connected to the drain of switch tube M5, the gate of switch tube M5 and the controlled end of feedback module 150, and the source of switch tube M5 is connected to the input power supply VDD.

[0099] In the embodiment of the present application, the switch tube M1 , the switch tube M2 , and the switch tube M3 are N-channel MOS tubes, and the switch tube M5 is a P-channel MOS tube.

[0100] The voltage divider module includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the second end of the resistor R3 and the output end of the feedback module 140. The second end of the resistor R1 is connected to the first end of the resistor R2 and the base of the transistor Q2. The second end of the resistor R2 is grounded.

[0101] In the embodiment of the present application, the resistance value of the resistor R1 is equal to the resistance value of the resistor R3.

[0102] The feedback module includes a switch tube M4, the gate of the switch tube M4 is connected to the gate of the switch tube M5 and the drain of the switch tube M5, the drain of the switch tube M4 is connected to the input power supply VDD, and the source of the switch tube M4 is connected to the first end of the resistor R1 and the second end of the resistor R3.

[0103] In the embodiment of the present application, the switch tube M4 is an N-channel MOS tube.

[0104] The emitter of transistor Q2 outputs a reference power supply VREF.

[0105] The specific working principle is the same as Figure 4 The difference of the bandgap reference circuit shown is that the bias voltage of the switch tube M6 in this embodiment can be obtained from the driving voltage of the switch tube M5. Different from the above two embodiments, this embodiment does not require an additional constant current source or bias voltage source.

[0106] In other embodiments of the present application, a circuit structure diagram of a fourth bandgap reference circuit is provided, such as Figure 6 shown.

[0107] The current module 110 includes a switch tube M6 , a source of the switch tube M6 connected to the input power supply VDD, a gate of the switch tube M6 connected to the gate of the switch tube M5 in the limit module 130 , and a drain of the switch tube M6 connected to the input end of the differential input module 120 .

[0108] In the embodiment of the present application, the switch tube M6 is a P-channel MOS tube.

[0109] The differential input module 120 includes a transistor Q1, a transistor Q2 and a resistor R3. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the drain of the switch tube M6. The base of the transistor Q1 is connected to the first end of the resistor R3. The collector of the transistor Q1 is connected to the first input end of the limit module 140. The collector of the transistor Q2 is connected to the second input end of the limit module 140.

[0110] The limit module includes a switch tube M1, a switch tube M2, a switch tube M3, a switch tube M5, a resistor R6, a resistor R7 and a resistor R8. The drain of the switch tube M1 is connected to the gate of the switch tube M3 and the collector of the transistor Q1. The gate of the switch tube M1 is connected to the gate of the switch tube M2, the drain of the switch tube M2 and the collector of the transistor Q2. The source of the switch tube M3 is connected to the first end of the resistor R3. The first end of the resistor R6 is connected to the source of the switch tube M1. The first end of the resistor R7 is connected to the source of the switch tube M2. The second end of the resistor R6, the second end of the resistor R7 and the second end of the resistor R8 are grounded. The gate of the switch tube M3 is connected to the drain of the switch tube M5, the gate of the switch tube M5 and the controlled end of the feedback module 150. The source of the switch tube M5 is connected to the input power supply VDD.

[0111] In the embodiment of the present application, the switch tube M1 , the switch tube M2 , and the switch tube M3 are N-channel MOS tubes, and the switch tube M5 is a P-channel MOS tube.

[0112] The voltage divider module includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the second end of the resistor R3 and the output end of the feedback module 140. The second end of the resistor R1 is connected to the first end of the resistor R2 and the base of the transistor Q2. The second end of the resistor R2 is grounded.

[0113] In the embodiment of the present application, the resistance value of the resistor R1 is equal to the resistance value of the resistor R3.

[0114] The feedback module includes a switch tube M4, the gate of the switch tube M4 is connected to the gate of the switch tube M5 and the drain of the switch tube M5, the source of the switch tube M4 is connected to the input power supply VDD, and the drain of the switch tube M4 is connected to the first end of the resistor R1 and the second end of the resistor R3.

[0115] In the embodiment of the present application, the switch tube M4 is a P-channel MOS tube.

[0116] The emitter of transistor Q2 outputs a reference power supply VREF.

[0117] The specific working principle is the same as Figure 5 The difference of the bandgap reference circuit shown in FIG. 1 is that matching resistors, namely resistors R6, R7, and R8, are further provided in this embodiment. Resistors R6 and R7 are used to reduce the impact caused by the mismatch between the switch tube M1 and the switch tube M2; and resistor R8 is used to match the current of the switch tube M5 and the switch tube M6.

[0118] In other embodiments of the present application, a circuit structure diagram of a fifth bandgap reference circuit is provided, such as Figure 7 shown.

[0119] The current module 110 includes a constant current source I1 , a positive electrode of the constant current source I1 is connected to the input power supply VDD, and a negative electrode of the constant current source I1 is connected to the input end of the differential input module 120 .

[0120] The differential input module 120 includes a transistor Q1, a transistor Q2 and a resistor R3. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the drain of the switch tube M6. The base of the transistor Q1 is connected to the first end of the resistor R3. The collector of the transistor Q1 is connected to the first input end of the limit module 140. The collector of the transistor Q2 is connected to the second input end of the limit module 140.

[0121] The limit module 130 includes an operational amplifier U1, a resistor R4 and a resistor R5. The non-inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q1 and the first end of the resistor R4. The inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q2 and the first end of the resistor R5. The output terminal of the operational amplifier U1 is connected to the controlled end of the feedback module 150. The second end of the resistor R4 and the second end of the resistor R5 are grounded.

[0122] The voltage divider module includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the second end of the resistor R3 and the output end of the feedback module 140. The second end of the resistor R1 is connected to the first end of the resistor R2 and the base of the transistor Q2. The second end of the resistor R2 is grounded.

[0123] In the embodiment of the present application, the resistance value of the resistor R1 is equal to the resistance value of the resistor R3.

[0124] The feedback module includes a switch tube M4, a gate of the switch tube M4 connected to the output end of the operational amplifier U1, a drain of the switch tube M4 connected to the input power supply VDD, and a source of the switch tube M4 connected to the first end of the resistor R1 and the second end of the resistor R3.

[0125] In the embodiment of the present application, the switch tube M4 is an N-channel MOS tube.

[0126] The emitter of transistor Q2 outputs a reference power supply VREF.

[0127] Specifically, the constant current source I1 provides a stable current for the transistor Q1 and the transistor Q2. The operational amplifier U1, the switch tube M4, the constant current source I1, the resistor R1, the resistor R2, the transistor Q1 and the transistor Q2 form a negative feedback loop.

[0128] Transistor Q1 generates a first conduction current in response to a first voltage signal provided at the first end of resistor R1, and transistor Q2 generates a second conduction current in response to a second voltage signal provided at the second end of resistor R1, thereby outputting a first output current and a second output current, respectively. Operational amplifier U1 compares the first output current and the second output current. Based on the comparison result, operational amplifier U1 generates a drive signal that is output to switch M4 to control the gate voltage of switch M4, thereby adjusting the conduction current of switch M4. This adjusts the voltage across resistor R1, i.e., the first voltage signal and the second voltage signal, so that the base current of transistor Q1 equals the base current of transistor Q2, i.e., the first conduction current equals the second conduction current.

[0129] When the base currents of transistors Q1 and Q2 are equal, the voltage difference between the voltage at the first terminal of resistor R3 and the voltage at the first terminal of resistor R2 is ΔVBE. ΔVBE is a positive temperature coefficient voltage. ΔVBE is equal to the voltage across resistor R1 plus the voltage across resistor R3: ΔVBE = I1 * R1 + I3 * R3.

[0130] I3 is the current flowing through the resistor R3, that is, the base current of the transistor Q1, and I1 is the current flowing through the resistor R1.

[0131] It can be obtained that I1=(ΔVBE- I3* R3) / R1,

[0132] It is not difficult to understand that I1 is a positive temperature coefficient current.

[0133] Since the current flowing through the resistor R2 is the sum of I1 and the base current of the transistor Q2 , it can be understood that the voltage across the resistor R2 is a positive temperature coefficient voltage.

[0134] Because the voltage difference VBE2 between the base and emitter of transistor Q2 is a negative temperature coefficient voltage, the negative temperature coefficient voltage and the positive temperature coefficient voltage can be combined through the electrical connection between resistor R2 and transistor Q2, thereby obtaining a reference voltage VREF with a zero temperature coefficient. In other words, the reference voltage VREF does not change with changes in temperature.

[0135] According to the above, we can get

[0136] VREF=I2*R2+VBE2,

[0137] I2 is the current flowing through the resistor R2, that is, I2=I1+I3.

[0138] Therefore, we can get

[0139] VREF=((ΔVBE- I3*R3) / R1+I3)*R2+VBE2,

[0140] Assuming R3=R1, VREF=ΔVBE / R1*R2+VBE2.

[0141] Although the reference voltage may be affected by the offset voltage of the operational amplifier in practice, this embodiment provides matching resistors, namely resistor R4 and resistor R5, to limit the collector current of transistor Q1 and the collector current of transistor Q2 to avoid the influence of the offset voltage of the operational amplifier.

[0142] In other embodiments of the present application, a circuit structure diagram of a sixth bandgap reference circuit is provided, such as Figure 8 shown.

[0143] The current module 110 includes a switch tube M6 , a source of the switch tube M6 connected to the input power supply VDD, a gate of the switch tube M6 connected to the gate of the switch tube M4 in the feedback module 140 , and a drain of the switch tube M6 connected to the input end of the differential input module 120 .

[0144] The differential input module 120 includes a transistor Q1, a transistor Q2 and a resistor R3. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the drain of the switch tube M6. The base of the transistor Q1 is connected to the first end of the resistor R3. The collector of the transistor Q1 is connected to the first input end of the limit module 140. The collector of the transistor Q2 is connected to the second input end of the limit module 140.

[0145] The limit module 130 includes an operational amplifier U1, a resistor R4 and a resistor R5. The inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q1 and the first end of the resistor R4. The non-inverting input terminal of the operational amplifier U1 is connected to the collector of the transistor Q2 and the first end of the resistor R5. The output terminal of the operational amplifier U1 is connected to the controlled end of the feedback module 150. The second end of the resistor R4 and the second end of the resistor R5 are grounded.

[0146] The voltage divider module includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the second end of the resistor R3 and the output end of the feedback module 140. The second end of the resistor R1 is connected to the first end of the resistor R2 and the base of the transistor Q2. The second end of the resistor R2 is grounded.

[0147] In the embodiment of the present application, the resistance value of the resistor R1 is equal to the resistance value of the resistor R3.

[0148] The feedback module includes a switch tube M4, a gate of the switch tube M4 connected to the output end of the operational amplifier U1, a source of the switch tube M4 connected to the input power supply VDD, and a drain of the switch tube M4 connected to the first end of the resistor R1 and the second end of the resistor R3.

[0149] In the embodiment of the present application, the switch tube M4 is a P-channel MOS tube.

[0150] The emitter of transistor Q2 outputs a reference power supply VREF.

[0151] The specific working principle is the same as Figure 7 The difference of the bandgap reference circuit shown is that the bias voltage of the switch tube M6 in this embodiment can be obtained from the driving voltage of the switch tube M4. Different from the above embodiment, this embodiment does not require an additional constant current source or bias voltage source.

[0152] Different from the prior art, the embodiment of the present invention uses an isolation structure formed by a PNP transistor. By setting a matching resistor in the limit module to reduce the offset, or setting a low transconductance switch tube whose transconductance is much lower than the transconductance of the transistor, the injection of minority carriers is avoided, the influence of the offset voltage of the limit module is reduced, and the accuracy of the reference voltage is improved.

[0153] based on Figure 2The embodiment shown provides a bandgap reference circuit. The embodiment of the present invention further provides a reference voltage source, which includes the bandgap reference circuit provided by any of the above embodiments.

[0154] based on Figure 2 The embodiment of the present invention further provides a method for generating a reference voltage. The method for generating a reference voltage is applied to the bandgap reference circuit provided in any of the above embodiments. The flow chart thereof is shown in FIG. Figure 9 As shown, the specific steps include:

[0155] Step S100: under the action of the first voltage signal and the second voltage signal provided by the voltage divider module, the differential input module is controlled to generate a first conduction current and a second conduction current respectively, thereby outputting a first output current and a second output current.

[0156] Specifically, when the feedback module is turned on, the input power supply supplies power to the voltage divider module 1, causing the voltage divider module 140 to output a first voltage signal and a second voltage signal. Under the influence of the first and second voltage signals provided by the voltage divider module, the differential input module generates a first conduction current and a second conduction current, respectively, and further outputs a first output current and a second output current.

[0157] Step S200: Under the effects of the first output current and the second output current, the limit module is controlled to output a driving signal.

[0158] Specifically, the limiting module compares the first output current and the second output current, and further outputs a corresponding driving signal according to the comparison result.

[0159] Step S300: Under the action of the driving signal, the control feedback module adjusts the first voltage signal and the second voltage signal to make the first conduction current and the second conduction current equal, thereby making the first output current and the second output current equal.

[0160] Specifically, under the action of the driving signal, the feedback module adjusts its on-current, and then adjusts the first voltage signal and the second voltage signal, so that the first on-current and the second on-current are equal, and thus the first output current and the second output current are equal.

[0161] Step S400: When the first output current and the second output current are equal, control the differential input module to output a reference voltage with a zero temperature coefficient.

[0162] Specifically, when the first conduction current and the second conduction current are equal, the differential input module generates a current with a positive temperature coefficient, which flows through the voltage divider module to generate a voltage with a positive temperature coefficient. The positive temperature coefficient voltage is combined with a voltage with a negative temperature coefficient of the differential input module itself to obtain a reference voltage with a zero temperature coefficient.

[0163] Step S500: enabling the limit module to provide a matching resistor or a low transconductance switch tube that is smaller than the transconductance of the transistor of the differential input module, so as to reduce the offset voltage.

[0164] Specifically, the limit module will bring an offset voltage to the positive temperature coefficient voltage to reduce the accuracy of the zero temperature coefficient reference voltage. Therefore, the limit module further provides a matching resistor or a low transconductance switch tube with a smaller transconductance than the transistor of the differential input module to reduce the offset voltage and thereby improve the accuracy of the zero temperature coefficient reference voltage.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Based on the idea of ​​the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the present application as above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A bandgap reference circuit, characterized in that: Including: current module, differential input module, limit module, feedback module and voltage divider module, The current module is connected to the input power supply and the differential input module, and is used to provide current to the differential input module; the limit module is connected to the feedback module and the differential input module, and the feedback module is connected to the input power supply; The differential input module is configured to generate a first conduction current and a second conduction current respectively in response to the first voltage signal and the second voltage signal of the voltage divider module, and further output a first output current and a second output current respectively; The limit module outputs a driving signal to the feedback module in response to the first output current and the second output current to adjust the output current of the feedback module, wherein the output current causes the voltage divider module to generate the first voltage signal and the second voltage signal; When the first output current and the second output current are equal, the differential input module outputs a reference voltage with a zero temperature coefficient; The limit module includes a matching resistor or a low transconductance switch tube to reduce the offset voltage, and the transconductance of the low transconductance switch tube is smaller than the transconductance of the transistor of the differential input module; The differential input module includes transistor Q1, transistor Q2 and resistor R3. The emitter of the transistor Q1 and the emitter of the transistor Q2 are connected to the output end of the current module, the base of the transistor Q1 is connected to the first end of the resistor R3, the collector of the transistor Q1 is connected to the first input end of the limit module, and the collector of the transistor Q2 is connected to the second input end of the limit module; The voltage divider module includes a resistor R1 and a resistor R2, wherein a first end of the resistor R1 is connected to a second end of the resistor R3 and an output end of the feedback module, a second end of the resistor R1 is connected to a first end of the resistor R2 and a base of the transistor Q2, and a second end of the resistor R2 is grounded; The resistance of the resistor R3 is equal to the resistance of the resistor R1 ; the emitter of the transistor Q2 outputs a reference power supply VREF.

2. The circuit according to claim 1, characterized in that The limit module includes a switch tube M1, a switch tube M2, a switch tube M3 and a switch tube M5. The drain of the switch tube M1 is connected to the gate of the switch tube M3 and the first output terminal of the differential input module, the gate of the switch tube M1 is connected to the gate of the switch tube M2, the drain of the switch tube M2 and the second output terminal of the differential input module, and the source of the switch tube M1, the source of the switch tube M2 and the source of the switch tube M3 are grounded; The gate of the switch tube M3 is connected to the drain of the switch tube M5 , the gate of the switch tube M5 and the controlled end of the feedback module, and the source of the switch tube M5 is connected to the input power supply.

3. The circuit according to claim 2, characterized in that The limit module also includes a resistor R6, a resistor R7 and a resistor R8. The first end of the resistor R6 is connected to the source of the switch tube M1, the first end of the resistor R7 is connected to the source of the switch tube M2, and the first end of the resistor R8 is connected to the source of the switch tube M3. The second end of the resistor R6, the second end of the resistor R7 and the second end of the resistor R8 are grounded.

4. The circuit according to claim 1, wherein: The current module includes a constant current source I1 , a positive electrode of the constant current source I1 is connected to the input power supply, and a negative electrode of the constant current source I1 is connected to the input end of the differential input module.

5. The circuit according to claim 1, wherein: The current module includes a switch tube M6 , a source of the switch tube M6 is connected to the input power supply, a gate of the switch tube M6 is connected to a bias voltage source, and a drain of the switch tube M6 is connected to the input end of the differential input module.

6. The circuit according to claim 1, wherein: The current module includes a switch tube M6, a gate of the switch tube M6 is connected to the controlled end of the feedback module, a source of the switch tube M6 is connected to the input power supply, and a drain of the switch tube M6 is connected to the input end of the differential input module.

7. The circuit according to claim 1, wherein: The limit module includes an operational amplifier U1, a resistor R4 and a resistor R5. The non-inverting input terminal of the operational amplifier U1 is connected to the first output terminal of the differential input module and the first end of the resistor R4, the inverting input terminal of the operational amplifier U1 is connected to the second output terminal of the differential input module and the first end of the resistor R5, the output terminal of the operational amplifier U1 is connected to the controlled end of the feedback module, and the second end of the resistor R4 and the second end of the resistor R5 are grounded.

8. The circuit according to claim 1, wherein: The feedback module includes a switch tube M4, a gate of the switch tube M4 is connected to the output end of the limit module, a source of the switch tube M4 is connected to the input power supply, and a drain of the switch tube M4 is connected to the first end of the voltage divider module and the third output end of the differential input module.

9. A reference voltage source, characterized in that: include: A bandgap reference circuit as claimed in any one of claims 1 to 8.

10. A reference voltage generating method, applied to a bandgap reference circuit according to any one of claims 1 to 8, characterized in that: include: Under the action of the first voltage signal and the second voltage signal provided by the voltage divider module, the differential input module is controlled to generate a first conduction current and a second conduction current respectively, thereby outputting a first output current and a second output current; Under the action of the first output current and the second output current, the limit module is controlled to output a driving signal; Under the action of the driving signal, the control feedback module adjusts the first voltage signal and the second voltage signal so that the first conduction current and the second conduction current are equal, thereby making the first output current and the second output current equal; When the first output current and the second output current are equal, controlling the differential input module to output a reference voltage with a zero temperature coefficient; The limit module is configured to provide a matching resistor or a low transconductance switch tube that is smaller than the triode transconductance of the differential input module, so as to reduce the offset voltage.

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