PCIE link training device and method, computer equipment and storage medium

Abstract

The invention discloses a PCIE (Peripheral Component Interface Express) link training device and method, computer equipment and a storage medium, and relates to the technical field of PCIE links, and the method comprises the steps that a host end identifies an in-place signal of the PCIE link training device, and confirms that the current PCIE link rate is a preset rate; sending a test request to the host end, so that the host end returns a test signal according to the test request; receiving a test signal from the host end, converting the test signal to form an eye pattern, and combining one or more eye patterns to form an eye pattern test result; and acquiring a parameter value corresponding to the maximum value in the eye pattern test result as an optimal parameter value, and configuring the optimal parameter value to the host end. According to the method and the device, the parameters adaptive to the link can be obtained according to the type of the link, and the link and the adaptive parameters form the reference database, so that the reference database is used as parameters of similar links under the condition that other similar links appear.

Description

Technical Field

[0001] The present application relates to the field of PCIE links, and in particular to a PCIE link training device, method, computer equipment and storage medium. Background Art

[0002] PCIE (peripheral component interconnect express, a high-speed serial computer expansion bus standard) is used in the interactive communication of servers. The signal transmission path between PCIE devices is called a PCIE link, and the PCIE link consists of one or more transceiver channels. In order to ensure the stability and accuracy of the PCIE link during signal transmission, the PCIE link needs to be trained so that the parameters associated with the PCIE link maintain a balanced result.

[0003] In some related technologies, the PCIE signal of the current PCIE link has the problems of reduced coverage and channel attenuation. Moreover, since different PCIE links have different adaptation parameters for components, improper setting of the adaptation parameters will lead to the problem of PCIE device bandwidth reduction and rate reduction. In addition, although the test tools provided by the manufacturer are used to test the links involved, this test power is not suitable for all PCIE links. In actual use, relevant firmware and version adjustments need to be made, which is cumbersome and increases the testing cost. Summary of the invention

[0004] In order to solve at least one of the problems mentioned in the above background technology, the present application provides a PCIE link training device, method, computer equipment and storage medium, which can obtain parameters adapted to the link according to the type of link, and form a reference database of the link and the adapted parameters to serve as a reference for the parameters of similar links when other similar links appear.

[0005] The specific technical solutions provided by the embodiments of this application are as follows:

[0006] In a first aspect, a PCIE link training device is provided, which is communicatively connected to a host end, and includes a first interface for communicating with the host end, a sending module, a receiving module, an analyzing module, and a second interface;

[0007] The sending module is in communication with the receiving module, and the sending module is used to send a test request to the host end;

[0008] The receiving module is used to receive the test signal returned by the host end, convert the test signal into an eye diagram, and send the eye diagram to the analysis module;

[0009] The analysis module is in communication connection with the receiving module, and is used for recording the eye diagram, and combining one or more eye diagrams to form an eye diagram test result, so as to obtain an optimal parameter value according to the eye diagram test result.

[0010] In a specific embodiment, it also includes a second interface that is communicatively connected to an end of the analysis module away from the receiving module; the second interface is used to communicate with an external computer device so as to transmit the eye diagram test result to the external computer device through the second interface, and analyze the parameter value corresponding to the maximum eye diagram value in the eye diagram test result through the external computer device as the optimal parameter value.

[0011] In a second aspect, a PCIE link training method is provided, based on the PCIE link training device as described above, wherein the PCIE link training device is connected to a host end via a PCIE link communication, and the method comprises:

[0012] The host side identifies the in-place signal of the PCIE link training device and confirms that the PCIE link rate is a preset rate;

[0013] Sending a test request to the host end, so that the host end returns a test signal according to the test request;

[0014] Receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result;

[0015] A parameter value corresponding to the maximum eye diagram value in the eye diagram test result is obtained as an optimal parameter value, and the optimal parameter value is configured in the host end.

[0016] In a specific embodiment, the method further includes: the PCIE link training device is connected to the host end through a slot, so that the host end recognizes the presence signal.

[0017] In a specific embodiment, confirming that the PCIE link rate is a preset link rate specifically includes: in response to identifying the in-place signal, reading the value of the PCIE link rate, and comparing the PCIE link rate value with the preset rate value; if the PCIE link rate value is the same as the preset rate value, confirming that the PCIE link rate is the preset link rate; or, if the PCIE link rate value is different from the preset rate value, issuing an alarm.

[0018] In a specific embodiment, after confirming that the PCIE link rate is a preset link rate: obtain a preset test request sequence associated with the PCIE link rate according to the PCIE link rate value; obtain the test request at the first position in the preset test request sequence to send the test request to the host end; query the next test request in the preset test request sequence according to the test request; in response to receiving a test signal from the host end, execute sending the next test request to the host end; receive the next test signal from the host end, convert the next test signal into an eye diagram associated with the next test signal, and add the eye diagram associated with the next test signal to the eye diagram test result; collect the PCIE link and the eye diagram test result corresponding to the PCIE link, and set the current link to be associated with the eye diagram test result to form a data set.

[0019] In a specific embodiment, in response to training other PCIE links, the rate values ​​of the other PCIE links are read; the data set is queried according to the rate values ​​of the other PCIE links to obtain the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links; and the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links are set as the optimal parameter values ​​of the other PCIE links.

[0020] In a specific embodiment, the method also includes: obtaining a parameter value corresponding to the second largest eye diagram value in the eye diagram test result as an alternative parameter value; in response to configuring the optimal parameter value to the host side, performing a path status test on the PCIE link; if the path status of the PCIE link is abnormal, modifying the optimal parameter value in the host side to the alternative parameter value.

[0021] In a third aspect, a computer program product is provided, including a computer program, which, when executed by a processor, implements the steps of the method described below:

[0022] Step A: identifying the presence signal of the PCIE link training device through the host side, and confirming that the PCIE link rate is a preset rate;

[0023] Step B: sending a test request to the host end, so that the host end returns a test signal according to the test request;

[0024] Step C: receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result;

[0025] Step D: obtaining a parameter value corresponding to the maximum eye diagram value in the eye diagram test result as an optimal parameter value, and configuring the optimal parameter value to the host end.

[0026] In a fourth aspect, a computer device is provided, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the following steps are implemented:

[0027] Step A: identifying the presence signal of the PCIE link training device through the host side, and confirming that the PCIE link rate is a preset rate;

[0028] Step B: sending a test request to the host end, so that the host end returns a test signal according to the test request;

[0029] Step C: receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result;

[0030] Step D: obtaining a parameter value corresponding to the maximum eye diagram value in the eye diagram test result as an optimal parameter value, and configuring the optimal parameter value to the host end.

[0031] In a fifth aspect, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0032] Step A: identifying the presence signal of the PCIE link training device through the host side, and confirming that the PCIE link rate is a preset rate;

[0033] Step B: sending a test request to the host end, so that the host end returns a test signal according to the test request;

[0034] Step C: receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result;

[0035] Step D: obtaining a parameter value corresponding to the maximum eye diagram value in the eye diagram test result as an optimal parameter value, and configuring the optimal parameter value to the host end.

[0036] The embodiments of the present application have the following beneficial effects:

[0037] 1. The PCIE link training device provided in the embodiment of the present application integrates a first interface in the PCIE training device, which is plugged into a slot on the host side to achieve communication connection with the host side, and then sends a test request to the host side through the PCIE link training device, and receives a test signal returned from the host side, and records the test signals of multiple test requests through an analysis module to form an eye diagram test result, and obtains the optimal parameter value according to the eye diagram test result, thereby achieving testing of the PCIE link through the training device to obtain configuration parameters suitable for the PCIE link, and the device can be applicable to the testing of various host sides and PCIE links.

[0038] 2. The present application collects multiple different PCIE links and the optimal parameter values ​​corresponding to the PCIE links, and constructs a data set based on the PCIE link type and parameters. When it is necessary to configure the parameters of other PCIE links, the rate values ​​of other PCIE links are obtained and analyzed and compared with the existing links in the data set to obtain links similar to other PCIE links and their corresponding parameters, thereby obtaining parameters adapted to the link according to the type of link, and forming a reference database of the links and the adapted parameters, so as to use the parameters of similar links as a reference when other similar links appear. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of a PCIE link training device according to the present application is shown;

[0041] Figure 2 A schematic diagram showing the connection between the PCIE link training device and the host end according to the present application is shown;

[0042] Figure 3 A schematic diagram showing a PCIE link training method according to the present application is shown;

[0043] Figure 4 A schematic diagram showing a computer device according to the present application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] The present application provides a PCIE link training device, such as Figure 1 and Figure 2 As shown, by inserting this PCIE link training device into the slot to realize its communication connection with the host side, the PCIE link training device includes a first interface, a sending module, a receiving module, an analysis module and a second interface; wherein the first interface is a gold finger external interface, the first interface is used to communicate with the host side, the sending module is communicated with the receiving module, and the sending module is used to send a test request to the host side; the receiving module is used to receive the test signal returned by the host side, convert the test signal to form an eye diagram, and send the eye diagram to the analysis module; the analysis module is communicated with the receiving module, and the analysis module is used to record the eye diagram, and combine one or more eye diagrams to form an eye diagram test result, so as to obtain the optimal parameter value according to the eye diagram test result.

[0046] After the host side is powered on, it identifies the in-place signal of the PCIE link training device, obtains the PCIE link rate and the preset rate, and confirms that the PCIE link rate data is equal to the preset rate value, thereby confirming that the PCIE link rate is the preset rate; sends a test request to the host side through the sending module, so that the host side returns a test signal according to the test request, receives the test signal from the host side, converts the test signal to form an eye diagram, and combines one or more of the eye diagrams to form an eye diagram test result.

[0047] In order to ensure the continuity of the parameter testing process, when receiving the test signal from the host side, the trigger sending module sends the next test request to the host side to test the next set of parameters; wherein there are multiple test requests to realize the screening of parameter values ​​adapted to this PCIE link, and the device in this embodiment sends multiple groups of parameters to the host side respectively and tests them, and the receiving module receives multiple test signals returned from the host side, converts the test signals into eye diagrams, and forms eye diagram test results based on multiple eye diagrams, obtains the parameter value corresponding to the maximum eye diagram value in the eye diagram test result as the optimal parameter value, and configures the optimal parameter value to the host side.

[0048] It should be noted that the host end in this embodiment can be implemented by, but is not limited to, an independent server or a server cluster consisting of multiple servers.

[0049] The device also includes a second interface, which is used to communicate with an external computer device to transmit the eye diagram test result to the external computer device through the second interface, and analyze the parameter value corresponding to the maximum eye diagram value in the eye diagram test result through the external computer device as the optimal parameter value.

[0050] Exemplarily, the second interface in this embodiment is a serial port. After the analysis module records multiple eye diagram data obtained by multiple test requests, the eye diagram test results are sent to an external computer device through the serial port. The eye diagram test results are presented in the form of graphics or tables through the external computer device to more clearly and efficiently obtain the parameter value corresponding to the maximum eye diagram value in the eye diagram test result as the optimal parameter value, and configure the optimal parameter value to the host end.

[0051] Exemplarily, the parameter value corresponding to different test requests is P0, and the corresponding eye diagram value is 0.52; the parameter value is P9, and the corresponding eye diagram value is 0.51; the parameter value is P7, and the corresponding eye diagram value is 0.55; It can be seen from the above data that the maximum eye diagram value is 0.55, and the corresponding optimal parameter value is P7.

[0052] Through the scheme in this embodiment, the PCIE link is tested through the training device to obtain configuration parameters suitable for the PCIE link, and the device can be applicable to the testing of various host ends and PCIE links.

[0053] In one embodiment, Figure 2 and Figure 3 As shown, a PCIE link training method is provided, based on the PCIE link training device as described above, the PCIE link training device is connected to the host end through a PCIE link communication, and the method includes:

[0054] Step 101: The host side identifies the presence signal of the PCIE link training device and confirms that the PCIE link rate is a preset rate.

[0055] In this embodiment, the PCIE link training device is connected to the host end through a slot, so that the host end can recognize the presence signal of the PCIE link training device and continue to confirm the relevant parameters of the current PCIE link.

[0056] Confirming that the PCIE link rate is a preset link rate specifically includes: in response to identifying the in-place signal, reading the value of the PCIE link rate, and comparing the PCIE link rate value with the preset rate value; if the PCIE link rate value is the same as the preset rate value, confirming that the PCIE link rate is the preset link rate; or, if the PCIE link rate value is different from the preset rate value, issuing an alarm.

[0057] Exemplarily, the current PCIE link to be tested is PCIE4.0, that is, the rate of the current PCIE link is 16GT / s, and the preset link rate in the host side is obtained and compared with the rate of the current PCIE link; exemplarily, the preset link rate is set to 4.0, and through comparative analysis it can be confirmed that the rate of the current PCIE link is the same as the preset link rate, so it is confirmed that the PCIE link rate is the preset link rate.

[0058] Step 102: Send a test request to the host end, so that the host end returns a test signal according to the test request.

[0059] After confirming that the current PCIE link rate is the same as the preset link rate, a test request is sent to the host, wherein the test request is sent in sequence according to a preset test request sequence associated with its PCIE link rate; exemplarily, the test requests in the preset test request sequence are arranged in sequence according to the values ​​of the parameters to be tested of the PCIE link, i.e., P0, P1, P2, P3, P4, P5, P6, P7, P8 and P9; after receiving the test request, the host side sends a corresponding full-swing signal, i.e., a test signal to the receiving module according to the relevant information of the test request.

[0060] Step 103: Receive a test signal from the host end, convert the test signal to form an eye diagram, and combine one or more eye diagrams to form an eye diagram test result.

[0061] In a specific embodiment, after confirming that the PCIE link rate is a preset link rate, a preset test request sequence associated with the PCIE link rate is obtained according to the PCIE link rate value; the test request at the first position in the preset test request sequence is obtained to send the test request to the host end; the next test request in the preset test request sequence is queried according to the test request; in response to receiving a test signal from the host end, the next test request is sent to the host end; the next test signal from the host end is received, the next test signal is converted into an eye diagram associated with the next test signal, and the eye diagram associated with the next test signal is added to the eye diagram test result; the PCIE link and the eye diagram test result corresponding to the PCIE link are collected, and the current link is set to be associated with the eye diagram test result to form a data set.

[0062] It should be noted that after the host side returns the test signal according to the test request at the first position, the receiving module will be triggered to receive the test signal from the host side; after the receiving module receives the test signal from the host side, the sending module will be triggered to send the next test request; based on the above-mentioned preset test request sequence, the test request at the first position is the P0 test parameter, and the next test request is the P1 test parameter. After the receiving module receives the test signal at the first position from the host side, the sending module is triggered to send the P1 test request related parameters to the host side.

[0063] In order to ensure the continuity and accuracy during the parameter test, one test request is set to correspond to receiving a test signal, and one test signal reception corresponds to one receiving module transmitting the eye diagram to the analysis module.

[0064] Step 104: Obtain a parameter value corresponding to the maximum eye diagram value in the eye diagram test result as an optimal parameter value, and configure the optimal parameter value to the host end.

[0065] The eye diagrams obtained by the multiple test request tests are recorded by the analysis module to form an eye diagram test result. In this embodiment, the analysis module transmits the eye diagram test result to an external computer device through a second interface, so that the eye diagram test result is analyzed by the external computer device to obtain the optimal parameter value. Specifically, the external computer device presents the eye diagram value data and parameter values ​​in the eye diagram test result through graphics and tables, so as to quickly and accurately obtain the optimal parameter value result. An exemplary table is shown in Table 1.

[0066] Table 1 Eye diagram test results

[0067]

[0068]

[0069] By collecting each tested PCIE link in actual use and the optimal parameter values ​​obtained from the test to obtain a data set, when testing other PCIE links, the optimal parameter value results of similar links can be obtained from the data set to provide a reference for configuring the parameters of other PCIE links.

[0070] In a specific embodiment, in response to training other PCIE links, the rate values ​​of the other PCIE links are read; the data set is queried according to the rate values ​​of the other PCIE links to obtain the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links; and the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links are set as the optimal parameter values ​​of the other PCIE links.

[0071] Furthermore, in order to ensure that other PCIE links can obtain the optimal parameter value with high accuracy in the data set as a reference, after obtaining the optimal parameter value corresponding to the PCIE link with the same rate value as the other PCIE link, the number of connectors of the other PCIE link is obtained, and based on the number of connectors of the other PCIE link, the PCIE link with the same number of connectors as the PCIE link in the data set is queried to obtain the existing PCIE link; in response to the query to obtain the existing PCIE link, the loss value of the other PCIE link is read, and the existing loss value of the existing PCIE link is obtained, and the loss value of the other PCIE link is compared and analyzed with the existing loss value of the existing PCIE link; if the loss value of the other PCIE link is the same as the existing loss value of the existing PCIE link, it is confirmed that the optimal parameter value of the existing PCIE link in the data set is the optimal parameter value of the other PCIE link.

[0072] In a specific embodiment, a parameter value corresponding to the second largest eye diagram value in the eye diagram test result is obtained as an alternative parameter value; in response to configuring the optimal parameter value to the host side, a path status test is performed on the PCIE link; if the path status of the PCIE link is abnormal, the optimal parameter value in the host side is modified to the alternative parameter value.

[0073] Through the solution in this embodiment, the parameters adapted to the link can be accurately obtained according to the type of link, and the link and the adapted parameters can be formed into a reference database to serve as a reference for the parameters of similar links when other similar links appear.

[0074] For the specific limitations on the PCIE link training device, please refer to the limitations on the PCIE link training device above, which will not be repeated here.

[0075] It should be understood that although Figure 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 3 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequentially, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0076] In one embodiment, a computer program product is provided, including a computer program, which, when executed by a processor, implements the steps of the method described below:

[0077] Step 201: The host terminal identifies the in-place signal of the PCIE link training device and confirms that the PCIE link rate is a preset rate;

[0078] Step 202: Send a test request to the host end, so that the host end returns a test signal according to the test request;

[0079] Step 203, receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result;

[0080] Step 204: Obtain a parameter value corresponding to the maximum eye diagram value in the eye diagram test result as an optimal parameter value, and configure the optimal parameter value to the host end.

[0081] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the PCIE link training device is connected to the host end through a slot so that the host end recognizes the presence signal.

[0082] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to identifying the in-place signal, reading the value of the PCIE link rate, and comparing the PCIE link rate value with the preset rate value; if the PCIE link rate value is the same as the preset rate value, confirming that the PCIE link rate is the preset link rate; or, if the PCIE link rate value is different from the preset rate value, issuing an alarm.

[0083] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0084] After confirming that the PCIE link rate is the preset link rate, obtain a preset test request sequence associated with it according to the PCIE link rate value; obtain the test request at the first position in the preset test request sequence to send the test request to the host end; query the next test request in the preset test request sequence according to the test request; in response to receiving a test signal from the host end, execute sending the next test request to the host end; receive the next test signal from the host end, convert the next test signal into an eye diagram associated with the next test signal, and add the eye diagram associated with the next test signal to the eye diagram test result; collect the PCIE link and the eye diagram test result corresponding to the PCIE link, and set the current link to be associated with the eye diagram test result to form a data set.

[0085] In one embodiment, when the computer program is executed by a processor, the following steps are also implemented:

[0086] In response to training other PCIE links, the rate values ​​of the other PCIE links are read; the data set is queried according to the rate values ​​of the other PCIE links to obtain the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links; and the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links are set as the optimal parameter values ​​of the other PCIE links.

[0087] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining the parameter value corresponding to the second largest eye diagram value in the eye diagram test result as an alternative parameter value; in response to configuring the optimal parameter value to the host side, performing a path status test on the PCIE link; if the path status of the PCIE link is abnormal, modifying the optimal parameter value in the host side to the alternative parameter value.

[0088] In one embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as follows: Figure 4 As shown. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store eye diagram test result data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a PCIE link training method is implemented.

[0089] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0090] In one embodiment, a computer device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the following steps when executing the computer program:

[0091] Step 301: The host terminal identifies the in-place signal of the PCIE link training device and confirms that the PCIE link rate is a preset rate;

[0092] Step 302: Send a test request to the host end, so that the host end returns a test signal according to the test request;

[0093] Step 303: receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result;

[0094] Step 304: Obtain a parameter value corresponding to the maximum eye diagram value in the eye diagram test result as an optimal parameter value, and configure the optimal parameter value to the host end.

[0095] In one embodiment, when the processor executes the computer program, the following steps are also implemented: the PCIE link training device is connected to the host end through a slot so that the host end recognizes the presence signal.

[0096] In one embodiment, the processor further implements the following steps when executing the computer program: in response to identifying the in-place signal, reading the value of the PCIE link rate, and comparing the PCIE link rate value with a preset rate value; if the PCIE link rate value is the same as the preset rate value, confirming that the PCIE link rate is the preset link rate; or, if the PCIE link rate value is different from the preset rate value, issuing an alarm.

[0097] In one embodiment, the processor further implements the following steps when executing the computer program: after confirming that the PCIE link rate is a preset link rate, obtaining a preset test request sequence associated with it according to the PCIE link rate value; obtaining the test request at the first position in the preset test request sequence to send the test request to the host end; querying the next test request in the preset test request sequence according to the test request; in response to receiving a test signal from the host end, executing to send the next test request to the host end; receiving the next test signal from the host end, converting the next test signal into an eye diagram associated with the next test signal, and adding the eye diagram associated with the next test signal to the eye diagram test result; collecting the PCIE link and the eye diagram test result corresponding to the PCIE link, and setting the current link to be associated with the eye diagram test result to form a data set.

[0098] In one embodiment, when the processor executes the computer program, the following steps are also implemented: in response to training other PCIE links, reading the rate values ​​of the other PCIE links; querying the data set according to the rate values ​​of the other PCIE links to obtain the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links; setting the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links as the optimal parameter values ​​of the other PCIE links.

[0099] In one embodiment, when the processor executes the computer program, the following steps are also implemented: obtaining the parameter value corresponding to the second largest eye diagram value in the eye diagram test result as an alternative parameter value; in response to configuring the optimal parameter value to the host side, performing a path status test on the PCIE link; if the path status of the PCIE link is abnormal, modifying the optimal parameter value in the host side to the alternative parameter value.

[0100] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0101] Step 401: identifying the presence signal of the PCIE link training device through the host end, and confirming that the PCIE link rate is a preset rate;

[0102] Step 402: Send a test request to the host end, so that the host end returns a test signal according to the test request;

[0103] Step 403: receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result;

[0104] Step 404: Obtain a parameter value corresponding to the maximum eye diagram value in the eye diagram test result as an optimal parameter value, and configure the optimal parameter value to the host end.

[0105] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: the PCIE link training device is connected to the host end through a slot so that the host end recognizes the presence signal.

[0106] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to identifying the in-place signal, reading the value of the PCIE link rate, and comparing the PCIE link rate value with the preset rate value; if the PCIE link rate value is the same as the preset rate value, confirming that the PCIE link rate is the preset link rate; or, if the PCIE link rate value is different from the preset rate value, issuing an alarm.

[0107] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: after confirming that the PCIE link rate is a preset link rate, obtaining a preset test request sequence associated with it according to the PCIE link rate value; obtaining the test request at the first position in the preset test request sequence to send the test request to the host end; querying the next test request in the preset test request sequence according to the test request; in response to receiving a test signal from the host end, executing to send the next test request to the host end; receiving the next test signal from the host end, converting the next test signal into an eye diagram associated with the next test signal, and adding the eye diagram associated with the next test signal to the eye diagram test result; collecting the PCIE link and the eye diagram test result corresponding to the PCIE link, and setting the current link to be associated with the eye diagram test result to form a data set.

[0108] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: in response to training other PCIE links, reading the rate values ​​of the other PCIE links; querying the data set according to the rate values ​​of the other PCIE links to obtain the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links; setting the optimal parameter values ​​corresponding to the PCIE links with the same rate values ​​as the other PCIE links as the optimal parameter values ​​of the other PCIE links.

[0109] In one embodiment, when the computer program is executed by the processor, the following steps are also implemented: obtaining the parameter value corresponding to the second largest eye diagram value in the eye diagram test result as an alternative parameter value; in response to configuring the optimal parameter value to the host side, performing a path status test on the PCIE link; if the path status of the PCIE link is abnormal, modifying the optimal parameter value in the host side to the alternative parameter value.

[0110] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0111] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0112] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A PCIE link training device, connected to a host terminal for communication, characterized in that: It includes a first interface for communicating with the host end, a sending module, a receiving module, an analyzing module and a second interface; The sending module is in communication with the receiving module, and the sending module is used to send a test request to the host end; The receiving module is used to receive the test signal returned by the host end, convert the test signal into an eye diagram, and send the eye diagram to the analysis module; The analysis module is in communication connection with the receiving module, and is used for recording the eye diagram, and combining one or more eye diagrams to form an eye diagram test result, so as to obtain an optimal parameter value according to the eye diagram test result.

2. The PCIE link training device according to claim 1, characterized in that: Also includes a second interface communicatively connected to an end of the analysis module away from the receiving module; The second interface is used to communicate with an external computer device to transmit the eye diagram test result to the external computer device through the second interface; The parameter value corresponding to the maximum eye diagram value in the eye diagram test result is analyzed by the external computer device as the optimal parameter value.

3. A PCIE link training method, based on the PCIE link training device described in claim 1 or 2, characterized in that: The PCIE link training device is connected to the host via a PCIE link communication, and the method includes: The host side identifies the in-place signal of the PCIE link training device and confirms that the PCIE link rate is a preset rate; Sending a test request to the host end, so that the host end returns a test signal according to the test request; Receiving a test signal from the host end, converting the test signal to form an eye diagram, and combining one or more eye diagrams to form an eye diagram test result; A parameter value corresponding to the maximum eye diagram value in the eye diagram test result is obtained as an optimal parameter value, and the optimal parameter value is configured in the host end.

4. The PCIE link training method according to claim 3, characterized in that: The method further comprises: The PCIE link training device is connected to the host end through a slot so that the host end can recognize the presence signal.

5. The PCIE link training method according to claim 4, characterized in that: Confirm that the PCIE link rate is the preset link rate, including: In response to identifying the in-place signal, reading a value of the PCIE link rate, and comparing the PCIE link rate value with a preset rate value; If the PCIE link rate value is the same as the preset rate value, confirming that the PCIE link rate is the preset link rate; Alternatively, if the PCIE link rate value is different from the preset rate value, an alarm is issued.

6. The PCIE link training method according to claim 5, characterized in that: After confirming that the PCIE link rate is a preset link rate, the method further includes: Acquire a preset test request sequence associated with the PCIE link rate value according to the PCIE link rate value; Obtaining a test request at a first position in the preset test request sequence to send the test request to the host end; Querying the next test request in the preset test request sequence according to the test request; In response to receiving a test signal from the host end, executing sending the next test request to the host end; receiving a next test signal from the host end, converting the next test signal into a next test signal associated eye diagram, and adding the next test signal associated eye diagram to the eye diagram test result; The PCIE link and the eye diagram test result corresponding to the PCIE link are collected, and the current link is associated with the eye diagram test result to form a data set.

7. The PCIE link training method according to claim 6, characterized in that: The method further comprises: In response to training other PCIE links, reading rate values ​​of the other PCIE links; Querying the data set according to the rate values ​​of the other PCIE links to obtain the optimal parameter value corresponding to the PCIE link having the same rate value as the other PCIE link; The optimal parameter value corresponding to the PCIE link having the same rate value as the other PCIE link is set as the optimal parameter value of the other PCIE link.

8. The PCIE link training method according to claim 3 or 4, characterized in that: The method further comprises: Obtaining a parameter value corresponding to a second largest eye diagram value in the eye diagram test result as a candidate parameter value; In response to configuring the optimal parameter value to the host end, performing a path status test on the PCIE link; If the path state of the PCIE link is abnormal, the optimal parameter value in the host side is modified to the candidate parameter value.

9. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method according to any one of claims 3 to 8 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 3 to 8 are implemented.

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