Optical Proximity Effect Correction Method for Ion Implantation Layer and Semiconductor Device Manufacturing Method

Abstract

The present invention provides an optical proximity effect correction method for an ion implantation layer and a semiconductor device manufacturing method. In the optical proximity effect correction method for the ion implantation layer, first, the convex corners in the small-pitch corner-to-corner structures in the original layout of the ion implantation layer are cut off, and then optical proximity effect correction (OPC) is performed on the layout after the corner cutting. This can avoid the restrictions of mask rule checking on these corner-to-corner structures, increase the space for optical proximity effect correction, so that the critical dimensions of the final layout obtained by OPC can meet the target values, and can solve the problem that the corner-to-corner structure patterns in the ion implantation layer in the prior art are prone to distortion, resulting in process hotspots, improve the accuracy of OPC correction, and further provide a more accurate final layout of the ion implantation layer. In the semiconductor device manufacturing method of the present invention, since the optical proximity effect correction method of the ion implantation layer of the present invention is used to obtain the required final layout of the ion implantation layer, the yield and performance of the product can ultimately be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device manufacturing, and particularly relates to an optical proximity effect correction method for an ion implantation layer and a semiconductor device manufacturing method. Background Art

[0002] Ion implantation is an indispensable process in the semiconductor device manufacturing process. First, a photoresist is used to cover the silicon wafer area that does not need to be ion implanted through a lithography process, and then a specific impurity atom is implanted into the silicon wafer area exposed by the photoresist by an ion implanter to achieve doping of a specific area of the silicon wafer.

[0003] In advanced semiconductor device manufacturing processes, due to the particularity of the ion implantation layer, the original layout of the ion implantation layer is usually generated by logical operations of other layer layouts, and some corner-to-corner structures are likely to appear.

[0004] Moreover, with the continuous development of semiconductor device manufacturing process technology, the feature size of the layout pattern of the ion implantation layer is getting smaller and smaller, and the spacing of these corner-to-corner structures is also getting smaller and smaller. It is very likely to become a process hot spot with insufficient actual windows in the lithography process, ultimately leading to the problem of poor lithography.

[0005] Please refer to Figure 1 , in the prior art, although the optical proximity correction (OPC) technology has been adopted to compensate and correct the pattern of the original layout of the ion implantation layer to avoid the problem of certain deformation and deviation between the lithography pattern obtained on the actual silicon wafer and the layout pattern of the ion implantation layer. However, since the layout pattern of the ion implantation layer is mostly generated by logical operations, the pattern is complex, and the influence of the reflection of the previous layer varies. To avoid waste of OPC computing resources, the existing OPC technology often undercompensates these corner-to-corner structures, or even does not compensate these corner-to-corner structures due to the limitation of mask rule check (MRC, which refers to the check that must be done before the designed pattern is sent to the mask manufacturer after being processed by optical proximity correction). This directly leads to obvious distortion of the corner-to-corner structures in the ion implantation layer lithography pattern obtained by the final exposure. Summary of the Invention

[0006] An object of the present invention is to provide an optical proximity effect correction method for an ion implantation layer, which can solve the problem that the corner-to-corner structure pattern in the ion implantation layer is prone to distortion and cause process hot spots, and improve the accuracy of OPC correction.

[0007] Another object of the present invention is to provide a semiconductor device manufacturing method, which can improve the product yield and electrical performance.

[0008] To achieve the above object, the present invention provides an optical proximity effect correction method for an ion implantation layer, which includes the following steps:

[0009] Provide the original layout of the ion implantation layer;

[0010] Find the corner-to-corner structure to be processed from the original layout, where the corner-to-corner structure includes two convex corners with different opening angles, and the distance between the vertices of the two convex corners is less than a preset distance;

[0011] Cut off each of the convex corners in the corner-to-corner structure. After cutting the corners, a new straight edge or a rounded corner protruding outward is generated at each convex corner to obtain the layout after cutting the corners;

[0012] Perform optical proximity effect correction on the layout after cutting the corners to obtain the final layout of the ion implantation layer.

[0013] Optionally, the preset distance is greater than or equal to the minimum spacing of the layout; and / or, before cutting the corners, the distance between the vertices of the two convex corners is less than the minimum spacing of the layout.

[0014] Optionally, each of the convex corners is a right angle; and / or, the vertices of the two convex corners in the corner-to-corner structure coincide.

[0015] Optionally, the corner-to-corner structure is two ion implantation regions that are corner-to-corner and rectangular in the ion implantation layer, and the distance between the convex corners of the two ion implantation regions after cutting the corners is greater than or equal to the preset distance.

[0016] Optionally, before cutting the corners, the length of each side of each convex corner is greater than the minimum feature size of the layout.

[0017] Optionally, the sizes of the convex corners cut off in the corner-to-corner structure are the same; and / or, when a new straight edge is generated at each convex corner after cutting the corners, the new straight edges generated at each convex corner are parallel.

[0018] Optionally, the length of each side of each convex corner cut off is not greater than 1 / 2 of the length of the corresponding side of the convex corner before the corner cutting process.

[0019] Optionally, the length of each side of each convex corner cut off is not greater than .

[0020] Optionally, provide the layout of the relevant previous layer, and perform logical operations based on the layout of the relevant previous layer to generate the original layout; and / or, cut off each of the convex corners in the corner-to-corner structure through EDA tool layout design software.

[0021] Based on the same inventive concept, the present invention further provides a method for manufacturing a semiconductor device, which includes:

[0022] Adopting the optical proximity effect correction method of the ion implantation layer as described in the present invention to obtain the final layout of the required ion implantation layer;

[0023] Transferring the final layout of the ion implantation layer onto a photomask;

[0024] Transferring the pattern on the photomask into the photoresist on the corresponding silicon wafer through a photolithography process;

[0025] Using an ion implanter to inject specific impurity atoms into the area of the silicon wafer exposed by the photoresist to form the required ion implantation layer in the silicon wafer.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] 1. In the optical proximity effect correction method of the ion implantation layer of the present invention, the convex corners in the small-spacing corner-to-corner structure of the original layout of the ion implantation layer are first cut off, and then the optical proximity effect correction (OPC) is performed on the layout after corner cutting. This can avoid the restrictions of the mask rule check (MRC) on these corner-to-corner structures, increase the space for optical proximity effect correction, so that the critical dimensions of the final layout obtained by OPC can meet the target values, and can solve the problem that the corner-to-corner structure patterns in the ion implantation layer are prone to distortion and cause process hotspots in the prior art, improve the accuracy of OPC correction, and further provide a more accurate final layout of the ion implantation layer.

[0028] 2. In the method for manufacturing a semiconductor device of the present invention, the optical proximity effect correction method of the ion implantation layer of the present invention is used to obtain the final layout of the required ion implantation layer, transfer the final layout of the ion implantation layer onto a photomask, and further transfer it into the photoresist on the silicon wafer through a photolithography process. Since the final layout of the ion implantation layer is accurate, the difference between the photoresist pattern obtained on the actual silicon wafer and the layout pattern of the ion implantation layer can meet the requirements of the ion implantation process, so that the final product yield and performance can be improved. Description of the Drawings

[0029] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0030] Figure 1 is a schematic diagram of the layout change in the existing optical proximity effect correction method of the ion implantation layer.

[0031] Figure 2 is a schematic flowchart of the optical proximity effect correction method of the ion implantation layer in a specific embodiment of the present invention.

[0032] Figure 3 It is an example schematic diagram of layout change in the method for correcting the proximity effect of the ion implantation layer in a specific embodiment of the present invention.

[0033] Figure 4 It is another example schematic diagram of layout change in the method for correcting the proximity effect of the ion implantation layer in a specific embodiment of the present invention.

[0034] Figure 5 It is a schematic flow diagram of the method for manufacturing a semiconductor device in a specific embodiment of the present invention.

[0035] Figure 6 It is a schematic diagram of the device cross-sectional structure in the method for manufacturing a semiconductor device in a specific embodiment of the present invention. Detailed implementation manners

[0036] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without one or more of these details. In other instances, well-known technical features are not described to avoid obscuring the present invention. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the present invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0037] The technical solutions proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0038] Please refer to Figure 2 and Figure 3, an embodiment of the present invention provides an optical proximity effect correction method for an ion implantation layer, which includes the following steps:

[0039] S11, providing the original layout of the ion implantation layer;

[0040] S12, finding the corner-to-corner structure to be processed from the original layout, the corner-to-corner structure includes two convex corners with different opening angles, and the distance between the vertices of the two convex corners is less than a preset distance;

[0041] S13, cutting off each of the convex corners in the corner-to-corner structure, and after cutting, a new straight edge or a rounded corner protruding outward is generated at each convex corner to obtain the layout after cutting;

[0042] S14, performing optical proximity effect correction on the layout after cutting to obtain the final layout of the ion implantation layer.

[0043] In step S11, the layout of the relevant front layer (not shown) is provided, and the relevant front layer may include at least one of fins, shallow trench isolation structures, active regions, and gates; then, based on the layout of the relevant front layer, logical operations are performed to generate the original layout of the ion implantation layer. The original layout of the ion implantation layer may have a plurality of ion implantation regions spaced apart from each other, and these ion implantation regions may include any suitable at least one of graphics such as rectangles, L-shapes, right-angled U-shapes, etc. Adjacent ion implantation regions (such as Figure 2 indicated by "1" and "2" in Figure 2 may form a corner-to-corner structure due to the proximity of the top corners (as shown by the dashed box in

[0044] Please refer to Figure 2 and Figure 3 , in step S12, the corner-to-corner structures to be processed are found from the original layout of the ion implantation layer. These corner-to-corner structures include two convex corners 3 and 4 with different opening angles, and the distance between the vertices of the two convex corners 3 and 4 is less than a preset distance. The preset distance may be greater than or equal to the minimum layout distance. For example, the preset distance is 1 to 3 times the minimum layout distance. The minimum layout distance refers to the minimum distance requirement between different layers or different geometric figures in layout design, and it is also the minimum line width and minimum distance allowed for photomask manufacturing. In layout design, the minimum distance rule is one of the very important design rules, which ensures the minimum distance between different geometric figures, avoids electrical short circuits or open circuits, and ensures the stability and reliability of the layout design. The "minimum layout distance" described in the present invention includes the minimum distance between the outer boundaries of geometric figures of different ion implantation regions in the same layer of layout.

[0045] In one example, the preset distance is the minimum layout spacing. The distance between the vertices of the two convex corners 3 and 4 in the corner-to-corner structure that needs to be processed (i.e., the corners need to be chamfered subsequently) found in this step is less than the minimum layout spacing, and it can be equal to 0, or even less than 0 (in this case, there is an overlap within the extent of the minimum layout spacing). The convex corners 3 and 4 in such a corner-to-corner structure need to be chamfered subsequently, and the side length of the chamfered convex corner is greater than 0. If the distance between the vertices of the two convex corners 3 and 4 is greater than or exactly equal to the minimum layout spacing, it is not the corner-to-corner structure that needs to be processed (i.e., the corners need to be chamfered subsequently) found in this step, that is, such convex corners do not need to be chamfered subsequently.

[0046] In one example, the vertices of the two convex corners 3 and 4 in the corner-to-corner structure that needs to be processed found in this step coincide (i.e., the distance between the vertices of the two convex corners 3 and 4 is 0).

[0047] In addition, it should be understood that the angular sizes of the two convex corners 3 and 4 in the corner-to-corner structure that needs to be processed found in this step depend on the graphic shape design of the ion implantation regions 1 and 2. For example, in one example, the corner-to-corner structure that needs to be processed found in this step is the corner-to-corner in the ion implantation layer and the two ion implantation regions 1 and 2 are rectangular. At this time, both of the two convex corners 3 and 4 in this corner-to-corner structure are right angles. In other examples, one or both of the convex corners 3 and 4 are acute angles or obtuse angles.

[0048] Furthermore, the length of each side of each convex corner 3 and 4 in the corner-to-corner structure that needs to be processed found in this step is greater than the minimum layout graphic size. The minimum layout graphic size refers to the minimum size allowed for graphic elements specified in the layout design rules (including the minimum line width, minimum spacing, minimum line length, etc. allowed in the layout design). The minimum layout graphic size ensures the manufacturability and reliability of the geometric figures in the layout, preventing problems such as open circuits or short circuits during the integrated circuit manufacturing process. Generally speaking, the minimum layout spacing is less than the minimum layout graphic size. The "minimum layout graphic size" described in the present invention includes the minimum value of the geometric figure side length of the ion implantation region, etc.

[0049] For example, when the corner-to-corner structure that needs to be processed found in this step is two rectangular ion implantation regions 1 and 2, the length and width of the ion implantation regions 1 and 2 before chamfering are both greater than the minimum layout graphic size.

[0050] Please continue to refer to Figure 2 and Figure 3 In step S13, each convex corner 3 and 4 in the corner-to-corner structure is cut off through the layout design software of the EDA tool to obtain the layout after chamfering. After chamfering, the distance d at the convex corners of the two ion implantation regions 1 and 2 is greater than or equal to the preset distance. For example, that is, after chamfering, the distance d at the convex corners of the two ion implantation regions 1 and 2 is greater than or equal to the minimum layout spacing.

[0051] Optionally, in this step S13, the sizes of the respective convex corners 3 and 4 cut off in the corner-to-corner structure are the same.

[0052] In one example, in step S13, the respective convex corners 3 and 4 cut off in the corner-to-corner structure are triangles, and a new straight edge 5 and 6 are generated at each of the convex corners 3 and 4 after the chamfering. Further optionally, the new straight edges 5 and 6 generated at each of the convex corners 3 and 4 are parallel. The distance between the straight edges 5 and 6 is also greater than or equal to a preset distance.

[0053] Please refer to Figure 4 , in another example, in step S13, a rounded corner 3' and 4' protruding outward can be generated at each of the convex corners 3 and 4 after cutting off each convex corner 3 and 4. The distance between the rounded corners 3' and 4' of the two ion implantation regions 1 and 2 after the chamfering is also greater than or equal to a preset distance.

[0054] It should be understood that each of the convex corners 3 and 4 cut off in this step S13 cannot be too small, otherwise the required optical proximity correction (OPC) effect cannot be achieved here subsequently. Optionally, in this step S13, the lengths of the respective sides of each of the convex corners 3 and 4 cut off are all greater than 0, and the distance between the straight edges 5 and 6 generated after the chamfering is not less than the minimum layout pitch. Similarly, each of the convex corners 3 and 4 cut off in this step S13 cannot be too large, otherwise it will affect the requirements of the implantation region corresponding to the ion implantation layer. Optionally, the lengths of the respective sides of each of the cut-off convex corners are not greater than 1 / 2 of the length of the corresponding side of the convex corner before the chamfering process. For example, when the ion implantation regions 1 and 2 are rectangles, the side lengths of the cut-off convex corners 3 and 4 are not greater than 1 / 2 of the long side length of the ion implantation regions 1 and 2, nor greater than 1 / 2 of the short side length of the ion implantation regions 1 and 2.

[0055] In one example, the lengths of the respective sides of each of the cut-off convex corners 3 and 4 are not greater than of the minimum layout pitch, and the distance between the straight edges 5 and 6 generated after the chamfering is not less than the minimum layout pitch.

[0056] Please continue to refer to Figure 2 and Figure 3 , in step S14, use optical proximity correction (OPC) software to perform optical proximity correction on the layout after chamfering according to the previously determined correction rules to obtain the final layout of the ion implantation layer. Among them, the optical proximity correction in this step can be an experience-based optical proximity correction, and the correction rules it follows can be any suitable correction rules. For example, it can include moving the graphic edges of the corresponding ion implantation regions in the layout of the ion implantation layer, adding additional polygons to the corresponding positions of the ion implantation regions, etc., which will not be elaborated here.

[0057] Comparison Figure 1 and Figure 3 It can be found that, when the modification to the layout design of the ion implantation layer is relatively small, the optical proximity effect correction method for the ion implantation layer according to the present invention avoids the problem of the limitation of the mask rule check (MRC) on the corner-to-corner structure that is prone to becoming a process hot spot in the ion implantation layer. After cutting off the convex corners in the corner-to-corner structure, the space for optical proximity effect correction can be increased, so that the critical dimension of the final layout obtained by OPC can meet the target value, and it can solve the problem that the corner-to-corner structure pattern in the ion implantation layer in the prior art is prone to distortion and cause process hot spots, improve the accuracy of OPC correction, and further provide a more accurate final layout of the ion implantation layer. Thus, the photoresist pattern after exposure obtained from the final layout obtained by OPC is closer to the target value. Furthermore, when manufacturing semiconductor devices, it can have a better coverage range for both the front layer structure formed in the silicon wafer before the ion implantation layer and the back layer structure formed after the ion implantation layer, improving the product yield and performance of the product.

[0058] Based on this, please refer to Figure 5 and Figure 6 An embodiment of the present invention further provides a method for manufacturing a semiconductor device, which includes:

[0059] S20, adopting the optical proximity effect correction method for the ion implantation layer as described in the present invention to obtain the required final layout of the ion implantation layer;

[0060] S21, transferring the final layout of the ion implantation layer to a photomask 7;

[0061] S22, transferring the pattern on the photomask 7 to the photoresist 9 on the corresponding silicon wafer 8 through a lithography process (including a series of processes such as coating, exposure, and development);

[0062] S23, using an ion implanter (not shown) to implant specific impurity atoms into the silicon wafer area exposed by the photoresist 9 to form the required ion implantation layer 10 in the silicon wafer 8.

[0063] The method for manufacturing a semiconductor device according to the present invention utilizes the optical proximity effect correction method for the ion implantation layer of the present invention to obtain the required final layout of the ion implantation layer, transfers the final layout of the ion implantation layer to a photomask, and further transfers it to the photoresist on the silicon wafer through a lithography process. Since the final layout of the ion implantation layer is accurate, the difference between the actual photoresist pattern obtained on the silicon wafer and the layout pattern of the ion implantation layer can meet the requirements of the ion implantation process. Therefore, the product yield and performance of the product can be ultimately improved.

[0064] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for correcting the optical proximity effect of an ion implantation layer, characterized in that: The following steps are involved: Providing a layout of a related front layer, and performing a logic operation based on the layout of the related front layer to generate an original layout of the ion implantation layer; Finding a corner-to-corner structure to be processed from the original layout, wherein the corner-to-corner structure includes two convex corners with different angular directions, and the distance between the vertices of the two convex corners is less than a preset distance; Cut off each of the convex corners in the corner-to-corner structure by using EDA tool layout design software, and after cutting, a new straight edge or a rounded corner protruding outward is generated at each of the convex corners to obtain a layout after cutting; Performing optical proximity effect correction on the corner-cut layout using optical proximity effect correction software to obtain a final layout of the ion implantation layer; When performing optical proximity effect correction, the corner-to-corner structure after each of the convex corners is cut off by the EDA tool layout design software will be adequately compensated so that the exposed photoresist pattern obtained using the final layout is closer to the target value.

2. The optical proximity effect correction method according to claim 1, characterized in that: The preset distance is greater than or equal to the minimum spacing of the layout; and / or, before cutting the corners, the distance between the vertices of the two convex corners is less than the minimum spacing of the layout.

3. The optical proximity effect correction method according to claim 1, characterized in that: The corner-to-corner structure is two ion implantation regions in the ion implantation layer that are corner-to-corner and rectangular, and after corner cutting, the distance between the convex corners of the two ion implantation regions is greater than or equal to the preset distance.

4. The optical proximity effect correction method according to claim 1, wherein: Each of the convex angles is a right angle; and / or, the vertices of the two convex angles in the corner-to-corner structure coincide.

5. The optical proximity effect correction method according to claim 1, wherein: The sizes of the convex corners cut off in the corner-to-corner structure are the same; and / or, when a new straight edge is generated at each convex corner after cutting, the new straight edges generated at each convex corner are parallel.

6. The optical proximity effect correction method according to claim 1, wherein: Before corner cutting, the length of each side of each convex corner is greater than the minimum graphic size of the layout.

7. The method for correcting the optical proximity effect according to claim 6, wherein: The length of each side of each of the convex corners that is cut off is not greater than 1 / 2 of the length of the corresponding side of the convex corner before the corner cutting process.

8. The method for correcting the optical proximity effect according to claim 6, wherein: The length of each side of each convex corner cut off is not greater than the minimum spacing of the layout. .

9. A method for manufacturing a semiconductor device, characterized in that: include: Using the optical proximity effect correction method of the ion implantation layer according to any one of claims 1 to 8 to obtain the desired final layout of the ion implantation layer; transferring the final layout of the ion implantation layer onto a photomask; Transferring the pattern on the photomask to the photoresist on the corresponding silicon wafer through a photolithography process; An ion implanter is used to implant specific impurity atoms into the silicon wafer region exposed by the photoresist, so as to form a desired ion implantation layer in the silicon wafer.

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