Chip verification method and system

Abstract

The invention provides a chip verification method and system, and the method can obtain a test case, the test case comprises a plurality of operation tasks, address check information is generated according to the operation tasks, and the address check information comprises an accessible address range. The chip design module is controlled to execute the operation task, an access address when the chip design module executes the operation task is collected, and the access address is a memory address for reading or writing data when the operation task is executed. And if the access address is within the accessible address range, controlling the chip design module to continue executing the operation task to obtain an execution result of the operation task. And if the access address is not in the accessible address range, controlling the chip design module to stop executing the operation task, and generating border crossing address information based on the access address. According to the method, in the simulation process, the problem of address border crossing is solved by checking whether an access address exceeds an accessible address range of an operation task or not.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a chip verification method and system. Background Art

[0002] AI chips refer to chips that have an AI computing core (Neural Processing Unit, NPU) integrated into the chip. The AI ​​computing core is a hardware concept. The AI ​​computing core is the core part of the AI ​​chip, which can accelerate the operation of the neural network model (AI model). The use of the AI ​​computing core can quickly complete the operation of the AI ​​model. The AI ​​model is a software concept. The AI ​​model can perform various complex tasks, such as image recognition, speech recognition, natural language processing, etc.

[0003] In order to ensure that the computing tasks can be executed correctly and efficiently in the actual chip after tape-out, it is necessary to verify the operation process of the computing tasks on the register transfer level model. In chip verification, in order to ensure the validity of the skip read operation and the skip write operation in the computing task, the skip read address or the skip write address can be calculated by randomly generating the register configuration under the specified constraints, and data can be read from the skip read address or written to the skip write address. However, due to the computational complexity of the skip read address or the skip write address, positive overflow, negative overflow or illegal value problems may occur when randomly generating these register configurations, resulting in the calculated skip read address or the skip write address exceeding the legal address range, which in turn causes the address trampling problem and ultimately leads to verification failure. Summary of the invention

[0004] The present application provides a chip verification method and system to solve the problem of address crossing the boundary during chip verification.

[0005] In a first aspect, the present application provides a chip verification method, the method comprising:

[0006] Obtaining a test case, wherein the test case includes a plurality of computing tasks;

[0007] generating address check information according to the computing task, the address check information including an accessible address range;

[0008] Controlling the chip design module to execute the computing task;

[0009] Collecting an access address when the chip design module executes the computing task, wherein the access address is a memory address for reading or writing data when executing the computing task;

[0010] If the access address is within the accessible address range, controlling the chip design module to continue executing the computing task to obtain an execution result of the computing task;

[0011] If the access address is not within the accessible address range, the chip design module is controlled to stop executing the computing task, and out-of-bounds address information is generated based on the access address.

[0012] In a second aspect, the present application provides a chip verification system, including a simulation control component, a chip design module and an address checker; the simulation control component is configured to:

[0013] Obtaining a test case, wherein the test case includes a plurality of computing tasks;

[0014] generating address check information according to the computing task, the address check information including an accessible address range;

[0015] Controlling the chip design module to execute the computing task;

[0016] Control the address checker to collect the access address when the chip design module executes the computing task, and detect whether the access address is within the accessible address range, wherein the access address is a memory address for reading or writing data when executing the computing task;

[0017] If the access address is within the accessible address range, controlling the chip design module to continue executing the computing task to obtain an execution result of the test case;

[0018] If the access address is not within the accessible address range, the chip design module is controlled to stop executing the computing task, and out-of-bounds address information is generated based on the access address.

[0019] It can be seen from the above technical solutions that the present application provides a chip verification method and system, the method can obtain test cases, the test cases include multiple computing tasks, and address check information is generated according to the computing tasks, and the address check information includes an accessible address range. The chip design module is controlled to execute the computing task, and the access address when the chip design module executes the computing task is collected. The access address is the memory address for reading or writing data when executing the computing task. If the access address is within the accessible address range, the chip design module is controlled to continue to execute the computing task to obtain the execution result of the computing task. If the access address is not within the accessible address range, the chip design module is controlled to stop executing the computing task, and out-of-bounds address information is generated based on the access address. During the simulation process, the method solves the problem of address out-of-bounds by checking whether the access address exceeds the accessible address range of the computing task. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A schematic diagram of the architecture of a chip verification system provided in an embodiment of the present application;

[0022] Figure 2 A flowchart of address checking provided in an embodiment of the present application;

[0023] Figure 3 A schematic diagram of the verification process of a multi-task sequence a provided in an embodiment of the present application;

[0024] Figure 4 A schematic diagram of the verification process of the multi-task sequence b provided in an embodiment of the present application;

[0025] Figure 5 A schematic diagram of the verification process of the multi-task sequence c provided in an embodiment of the present application. DETAILED DESCRIPTION

[0026] The following embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following embodiments do not represent all implementations consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application as detailed in the claims.

[0027] AI chip refers to a chip (such as a system on a chip (SOC)) with an AI computing core (Neural Processing Unit, NPU) integrated into it, which is a dedicated processor for neural network models (AI models). AI computing core is a hardware concept. AI computing core is the core part of AI chip, which can accelerate the operation of neural network models. Using AI computing core can quickly complete the operator operation of AI model. AI model is a software concept. AI model can perform various complex tasks, such as image recognition, speech recognition, natural language processing, etc.

[0028] An operator is a single node on the AI ​​model. Each node represents an operator. The AI ​​model is composed of multiple nodes. Operators include: conv, pool, matmul, softmax, gather, scatter, etc. The operation of the neural network is to calculate each operator one by one according to certain topological sorting rules. Therefore, each operator can run independently on the AI ​​computing core.

[0029] In some embodiments, the gather operator and the scatter operator are used as skip read operators / skip write operators in various neural network models. AI chips need to build a dedicated hardware solution to support the above two operators to perform skip read operations and skip write operations on hardware. Skip read operations refer to reading data from multiple non-contiguous memory addresses, and skip write operations refer to writing data to multiple non-contiguous memory addresses.

[0030] For example, for the skip operation of the gather operator, the calculation formula for the skip address can be set: skip address (gather_addr) = starting address (gather_start_addr) + offset address (offset) + skip stride (stride) * index value (index). By configuring different starting addresses, offset addresses, skip strides, and index values ​​for registers as data to limit the value range, the AI ​​chip can access any address space of memories such as dynamic random access memory (DRAM) and static random access memory (SRAM) through the above formula to read or write data to the address. In verifying the hardware functions of the above chips, the starting address, offset address, skip stride, and index value randomly generated by the verification system may cause the skip address to cross the boundary, thereby causing the address trampling problem.

[0031] In some embodiments, in order to avoid the address trampling problem caused by the skip read address crossing the boundary, a memory management component can be used to allocate a certain size of memory space as a skip read range. This memory space is only used for skip read operations and other hardware modules shall not use it. The skip read address shall not exceed the address range corresponding to the memory space.

[0032] However, the starting address, offset address, skip step, and index value are all randomly generated by the verification system. The Register Transfer Level (RTL) module in the AI ​​computing core uses these register configurations and index data to calculate the skip address. Although constraints on the skip range are set in the verification scheme, verification errors still exist due to the complexity of the skip operation.

[0033] For example, when verification engineers are thinking about solutions or modifying constraints, they may fail to consider certain special scenarios due to typos or fail to pay attention to details such as register bit width and sign bit, which may lead to loopholes in the constraints they write. When the verification system randomly generates the starting address, offset address, skip step length, and index value under the specified constraints, there may be some positive overflows, negative overflows, and illegal values ​​generated due to the lack of constraints in special scenarios, which in turn leads to errors in the skip address calculated by the RTL module, and the skip accesses an illegal address, which ultimately leads to probabilistic errors in the data comparison results. This kind of error is not inevitable. It will only go wrong when the skip address is out of bounds and causes a specific address to be trampled. For example, the skip accesses an idle address. Although the skip address is out of bounds, the address is idle and there is no trampling problem, so there will be no error. This also leads to a certain degree of concealment of this kind of error, and a large number of regressions are required to discover the problem. A large number of regressions are time-consuming, which slows down the project progress.

[0034] In addition, even if errors are found, there are many reasons for data comparison errors, such as RTL module design errors, reference model component implementation errors, address trampling, etc. There are many causes of such errors, and the error location process is complex and time-consuming, which reduces verification efficiency and increases labor costs.

[0035] Based on the above embodiment, in order to ensure the validity of the skip read operation or the skip write operation, the verification system can calculate the skip read address or the skip write address by randomly generating a register configuration under specified constraints, and read data from the skip read address or write data to the skip write address. However, due to the complexity of the skip read address or the skip write address, problems such as positive overflow, negative overflow or illegal value may occur when randomly generating these register configurations, resulting in the calculated skip read address or the skip write address exceeding the legal address range, thereby causing the address trampling problem, and finally the problem of data comparison error occurs probabilistically, resulting in verification failure. In addition, the problem of data comparison error is related to multiple reasons, and the complexity of locating errors is high.

[0036] Therefore, some embodiments of the present application provide a chip verification system, such as Figure 1 As shown, it is a schematic diagram of the architecture of the chip verification system provided by an embodiment of the present application. The chip verification system includes a memory management component, a simulation control component, an address checker, a reference model component, a data packet transceiver, a comparison component and a simulation report component. The components in the verification system are interconnected. In order to realize chip verification, the chip design module to be verified, that is, the RTL module, is integrated in the verification system. The RTL module is connected to the components in the verification system by electrical signals, and an electrical signal level control and data interaction channel is created so that the RTL module can be correctly and effectively verified in the chip verification system.

[0037] The simulation control component is used to control the start and end of the simulation, configure the function registers for the RTL module, configure the function registers for the reference model component, initialize the data and write it to the memory management component, and configure the address check information for the address checker.

[0038] The address checker is used to check the out-of-bounds problem of the access address. The address checker is connected to the bus interface of the RTL module with an electrical signal to perform address sampling and checking. The interface of the address checker can be passed to the simulation control component to connect the simulation control component and the address checker, so that the simulation control component configures the address check information to the address checker.

[0039] The data packet transceiver is used to read or write data from the memory management component, and pack or unpack the data into data packets according to a specific bus protocol (such as the AXI protocol), and then transmit the data packets electrically to the RTL module.

[0040] The memory management component is used to manage memory space and implement unified memory management of the verification system. It can interact with multiple components in the verification system and perform corresponding operations, including initializing data in the specified memory area, reading and writing data, and other operations.

[0041] The reference model component is a functional module having the execution function of the RTL module and is used to simulate the function of the RTL module.

[0042] The comparison component is used to compare the output results of the RTL module with the output results of the reference model component, and write the comparison results into the simulation log file to ensure the correctness of the chip design function.

[0043] The simulation report component is used to retrieve the simulation log file, read and analyze the comparison results in the simulation log file, and generate and output a verification simulation report based on the comparison results.

[0044] For example, Figure 1As shown, the RTL module includes an operation unit for executing operation logic, such as an operation unit supporting the operation of the gather operator. It also includes three direct memory read access (Read Direct Memory Access, RDMA) modules, namely RDMA_0, RDMA_1 and RDMA_2, and two direct memory write access (WDMA) modules, namely WDMA_0 and WDMA_1. The verification system and the RTL module are connected by electrical signal lines, that is, the electrical signal lines between the data packet transceiver and the RTL module, the electrical signal lines between the simulation control component and the RTL module, and the electrical signal lines between each bus interface of the RTL module and the corresponding address checker, so as to realize data transmission. When the RTL module is running, RDMA_0, RDMA_1 and RDMA_2 read data from the internal management component to the inside of the chip through the data packet transceiver. The operation unit performs data processing on the data, such as matrix multiplication, convolution operation, etc. WDMA_0 and WDMA_1 write the processed data to the internal management component through the data packet transceiver.

[0045] like Figure 1 As shown, the verification system includes three address checkers, namely address checker 1, address checker 2 and address checker 3. The three address checkers are mounted on different bus interfaces to realize address checking of multiple bus interfaces. The three address checkers can be mounted on RDMA_0 bus interface, WDMA_0 bus interface and WDMA_1 bus interface respectively. The defined address checker can be instantiated into three copies in the verification system, and its electrical signal lines are connected to different bus interfaces respectively to complete the connection between the address checker and the RTL module. Then, the uvm_config_db mechanism (a mechanism for transmitting configuration information in Universal Verification Methodology (UVM)) is used to transmit the interfaces of the three address checkers to the simulation control component, so that the simulation control component can obtain the interfaces of the three address checkers, configure the address check information to each address checker through the interface, and realize the dynamic configuration of the address check range.

[0046] Address checker 1 can collect the memory address that RDMA_0 needs to read data from the memory area, and perform an address check on the memory address based on the address check information. Address checker 2 can collect the memory address that WDMA_0 needs to write data to the memory area, and perform an address check on the memory address based on the address check information. Address checker 3 can collect the memory address that WDMA_1 needs to write data to the memory area, and perform an address check on the memory address based on the address check information.

[0047] In this embodiment, an address checker is set in the verification system. The address checker is a special component used to check whether the access address is out of bounds. When it is detected that the access address is out of bounds, the simulation will be stopped immediately, and the accessible address range and the actual access address that is out of bounds will be recorded in the simulation log file to facilitate the analysis of the reason for the access address being out of bounds.

[0048] The address checker is a universal component that can be mounted on any address bus to implement the legality check of the valid address sent on the address bus. The address checker's address check range can be dynamically configured during the simulation process, that is, in a simulation, different address check ranges can be configured for the address checker in different time periods to cope with the problem that the access address range of each computing task is different during the multi-task execution process.

[0049] In some embodiments, Figure 2 As shown, the address checker includes 7 special registers, namely the first register (enable_check), the second register (max_addr), the third register (min_addr), the fourth register (print_addr_enable), the fifth register (elk), the sixth register (addr_valid) and the seventh register (actual_addr).

[0050] Among them, elk, addr_valid, actual_addr are directly connected to the RTL module by electrical signal lines to realize real-time sampling of the interface signal of the RTL module. enable_check, max_addr, min_addr, and print_addr_enable are configured to the verification system by means of an interface (such as the interface method). After the simulation control component in the verification system obtains the interface, the above four special registers can be dynamically configured at any time through the interface, thereby realizing the control of the address checker. The specific control content includes: controlling whether to perform address checking through enable_check, configuring the minimum memory address of the accessible address range through min_addr, configuring the maximum memory address of the accessible address range through max_addr, and controlling whether to print legal address information through print_addr_enable.

[0051] The following is an explanation of the functions of the above 7 registers:

[0052] clk: Clock signal, used for synchronous operation. The clk direct electrical signal line is connected to the clock of the RTL module to ensure that the clocks of the address checker and the RTL module are consistent and to ensure stable sampling.

[0053] addr_valid: address valid flag, indicating whether the current access address is valid. The address valid flag is the third flag or the fourth flag. The third flag is used to indicate that the access address is valid, and the fourth flag is used to indicate that the access address is invalid. The addr_valid direct electrical signal line is connected to the address valid indication bit of the RTL module, such as the axi_arvalid signal connected to the AXI bus, which is used to check whether the current access address is a valid address. If it is valid, the address check is performed.

[0054] actual_addr: address bit, representing the access address actually collected. The bit width of actual_addr can be dynamically configured to meet different address width requirements, such as the default bit width of actual_addr is configured as 64 bits. The actual_addr direct electrical signal line is connected to the address bit of the RTL module, such as the axi_araddr signal connected to the AXI bus, which is used to sample the access address issued by the RTL module for address checking.

[0055] enable_check: address check flag, which is a control bit that indicates whether address check is enabled. The address check flag is a first flag or a second flag, the first flag is used to indicate that address check is enabled, and the second flag is used to indicate that address check is not enabled. The enable_check is controlled by the simulation control component. For example, when the simulation control component sets it to 1, it indicates that address check is enabled, and when the simulation control component sets it to 0, it indicates that address check is not enabled. If the simulation control component sets it to 1 again after a certain period of time, the address check will be re-enabled.

[0056] max_addr: The maximum memory address allowed by the address check, which is controlled by the simulation control component. When actual_addr>max_addr, the address checker will report an error, record actual_addr, max_addr, and min_addr in the simulation log file, and trigger the simulation to stop.

[0057] min_addr: The minimum memory address allowed by the address check, which is controlled by the simulation control component. When actual_addr < min_addr, the checker will report an error, record actual_addr, max_addr, and min_addr in the simulation log file, and trigger the simulation to stop.

[0058] print_addr_enable: address printing flag, which is a control signal indicating whether to print normal address information. The address printing flag is the fifth flag or the sixth flag. The fifth flag is used to indicate that the access address is stored, and the sixth flag is used to indicate that the access address is not stored. The print_addr_enable is controlled by the simulation control component. For example, when the simulation control component sets it to 1, it indicates that the normal address information is printed, and when the simulation control component sets it to 0, it indicates that the normal address information is not printed.

[0059] Based on the above verification system, the process of executing chip verification by the verification system can be controlled by the simulation control component, which specifically includes the following steps:

[0060] The simulation control component obtains the test case. The test case is used to describe the execution operation sequence of the RTL module. The test case includes multiple operation tasks, and the operation process of the RTL module can be verified through the test case.

[0061] The simulation control component generates address check information according to the computing task. The address check information includes an accessible address range, and the accessible address range includes an upper address boundary and a lower address boundary. The upper address boundary is the maximum memory address accessible in the memory area when executing the computing task, and the lower address boundary is the minimum memory address accessible in the memory area when executing the computing task. The simulation control component can parse each computing task and the specific configuration of each computing task according to the test case, calculate the upper address boundary and the lower address boundary of each computing task according to the specific configuration, and generate the address check information corresponding to the computing task based on the upper address boundary and the lower address boundary.

[0062] After obtaining the address check information, the simulation control component can configure the address check information to the address checker so that the address checker performs the address check. Figure 2 In the address checker architecture shown, enable_check is used to indicate whether address checking is enabled, max_addr and min_addr are used to specify the accessible address range, and print_addr_enable is used to indicate whether to print the normal access address. Therefore, the simulation control component can configure four registers: enable_check, max_addr, min_addr, and print_addr_enable. Enable_check can be configured as the first identifier or the second identifier to indicate whether address checking is enabled. Configure max_addr as the upper boundary of the address and configure min_addr as the lower boundary of the address to specify the accessible address range. Configure print_addr_enable as the fifth identifier or the sixth identifier to indicate whether to print the normal access address.

[0063] After the address check information is configured, the simulation control component can configure the function registers of the RTL module according to the calculation task so that the RTL module can perform the calculation task. The function register is a register used to control the RTL module to perform the calculation function. The simulation control component can parse the configuration parameters of the register when performing the calculation task, and configure the function register of the RTL module according to the configuration parameters, thereby defining the calculation type, data format, precision, etc. of the RTL module, so that the RTL module can perform the corresponding calculation operation according to the requirements of the calculation task. In the process of the RTL module performing the calculation task, the access address will be calculated, and the data when performing the calculation task will be read or written in the memory area based on the access address.

[0064] When the RTL module executes a computing task, the address checker can collect the access address when the RTL module executes the computing task, and detect whether the access address is within the accessible address range based on the address check information.

[0065] The address checker can read the address check flag (enable_check) in the address check information to determine whether to perform an address check. If the address check flag is the first flag, it means that an address check is required, and then it is detected whether the access address is within the accessible address range. If the address check flag is the second flag, it means that an address check is not required, and then it is not detected whether the access address is within the accessible address range.

[0066] The address checker can also read the address valid flag (addr_valid) of the access address to determine whether the current access address is valid. If the address valid flag is the third flag, it means that the access address is valid, and then it is detected whether the access address is within the accessible address range. If the address valid flag is the fourth flag, it means that the access address is invalid, and then it is not detected whether the access address is within the accessible address range. In other words, the address out-of-bounds check is performed only when the current access address is valid and an address check is required.

[0067] When performing an address check, the address checker compares the collected access address (actual_addr) with the upper address boundary (max_addr) and the lower address boundary (min_addr). If the access address is greater than the upper address boundary, or the access address is less than the lower address boundary, it means that the access address is out of bounds, and the access address is marked as not within the accessible address range. If the access address is less than or equal to the upper address boundary, and the access address is greater than or equal to the lower address boundary, it means that the access address is not out of bounds, and the access address is marked as within the accessible address range.

[0068] If the access address is not within the range of accessible addresses, the simulation is triggered to stop. The address checker sends a simulation stop request to the simulation control component, so that the simulation control component, in response to the simulation stop request, controls the RTL module to stop executing arithmetic tasks. At the same time, out-of-bounds address information can also be generated based on the access address and recorded in the simulation log file.

[0069] If the access address is within the range of accessible addresses, the address checker can read the address print flag (print_addr_enable) in the address check information. If the address print flag is the fifth flag, the access address is stored and recorded in the simulation log file. If the address print flag is the sixth flag, the access address is not stored.

[0070] Since the access address is within the range of accessible addresses, the simulation stop is not triggered, and the address checker does not send a simulation stop request to the simulation control component. The RTL module will continue to execute arithmetic tasks to obtain the execution result of the arithmetic tasks.

[0071] Exemplarily, as Figure 2 shown, it is a schematic flowchart of the address checker performing address check provided by the embodiment of the present application. After the simulation control module controls the simulation to start, the address check logic of the address checker performs an address acquisition and check operation at the rising edge of each clock cycle. The address checker waits for the rising edge of the clock signal. At the rising edge of the clock, the address checker acquires the current access address and performs an address check according to the configured address check information.

[0072] First, it is detected whether (addr_valid && enable_check) is 1. If it is 1, it means that the current access address is valid and an address check is required, and the judgment of address out-of-bounds continues. If it is 0, it means that the current address is invalid or an address check is not required, and then continue to wait for the rising edge of the clock signal (clk).

[0073] If (addr_valid && enable_check) is 1, then continue to judge whether ((actual_addr > max_addr) || (actual_addr < min_addr)) is 1. If it is 1, it means the address is out of bounds. The out-of-bounds address information is recorded in the simulation log, and a simulation stop request is sent to the simulation control component to stop the simulation.

[0074] If ((actual_addr>max_addr) || (actual_addr<min_addr)) is 0, it indicates that the address is not out of bounds. Then, it is judged whether print_addr_enable is 1. If it is 1, the access address is recorded in the simulation log, and continue to wait for the rising edge of the clock. If it is 0, no processing is performed, and continue to wait for the rising edge of the clock.

[0075] In some embodiments, when the RTL module finishes executing a single arithmetic task, an end signal is generated. The simulation control component can respond to the end signal generated after the arithmetic task is executed, and configure the functional register of the reference model component according to the arithmetic task, so that the reference model component executes the arithmetic task to obtain the reference result of the arithmetic task.

[0076] The comparison component can obtain the execution result of the RTL module executing the arithmetic task and the reference result of the reference model component executing the arithmetic task, compare the execution result and the reference result to obtain a comparison result, and record the comparison result in the simulation log file.

[0077] The simulation report component is used to read and analyze the comparison result in the simulation log file, generate a verification simulation report according to the comparison result, and output the verification simulation report. For example, if the comparison result includes keywords such as ERROR and FAIL, a verification simulation report indicating simulation failure is generated, otherwise a verification simulation report indicating simulation success is generated.

[0078] In this embodiment, an address checker is set in the verification system to check whether the access address is out of bounds. And the range of address check can be dynamically configured during the simulation process. For example, during the multi-task simulation process, the access address range of each arithmetic task is different, so it only needs the simulation control component to configure the address check range of this arithmetic task before the start of each arithmetic task.

[0079] The address check can be started and stopped at any time during the simulation process. During the multi-task simulation process, only the skip read task or the skip write task needs to enable the check. During the execution phase of other arithmetic tasks that do not require address check, enable_check = 0 can be configured to turn off the address check, which has high flexibility.

[0080] The address checker can support skip read tasks, skip write tasks, and ordinary tasks at the same time. Since the effective address range of the skip read task or the skip write task changes each time, it needs to be dynamically configured. The address range of each access of the ordinary read and write task is fixed, and a fixed value can be configured for use, which improves the compatibility of the verification system.

[0081] The address checker can be freely bound to the address channel interface of any RTL module for address legality check. And the mounting method is simple, which improves the versatility and usability.

[0082] The address checker can quickly detect address out-of-bounds problems. Once an address out-of-bounds problem is detected, the simulation will be stopped immediately and relevant out-of-bounds address information will be printed, which will speed up the efficiency of verification engineers in self-checking address out-of-bounds problems, reduce the manpower input for debugging, and improve the R&D progress of the project.

[0083] For errors of illegal address access, the error report is clear and the result is clear. There is no problem of incorrect comparison of reference model components and RTL module output results due to illegal address access. It is easy to locate the cause of the error, such as reference model components, RTL modules, address trampling, etc.

[0084] The verification system provided by this application is described below with reference to specific embodiments.

[0085] Embodiment 1: A multi-task sequence a includes 4 skip read tasks and 2 common tasks. An address checker 1 is used to check whether an access address is out of bounds. Assume that an address out of bounds occurs in the middle.

[0086] Start the simulation, the simulation control component reads the test case and parses the Figure 3 The six computing tasks and the specific configuration of each computing task are shown. The min_addr and max_addr of each computing task are calculated according to the specific configuration, thereby generating address check information of each computing task.

[0087] At time t0, the simulation control component configures the function register of skip task 1 for the RTL module, and configures the address check information corresponding to skip task 1 for address checker 1: enable_check=1, max_addr=2M, min_addr=0.8M, print_addr_enable=0.

[0088] The simulation control component starts the RTL module to execute the skip reading task 1. During the execution of the skip reading task 1, the address checker 1 collects the skip reading address during the execution of the skip reading task 1, and performs address out-of-bounds detection based on the address check information.

[0089] The simulation control component waits for the end signal of the RTL module executing the skip task 1, and in response to the end signal, configures and starts the reference model component to execute the skip task 1.

[0090] The comparison component compares the execution result of the RTL module executing the skip task 1 with the execution result of the reference model component executing the skip task 1, and writes the comparison result to the simulation log file.

[0091] At time t1, the simulation control component configures the function register of the common task 2 for the RTL module, and configures the address check information corresponding to the common task 2 for the address checker 1: enable_check=0, indicating that no address check is performed.

[0092] The simulation control component starts the RTL module to execute the common task 2. Waiting for the end signal of the RTL module completing the execution of the common task 2, in response to the end signal, configures and starts the reference model component to execute the common task 2.

[0093] The comparison component compares the execution result of the RTL module executing the common task 2 with the execution result of the reference model component executing the common task 2, and writes the comparison result into the simulation log file.

[0094] At time t2, the simulation control component configures the function register of skip task 3 for the RTL module, and configures the address check information corresponding to skip task 3 for address checker 1, enable_check=1, max_addr=6.5M, min_addr=4M, print_addr_enable=1.

[0095] The simulation control component starts the RTL module to execute the skip reading task 3. During the execution of the skip reading task 3, the address checker 1 collects the skip reading address during the execution of the skip reading task 3, and performs address cross-bounds detection based on the address check information.

[0096] When the address checker 1 detects that actual_addr=9M and actual_addr>max_addr, the out-of-bounds address information and the error keyword (such as ERROR) are recorded in the simulation log file, and the simulation is triggered to stop.

[0097] The simulation report component checks the simulation log file and outputs a verification simulation report indicating the simulation failure if an error keyword is detected, so that the verification engineer can view the simulation log file and debug the cause of the illegal address.

[0098] Embodiment 2: The multi-task sequence b includes 2 skip read tasks and 1 normal task. The address checker 1 is used to check whether the access address is out of bounds. It is assumed that no address out of bounds occurs in the middle.

[0099] Start the simulation, the simulation control component reads the test case and parses the Figure 4 The three computing tasks and the specific configuration of each computing task are shown. The min_addr and max_addr of each computing task are calculated according to the specific configuration, thereby generating address check information of each computing task.

[0100] At time t0, the simulation control component configures the function register of skip task 1 for the RTL module, and configures the address check information corresponding to skip task 1 for address checker 1: enable_check=1, max_addr=2M, min_addr=0.8M, print_addr_enable=0.

[0101] The simulation control component starts the RTL module to execute the skip reading task 1. During the execution of the skip reading task 1, the address checker 1 collects the skip reading address during the execution of the skip reading task 1, and performs address out-of-bounds detection based on the address check information.

[0102] The simulation control component waits for the end signal of the RTL module executing the skip task 1, and in response to the end signal, configures and starts the reference model component to execute the skip task 1.

[0103] The comparison component compares the execution result of the RTL module executing the skip task 1 with the execution result of the reference model component executing the skip task 1, and writes the comparison result to the simulation log file.

[0104] At time t1, the simulation control component configures the function register of the common task 2 for the RTL module, and configures the address check information corresponding to the common task 2 for the address checker 1: enable_check=0, indicating that no address check is performed.

[0105] The simulation control component starts the RTL module to execute the common task 2. Waiting for the end signal of the RTL module completing the execution of the common task 2, in response to the end signal, configures and starts the reference model component to execute the common task 2.

[0106] The comparison component compares the execution result of the RTL module executing the common task 2 with the execution result of the reference model component executing the common task 2, and writes the comparison result into the simulation log file.

[0107] At time t2, the simulation control component configures the function register of skip task 3 for the RTL module, and configures the address check information corresponding to skip task 3 for address checker 1, enable_check=1, max_addr=6.5M, min_addr=4M, print_addr_enable=1.

[0108] The simulation control component starts the RTL module to execute the skip reading task 3. During the execution of the skip reading task 3, the address checker 1 collects the skip reading address during the execution of the skip reading task 3, and performs address out-of-bounds detection based on the address check information. If no address out-of-bounds is detected, the currently collected skip reading address is recorded in the simulation log file.

[0109] The simulation control component waits for the end signal of the RTL module executing the skip task 3, and in response to the end signal, configures and starts the reference model component to execute the skip task 3.

[0110] The comparison component compares the execution result of the RTL module executing the skip task 3 with the execution result of the reference model component executing the skip task 3, and writes the comparison result into the simulation log file.

[0111] The simulation control component actively ends the simulation. After the simulation ends, the simulation report component checks the simulation log file. If no error keywords are detected, a verification simulation report indicating a successful simulation is output.

[0112] Embodiment 3: Multi-task sequence c includes 3 common tasks, and uses address checker 2 to check whether the access address is out of bounds, assuming that no address out of bounds occurs in the middle. In this scenario, since the address range accessed by the common task is fixed each time, the address check information only needs to be configured once.

[0113] Start the simulation, the simulation control component reads the test case and parses the Figure 5 The three computing tasks and the specific configuration of each computing task are shown. The min_addr and max_addr of each computing task are calculated according to the specific configuration, thereby generating address check information of each computing task.

[0114] At time t0, the simulation control component configures the function register of ordinary task 1 for the RTL module, and configures the address check information for address checker 1: enable_check=1, max_addr=100M, min_addr=0M, print_addr_enable=0.

[0115] The simulation control component starts the RTL module to execute the common task 1. During the execution of the common task 1, the address checker 1 collects the access address during the execution of the common task 1, and performs address out-of-bounds detection based on the address check information.

[0116] The simulation control component waits for the end signal of the RTL module executing the common task 1, and in response to the end signal, configures and starts the reference model component to execute the common task 1.

[0117] The comparison component compares the execution result of the RTL module executing the common task 1 with the execution result of the reference model component executing the common task 1, and writes the comparison result into the simulation log file.

[0118] At time t1, the simulation control component configures the function register of the common task 2 for the RTL module. The simulation control component starts the RTL module to execute the common task 2. During the execution of the common task 2, the address checker 1 collects the access address during the execution of the common task 2, and performs address out-of-bounds detection based on the address check information.

[0119] The simulation control component waits for the end signal of the RTL module executing the common task 2, and in response to the end signal, configures and starts the reference model component to execute the common task 2.

[0120] The comparison component compares the execution result of the RTL module executing the common task 2 with the execution result of the reference model component executing the common task 2, and writes the comparison result into the simulation log file.

[0121] At time t2, the simulation control component configures the function register of the common task 3 for the RTL module. The simulation control component starts the RTL module to execute the common task 3. During the execution of the common task 3, the address checker 1 collects the access address during the execution of the common task 3, and performs address out-of-bounds detection based on the address check information.

[0122] The simulation control component waits for the end signal of the RTL module executing the common task 3, and in response to the end signal, configures and starts the reference model component to execute the common task 3.

[0123] The comparison component compares the execution result of the RTL module executing the common task 3 with the execution result of the reference model component executing the common task 3, and writes the comparison result into the simulation log file.

[0124] The simulation control component actively ends the simulation. After the simulation ends, the simulation report component checks the simulation log file. If no error keywords are detected, a verification simulation report indicating a successful simulation is output.

[0125] Based on the above chip verification system. Some embodiments of the present application also provide a chip verification method, which is applied to the chip verification system described in the above embodiment. The method comprises the following steps:

[0126] Get a test case, which includes multiple computing tasks.

[0127] Address check information is generated according to the operation task, and the address check information includes an accessible address range.

[0128] The control chip design module performs computing tasks.

[0129] The access address of the acquisition chip design module when performing a computing task. The access address is the memory address where data is read or written when performing a computing task.

[0130] If the access address is within the accessible address range, the control chip design module continues to execute the calculation task to obtain the execution result of the calculation task.

[0131] If the access address is not within the accessible address range, the control chip design module stops executing the calculation task and generates out-of-bounds address information based on the access address.

[0132] The same and similar parts between the various embodiments in this specification can be referenced to each other and will not be described again here.

[0133] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A chip verification method, characterized in that: The method comprises: Obtaining a test case, wherein the test case includes a plurality of computing tasks; generating address check information according to the computing task, the address check information including an accessible address range; Controlling the chip design module to execute the computing task; Collecting an access address when the chip design module executes the computing task, wherein the access address is a memory address for reading or writing data when executing the computing task; If the access address is within the accessible address range, controlling the chip design module to continue executing the computing task to obtain an execution result of the computing task; If the access address is not within the accessible address range, the chip design module is controlled to stop executing the computing task, and out-of-bounds address information is generated based on the access address.

2. The chip verification method according to claim 1, characterized in that: The method further comprises: According to the test case, an upper address boundary and a lower address boundary of the computing task are set, wherein the upper address boundary is a maximum memory address accessible in a memory area when executing the computing task, and the lower address boundary is a minimum memory address accessible in a memory area when executing the computing task; The address check information is generated based on the upper address boundary and the lower address boundary.

3. The chip verification method according to claim 2, characterized in that: The method further comprises: If the access address is greater than the upper address boundary, or the access address is less than the lower address boundary, mark the access address as not being within the accessible address range; If the access address is less than or equal to the upper address boundary, and the access address is greater than or equal to the lower address boundary, the access address is marked as being within the accessible address range.

4. The chip verification method according to claim 1, characterized in that: The address check information further includes an address check identifier, the address check identifier is a first identifier or a second identifier, the first identifier is used to indicate that the address check is enabled, and the second identifier is used to indicate that the address check is not enabled, and the method further includes: Reading the address check identifier in the address check information; If the address check identifier is the first identifier, detecting whether the access address is within the accessible address range; If the address check flag is the second flag, it is not detected whether the access address is within the accessible address range.

5. The chip verification method according to claim 1, characterized in that: The method further comprises: Reading an address validity identifier of the access address; the address validity identifier is a third identifier or a fourth identifier, the third identifier is used to indicate that the access address is valid, and the fourth identifier is used to indicate that the access address is invalid; If the address valid identifier is the third identifier, detecting whether the access address is within the accessible address range; If the address validity identifier is the fourth identifier, it is not detected whether the access address is within the accessible address range.

6. The chip verification method according to claim 1, characterized in that: The address check information further includes an address printing mark, the address printing mark is a fifth mark or a sixth mark, the fifth mark is used to indicate that the access address is stored, and the sixth mark is used to indicate that the access address is not stored, and the method further includes: If the access address is within the accessible address range, reading the address printing mark in the address check information; If the address printing mark is the fifth mark, storing the access address; If the address printing mark is the sixth mark, the access address is not stored.

7. The chip verification method according to claim 1, characterized in that: The method further comprises: Configure the function register of the chip design module according to the computing task so that the chip design module performs the computing task; The chip design module calculates an access address, and based on the access address, reads or writes data when executing the computing task in a memory area.

8. The chip verification method according to claim 7, characterized in that: The method further comprises: In response to an end signal generated after the computing task is completed, configuring a function register of a reference model component according to the computing task so that the reference model component executes the computing task, the reference model component being a function module having an execution function of the chip design module; Obtaining a reference result of the reference model component executing the computing task; Comparing the execution result with the reference result to obtain a comparison result; Generate a verification simulation report according to the comparison result; The verification simulation report is output.

9. A chip verification system, characterized in that: The invention comprises a simulation control component, a chip design module and an address checker; the simulation control component is configured as follows: Obtaining a test case, wherein the test case includes a plurality of computing tasks; generating address check information according to the computing task, the address check information including an accessible address range; Controlling the chip design module to execute the computing task; Control the address checker to collect the access address when the chip design module executes the computing task, and detect whether the access address is within the accessible address range, wherein the access address is a memory address for reading or writing data when executing the computing task; If the access address is within the accessible address range, controlling the chip design module to continue executing the computing task to obtain an execution result of the test case; If the access address is not within the accessible address range, the chip design module is controlled to stop executing the computing task, and out-of-bounds address information is generated based on the access address.

10. The chip authentication system according to claim 9, characterized in that: The address checker includes a first register, a second register and a third register, wherein the first register is used to indicate whether to enable address checking, and the second register and the third register are used to specify an accessible address range; after the simulation control component executes the step of generating address checking information according to the computing task, the simulation control component is further configured to: Configuring the first register as a first identifier, where the first identifier is used to indicate that address checking is enabled; configuring the second register as an upper address boundary, wherein the upper address boundary is a maximum memory address accessible in the memory area when executing the computing task; The third register is configured as a lower address boundary, where the lower address boundary is a minimum memory address accessible in a memory area when executing the computing task.

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