Method and apparatus for electronic design automation

Abstract

The embodiment of the invention relates to the field of electronic design automation, and provides a method and equipment for electronic design automation. Boolean logic representing the circuit is logically optimized to obtain optimized Boolean logic. The Boolean logic is process mapped to obtain a netlist representing the circuitry. And performing netlist optimization on the netlist to obtain an optimized netlist. In response to determining that the optimized netlist is superior to the locally optimal netlist representing the circuit, the locally optimal netlist is replaced with the optimized netlist, and the optimized netlist is process mapped. In this way, the efficiency of logic synthesis can be significantly improved.

Description

Method and apparatus for electronic design automation Technical Field

[0001] Embodiments of the present disclosure relate to Electronic Design Automation (EDA), and more particularly, to methods and apparatus for electronic design automation. Background Art

[0002] In the integrated circuit design process, logic synthesis is a critical link that connects the entire process and contributes to circuit performance (smaller, faster, and more energy-efficient). Logic synthesis converts the high-level description of the designed digital circuit into a circuit connection netlist at the logic gate level after simplifying and optimizing it using Boolean functions. The existing logic synthesis process converts the register conversion-level circuit described in a hardware description language into a Boolean circuit and then optimizes it while meeting design constraints. Circuit delay and area are two important optimization objectives, and delay and area are closely related to the circuit hierarchy and number of nodes, respectively.

[0003] The logic synthesis optimization process typically includes logic optimization, mapping, and netlist optimization. These optimization problems are all NP-hard. Existing methods often achieve the optimization goals at each stage by iteratively applying different local or global optimization operators. These operators vary in design, resulting in varying optimization targets. The final logic synthesis optimization result is highly dependent on the sequence of operators used and their parameters, and the space for permutations and combinations of operators and their parameters is enormous.

[0004] Summary of the Invention

[0005] The embodiments of the present disclosure provide an electronic design automation solution, particularly a logic synthesis solution.

[0006] In a first aspect of the present disclosure, a method for electronic design automation is provided. In this method, logic optimization is performed on Boolean logic representing a circuit to obtain an optimized Boolean logic. The Boolean logic is subjected to process mapping to obtain a netlist representing the circuit. Netlist optimization is performed on the netlist to obtain an optimized netlist. In response to determining that the optimized netlist is superior to a local optimal netlist representing the circuit, the local optimal netlist is replaced with the optimized netlist, and process mapping is performed on the optimized netlist.

[0007] In addition to the traditional outer-level iterations of logic optimization, process mapping, and netlist optimization, inner-level iterations of process mapping and netlist optimization oriented towards final netlist performance can accelerate convergence and improve the optimization effect of logic synthesis.

[0008] In each iteration, the operator sequence can be specified through expert experience, or dynamically recommended operator combinations and parameters using data-driven algorithms. Furthermore, detailed circuit features are designed to accurately model circuit states for dynamic operator recommendation.

[0009] In a second aspect of the present disclosure, the present disclosure provides a device, comprising: a processor; and a memory coupled to the processor and containing instructions stored therein, wherein when the instructions are executed by the processor, the device performs the method of the first aspect of the present disclosure.

[0010] In a third aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program / instruction is stored. When the computer program / instruction is executed by a processor, the steps of the method in the first aspect of the present disclosure are implemented.

[0011] In a fourth aspect of the present disclosure, a computer program product is provided, comprising a computer program / instruction, which implements the steps of the method in the first aspect of the present disclosure when the computer program / instruction is executed by a processor.

[0012] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the disclosure, nor is it intended to limit the scope of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present disclosure.

[0014] FIG1 shows a flowchart of a method for designing an integrated circuit according to some embodiments of the present disclosure.

[0015] FIG2 shows a schematic flowchart of a logic synthesis method according to some embodiments of the present disclosure.

[0016] FIG3 shows a schematic flowchart of a logic synthesis method according to some embodiments of the present disclosure.

[0017] FIG4 shows a schematic flow chart of a logic synthesis method according to some embodiments of the present disclosure.

[0018] FIG5 shows a schematic block diagram of a device that can be used to implement an embodiment of the present disclosure.

[0019] As is common practice, the various features shown in the accompanying drawings may not be drawn to scale. Therefore, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. Additionally, some of the accompanying drawings may not depict all components of a given system, method, or apparatus. Finally, similar reference numerals may be used to denote similar features throughout the specification and accompanying drawings. DETAILED DESCRIPTION

[0020] The following describes embodiments of the present disclosure in more detail with reference to the accompanying drawings. Although certain embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are for illustrative purposes only and are not intended to limit the scope of protection of the present disclosure.

[0021] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. can refer to different or the same objects. The term "and / or" means at least one of the two items it is associated with. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below.

[0022] It should be understood that in the technical solutions provided by the embodiments of the present application, some repetitions may not be repeated in the introduction of the following specific embodiments, but these specific embodiments should be regarded as having been referenced to each other and can be combined with each other.

[0023] FIG1 illustrates a flow chart of a method 100 for designing a semiconductor chip according to some embodiments of the present disclosure. Method 100 may be implemented, at least in part, by an electronic design automation (EDA) tool. At block 102, functional requirements for a chip are defined. The chip may be a processor, a memory chip, or a system on chip (SoC) having multiple components. The functional requirements may include the properties of the chip and performance targets for the chip.

[0024] At block 104, an Electronic System Level (ESL) description is generated based on the functional requirements of the chip. An ESL description focuses on a higher level of abstraction without considering lower-level implementations. The goal of an ESL description is to increase the likelihood of successful functional implementation. Appropriate abstractions are used to generate a global understanding of the chip being designed.

[0025] At block 106, a Register Transfer Level (RTL) description is generated from the ESL description. The RTL description is a description of the semiconductor chip design in terms of its operation. Specifically, the behavior of the circuit is defined based on the signal flow between hardware registers in the RTL description. For example, a Hardware Description Language (HDL) can be used to create a high-level representation of the circuit, from which a low-level representation and ultimately the actual discrete components and wiring can be derived.

[0026] At block 108, logic synthesis is performed on the chip's RTL description. For example, the chip's HDL RTL description is converted into a gate-level description of the chip. Specifically, the gate-level description is a discrete netlist of logic gate primitives, i.e., netlist 110. After obtaining netlist 110, it can be simulated to determine whether the design implements the intended functionality or design intent. This simulation is also called "pre-simulation" or "pre-layout simulation."

[0027] At block 112, the chip is physically designed based on the netlist 110 to construct the physical layout of the chip. For example, components such as logic gates may be placed and wired to provide interconnections between the components' signal and power terminals. In this manner, a chip layout 114 may be constructed.

[0028] At block 116 , the layout 114 is physically verified. For example, a design rule check (DRC) may be performed on the layout 114 . The layout is drawn according to design rules, which may be provided by the foundry. During the DRC, the layout 114 is checked to see if it meets the corresponding design rules.

[0029] After layout 114 passes the design rule check, there may still be errors in layout 114. These errors are not caused by violating the design rules, but may be caused by inconsistency with the circuit diagram. For example, layout 114 may be missing a connection line. This small defect is also fatal to the entire chip. Therefore, layout 114 can also be subjected to layout and schematic comparison (Layout Versus Schematic, LVS), also known as consistency check. In the consistency check, a netlist is extracted from layout 114 and compared with netlist 110 to ensure that the extracted netlist is consistent with netlist 110. In addition, parasitic extraction (PEX) can be performed on layout 114. In parasitic extraction, parasitic parameters such as resistors and capacitors can be extracted from layout 114, and a netlist containing these parasitic parameters is output, also known as a parasitic netlist.

[0030] At block 118, the netlist containing the parasitic parameters is simulated. This simulation is also referred to as "post-simulation" or "post-layout simulation." Therefore, the parasitic parameter netlist used for post-simulation is also referred to as a post-simulation netlist. In post-simulation, an accurate analog model of the circuit is constructed to simulate the response of an actual digital and / or analog circuit.

[0031] At block 118 , layout post-processing may be performed on the layout 114 . For example, structures such as seal rings may be added, resolution enhancement techniques may be applied, etc. After layout post-processing, mask data 120 may be generated for final chip fabrication.

[0032] It should be understood that Figure 1 merely illustrates a schematic flow chart of IC design. In some embodiments, some steps may be added or deleted, or the order of some steps may be modified.

[0033] FIG2 shows a schematic flow chart of a logic synthesis method 200 according to some embodiments of the present disclosure. For example, the logic synthesis method 200 may be implemented at block 108 as shown in FIG1 .

[0034] The initial netlist 202 may be an RTL description of the chip, for example, a representation in HDL language. For example, the initial netlist 202 may be determined according to the RTL description of the chip (for example, HDL description).

[0035] At block 204 , logic optimization is performed on the initial netlist 202 . Logic optimization involves optimizing and simplifying the logic of the Boolean circuit and is a process-independent optimization. For example, the logic of the Boolean circuit can be represented by Boolean functions or logic graphs. Examples of logic graphs include an And-Inverter Graph (AIG) and a Majority-Inverter Graph (MIG).

[0036] When performing logic optimization on the initial netlist 202 , the initial netlist 202 may be first converted into a representation of the logic of a Boolean circuit, such as a Boolean function, a logic diagram, etc. Then, one or more logic optimization operators are used to optimize the logic of the Boolean circuit.

[0037] In some embodiments, at block 204, a sequence of logic optimization operators may be invoked to optimize the logic graph. An operator may represent an optimization method and its parameters. For example, the sequence of logic optimization operators may be empirically determined, or dynamically determined using algorithms such as random search, simulated annealing, reinforcement learning, or Bayesian optimization, given a set of operators and a range of parameters.

[0038] In block 206, process mapping is performed on the Boolean logic representing the circuit to determine a netlist representing the circuit. Process mapping maps the logical structure of the Boolean circuit into an implementable gate-level circuit structure. For example, process mapping can be a lookup table (LUT) mapping, a standard cell mapping, etc. In some embodiments, a process mapping operator sequence can be called to perform process mapping. For example, the process mapping operator sequence can be set empirically or dynamically determined using algorithms such as random search, simulated annealing, reinforcement learning, Bayesian optimization, etc., given a set of operators and a parameter range.

[0039] At block 208, netlist optimization is performed on the netlist representing the circuit to obtain an optimized netlist. In some embodiments, a sequence of netlist optimization operators may be invoked to perform netlist optimization. For example, the sequence of netlist optimization operators may be empirically determined or dynamically determined using algorithms such as random search, simulated annealing, reinforcement learning, Bayesian optimization, etc., given a set of operators and a parameter range.

[0040] At block 210 , a determination is made as to whether to perform a mapping iteration. For example, the determination as to whether to continue the process mapping-netlist optimization iteration loop may be based on preset configurations such as historical circuit characteristics, operator operation status, and iteration termination conditions. This loop is also referred to as the inner loop.

[0041] In the inner loop, the performance, power, and area (PPA) of the mapped netlist are the primary optimization targets, thereby accelerating convergence. During the inner loop of process mapping and netlist optimization, if the netlist obtained after executing block 206 or 208 is better than the local optimal netlist 216, that netlist is used to replace the local optimal netlist 216 to update the local optimal netlist 216.

[0042] At block 210, the circuit characteristics of the final netlist from the previous inner-level iteration and the current netlist are analyzed to determine whether to continue inner-level iterations. If it is determined at block 210 that inner-level iterations should continue, the current netlist is passed to block 206 to continue the inner-level loop. If it is determined at block 210 that inner-level iterations should not continue, the locally optimal netlist is passed to block 212.

[0043] In some embodiments, at block 210 , the number of search degradations or pre-set number of cycles that the current netlist is worse than the local optimal netlist can be counted. If the number of search degradations or cycles reaches a threshold, the output is no, otherwise the output is yes.

[0044] At block 212, a determination is made as to whether to continue the outer loop based on preset configurations, including historical circuit characteristics, operator execution status, and iteration termination conditions. In some embodiments, the determination as to whether to continue the outer iteration is made by analyzing the circuit characteristics of the local optimal netlist from previous outer iterations and the current local optimal netlist. If the current local optimal netlist is superior to the global optimal netlist, the current local optimal netlist replaces the global optimal netlist. If the output is yes, the global optimal netlist is passed to block 204. If not, the global optimal netlist is output as the final synthesized netlist 214.

[0045] In some embodiments, configuration file 218 may include all runtime configuration files required for process-independent logic synthesis, specifically operator and parameter settings, constraints, process library 220, and optimization targets and iteration termination conditions 222. Operator and parameter settings, constraints, and process library 220 include the operator pools and their associated parameters for the logic optimization phase, process mapping phase, and netlist optimization phase, along with the approximate correspondence between these parameters and optimization results, constraints such as maximum area and maximum delay, and the process device library required for mapping and netlist optimization. Optimization targets and iteration termination conditions 222 include weights for key optimization targets such as delay, area, and runtime, as well as runtime, the number of iterations, optimization target constraints, and iteration termination conditions such as the degree of relaxation for constraint conflicts.

[0046] Feature extraction and operator recommendation 224 can obtain the current circuit state from block 204, 206, or 208 and, based on the optimization results of the historical operator sequence, determine the operator sequence for the next iteration and recommend it to block 204, 206, or 208, respectively. Refined circuit features include circuit statistical features such as the number of circuit nodes and critical path length, as well as fine-grained operator benefit distribution. When determining the operator sequence, feature extraction and operator recommendation 224 can obtain relevant configuration information from configuration file 218, such as operator and parameter settings, constraints, process library 220, and optimization objectives and iteration termination conditions 222. In one embodiment, feature extraction and operator recommendation 224 can dynamically determine the operator sequence for the next iteration, given an operator set and parameter range, using algorithms such as random search, simulated annealing, reinforcement learning, and Bayesian optimization.

[0047] 3 shows a schematic flow chart of a logic synthesis method 300 according to some embodiments of the present disclosure. The method 300 may be a specific embodiment of the method 200.

[0048] In Figure 3, logic optimization includes blocks 303 and 304. In block 303, area-first logic optimization is performed. For example, area-first logic optimization uses a sequence of area-first logic optimization operators to optimize the Boolean logic of the circuit. In block 304, level-first logic optimization is performed. For example, level-first logic optimization uses a sequence of level-first logic optimization operators to optimize the Boolean logic of the circuit. For example, block 303 can optimize the area of ​​the logic diagram without degrading the level. In some cases, block 303 can simultaneously optimize both the area and the level of the logic diagram. For example, block 304 can optimize the level of the logic diagram, but may degrade the area of ​​the logic diagram. In some cases, block 304 can simultaneously optimize both the area and the level of the logic diagram.

[0049] In FIG3 , process mapping includes blocks 305 and 306 . In block 305 , area-first process mapping is performed, e.g., using a sequence of area-first process mapping operators. In block 306 , level-first process mapping is performed, e.g., using a sequence of level-first process mapping operators. For example, block 305 may be area-first LUT netlist process mapping, but may degrade level. Block 306 may be level-first LUT netlist process mapping, but may degrade area. In some cases, block 306 may optimize both area and level simultaneously.

[0050] In FIG3 , the netlist optimization includes a box 307 and a box 308 , wherein, in box 307 , area-first netlist optimization is performed, for example, area-first netlist optimization uses an area-first netlist optimization operator sequence to perform netlist optimization, and in box 308 , level-first netlist optimization is performed, for example, level-first netlist optimization uses a level-first netlist optimization operator sequence to perform netlist optimization.

[0051] In boxes 303-308, operator combinations can be set based on expert experience, or given an operator set and parameter range, algorithms such as random search, simulated annealing, reinforcement learning, Bayesian optimization, etc. can be called to dynamically search the operator sequence in any box in boxes 303-308.

[0052] In method 300, the outer loop includes logic optimization, process mapping, and netlist optimization, where the optimization target of logic optimization is the relevant indicators of the logic diagram, while the optimization target of process mapping and netlist optimization is the PPA of the netlist. In other words, the inner loop of process mapping and netlist optimization is oriented towards the final optimization target, that is, the PPA of the netlist. The outer loop of logic optimization, process mapping, and netlist optimization (boxes 303-308) adjusts the starting optimization point of process mapping and netlist optimization by modifying the logic diagram through logic optimization, thereby introducing a certain degree of randomness or robustness and jumping out of the local minimum during the search. Moreover, in method 300, area optimization and hierarchy optimization can be performed alternately to search for a better point.

[0053] 4 shows a flow chart of a logic synthesis method 400 according to some embodiments of the present disclosure. In block 402, operators and parameter settings, constraints, process library modules, optimization goals, and iteration termination conditions are set in a configuration file.

[0054] In block 404 , a circuit file is input, and an operator sequence and a final circuit netlist file are automatically generated by searching.

[0055] At block 406, the final circuit netlist file and report are analyzed. If, at block 408, all constraints are satisfied, method 400 ends and the netlist is passed to the next stage. If, at block 408, some constraints are unsatisfactory, method 400 proceeds to block 410. If, at block 410, conflicts are acceptable or runtime limits are met, method 400 proceeds to the next stage. If, at block 410, conflicts are unacceptable and runtime limits are not met, method 400 returns to block 402 to adjust the configuration file accordingly.

[0056] FIG5 shows a schematic block diagram of a device 500 that can be used to implement an embodiment of the present disclosure. The methods 100 - 400 shown in FIG1 - FIG4 can be implemented by the device 500.

[0057] As shown in Figure 5, the device 500 includes a central processing unit (CPU) 501, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 502 or loaded from a storage unit 508 into a random access memory (RAM) 503. Various programs and data required for the operation of the device 500 can also be stored in the RAM 503. The CPU 501, ROM 502, and RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0058] Various components in device 500 are connected to I / O interface 505, including: an input unit 506, such as a keyboard, mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, optical disk, etc.; and a communication unit 509, such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0059] The various processes and treatments described above, such as methods 100-400, may be performed by the processing unit 501. For example, in some embodiments, the methods 100-400 may be implemented as a computer software program that is tangibly contained in a machine-readable medium, such as the storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed onto the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the CPU 501, one or more steps of the methods 100-400 described above may be performed. Alternatively, in other embodiments, the CPU 501 may be configured to perform the methods 100-400 in any other suitable manner (e.g., by means of firmware).

[0060] The present disclosure may be a method, an apparatus, a system and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present disclosure.

[0061] A computer-readable storage medium may be a tangible device that can hold and store instructions for use by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM) or flash memory, a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disc (DVD), a memory stick, a floppy disk, a mechanical encoding device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination thereof. The computer-readable storage medium used herein is not to be construed as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses through a fiber optic cable), or an electrical signal transmitted through wires.

[0062] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to be stored in the computer-readable storage medium in each computing / processing device.

[0063] The computer program instructions for performing the operations of the present disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Python, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as a separate software package, partially on a user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, by utilizing state information of computer-readable program instructions to personalize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit can execute the computer-readable program instructions to implement various aspects of the present disclosure.

[0064] Various aspects of the present disclosure are described herein with reference to flowcharts and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, and combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer-readable program instructions.

[0065] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, such that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device is generated that implements the functions / actions specified in one or more blocks in the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium, where these instructions cause the computer, programmable data processing device, and / or other device to operate in a specific manner. Thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing various aspects of the functions / actions specified in one or more blocks in the flowchart and / or block diagram.

[0066] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device, so that a series of operational steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0067] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or instruction, and the part of the module, program segment or instruction contains one or more executable instructions for realizing the prescribed logical function. In some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the prescribed function or action, or can be implemented by a combination of dedicated hardware and computer instructions.

[0068] The embodiments of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for electronic design automation, comprising: performing logic optimization on the Boolean logic representing the circuit to obtain optimized Boolean logic; Process mapping the Boolean logic to obtain a netlist representing the circuit; Performing netlist optimization on the netlist to obtain an optimized netlist; and In response to determining that the optimized netlist is better than a local optimal netlist representing the circuit, the local optimal netlist is replaced with the optimized netlist and process mapped.

2. The method according to claim 1, further comprising: In response to determining that the optimized netlist is worse than the local optimal netlist, determining whether the local optimal netlist is better than the global optimal netlist; and In response to determining that the local optimal netlist is better than the global optimal netlist, logic optimization is performed on the local optimal netlist.

3. The method according to claim 2, further comprising: In response to determining that the local optimal netlist is worse than the global optimal netlist, the global optimal netlist is determined as a synthesized netlist representing the circuit.

4. The method according to claim 1, wherein the logic optimization comprises at least one of the following: performing area-first logic optimization on the Boolean logic; and A level-first logic optimization is performed on the Boolean logic.

5. The method of claim 1 , wherein the process mapping comprises at least one of the following: performing area-first process mapping on the Boolean logic; and A hierarchical first process mapping is performed on the Boolean logic.

6. The method according to claim 1, wherein the netlist optimization comprises at least one of the following: performing area-first netlist optimization on the netlist; and A level-first netlist optimization is performed on the netlist.

7. A device comprising: processor; as well as A memory is coupled to the processor and stores instructions that, when executed by the processor, cause the apparatus to implement the method according to any one of claims 1 to 6.

8. A computer-readable storage medium storing computer-executable instructions, wherein: The computer executable instructions, when executed by at least one processor, cause the at least one processor to perform the method according to any one of claims 1-6.

9. A computer program, wherein The computer program, when executed by at least one processor, causes the at least one processor to perform the method according to any one of claims 1-6.

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