Rapid logic equivalence verification method for multi-FPGA system circuit division

Abstract

The invention discloses a multi-FPGA system circuit division-oriented rapid logic equivalence verification method, which comprises the following steps of: carrying out logic optimization on an original design to obtain a to-be-verified optimization design, and dividing the original design by utilizing a division tool to obtain a to-be-verified division design; performing logic equivalence verification on the to-be-verified optimization design and the original design to obtain a first verification result; when the first verification result is that the logic functions of the to-be-verified optimization design and the original design are consistent, black box module processing is carried out on modules which are not involved in the original design and the to-be-verified division design based on the division boundary information, and logic equivalence verification is carried out on the processed original design and the to-be-verified division design to obtain a second verification result; and when the second verification result is that the logic functions of the original design processed by the black box module and the to-be-verified division design are consistent, mapping the to-be-verified division design to a plurality of independent FPGAs. According to the invention, efficient verification of multi-FPGA system circuit division is realized.

Description

Technical Field

[0001] The present invention belongs to the technical fields of integrated circuit logic equivalence verification and FPGA prototype verification, and particularly relates to a fast logic equivalence verification method for circuit partitioning of a multi-FPGA system. Background Art

[0002] With the continuous progress of integrated circuit manufacturing technology, the integration and complexity of chips have increased exponentially, and the current chip design has entered the era of very large scale integrated circuits. This has brought unprecedented challenges to chip verification. The traditional simulation-based verification method is difficult to meet the requirements of the increasingly shortened chip development cycle due to its excessive time consumption. FPGA (Field Programmable Gate Array) has been widely used in complex system electronic devices due to its short development cycle, low design cost, and real-time online verification. To address the challenges of very large scale integrated circuit verification, FPGA-based prototype verification technology has emerged and gradually become the mainstream verification method. This technology allows verification using hardware before chip tape-out, which can significantly improve the verification speed and detect functional defects in the design in advance. In particular, multi-FPGA prototype verification systems provide new solutions for the verification of very large scale integrated circuits.

[0003] In recent years, with the rapid development of high-performance modules such as artificial intelligence, GPU, and CPU and the increasing computing requirements, the demand for high-performance ASIC chips has been growing. However, it is difficult to meet the verification requirements of such complex designs only relying on the on-chip logic resources of a single advanced FPGA. Therefore, multi-FPGA high-density prototype verification technology has become an important option for current very large scale integrated circuit verification. In multi-FPGA prototype verification, the designer needs to perform a reasonable and effective partitioning of the original design, that is, decompose the originally huge and complex overall design into multiple sub-modules of appropriate scale so that they can be mapped onto multiple FPGA devices. This design partitioning needs to be carried out without changing the original design logic, and each sub-module after partitioning must be able to work together to jointly implement the complete function of the original design. Therefore, in order to ensure that the circuit logic functions before and after partitioning are completely consistent and to ensure the accuracy and effectiveness of the verification results, effective logic partitioning operations must be carried out and supplemented by strict verification means. The quality of logic partitioning is directly related to the success or failure of multi-FPGA prototype verification.

[0004] According to different segmentation implementation stages, the design partitioning strategy can be divided into netlist-level partitioning and register transfer level (RTL) partitioning. Netlist-level partitioning requires prior synthesis of the design. However, for ultra-large-scale designs, the computational complexity of the synthesis process is extremely high, and a single synthesis may take days or even weeks, which not only severely restricts the verification efficiency but may even cause the compilation software or server to crash, making it inapplicable to large-scale circuit verification and simulation scenarios. Different from netlist-level partitioning, RTL-level partitioning can directly perform design segmentation at the RTL code level, avoiding the time-consuming synthesis process, thus significantly improving the partitioning efficiency. In addition, the synthesis implementation after RTL-level partitioning can be completed in parallel on multiple FPGA boards, further improving the simulation efficiency. Therefore, adopting RTL-level partitioning is a more ideal choice in multi-FPGA prototype verification. A typical multi-FPGA prototype verification process usually includes links such as design partitioning, mapping, placement and routing, and board-level testing. However, once problems are found in the board-level testing link, it often needs to return to the design or partitioning stage for iteration, which will undoubtedly increase the number of verification iterations and extend the verification cycle. Considering the unique advantages of formal verification tools in the verification field, effectively integrating them into the FPGA prototype verification process is expected to reduce the number of verification iterations, lower the verification cost, and improve the overall verification efficiency. Logic equivalence verification, as a technology for checking the functional logic between a reference design and an implementation design, has been widely used in integrated circuit design verification. The logic equivalence verification tools in the prior art mainly use mathematical methods to directly compare the consistency of netlists at each stage. Its basic idea is that for two netlists to be compared, if the output results are the same for all possible inputs, it proves that the combinational logic between the input and output is correct, that is, the netlists are consistent.

[0005] However, most of the existing formal verification technologies are used for single-FPGA design verification, with insufficient applicability in a multi-FPGA environment and a lack of mature and widely used solutions; although logic equivalence verification avoids repeated simulations, for large-scale designs, directly comparing the consistency of netlists still requires consuming a large amount of computing resources and time. Especially in a multi-FPGA prototype verification environment, since the design is partitioned into multiple FPGAs, its verification complexity is higher, and the existing methods are difficult to meet the requirements of rapid verification; in the prior art, the combination of the logic equivalence verification method and the FPGA prototype verification process is not tight enough to give full play to its advantages in prototype verification. Summary of the Invention

[0006] To solve the above problems existing in the prior art, the present invention provides a fast logic equivalence verification method for circuit partitioning of a multi-FPGA system. The technical problems to be solved by the present invention are realized through the following technical solutions:

[0007] An embodiment of the present invention provides a fast logic equivalence verification method for circuit partitioning of a multi-FPGA system, which is applied to the verification process of circuit partitioning of multiple independent FPGA systems. The corresponding method includes:

[0008] S10. Perform logic optimization processing on the original design to obtain an optimized design to be verified, and use a partitioning tool to perform partitioning processing on the original design to obtain a partitioned design to be verified; among them, for the optimized design to be verified and the partitioned design to be verified with a changed design hierarchy, a naming rule file is introduced to ensure the correct correspondence of the logic cones.

[0009] S20. Use a logic equivalence verification tool to perform logic equivalence verification on the optimized design to be verified and the original design to obtain a first verification result; when the first verification result is that the logic functions of the optimized design to be verified and the original design are consistent, perform black-box module processing on the modules not involved in the original design and the partitioned design to be verified based on the partitioning boundary information, and use a logic equivalence verification tool to perform logic equivalence verification on the original design and the partitioned design to be verified after black-box module processing to obtain a second verification result. When the second verification result is that the logic functions of the original design and the partitioned design to be verified after black-box module processing are consistent, map the partitioned design to be verified to multiple independent FPGAs.

[0010] In an embodiment of the present invention, the process of performing logic optimization processing on the original design in S10 includes:

[0011] Convert XMR statements into equivalent traditional Verilog logic structures; infer the inout port direction and convert it into a clear input or output port; perform cross-hierarchy constant passing on the constant ports connected to sub-modules; delete buf buffers used only for signal passing; remove floating logic.

[0012] In an embodiment of the present invention, if a tri-state gate is used in the original design, the process of performing logic optimization processing on the original design in S10 further includes:

[0013] Promote all instances related to tri-state gates to the top-level module.

[0014] In an embodiment of the present invention, the naming rules in the naming rule file introduced in S10 include: ignoring the module instance prefix and register naming suffix fields automatically added by the partitioning tool, and changing the naming method of registers.

[0015] In one embodiment of the present invention, for the Xilinx FPGA primitives of the top-level module in the to-be-verified partition design in S20, the instance command with increased functional equivalence is used to clearly inform the logic equivalence verification tool that the registers on the corresponding path are functionally equivalent.

[0016] In one embodiment of the present invention, in S20, if the first verification result shows that the logical functions of the to-be-verified optimized design and the original design are inconsistent, the logic equivalence verification tool is used to locate and analyze the reasons for the inconsistency, and the original design is re-logically optimized until the first verification result shows that the logical functions of the to-be-verified optimized design and the original design are consistent.

[0017] In one embodiment of the present invention, in S20, if a module not involved in a certain partition drives the partition boundary and the involved modules, backtracking analysis is performed along the driving signal to ensure that the partition boundary and the involved modules are not processed as black-box modules.

[0018] In one embodiment of the present invention, in S20, if the second verification result shows that the logical functions of the original design after black-box module processing and the to-be-verified partition design are inconsistent, the process ends.

[0019] In one embodiment of the present invention, an automated script is edited, and steps S10 to S20 are executed on the automated script.

[0020] Advantages of the present invention:

[0021] The fast logic equivalence verification method for circuit partitioning of multi-FPGA systems proposed by the present invention is an equivalence verification method for black-box modules based on RTL-level partitioning, aiming at the problems of low efficiency and long time consumption in logic equivalence verification in multi-FPGA prototype verification in the prior art. This method aims to solve the potential errors introduced by the logic partitioning tool and accelerate the verification process to ensure the correctness and efficiency of multi-FPGA prototype verification. Specifically: This method first verifies the correctness of the design after logical optimization, providing a technical basis for reducing the equivalence verification time by using partition boundary information subsequently. On this basis, the present invention reasonably sets black-box modules by using partition boundary information, significantly reducing the computational complexity of equivalence verification, thereby improving the verification efficiency. The logical equivalence before and after design partitioning is verified by the proposed method, ensuring that no logical errors are introduced during the partitioning process, and thus reducing the number of iterations in the prototype verification process. Finally, the present invention effectively combines the logic equivalence verification tool with the FPGA prototype verification process, greatly shortening the verification time and providing an important technical reference for optimizing the FPGA design verification process.

[0022] The following will further elaborate on the present invention in conjunction with the drawings and embodiments. Description of the Drawings

[0023] Figure 1 is a schematic flowchart of a fast logic equivalence verification method for circuit partitioning of a multi - FPGA system provided by an embodiment of the present invention;

[0024] Figure 2 is a schematic diagram of the change of the naming rule during the logic optimization process provided by an embodiment of the present invention;

[0025] Figure 3 is a schematic diagram of the automation process provided by an embodiment of the present invention;

[0026] Figure 4 is a schematic diagram of the complete framework of logic equivalence verification provided by an embodiment of the present invention;

[0027] Figure 5 is a schematic flowchart of the logic equivalence verification process in the logic optimization stage provided by an embodiment of the present invention;

[0028] Figure 6 is a schematic diagram of mapping the design before and after partitioning to multiple independent FPGAs provided by an embodiment of the present invention. Detailed Embodiments

[0029] The following further describes the present invention in detail with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0030] To ensure the correctness of the RTL partitioning process and prevent the introduction of new logic errors during partitioning, two key verification problems must be solved: First, it is necessary to verify the optimization operations performed by the partitioning tool on the design to ensure that these optimization operations do not change the original function of the design; Second, it is necessary to quickly verify the logical equivalence between the partitioned sub - design and the original design to ensure the validity of the partitioning result. Based on this requirement, please refer to Figure 1 In an embodiment of the present invention, a fast logic equivalence verification method for circuit partitioning of a multi - FPGA system is provided, which is applied to the verification process of circuit partitioning of multiple independent FPGA systems. The corresponding method specifically includes the following steps:

[0031] S10. Perform logic optimization processing on the original design to obtain an optimized design to be verified, and use a partitioning tool to perform partitioning processing on the original design to obtain a partitioned design to be verified; Among them, for the optimized design to be verified and the partitioned design to be verified with changed design levels, a naming rule file is introduced to ensure the correct correspondence of the logic cones.

[0032] In the multi-FPGA prototype verification process, the RTL description is first transformed into a circuit netlist through logic synthesis. Subsequently, operations such as netlist optimization, technology mapping, and FPGA placement and routing are performed on the netlist, and finally, FPGA configuration data (bitstream) is generated. In the above process, logic synthesis and technology mapping, as key links in front-end engineering, not only verify the correctness of Verilog HDL syntax but also provide an important basis for estimating the total number of FPGA on-chip resources required for the design. However, when performing RTL partitioning operations, existing technologies usually need to first perform logic synthesis on the entire design to obtain the netlist structure, so as to perform subsequent FPGA resource estimation. For designs targeting large FPGAs, this method will consume a lot of time and result in low partitioning efficiency. Usually, a more efficient method is adopted: first perform static refinement or preliminary refinement on the design to convert the RTL-level design into a pseudo-netlist in memory. Refinement is a lightweight conversion process that unfolds the high-level structures in the RTL code into more low-level logic primitives without performing in-depth logic optimization. Then, based on the pseudo-netlist, preliminary logic optimization, technology mapping, and resource estimation can be performed. To ensure the correctness of the processing process, equivalence checking must be performed to ensure that the converted logical structure is functionally consistent with the original design.

[0033] Therefore, the embodiment of the present invention proposes to use a partitioning tool to perform logic optimization processing on the main verification points involved, denoted as the logic optimization stage, including: converting XMR (cross-module reference) statements into equivalent traditional Verilog logical structures; inferring the inout port direction and converting it into a clear input or output port; performing cross-level constant passing on the constant ports connected to sub-modules; deleting buf buffers used only for signal passing; removing floating logic. More specifically:

[0034] (1) XMR statement processing: In large Verilog designs, the module hierarchy is complex, and the traditional way of accessing and modifying signals or registers in underlying modules through layer-by-layer instantiation paths is inefficient. Although XMR statements provide a concise cross-level assignment mechanism and improve code readability, this method is not conducive to subsequent design optimization. Therefore, the partitioning tool can automatically parse and convert XMR statements into equivalent traditional Verilog logical structures for subsequent optimization and partitioning operations. To ensure the correctness of the XMR statement processing process, equivalence checking must be performed to ensure that the converted logical structure is functionally consistent with the original design.

[0035] (2) Inout Port Direction Inference and Conversion: The inout port in Verilog design represents a bidirectional connection. However, there is no truly bidirectional port inside the FPGA. Its essence is a bidirectional connection at the external pin. To improve design efficiency, designers may use inout port declarations to indicate the data flow direction. In this case, the partitioning tool will analyze the connection relationships of sub-modules, automatically infer the specific data flow direction of the inout port, and convert it into a clear input or output port. This conversion aims to ensure that no cuts are made on the inout port during cross-FPGA partitioning, avoid bidirectional connections between multiple FPGAs, and thus guarantee the correctness of the partitioning.

[0036] (3) Buf Buffer Deletion: In RTL design, there may be unnecessary buf buffer levels. These buffers are only used for signal transmission and do not contribute substantially to the circuit function. The partitioning tool simplifies the design and reduces redundant logic by identifying and removing these levels that only contain buf buffers.

[0037] (4) Constant Logic Optimization: First, constant propagation and related logic optimizations are performed inside the module. For constant ports connected to sub-modules, the partitioning tool also performs cross-level constant propagation to ensure the transmission and utilization of constant information, thereby reducing logical complexity.

[0038] (5) Floating Logic Removal: In a multi-FPGA prototype verification environment, the design instantiation process may introduce a large number of unused module instances. These instances exhibit zero fan-out or are inactive within the target verification scope. Such instances constitute redundant parts of the design, which are floating logic. Floating logic does not contribute to the verification target of interest and reduces the effective utilization rate of FPGA resources. Therefore, the partitioning tool simplifies the design complexity and improves resource utilization efficiency by identifying and removing these redundant modules.

[0039] Furthermore, in the embodiments of the present invention, when tri-state gates are used in the original design, the logic optimization process of the original design using the partitioning tool in S10 further includes: promoting all instances related to tri-state gates to the top-level module. More specifically:

[0040] When tri-state gates are truly used in the original design, their output states and functions in the circuit are jointly determined by the modules they are connected to and the states of their enable control terminals. To avoid the partitioning complexity caused by tri-state gates, the embodiments of the present invention promote all tri-state gate instances in the original design to the top-level module. This processing strategy does not introduce changes in the overall design logic, but it will affect the module-level equivalence verification. That is, if the module-to-module comparison method is used, originally equivalent modules may become non-equivalent due to the change in the position of tri-state gates.

[0041] It should be particularly noted that for test cases where the design hierarchy changes, a naming rule file needs to be introduced. The naming rules in the introduced naming rule file include: ignoring the module instance prefix and register naming suffix fields automatically added by the partitioning tool, and changing the naming method of registers to ensure the correct correspondence of the logic cone, thereby avoiding verification failures. More specifically:

[0042] To verify the correctness of the partitioning operation, this study adopted the open-source OpenRISC design as a test case. It should be noted that the partitioning tool renamed some registers of the original design during the processing, and since the design was partitioned onto different FPGA boards, its hierarchical structure also changed accordingly, as Figure 2 shown. Therefore, to ensure the accuracy of the logic equivalence verification, corresponding naming rules must be configured during the verification process. These naming rules are to ignore fields such as the module instance prefix (such as FPGA_2_inst) and register naming suffix (such as _reg_s2c_reg) automatically added by the partitioning tool. In addition, it is also necessary to handle the change in the register naming method. For example, convert the register name in the form of reg

[31] to the form of reg_31_. The correct configuration of these naming rules is crucial for ensuring the accuracy of the mapping stage and the validity of the verification results. If such naming rule configuration is not performed, a large number of register matching failures will occur in the mapping stage, resulting in the subsequent verification (verify) stage being unable to proceed smoothly.

[0043] S20. Use a logic equivalence verification tool to perform logic equivalence verification on the to-be-verified optimized design and the original design to obtain a first verification result; when the first verification result indicates that the logic functions of the to-be-verified optimized design and the original design are consistent, perform black-box module processing on the modules not involved in the original design and the to-be-verified partitioned design based on the partitioning boundary information, and use the logic equivalence verification tool to perform logic equivalence verification on the original design and the to-be-verified partitioned design after black-box module processing to obtain a second verification result. When the second verification result indicates that the logic functions of the original design and the to-be-verified partitioned design after black-box module processing are consistent, map the to-be-verified partitioned design into multiple independent FPGAs.

[0044] In the multi-FPGA prototype verification process, after the S10 logic optimization processing and partitioning, it enters the verification stage. However, traditional equivalence verification methods usually directly verify the entire design. When faced with very large scale integrated circuit designs, this method will encounter serious computational bottlenecks. Specifically, the direct verification of large-scale designs will lead to an exponential increase in verification time and may result in the uncertainty of verification results due to insufficient computing resources, thus seriously restricting the efficiency and reliability of prototype verification. To address this problem, the embodiments of the present invention first use a logic equivalence verification tool to perform logic equivalence verification on the optimized design to be verified and the original design to obtain a first verification result. If the first verification result indicates that the logic functions of the optimized design to be verified and the original design are consistent, it means that the logic equivalence verification passes. If the first verification result indicates that the logic functions of the optimized design to be verified and the original design are inconsistent, it means that the logic equivalence verification fails. When the logic equivalence verification passes at this time, based on the partitioning boundary information, the modules not involved in the partitioning process of the original design and the partitioned design to be verified can be regarded as black box modules for processing. Then, use the logic equivalence verification tool to perform logic equivalence verification on the original design and the partitioned design to be verified after the black box module processing to obtain a second verification result. When the second verification result indicates that the logic functions of the original design and the partitioned design to be verified after the black box module processing are consistent, it means that the logic equivalence verification passes. At this time, the partitioned design to be verified can be mapped to multiple independent FPGAs to ensure the accuracy of multi-FPGA prototype verification. If the second verification result indicates that the logic functions of the original design and the partitioned design to be verified after the black box module processing are inconsistent, it means that the logic equivalence verification fails, and the process ends.

[0045] In addition, for the common Xilinx FPGA primitives in the top-level module of the partitioned design to be verified, they will appear on each FPGA board after partitioning, that is, replication processing is performed. If no constraints are imposed on these replicated primitive modules during the verification process, warning messages will be generated, and the specific content is as follows:

[0046] WARN:Revised point:FPGA_2_inst / IBUFDS_ginst / o_out_reg repeats withFPGA_1_inst / IBUFDS_ginst / o_out_reg after using the name rule.Please use othername rule.

[0047] WARN: Revised point: FPGA_3_inst / IBUFDS_ginst / o_out_reg repeats with FPGA_1_inst / IBUFDS_ginst / o_out_reg after using the name rule. Please use other name rule.

[0048] Regarding the problems caused by the above replication process, when performing logic equivalence verification, the instance command for adding functionally equivalent instances (add_instance_equivalence) is used to clearly inform the logic equivalence verification tool that the registers in the corresponding path are functionally equivalent.

[0049] It should be noted that if a module not involved in a certain partition (a module that should be set as a black box module by reason) drives a module involved in the partition boundary, treating it as a black box module will cause verification errors. For example:

[0050] ERROR: Driver not found: c_glip_out.ready!

[0051] At this time, it is necessary to trace back and analyze along the drive signal to ensure that the partition boundary and the involved modules are not set as black box modules.

[0052] In the actual verification process, not all designs can pass the equivalence verification at one time. That is, when the first verification result shows that the logical functions of the design to be verified and optimized and the original design are inconsistent, it is necessary to perform parameter Debug on the design to be verified and optimized. Locate and analyze the reasons for the inconsistency through the logic equivalence verification tool, determine the mismatch points, re-optimize the original design logically to obtain the design to be verified and optimized, and use the partitioning tool to partition the original design to obtain the partitioned design to be verified until the first verification result shows that the logical functions of the design to be verified and optimized and the original design are consistent. Through this verification method, design analysis can be carried out efficiently and intuitively from the perspective of the pure logical structure, which is convenient for quickly discovering design problems.

[0053] The core technical idea of the present invention is: making full use of the verification results obtained in the logic optimization stage. If the design after logic optimization has passed the verification, since the partitioning process only involves the physical layout of the modules and the logical function has not changed, it can be inferred that the design after partitioning is logically equivalent to the optimized design. Therefore, the optimized equivalence verification scheme proposed by the present invention only needs to perform logic equivalence verification on the partition boundary and related modules, without verifying the entire design, thus significantly reducing the computational complexity and verification time of the equivalence verification and improving the verification efficiency.

[0054] The overview of the logic equivalence verification process in the embodiments of the present invention is as follows:

[0055] The first step: Design reading. Read the golden design and the revised design. The golden design is the standard original design model. The revised design is the design after logical optimization processing and partitioning, and is the design to be verified, that is, it includes the optimized design to be verified and the partitioned design to be verified.

[0056] The second step: Map. Traverse the matching points such as inputs, outputs, registers, BlockBoxes, etc. in the golden design and the revised design through a mathematical model, and map them one by one.

[0057] The third step: Verify: Establish a logic cone model for all logical points of the map, as Figure 2 shown. Through traversing all input excitation conditions, perform mathematical operations on the logic cone, and compare the consistency of the mathematical operation results of the revised design with the golden design results.

[0058] Furthermore, in order to efficiently implement logic equivalence verification and maximize the saving of manpower, material resources, and shorten the verification time, the present invention adopts an automated processing strategy: edit an automated script and execute steps S10 - S30 on the automated script. More specifically:

[0059] The logic equivalence verification process of the present invention is driven by an automated script. The commands used in the verification process are processed into an automated script, realizing the automation of key steps such as design reading, constraint configuration, matching point matching, and result checking. This automated processing flow first inputs the original design and the implementation design that need to be verified for equivalence, then generates a verification environment according to the verification constraints and realizes the matching of the logic cone, calls the tool to output the map result, and finally uses a logic equivalence verification tool for verification, thereby ensuring the efficiency and consistency of the logic equivalence verification process. The automation of the logic equivalence verification process is a key link in the verification process. It can avoid cumbersome manual operations and significantly improve the verification efficiency and reliability. Implementing an automated verification process can not only reduce manual intervention and the probability of human errors, but also quickly and accurately complete the equivalence verification task and generate a detailed verification report, thereby significantly accelerating the verification cycle and reducing the verification cost. Therefore, automated processing is a necessary means to achieve efficient logic equivalence verification. The automated process is as Figure 3 shown, Figure 3 where the design to be verified includes the optimized design to be verified and the partitioned design to be verified.

[0060] To verify the effectiveness and correctness of the fast logic equivalence verification method for circuit partitioning in a multi-FPGA system provided by the embodiments of the present invention, the embodiments of the present invention use a batch of small-scale designs from open-source websites to verify the consistency of the design before and after logic optimization, and use the OpenRISC design as a large-scale design to verify the consistency of design partitioning. The information of 10 specifically configured test cases is shown in Table 1. The second column in Table 1 is the name of the top-level module of the design, and the third column is the number of cells included in the design.

[0061] Table 1 Information of Configured Test Cases

[0062] No. top_module cells 1 aes_cipher_top 11309 2 asram16_axi4 1686 3 bsg_chip 1605001 4 ddrc_sequencer 3852 5 ibex_core 18600 6 bigTop 6992 7 swerv_wrapper 140490 8 uart_wb 474 9 usbf_device 3797 10 wujian100_open_top 136799

[0063] The logic equivalence verification in the embodiments of the present invention includes the equivalence verification between the original design and the optimized design to be verified, and the equivalence verification between the original design and the partitioned design to be verified as Figure 4 shown.

[0064] The equivalence verification between the original design and the optimized design to be verified is as follows:

[0065] As shown in Figure 5, after completing the configuration of the test cases, import them into the partitioning tool and start the compilation phase (run_compile). The main operations performed in this phase are as follows: Compile the original design, including syntax checking, multi-drive detection, etc.; perform logic optimization on the original design, such as converting XMR statements into equivalent traditional Verilog logic structures; infer the inout port direction and convert it into a clear input or output port; perform cross-hierarchy constant passing for constant ports connected to sub-modules; delete buf buffers used only for signal passing; remove floating logic. After the compilation phase is completed, the partitioning tool will output intermediate files of the optimization process, which record the logic optimization results of each step. For each test case, use a logic equivalence verification tool to perform logic equivalence verification between the original design and the optimized design to be verified. This verification aims to verify whether the optimization operations have changed the logic function of the original design and provide correctness guarantee for setting black-box modules in the subsequent partitioned design. The design of the test cases covers all optimization scenarios to ensure the comprehensiveness of the verification. The experimental results show that the above optimization operations have not changed the logic function of the design. Based on this, the method of setting black-box modules in the design partitioning process to improve the verification efficiency is feasible.

[0066] The equivalence verification between the original design and the partitioned design to be verified is as follows:

[0067] To ensure the correctness of the verification results, the present invention adopts two methods for equivalence verification before and after design partitioning. The first method is full design comparison, that is, without setting black box modules, the entire design is read into the verification tool for complete comparison of all logics. After applying correct verification constraints, the experimental results show that this method passes the verification, with a total time consumption of 1299 seconds. The second method is the black box verification method based on the partitioning boundary, that is, according to the partitioning boundary information, the modules not involved in the partitioning are set as black box modules. As Figure 6 shown, after the design is partitioned, it is mapped to four independent FPGA devices. During this process, module instances inst4 and inst6 participate in the partitioning operation. Therefore, the inst4 and inst6 modules themselves should not be set as black box modules. However, the next-level sub-modules of the inst4 and inst6 modules, namely inst4-1, inst4-2, inst6-1, inst6-2, and other modules not directly participating in the partitioning operation can be set as black box modules to simplify the verification scope. After correctly setting the black box modules, the experimental results show that this method passes the verification, with a total time consumption of 230 seconds. The experimental results prove that the method of setting black box modules based on the partitioning boundary can significantly reduce the verification time.

[0068] In summary, the fast logic equivalence verification method for circuit partitioning of a multi-FPGA system proposed in the embodiment of the present invention is an equivalence verification method based on black box modules at the RTL level partitioning, aiming at the problems of low efficiency and long time consumption in logic equivalence verification in multi-FPGA prototype verification in the prior art. This method aims to solve the potential errors introduced by the logic partitioning tool and accelerate the verification process to ensure the correctness and efficiency of multi-FPGA prototype verification. Specifically: this method first verifies the correctness of the design after logic optimization processing, providing a technical basis for subsequent reduction of equivalence verification time using partitioning boundary information. On this basis, the present invention reasonably sets black box modules by using the partitioning boundary information, significantly reducing the computational complexity of equivalence verification, thereby improving the verification efficiency. The logical equivalence before and after the design partitioning is verified by the proposed method, ensuring that no logical errors are introduced during the partitioning process, and thus reducing the number of iterations of the prototype verification process. Finally, the present invention effectively combines the logical equivalence verification tool with the FPGA prototype verification process, greatly shortening the verification time and providing an important technical reference for optimizing the FPGA design verification process.

[0069] In the description of the present invention, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality of" means two or more unless otherwise specifically defined.

[0070] Although the present invention has been described in conjunction with various embodiments, however, in the process of implementing the claimed invention, those skilled in the art can understand and achieve other variations of the disclosed embodiments by referring to the specification and its accompanying drawings. In the specification, the term "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of cases. Certain measures are described in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0071] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A fast logic equivalence verification method for multi-FPGA system circuit partitioning, characterized in that: Applied to the circuit partitioning verification process of multiple independent FPGA systems, the corresponding methods include: S10, performing logic optimization processing on the original design to obtain an optimized design to be verified, and using a partitioning tool to partition the original design to obtain a partitioned design to be verified; wherein, for the optimized design to be verified and the partitioned design to be verified whose design levels have changed, a naming rule file is introduced to ensure correct correspondence of logic cones; S20. Performing logic equivalence verification on the optimized design to be verified and the original design by using a logic equivalence verification tool to obtain a first verification result; when the first verification result shows that the logic functions of the optimized design to be verified and the original design are consistent, performing black box module processing on the modules not involved in the partition design to be verified based on the partition boundary information, and performing logic equivalence verification on the original design and the partition design to be verified after the black box module processing by using a logic equivalence verification tool to obtain a second verification result; when the second verification result shows that the logic functions of the original design and the partition design to be verified after the black box module processing are consistent, mapping the partition design to be verified to multiple independent FPGAs.

2. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 1 is characterized in that: The process of performing logic optimization on the original design in S10 includes: Convert XMR statements to equivalent traditional Verilog logic structures; infer the direction of inout ports and convert them to explicit input or output ports; pass constants across levels for constant ports connected to submodules; delete the buf buffer used only for signal transmission; and remove dangling logic.

3. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 2 is characterized in that: If the original design uses a tri-state gate, the process of performing logic optimization processing on the original design in S10 further includes: Promote all three-state gate related instances to the top-level module.

4. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 1 is characterized in that: The naming rules in the naming rule file introduced in S10 include: ignoring the module instance prefix and register naming suffix fields automatically added by the partitioning tool, and changing the register naming method.

5. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 1, characterized in that: In S20, for the Xilinx FPGA primitives of the top-level module in the partitioned design to be verified, the add functional equivalent instance command is used to explicitly inform the logic equivalence verification tool that the registers of the corresponding paths are functionally equivalent.

6. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 1, characterized in that: In S20, if the first verification result shows that the logical functions of the optimized design to be verified are inconsistent with those of the original design, the cause of the inconsistency is located and analyzed through a logical equivalence verification tool, and the original design is logically optimized again until the first verification result shows that the logical functions of the optimized design to be verified are consistent with those of the original design.

7. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 1, characterized in that: If a module not involved in a certain partition in S20 drives the partition boundary and the modules involved, a backtracking analysis is performed along the driving signal to ensure that the partition boundary and the modules involved are not processed as black box modules.

8. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 1, characterized in that: If the second verification result in S20 is that the logical functions of the original design after the black box module processing and the partition design to be verified are inconsistent, the process ends.

9. The fast logic equivalence verification method for multi-FPGA system circuit partitioning according to claim 1, characterized in that: The automation script is edited, and steps S10 to S20 are executed on the automation script.

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