Audio amplification method and device

Abstract

The invention relates to an audio amplification method and device. Signal processing is applied to a digital input audio signal. An analog audio output signal based on the digital input audio signal is provided by a switching converter circuit driven by the PWM signal. An analog audio output signal is detected to generate an analog feedback signal. Applying signal processing includes: generating a digital error signal indicative of a difference between a digital input audio signal and a digital word signal; applying a digital-to-analog conversion to the digital error signal to produce an analog copy of the digital error signal; generating an analog difference signal indicative of a difference between an analog copy of the digital error signal and the analog feedback signal; applying analog-to-digital conversion to the analog difference signal to produce a digital word signal; digital filtering is applied to the digital word signal to produce a filtered digital word signal that generates the PWM signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102023000012858, filed on June 21, 2023, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present specification relates to methods and devices for audio signal amplification (audio amplification for short).

[0004] One or more embodiments may be applied to power audio amplification devices for car entertainment systems, for example. Background Art

[0005] Due to the reduced cost of digital signal processing, digital audio signals have become common even in the field of power amplifiers, whose outputs inherently have analog characteristics in order to drive audio speakers.

[0006] Such power amplifier technology may therefore include a mix of digital and analog components, where noise and distortion performance play an important role for demanding applications.

[0007] The development of power amplifier structures suitable for processing digital input signals is also aimed at further improving performance at a lower cost.

[0008] There is a need in the art for solutions that help provide such improvements. Summary of the invention

[0009] One or more embodiments may be directed to a method.

[0010] One or more embodiments may relate to a corresponding audio amplification device.

[0011] One or more embodiments facilitate reducing the chip size of a power amplifier with digital inputs.

[0012] One or more embodiments increase the role of the digital portion of a circuit relative to the analog blocks.

[0013] One or more embodiments reduce the complexity of the circuit structure of existing solutions.

[0014] One or more embodiments facilitate reducing the area footprint and complexity of circuit blocks.

[0015] In one embodiment, a method includes: receiving a digital input audio signal; applying signal processing to the received digital input audio signal; providing an analog audio output signal based on the digital input audio signal via a switching converter circuit driven by a pulse width modulation (PWM) signal; and sensing the analog audio output signal and providing an analog feedback signal indicative of the sensed analog audio output signal.

[0016] Applying signal processing to the digital input audio signal includes: generating a digital error signal indicating the difference between the digital input audio signal and the digital word signal; applying a digital-to-analog conversion DAC to the digital error signal, thereby generating an analog copy of the digital error signal; generating an analog difference signal indicating the difference between the analog copy of the digital error signal and the analog feedback signal; applying an analog-to-digital conversion ADC to the analog difference signal, thereby generating a digital word signal as a result; digitally filtering the digital word signal to generate a filtered digital word signal; and driving the switching converter circuit with a PWM signal generated based on the filtered digital word signal.

[0017] In one embodiment, an audio amplification device includes: a digital input node configured to receive a digital input audio signal; a signal processing chain coupled to the digital input node to receive the digital input audio signal, the signal processing chain configured to provide an analog audio output signal based on the digital input audio signal via a switching converter circuit driven by a pulse width modulation (PWM) signal; and a sensing circuit branch coupled to the output node to sense the analog audio output signal and configured to provide an analog feedback signal indicative of the sensed analog audio output signal.

[0018] A signal processing chain, comprising: a first superposition node, coupled to an analog-to-digital conversion (ADC) circuit to receive a digital word signal and coupled to an input node to receive a digital input audio signal, the first superposition node being configured to generate a digital error signal indicating a difference between the digital input audio signal and the digital word signal; a digital-to-analog converter (DAC) circuit, coupled to the first superposition node to receive the digital error signal, the DAC circuit being configured to apply digital-to-analog conversion to the digital error signal, thereby generating an analog copy of the digital error signal; a second superposition node, coupled to a sensing circuit branch to receive an analog feedback signal and coupled to the DAC circuit to receive an analog copy of the digital error signal, the second superposition node being configured to generate an analog difference signal indicating a difference between an analog replica of the digital error signal and the analog feedback signal; an analog-to-digital converter (ADC) circuit coupled to the second superposition node to receive the analog difference signal and configured to apply analog-to-digital conversion to the analog difference signal to generate a digital word signal as a result; a digital filter circuit coupled to the ADC circuit to receive the digital word signal and configured to apply digital filtering to the digital word signal to generate a filtered digital word signal; and a pulse width modulation (PWM) generator circuit coupled to the digital filter circuit to receive the filtered digital error signal, the PWM generator circuit being configured to drive the switching converter circuit with a PWM signal generated based on the filtered digital word signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

[0020] Figure 1 is an example diagram of an audio amplification device;

[0021] Figure 2 is an example diagram of an audio amplification device;

[0022] Figure 3 is an example diagram of a digital-to-analog converter (DAC) circuit;

[0023] Figure 4 is an example graph of a signal changing over time;

[0024] Figure 5 is an example diagram of an alternative audio amplification device. DETAILED DESCRIPTION

[0025] Corresponding reference numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0026] The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0027] The edges of a feature drawn in a drawing do not necessarily indicate the end of the extent of the feature.

[0028] In the following description, one or more specific details are shown for the purpose of providing a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more specific details or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0029] References to "an embodiment" or "one embodiment" in the framework of this specification are intended to indicate that a particular configuration, structure, or characteristic described with respect to the embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in an embodiment" that may appear in one or more points of this specification do not necessarily refer to the same embodiment.

[0030] Furthermore, in one or more embodiments, the particular conformations, structures or characteristics may be combined in any suitable manner.

[0031] The drawings are in simplified form and not to exact scale.

[0032] In the drawings attached hereto, unless the context indicates otherwise, the same parts or elements are denoted by the same reference numerals / numbers, and the corresponding description will not be repeated for each figure for the sake of brevity.

[0033] The reference signs used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0034] Figure 1 An audio amplification device such as that discussed in US Patent Application Publication No. 20240088844 (corresponding to Italian Patent Application No. 102022000018453), the disclosure of which is incorporated herein by reference.

[0035] like Figure 1 As shown, the audio amplification device (or audio amplifier) ​​10 for performing audio amplification includes: an input node D configured to receive a digital input signal D; an output node V OUT , is configured to provide an output signal V OUT To drive the audio speaker, based on the output signal V OUT A digital-to-analog converter (DAC) circuit 12 is coupled to the input node D to receive the digital signal D, the DAC circuit 12 is configured to apply digital-to-analog conversion to the digital signal D, thereby providing an analog signal I IN (For example, the current signal I IN ); summing node 14, coupled to DAC circuit 12 and output node V OUT(For example, via a feedback resistor element R FB To provide feedback signal I FB The feedback branch 19), the summing node 14 is configured to generate an analog signal I IN and feedback signal I FB The difference between the error signal I E (e.g., as a current signal); a power (Pwr) circuit device 17, including at least one switching transistor, the at least one switching transistor being configured to be driven in a manner known per se based on at least one drive signal DRV to provide a switching voltage signal at a switching node SW; an inductor-capacitor (LC) network 18, for example, including an inductor L in series with a capacitor C referenced to ground, coupled to the switching node SW of the power circuit device 17 and configured to provide a switching voltage signal at an output node V OUT Provides an output (eg, voltage) signal V OUT ; The signal processing chain 16 is coupled to the summing node 14 to receive the error (eg, current) signal I E and coupled to the power circuit device 17 to provide an output (eg, voltage) signal V OUT The signal processing chain 16 is configured to provide at least one drive signal DRV to the power stage 17, the at least one drive signal being based on the error signal I E .

[0036] like Figure 1 As shown, the amplifier 10 is configured to be coupled to at least one audio speaker AS to provide an output signal V thereto. OUT , the audio amplifier 10 is configured to drive at least one audio speaker AS to reproduce an audio signal D received at an input node.

[0037] For example, applying signal processing to the digital input audio signal includes applying a digital-to-analog conversion (DAC) 12 to the digital input audio signal, resulting in a digital input signal I IN generating an analog error signal I indicating the difference between the analog copy of the digital input signal and the analog feedback signal 14 E ; Analog-to-digital conversion ADC 160 is performed on the analog error signal, and as a result, a digital error signal W is generated; digital filtering (Dflt) 162 is applied to the digital error signal to generate a filtered digital error signal D C ; and driving a switching converter circuit with a PWM signal generated based on the filtered digital error signal.

[0038] As illustrated herein, the audio amplifier comprises: a digital input node configured to receive a digital (audio) input signal D; a signal processing chain 12, 14, 56, 17 coupled to the digital input node to receive the digital input audio signal, the signal processing chain being configured to provide an analog output audio signal V based on the digital input audio signal via a switching converter circuit device 17 driven by a pulse width modulated PWM signal DRV. OUT ; Sensing circuit branch 19, R FB coupled to the output node to sense the analog audio output signal and configured to provide an analog feedback signal indicative of the sensed analog audio output signal.

[0039] For example, the signal processing chain comprises a digital-to-analog converter (DAC) circuit 12 configured to apply digital-to-analog conversion to the digital input audio signal, generating as a result a digital input signal I IN A superposition node 14, coupled to the sensing circuit branch to receive the analog feedback signal and coupled to the DAC circuit to receive the analog copy of the digital input signal, the superposition node is configured to generate an analog error signal I indicating the difference between the analog copy of the digital input signal and the analog feedback signal E ; Analog-to-digital converter (ADC) circuit 160, coupled to the superposition node to receive an analog error signal I therefrom E , and is configured to apply analog-to-digital conversion to the analog error signal, and as a result, generate a digital error signal W; a digital filter circuit 162, coupled to the ADC circuit to receive the digital error signal and configured to apply digital filtering to the digital error signal, and as a result, generate a filtered digital error signal D C and a pulse width modulation (PWM) generator circuit 166 coupled to the digital filter circuit to receive the filtered digital error signal, the PWM generator circuit being configured to drive the switching converter circuit with a PWM signal generated based on the filtered digital error signal.

[0040] In the exemplary scenario considered, a method according to the present disclosure comprises: receiving a digital input audio signal D; applying signal processing 21, 22, 24, 26 to the received digital input audio signal D; providing an analog audio output signal V based on the digital input audio signal by means of a switching converter circuit device 17 driven by a pulse width modulation (PWM) signal DRV; OUT ; and sensing 19R FB Analog audio output signal V OUT and provides an analog feedback signal I indicative of the sensed analog audio output signal FB .

[0041] like Figure 1As shown, the signal processing chain 16 includes: a (e.g., transimpedance) ADC circuit 160, including an analog-to-digital converter configured to receive the current signal and convert it into a digital word signal W (or a digital error signal W), the ADC circuit 160 is coupled to the summing node 14 to receive the error current signal I E , providing a digital word signal W as a result of applying analog-to-digital conversion thereto; a digital (e.g., loop) filter circuit 162, known per se, coupled to the ADC circuit 160 to receive the digital word signal W therefrom, the digital filter circuit 162 being configured to provide a digital control signal D based on the received digital word signal W C A digital PWM stage 166 coupled to the digital filter circuit 162 is configured to provide at least one control signal DRV to the power stage 17 based on the received digital control signal 16.

[0042] like Figure 2 As shown, the amplifier device 20 according to the present invention comprises: a first superposition node 21 for digital signals, coupled to the digital input node D to receive the digital input signal D therefrom, and coupled to the enhanced signal processing circuit block 26 via the digital feedback branch to receive the ADC conversion signal W therefrom, the first superposition node 21 being configured to subtract the ADC conversion signal DRV from the input signal D, and as a result generate a digital error signal D ERR ; A digital-to-analog converter (DAC) circuit 22, coupled to the digital superposition node 21 to receive a digital error signal D therefrom ERR DAC circuit 22 is configured to convert the digital error signal D ERR Applying a digital-to-analog conversion process, as a result, generates a DAC conversion signal I ERR , such as the analog current signal I ERR A second superposition node 24 for an analog signal, the second superposition node 24 is coupled to the DAC circuit 22 to receive a DAC conversion signal I therefrom ERR , and is coupled to the output node V of the audio amplifier circuit 20 via the feedback branch 19. OUT For analog signal to receive feedback signal I FB , such as the analog feedback current signal I FB , the analog superposition node 24 is configured to generate a DAC conversion signal I ERR The analog feedback current signal I FB The difference between the difference signal I DIFF (eg, transimpedance) analog-to-digital converter (ADC) circuit 26, coupled to the second superposition node 24 to receive the difference signal I therefrom DIFF , the ADC circuit 26 is configured to convert the difference signal I DIFF An analog-to-digital conversion process is applied, resulting in a digital word signal W being provided to the user circuit.

[0043] Figure 2 The arrangement illustrated in FIG. Figure 1 The arrangement illustrated in utilises the DAC 22 to reduce the complexity of the ADC arrangement 26 without compromising accuracy.

[0044] For example, applying signal processing to the digital input audio signal comprises: generating 21 a digital error signal D indicating a difference between the digital input audio signal and the digital word signal W ERR ; For the digital error signal D ERR A digital-to-analog converter (DAC) 22 is applied, and as a result a digital error signal I is generated. ERR Generates an analog copy of the digital error signal 24 indicating the analog copy and the analog feedback signal I FB The difference between the analog difference signal I DIFF ; Applying analog-to-digital conversion (ADC) 26 to the analog difference signal, as a result, a digital word signal is generated; applying digital filtering 162 to the digital word signal W; 562, as a result, a filtered result digital word signal D is generated C ; and driving a switching converter circuit with a PWM signal generated based on the filtered digital word signal.

[0045] Still in the example considered, for example: the analog output signal includes an output voltage signal; the analog feedback signal representing the sensed analog voltage signal includes a sensed analog voltage signal and a feedback resistance element R FB The feedback current signal I is obtained by the ratio of FB ; Applying digital-to-analog conversion (DAC) 22 to the digital error signal includes converting the digital error signal D ERR Converted into analog error current signal I ERR The analog difference signal representing the difference between the analog error current signal and the feedback current signal includes a difference current signal (I DIFF ); and the method includes applying a transimpedance analog-to-digital conversion (ADC) 26 to the differential current signal, generating a digital word signal as a result.

[0046] For example, applying transimpedance ADC conversion 26 to the difference current signal includes applying sigma-delta processing including: integrating 261 the difference current signal to generate an integrated version thereof; applying flash ADC conversion 264 to the integrated version of the difference current signal to generate a digital word W comprising a plurality of bits as a result.

[0047] like Figure 2 As shown, the (eg, transimpedance) ADC circuit 26 includes an input node E configured to receive a difference (eg, current) signal I from the second superposition node 24. E ; Integrator stage 261, C F , including being configured to receive the difference signal I at a (eg, inverting) input nodeDIFF (eg, operational) amplifier 261 and having a capacitive element C interposed between an input node and an output node O of the amplifier 261. F , integrator stage 261, C F is configured to provide an integrated (eg, voltage) signal indicative of a difference (eg, current) signal I DIFF Integration over time; Flash ADC circuit 264 is coupled to integrator stage 261, C F Flash ADC 264 receives an integrated difference signal (eg, a voltage signal) therefrom, and generates an analog input voltage based on comparing the analog input voltage to a set of reference voltages (eg, a reference voltage). Figure 2 The temperature measurement array not visible in the figure is provided in a manner known per se) to compare the analog input voltage to convert it into an n-bit size (2 n -1) of the digital signal principle, as a result, a digital word signal W is generated.

[0048] like Figure 2 As shown, the transimpedance ADC circuit 26 is configured to generate a digital word signal W that is as close as possible to the differential current I DIFF A copy of the current intensity value.

[0049] In one or more alternative embodiments, the other feedback branch 29 may be configured to provide the digital word signal W as the feedback digital signal directly from “inside” the flash ADC 264 to the first superposition node 21 .

[0050] In such an alternative, the digital word signal W is in thermometric form, whereas in the case where the digital word signal is the output of the ADC 26, it is in binary form (eg, a PWM modulated signal).

[0051] For simplicity, Figure 2 The integrator stage 261 illustrated in φ comprises a single pole. It should be noted that this arrangement is purely exemplary and by no means limiting, since the integrator stage 261 may also comprise a higher number of poles.

[0052] As illustrated herein, the gain C of the integrator 261 in the transimpedance ADC 26 can be F is set to a maximum value within the stability constraints in order to reduce the amplitude of the integrated signal, thereby improving the performance of the flash ADC converter 264. For example, the integrator 261 may include a variable gain amplifier, e.g., with a number of poles higher than 1 and a gain that can be increased over the frequency range of interest.

[0053] like Figure 2 As shown, for example, due to the clock signal generator circuit block ( Figure 2The DAC circuit 22 and the flash ADC 264 of the (e.g., transimpedance) ADC circuit 26 are provided with a clock signal CK having the same frequency (possibly with the same or different phases) in a manner known per se, so that the DAC circuit 22 and the flash ADC 264 are synchronized in time.

[0054] Still in order to be able to control the performance of the transimpedance ADC 260 , for example, the frequency of the clock signal CK of the sigma-delta modulator 26 and / or the number of bits of the digital signals DRV, DTR generated by the flash ADC 264 may be changed.

[0055] exist Figure 2 In the case shown, the accuracy of the sigma-delta modulator 26 is also based on the DAC converter 22 .

[0056] like Figure 3 As shown, the DAC circuit 22 includes a thermometric generator 220, optionally including a means to "disturb" the internal cells so as to reduce the effects of any mismatches therebetween.

[0057] like Figure 3 As shown, the temperature measurement generator 220 in the DAC circuit 22 includes: a plurality of current generators I 1P ,…,I NP ,I 1N ,…,I NN , is configured along the positive supply line V DD With the negative power line V SS The multiple current lines between provide corresponding currents (for example, the total current I ERR the same part of the

[0058] Multiple switches B 1P ,…,B NP ,B 1N ,…,B NN Includes multiple current generators I 1P ,…,I NP ,I 1N ,…,I NN The corresponding current generators in the switch are matched, wherein a plurality of switches B 1P ,…,B NP ,B 1N ,…,B NN The switches in are each configured to receive bits of the digital word signals DRV, DTR provided by the flash ADC 264, and to turn on the bits in response to the corresponding bits received having a first logic value (e.g., "1" or "true"), and to turn off the bits in response to the corresponding bits received having a second logic value (e.g., "0" or "false").

[0059] Arrangements as discussed in US Pat. No. 7,239,258 B2 (incorporated by reference) may be suitable for use in one or more embodiments.

[0060] For example, to obtain an audio amplifier with an input dynamic range of approximately 120 dB, ADC circuit 260 may be designed to provide the same dynamic range.

[0061] For example, a dynamic range of approximately 100 dB is sufficient for the ADC 260 .

[0062] As will be appreciated by those skilled in the art, the digital word signal W may correspond to a positive or negative value. ERR The value of can be smaller or larger than the value of the digital input signal D.

[0063] In order to generate the maximum output power, the audio amplifier is designed so that the current intensity I IN To achieve the output voltage V OUT .

[0064] As a result, the feedback current I FB is also limited because it is the output voltage V OUT function.

[0065] Therefore, the error current I generated by the DAC circuit 22 ERR The intensity of is also limited to current intensity values ​​below the current intensity value encoded in the digital input signal D.

[0066] In the example considered herein, for example, applying DAC conversion 22 comprises: providing a current generator I 1P ,…,I NP ,I 1N ,…,I NN array, current generator I 1P ,…,I NP ,I 1N ,…,I NN Arranged in a matrix and connected via a corresponding switch set B 1P ,…,B NP ,B 1N ,…,B NN Coupled in between, switch set B 1P ,…,B NP ,B 1N ,…,B NN Configured to be turned on or off based on a bit among multiple bits of the digital word signal W.

[0067] For example, the current generator array I 1P ,…,I NP ,I1N ,…,I NN The current generator in generates and passes through the switch set B 1P ,…,B NP ,B 1N ,…,B NN The currents coupled between the switch subsets turned on based on the digital word signal W are superimposed to generate an analog error signal I ERR , the simulated error signal I ERR The current intensity value of tends to the current intensity value of the current I represented by the input digital input audio signal D.

[0068] Figure 4 is the error signal I converted by the input signal I ERR Example of the relationship between the current intensity values ​​of and over time.

[0069] like Figure 4 As shown, even when the input current intensity I encoded in the input digital signal D rises to the threshold voltage V OUT (max) or above output voltage V OUT When the value is above, the DAC converts the error signal I ERR The current intensity is also clamped to a lower level.

[0070] This may affect the number of current generators N, P present in the thermometric generator 220 in the DAC circuit 22, which may be kept lower than or equal to 2×m.

[0071] like Figure 5 As illustrated, in an alternative, the audio amplification device 50 includes: a digital feed-forward (DFF) circuit block 55 configured to receive a digital input signal D and apply phase and amplitude correction thereto to generate a compensated digital signal D' as a result; and an adder circuit block 563 inserted between the digital filter circuit 562 and the digital PWM stage 566, the adder circuit block 563 being coupled to the digital feed-forward circuit block 55 and configured to receive the compensated digital signal D' from the digital feed-forward circuit block 55 to superimpose it on the digital signal provided by the digital filter circuit 562.

[0072] like Figure 5 As illustrated, in the case where the range of values ​​of the gain of the digital filter circuit 562 (e.g., in the audio frequency range above 10 kHz) cannot reach a suitable maximum value due to stability constraints, the digital signal W output by the ADC 26 may have a spurious signal component (e.g., a sinusoidal) at the frequency of the signal superimposed thereon. Figure 5 The digital feed-forward (DFF) circuit block 55 of the device 50 illustrated in FIG. 5 can compensate for such parasitic components.

[0073] As exemplified herein, the corresponding method includes: applying phase and amplitude correction 55 to the digital input signal, generating a compensated digital signal D' as a result; adding 563 the compensated digital signal to a filtered digital error signal; and generating a pulse width modulation (PWM) signal based on the sum of the filtered digital error signal and the compensated digital signal.

[0074] like Figures 2 to 5 As shown, the audio amplification device 20; 50 includes: a digital input node, configured to receive a digital input audio signal D; a signal processing chain 21, 22, 24, 26, coupled to the digital input node to receive the digital input audio signal, and the signal processing chain is configured to provide an analog audio output signal V based on the digital input audio signal via a switching converter circuit device 17 driven by a pulse width modulation (PWM) signal DRV. OUT ; Sensing circuit branch 19, R FB Coupled to the output node to sense the analog audio output signal V OUT , and is configured to provide an analog feedback signal I indicative of the sensed analog audio output signal FB .

[0075] For example, the signal processing chain includes: a first superposition node 21 coupled to an analog-to-digital conversion (ADC) circuit 26 to receive a digital word signal W and coupled to an input node to receive a digital input audio signal D, the first superposition node 21 being configured to generate a digital error signal D indicating a difference between the digital input audio signal and the digital word signal ERR ; a digital-to-analog converter (DAC) circuit 22 coupled to the first superposition node to receive the digital error signal, the DAC circuit being configured to apply digital-to-analog conversion to the digital error signal and produce an analog copy of the digital error signal as a result; a second superposition node 24 coupled to the sensing circuit branch 19, R F an analog-to-digital converter (ADC) circuit 26 coupled to the second superposition node to receive the analog feedback signal and coupled to the DAC circuit to receive an analog copy of the digital error signal, the second superposition node being configured to generate an analog difference signal indicating a difference between the analog copy of the digital error signal and the analog feedback signal; an analog-to-digital converter (ADC) circuit 26 coupled to the second superposition node to receive the analog difference signal and configured to apply analog-to-digital conversion 26 to the analog difference signal, generating a digital word signal as a result; a digital filter circuit 162; 562 coupled to the ADC circuit to receive the digital word signal and configured to apply digital filtering to the digital word signal, generating a filtered digital word signal D as a result C ; and a pulse width modulation (PWM) generator circuit 166; 566, coupled to the digital filter circuit to receive the filtered digital error signal, the PWM generator circuit being configured to drive the switching converter circuit with a PWM signal generated based on the filtered digital word signal.

[0076] For example, the analog output signal at the output node includes an output voltage signal; the analog feedback signal representing the sensed analog voltage signal includes a sensed analog voltage signal and a feedback resistance element R FB the DAC circuit is configured to apply digital-to-analog conversion to the digital error signal to convert the digital error signal into an error current signal; the analog difference signal indicating the difference between the error current signal and the feedback signal includes the difference current signal; the ADC circuit is configured to perform transimpedance analog-to-digital conversion on the difference current signal to generate a digital word signal as a result.

[0077] like Figures 2 to 5 As illustrated, the ADC circuit configured to apply transimpedance analog-to-digital conversion to the difference signal includes a Σ-Δ processing circuit, which includes: a subtraction node E, coupled to a second superposition node to receive an analog difference signal, the subtraction node being configured to subtract a second difference signal from the difference signal; an integrator circuit 261, coupled to the subtraction node, the integrator circuit being configured to integrate the difference signal to thereby generate an integrated version of the difference signal; a flash ADC converter 264, coupled to the integrator circuit to receive an integrated version of the difference signal, the flash ADC converter being configured to apply a flash ADC conversion to the integrated version of the difference signal, and as a result, generating a digital word W comprising a plurality of bits.

[0078] like Figures 2 to 5 As illustrated in the example, the DAC circuit includes: a current generator array I 1P ,…,I NP ,I 1N ,…,I NN , arranged in a matrix and connected via a corresponding switch set B 1P ,…,B NP ,B 1N ,…,B NN Coupled in between, switch B 1P ,…,B NP ,B 1N ,…,B NN is configured to be conductive or non-conductive based on a bit in a plurality of bits of a digital word signal; wherein the current generator array I 1P ,…,I NP ,I 1N ,…,I NN The superposition of currents generated by the current generator in and coupled between the subset of switches in the switch set that are turned on based on the digital word signal generates an analog error signal, and the current intensity value of the analog error signal tends to the current intensity value of the current I indicated by the input digital input audio signal.

[0079] like Figure 5As shown, the audio amplification device 20; 50 includes: a feedforward circuit 55, coupled to an input node to receive a digital input audio signal, the feedforward circuit being configured to apply phase and amplitude correction to the digital input signal, and generating a compensated digital signal as a result; an adder circuit 563, coupled to a digital filter circuit to receive a filtered digital word signal, the adder circuit being configured to add the compensated digital signal to the filtered digital word signal, thereby providing the resulting sum signal to a PWM generator circuit.

[0080] For example, the PWM generator circuit 566 is configured to drive the switching converter circuit with a PWM signal generated based on the sum of the filtered digital word signal and the compensated digital signal.

[0081] like Figures 1 to 5 As shown, the audio amplifier device 20; 50 is coupled to at least one audio speaker 18 to provide an output signal V OUT , the audio amplifier is configured to drive at least one audio speaker to reproduce an audio signal received at the input node.

[0082] It should also be understood that the various individual implementation options illustrated in the drawings throughout this specification are not necessarily employed in the same combination illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations illustrated in the drawings.

[0083] The claims are an integral part of the technical teaching provided herein with reference to the embodiments.

[0084] The details and embodiments may vary even significantly with respect to what is described merely by way of example, without prejudice to the essential principles and without departing from the scope of protection, which is defined by the appended claims.

Claims

1. A method comprising: receiving a digital input audio signal; applying signal processing to the digital input audio signal; providing an analog audio output signal based on the digital input audio signal via a switching converter circuit driven by a pulse width modulated (PWM) signal; as well as sensing the analog audio output signal and providing an analog feedback signal indicative of the sensed analog audio output signal; Wherein applying signal processing to the digital input audio signal comprises: generating a digital error signal indicative of a difference between the digital input audio signal and a digital word signal; applying a digital-to-analog conversion (DAC) to the digital error signal to generate an analog copy of the digital error signal; generating an analog difference signal indicative of a difference between the analog replica of the digital error signal and the analog feedback signal; Performing analog-to-digital conversion (ADC) on the analog difference signal to generate the digital word signal; applying digital filtering to the digital word signal to produce a filtered digital word signal; and The switching converter circuit is driven with the PWM signal generated based on the filtered digital word signal.

2. The method according to claim 1, wherein: The analog output signal includes an output voltage signal; The analog feedback signal indicative of the sensed analog voltage signal comprises a feedback current signal obtained as a ratio of the sensed analog voltage signal and a feedback resistance element; Applying a digital-to-analog conversion (DAC) to the digital error signal includes converting the digital error signal into an analog error current signal; The analog difference signal representing the difference between the analog error current signal and the feedback current signal comprises a difference current signal; and The method further includes applying a transimpedance analog-to-digital conversion (ADC) to the difference current signal to generate the digital word signal.

3. The method of claim 2, wherein applying a transimpedance conversion (ADC) to the difference current signal comprises applying a sigma-delta processing to the difference current signal, comprising: integrating the difference current signal to generate an integrated version of the difference current signal; as well as A flash ADC conversion is applied to the integrated version of the difference current signal to produce a digital word comprising a plurality of bits.

4. The method of claim 3, wherein applying digital-to-analog conversion (DAC) comprises: providing an array of current generators arranged in a matrix and coupled therebetween via corresponding sets of switches configured to conduct or not conduct based on a bit of the plurality of bits of the digital word; Wherein a superposition of currents generated by current generators in the array of current generators and coupled therebetween via a subset of switches in the set of switches produces the analog error signal, the current intensity value of the analog error signal tending towards a current intensity value representative of the current of the input digital input audio signal.

5. The method according to claim 1, comprising: applying phase and amplitude correction to the digital input audio signal to produce a compensated digital signal; adding the compensated digital signal to the filtered digital signal; as well as A pulse width modulation (PWM) signal is generated based on the sum between the filtered digital word signal and the compensated digital signal.

6. The method of claim 1, further comprising providing the output signal to at least one audio speaker and driving the at least one audio speaker.

7. The method of claim 1, applying analog-to-digital conversion (ADC) to the analog difference signal to generate the digital word signal comprises applying transimpedance conversion (ADC) by applying sigma-delta processing to the analog difference signal by: integrating to generate an integrated signal; and A flash ADC conversion is applied to the integrated signal to produce a digital word comprising a plurality of bits.

8. The method according to claim 7, wherein applying a digital-to-analog converter (DAC) comprises: providing an array of current generators arranged in a matrix and coupled therebetween via corresponding sets of switches configured to render the plurality of sets of switches conductive or non-conductive based on a bit of the plurality of bits of the digital word; as well as The analog error signal is generated using a superposition of currents generated by current generators in the array of current generators.

9. An audio amplification device, comprising: a digital input node configured to receive a digital input audio signal; a signal processing chain coupled to the digital input node to receive the digital input audio signal, the signal processing chain being configured to provide an analog audio output signal based on the digital input audio signal via a switching converter circuit driven by a pulse width modulated (PWM) signal; a sensing circuit branch coupled to the output node to sense the analog audio output signal and configured to provide an analog feedback signal indicative of the sensed analog audio output signal; The signal processing chain comprises: a first superposition node coupled to the analog-to-digital conversion ADC circuit to receive the digital word signal and coupled to the input node to receive the digital input audio signal, the first superposition node being configured to generate a digital error signal indicative of a difference between the digital input audio signal and the digital word signal; a digital-to-analog converter (DAC) circuit coupled to the first superposition node to receive the digital error signal, the DAC circuit being configured to apply digital-to-analog conversion to the digital error signal to produce an analog copy of the digital error signal; a second superposition node coupled to the sensing circuit branch to receive the analog feedback signal and to the DAC circuit to receive the analog copy of the digital error signal, the second superposition node being configured to generate an analog difference signal indicative of a difference between the analog copy of the digital error signal and the analog feedback signal; an analog-to-digital converter ADC circuit coupled to the second superposition node to receive the analog difference signal and configured to apply an analog-to-digital conversion to the analog difference signal to generate the digital word signal; a digital filter circuit coupled to the ADC circuit to receive the digital word signal and configured to apply digital filtering to the digital word signal to produce a filtered digital word signal; and A pulse width modulation (PWM) generator circuit is coupled to the digital filter circuit to receive the filtered digital error signal, the PWM generator circuit being configured to drive the switching converter circuit with a PWM signal generated based on the filtered digital word signal.

10. The audio amplification device according to claim 9, wherein: The analog output signal at the output node comprises an output voltage signal; The analog feedback signal indicative of the sensed analog voltage signal comprises a feedback current signal obtained as a ratio of the sensed analog voltage signal and a feedback resistance element; The DAC circuit is configured to apply digital-to-analog conversion to the digital error signal to convert the digital error signal into an error current signal; the analog difference signal representing the difference between the error current signal and the feedback signal comprises a difference current signal, and The ADC circuit is configured to apply transimpedance analog-to-digital conversion to the difference current signal to generate the digital word signal.

11. The audio amplification device of claim 10, wherein the ADC circuit configured to apply transimpedance analog-to-digital conversion to the difference signal comprises a sigma-delta processing circuit arrangement, the sigma-delta processing circuit arrangement comprising: a subtraction node coupled to the second superposition node to receive the analog difference signal, the subtraction node being configured to subtract a second difference signal from the difference signal; an integrator circuit coupled to the subtraction node, the integrator circuit configured to integrate the difference signal to produce an integrated version of the difference signal; A flash ADC converter is coupled to the integrator circuit to receive the integrated version of the difference signal, the flash ADC converter being configured to apply a flash ADC conversion to the integrated version of the difference signal to produce a digital word comprising a plurality of bits.

12. The audio amplification device according to claim 11, wherein the DAC circuit comprises: an array of current generators arranged in a matrix and coupled between the array of current generators via corresponding sets of switches, the corresponding sets of switches being configured to render the corresponding sets of switches conductive or non-conductive based on a bit of the plurality of bits of the digital word; Wherein a superposition of currents generated by current generators in the array of current generators and coupled therebetween via a subset of switches in the set of switches produces the analog error signal, the current intensity value of the analog error signal tending towards a current intensity value representative of the current of the input digital input audio signal.

13. The audio amplification device according to claim 9, comprising: a feed-forward circuit coupled to the input node to receive the digital input audio signal, the feed-forward circuit configured to apply phase and amplitude correction to the digital input signal to generate a compensated digital signal; as well as an adder circuit coupled to the digital filter circuit to receive the filtered digital word signal, the adder circuit being configured to add the compensated digital signal to the filtered digital word signal to provide a resulting sum signal to the PWM generator circuit, Wherein the PWM generator circuit is configured to drive the switching converter circuit with the PWM signal generated based on a sum between the filtered digital word signal and the compensated digital signal.

14. The audio amplification device of claim 9, coupled to at least one audio speaker to provide the output signal to the at least one audio speaker, the audio amplifier being configured to drive the at least one audio speaker to reproduce the audio signal.

15. The audio amplification device according to claim 9, wherein: The ADC circuit applies transimpedance analog-to-digital conversion and includes a sigma-delta processing circuit, the sigma-delta processing circuit comprising: a subtraction node configured to subtract a second difference signal from the difference signal; an integrator circuit coupled to the subtraction node, the integrator circuit configured to integrate the difference signal to produce an integrated version of the difference signal; and A flash ADC converter is coupled to the integrator circuit to receive the integrated version of the difference signal, the flash ADC converter being configured to apply a flash ADC conversion to the integrated version of the difference signal to produce a digital word comprising a plurality of bits.

16. The audio amplification device according to claim 15, wherein the DAC circuit comprises: an array of current generators arranged in a matrix and coupled therebetween via corresponding sets of switches configured to conduct or not conduct based on a bit of the plurality of bits of the digital word; as well as A circuit is configured to superimpose currents generated by current generators in the array of current generators to produce the analog error signal.

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