An acceleration system verified by simulation

Abstract

The present application relates to the field of simulation verification technology, and in particular to an acceleration system for simulation verification. It includes a design to be tested dut, a first verification component and a second verification component; dut includes a register channel rnoc and a module to be tested engine, the input interface of rnoc is iniu, and the output interface of rnoc is tniu; each first verification component and each second verification component include a sequencer; the sequencer of each first verification component is used to issue a request during the simulation verification of dut, and the request issued by the sequencer of each first verification component during the simulation verification of dut is sent to the sequencer of the matching second verification component after being processed by the sequencer mapping, so that the sequencer of the matching second verification component sends the request to the module to be tested connected to the matching second verification component after receiving the request. The present invention can improve the efficiency of simulation verification of the design to be tested.

Description

Technical Field

[0001] The present invention relates to the technical field of simulation verification, and in particular to an acceleration system for simulation verification. Background Art

[0002] The simulation verification system in the prior art includes a design to be tested and a verification component. The design to be tested includes a register channel and several modules to be tested. The register channel includes several input interfaces and several output interfaces. Each output interface of the register channel is connected to a module to be tested. When the design to be tested is subjected to UVM (Universal Verification Methodology) simulation verification, each input interface of the register channel is connected to a verification component. The request issued by each verification component enters the register channel through the input interface connected thereto, and then comes out from a certain output interface after being routed inside the register channel, and finally is sent to the test module connected to the output interface. The register channel is a hardware circuit structure, which includes units such as a delay unit, resulting in a long time for the request issued by the verification component from entering the register channel to coming out of the register channel, resulting in a long time for the simulation verification of the test component. How to reduce the time for simulation verification of the design to be tested, and thus improve the efficiency of simulation verification of the design to be tested, is a problem to be solved urgently. Summary of the invention

[0003] The present invention aims to provide an acceleration system for simulation verification, so as to reduce the time for simulation verification of a design to be tested, thereby improving the efficiency of simulation verification of the design to be tested.

[0004] According to the present invention, a simulation verification acceleration system is provided, the system comprising a design to be tested dut, a first verification component uvc1 and a second verification component uvc2; uvc1=(uvc 1,1 ,uvc 1,2 ,…,uvc 1,k ,…,uvc 1,m ), uvc 1,k is the kth first verification component, the value range of k is 1 to m, and m is the number of first verification components; uvc2=(uvc 2,1 ,uvc 2,2 ,…,uvc 2,i ,…,uvc 2,n ), uvc 2,i is the i-th second verification component, the value of i ranges from 1 to n, and n is the number of second verification components.

[0005] dut includes register channel rnoc and tested module engine, engine=(engine1,engine2,…,engine i ,…,engine n ), engine i The i-th module under test included in dut, engine i With uvc 2,i Connection; the input interface of rnoc is iniu, iniu=(iniu1, iniu2,…, iniu k ,…,iniu m ), iniu k is the kth input interface of rnoc; the output interface of rnoc is tniu, tniu=(tniu1, tniu2,…, tniu i ,…,tniu n ), tniu i is the i-th output interface of rnoc, tniu i With engine i connect.

[0006] Each uvc 1,k And every uvc 2,i Each includes 1 sequencer.

[0007] Each uvc 1,k The sequencer is used to issue a request during the simulation verification of the dut, and each uvc 1,k The request sent by the sequencer is sent to the sequencer of the matching second verification component after being mapped by the sequencer, so that the sequencer of the matching second verification component sends the request to the module under test connected to the matching second verification component after receiving the request.

[0008] Compared with the prior art, the present invention has at least the following beneficial effects:

[0009] The acceleration system for simulation verification of the present invention includes a design to be tested, and also includes a first verification component and a second verification component. The design to be tested includes a register channel and a module to be tested. The register channel includes an input interface and an output interface. The number of output interfaces is equal to the number of modules to be tested, and the number of input interfaces is equal to the number of first verification components. The number of modules to be tested in the acceleration system of the present invention is also equal to the number of second verification components. Each module to be tested is connected to one second verification component, and different modules to be tested are connected to different second verification components. When the acceleration system of the present invention performs simulation verification on the design to be tested, each request sent by the first verification component no longer enters the input interface of the register module, but is sent to the matching second verification component after being mapped by the sequencer. The sequencer of the component is then sent by the sequencer of the matching second verification component to the module under test connected to the matching second verification component; therefore, the acceleration system of the present invention no longer passes through the register channel in the design under test when simulating and verifying the design under test, which can save the time for request routing in the register channel; moreover, the present invention connects the second verification component to each module under test to realize the transmission of the request from the first verification component to the second verification component, and then to the module under test connected to the second verification component. The transmission path is no longer affected by the delay unit in the register channel, and the corresponding transmission time is shorter, thereby reducing the time for simulating and verifying the design under test, thereby improving the efficiency of simulating and verifying the design under test. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0011] Figure 1 A flowchart of a sequencer mapping process of an acceleration system for simulation verification provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0013] According to this embodiment, a simulation verification acceleration system is provided, the system comprising a design under test dut, a first verification component uvc1 and a second verification component uvc2; uvc1=(uvc 1,1 ,uvc1,2 ,…,uvc 1,k ,…,uvc 1,m ), uvc 1,k is the kth first verification component, the value range of k is 1 to m, and m is the number of first verification components; uvc2=(uvc 2,1 ,uvc 2,2 ,…,uvc 2,i ,…,uvc 2,n ), uvc 2,i is the i-th second verification component, the value of i ranges from 1 to n, and n is the number of second verification components.

[0014] Those skilled in the art are aware that any verification component in the prior art falls within the protection scope of the present invention; as an optional specific implementation, the verification component includes a sequencer, which can allow several sequences to generate requests and send these requests to the design to be tested to achieve simulation verification of the design to be tested.

[0015] dut includes register channel rnoc and tested module engine, engine=(engine1,engine2,…,engine i ,…,engine n ), engine i The i-th module under test included in dut, engine i With uvc 2,i Connection; the input interface of rnoc is iniu, iniu=(iniu1, iniu2,…, iniu k ,…,iniu m ), iniu k is the kth input interface of rnoc; the output interface of rnoc is tniu, tniu=(tniu1, tniu2,…, tniu i ,…,tniu n ), tniu t is the tth output interface of rnoc, tniu i With engine i connect.

[0016] In this embodiment, the register channel is connected to the module under test. Specifically, the number of output interfaces included in the register channel is equal to the number of modules under test. Each output interface of the register channel is connected to one module under test, and different output interfaces are connected to different modules under test. The number of input interfaces included in the register channel is equal to the number of first verification components. The function of the register channel is to route the request received by the input interface to the corresponding output interface and then transmit it to the module under test connected to the output interface. The basis for routing is the address mapping relationship corresponding to the register channel, that is, the mapping relationship between the address of the request of the input interface entering the register channel and the output interface. Each output interface corresponds to several addresses, and the addresses corresponding to different output interfaces are different. If the address of the request of the input interface entering the register channel belongs to several addresses corresponding to a certain output interface, then the register channel can realize the function of transmitting the request of the input interface entering the register channel to the output interface; the register channel is a hardware circuit mechanism. After the hardware circuit of the register channel is determined, the address mapping relationship corresponding to the register channel is also determined.

[0017] Each uvc 1,k And every uvc 2,i Each includes 1 sequencer. 1,k sequencer k Used to control sequence k Whether the generated request is sent, sequence k It is used to generate requests and pass through the sequencer when simulating and verifying the dut k The sequence sent, sequence k =(sequence k,1 ,sequence k,2 ,…,sequence k,j ,…,sequence k,z ), sequence k,j It is used to generate requests and pass through the sequencer when simulating and verifying the dut k The jth sequence sent, j ranges from 1 to z, z is used to generate requests and pass through the sequencer when simulating and verifying the dut k The number of sequences emitted.

[0018] Each uvc 1,k The sequencer is used to issue a request during the simulation verification of the dut, and each uvc 1,kThe request sent by the sequencer is sent to the sequencer of the matching second verification component after being mapped by the sequencer, so that the sequencer of the matching second verification component sends the request to the module under test connected to the matching second verification component after receiving the request.

[0019] When the acceleration system for simulation verification based on the present embodiment performs simulation verification on the design to be tested, the request issued by each first verification component no longer enters the input interface of the register channel. Thus, when the design to be tested is simulated and verified, the request can be bypassed from the input interface of the register channel to the register channel and then output from the output interface of the register channel, and then sent to the transmission channel of the module under test; instead, the request is transmitted from the sequencer that issues the request to the sequencer of a second verification component, and then transmitted to the module under test.

[0020] As a preferred specific embodiment, Figure 1 As shown, each UVC 1,k The request sent by the sequencer is processed by the sequencer mapping and sent to the sequencer of the matching second verification component, including:

[0021] S100, get uvc 1,k The sequencer sends a request req k,0 Addressadd k,0 .

[0022] Those skilled in the art are aware that each request issued by the sequencer carries an address, and the address is used to indicate the location of the operation object corresponding to the request.

[0023] S200, obtain the address mapping table A of uvc2; A=((uvc 2,1 ,add1),(uvc 2,2 ,add2),…,(uvc 2,i ,add i ),…,(uvc 2,n ,add n )), add i For uvc 2,i The corresponding address set, any two add i There is no intersection between them.

[0024] In this embodiment, A is obtained according to the address mapping relationship of rnoc, which includes the mapping relationship between the address of the request issued by the sequencer of uvc1 and tniu. If the address mapping relationship of rnoc indicates that the address of a request add' is mapped to tniu i There is a mapping relationship, then uvc in A 2,i The corresponding address set add iIncludes add'.

[0025] In this embodiment, A has a corresponding relationship with the address mapping relationship of rnoc. It is known that the address mapping relationship of rnoc has a corresponding relationship. If the address mapping relationship of rnoc indicates that the address add' of a certain request is i If there is a mapping relationship, then the constructed A that has a mapping relationship with add' is the same as tniu i The connected module under test engine i Connected uvc 2,i .

[0026] S300, add k,0 Match in A, if add k,0 belongs to add i , then add i Corresponding uvc 2,i The second verification component is determined to be a match.

[0027] S400, will req k,0 Sent to the matched second verification component.

[0028] Based on the above preferred specific implementation manner, simulation verification of the design function to be tested can be achieved without going through register channel routing, and the verification result of the design function to be tested is the same as the simulation verification result of the design function to be tested when going through register channel routing; and since the register channel routing process is omitted, the problem of long simulation verification time caused by the delay unit in the register channel is also solved.

[0029] As a preferred specific implementation, m≥2, S100 further includes: obtaining req k,0 Sequence preservation tag k,0 , according to tag k,0 Determine req k,0 Is order preservation required? If so, a request will be issued. k,0 The sequencer is determined as the target sequencer, and S400 further includes: k,0 Only the target sequencer is allowed to send requests to the engine within a preset sequence preservation time period after sending to the matching second verification component.

[0030] Optionally, the above preset sequence preservation time is an empirical value.

[0031] Based on the above preferred specific implementation, when multiple first verification components send requests to the module under test, the problem of mutual influence when multiple first verification components simultaneously access a unified register in the same module under test can be avoided, thereby improving the accuracy of the simulation verification results.

[0032] In this embodiment, if it is not necessary, S400 further includes: k,0 Any uvc is allowed within the preset sequence preservation time period after being sent to the matching second verification component 1,k The sequencer sends a request to the engine.

[0033] As a specific implementation, the tag k,0 Determine req k,0 Whether to preserve the order includes: if tag k,0 is the first preset value, then req k,0 Need to preserve order; if tag k,0 is the second preset value, then req k,0 No order preservation is required. Optionally, the first preset value is 1 and the second preset value is 0.

[0034] The acceleration system for simulation verification of the present embodiment includes a design to be tested, and also includes a first verification component and a second verification component. The design to be tested includes a register channel and a module to be tested. The register channel includes an input interface and an output interface. The number of output interfaces is equal to the number of modules to be tested, and the number of input interfaces is equal to the number of first verification components. The number of modules to be tested in the acceleration system of the present embodiment is also equal to the number of second verification components. Each module to be tested is connected to one second verification component, and different modules to be tested are connected to different second verification components. When the acceleration system of the present embodiment performs simulation verification on the design to be tested, each request sent by the first verification component no longer enters the input interface of the register module, but is sent to the matching second verification component after being processed by the sequencer mapping. The sequencer of the verification component is then sent by the sequencer of the matching second verification component to the module under test connected to the matching second verification component; thus, the acceleration system of this embodiment no longer passes through the register channel in the design under test when simulating and verifying the design under test, which can save the time for routing the request in the register channel; moreover, this embodiment connects the second verification component to each module under test to realize the transmission of the request from the first verification component to the second verification component, and then to the module under test connected to the second verification component. The transmission path is no longer affected by the delay unit in the register channel, and the corresponding transmission time is shorter, thereby reducing the time for simulating and verifying the design under test, thereby improving the efficiency of simulating and verifying the design under test.

[0035] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A simulation verification acceleration system, characterized in that: The system includes a design to be tested dut, a first verification component uvc1 and a second verification component uvc2; uvc1=(uvc 1,1 ,uvc 1,2 ,…,uvc 1,k ,…,uvc 1,m ), uvc 1,k is the kth first verification component, the value range of k is 1 to m, and m is the number of first verification components; uvc2=(uvc 2,1 ,uvc 2,2 ,…,uvc 2,i ,…,uvc 2,n ), uvc 2,i is the i-th second verification component, i ranges from 1 to n, and n is the number of second verification components; dut includes register channel rnoc and tested module engine, engine=(engine1,engine2,…,engine i ,…,engine n ), engine i The i-th module under test included in dut, engine i With uvc 2,i Connection; the input interface of rnoc is iniu, iniu=(iniu1, iniu2,…, iniu k ,…,iniu m ), iniu k is the kth input interface of rnoc; the output interface of rnoc is tniu, tniu=(tniu1, tniu2,…, tniu i ,…,tniu n ), tniu i is the i-th output interface of rnoc, tniu i With engine i connect; Each uvc 1,k And every uvc 2,i All include 1 sequencer; Each uvc 1,k The sequencer is used to issue a request during the simulation verification of the dut, and each uvc 1,k The request sent by the sequencer does not enter the input interface of rnoc, but is sent to the sequencer of the matching second verification component after being mapped by the sequencer, so that the sequencer of the matching second verification component sends the request to the module under test connected to the matching second verification component after receiving the request.

2. The acceleration system for simulation verification according to claim 1, characterized in that: In the process of simulating and verifying the DUT, each UVC 1,k The request sent by the sequencer does not enter the input interface of rnoc, but is sent to the sequencer of the matching second verification component after being processed by the sequencer mapping, including: S100, get uvc 1,k The sequencer sends a request req k,0 Addressadd k,0 ; S200, obtain the address mapping table A of uvc2; A=((uvc 2,1 ,add1),(uvc 2,2 ,add2),…,(uvc 2,i ,add i ),…,(uvc 2,n ,add n )), add i For uvc 2,i The corresponding address set, any two add i There is no intersection between them; S300, add k,0 Match in A, if add k,0 belongs to add i , then add i Corresponding uvc 2,i A second verification component determined to be a match; S400, will req k,0 Sent to the matched second verification component.

3. The acceleration system for simulation verification according to claim 2, characterized in that: A is obtained according to the address mapping relationship of rnoc. The address mapping relationship of rnoc includes the mapping relationship between the address of the request issued by the sequencer of uvc1 and tniu. If the address mapping relationship of rnoc indicates that the address add' of a request is mapped to tniu i There is a mapping relationship, then uvc in A 2,i The corresponding address set add i Includes add'.

4. The acceleration system for simulation verification according to claim 2, characterized in that: m≥2, S100 also includes: obtaining req k,0 Sequence preservation tag k,0 , according to tag k,0 Determine req k,0 Is order preservation required? If so, a request will be issued. k,0 The sequencer is determined as the target sequencer, and S400 further includes: k,0 Only the target sequencer is allowed to send requests to the engine within a preset sequence preservation time period after sending to the matching second verification component.

5. The acceleration system for simulation verification according to claim 4, characterized in that: According to the tag k,0 Determine req k,0 Whether to preserve the order includes: if tag k,0 is the first preset value, then req k,0 Need to preserve order; if tag k,0 is the second preset value, then req k,0 No order preservation is required.

6. The acceleration system for simulation verification according to claim 4, characterized in that: S100 further includes: if not required, then S400 further includes: after req k,0 Any uvc is allowed within the preset sequence preservation time period after being sent to the matching second verification component 1,k The sequencer sends a request to the engine.

7. The acceleration system for simulation verification according to claim 1, characterized in that: uvc 1,k sequencer k Used to control sequence k Whether the generated request is sent, sequence k It is used to generate requests and pass through the sequencer when simulating and verifying the dut k The sequence sent, sequence k =(sequence k,1 ,sequence k,2 ,…,sequence k,j ,…,sequence k,z ), sequence k,j It is used to generate requests and pass through the sequencer when simulating and verifying the dut k The jth sequence sent, j ranges from 1 to z, z is used to generate requests and pass through the sequencer when simulating and verifying the dut k The number of sequences emitted.

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