Circuit package for connecting electro-photonic memory structures

Abstract

The present disclosure relates to a thermal control system, a photonic memory structure, and an electro-absorption modulator (EAM). For example, a thermal control system efficiently moves data in a memory structure based on utilizing and controlling thermal control optical components. As such, EAM is an example of an optical modulator for efficiently moving data in a digital circuit while maintaining thermally stable optical modulation over a wide temperature range.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the following applications: U.S. patent application serial number 17 / 903,455, filed on September 6, 2022, entitled "PHOTONIC MEMORY FABRIC SUPPORTING MEMORY INTERCONNECTION", which claims priority to U.S. patent application serial number 63 / 321,453, filed on March 18, 2022, entitled "PHOTONIC MEMORY FABRIC FOR MEMORY INTERCONNECTION"; U.S. patent application serial number 17 / 807,694, filed on June 17, 2022, entitled "MULTI-CHIP ELECTRO-PHOTONIC NETWORK"; U.S. patent application serial number 17 / 807,694, filed on October 28, 2022, entitled "THERMALLY STABLE OPTICAL MODULATION ELEMENTS COUPLEDTO ELECTRONIC ELEMENTS”; and U.S. patent application serial number 63 / 420,330, filed on October 28, 2022, entitled “THERMAL CONTROL OF AN OPTICAL COMPONENT” and U.S. patent application serial number 63 / 420,323, filed on October 28, 2022. In addition, this application also claims priority to U.S. patent application serial number 18 / 123,170, filed on March 17, 2023, entitled “THERMAL CONTROL OF ANOPTICAL COMPONENT”; and U.S. patent application serial number 18 / 123,161, filed on March 17, 2023, entitled “CIRCUIT PACKAGE FOR CONNECTING TO AN ELECTRO-PHOTONIC MEMORY FABRIC”. All of the foregoing applications are incorporated herein by reference in their entirety. Technical Field Background Art

[0003] Over time, applications such as machine learning (ML), deep learning (DL), natural language processing (NLP), and machine vision (MV) have become more sophisticated and developed to handle more complex tasks. However, computing devices have not evolved to the point where they can effectively meet the needs of these new applications. For example, without sufficiently advanced computing paradigms, ML, DL, NLP, and MV applications cannot realize their full potential.

[0004] One solution is to connect many chips into a system where the chips can transmit data to each other with low latency and high speed. In one method, the connection between chips is made using a serializer / deserializer (SerDes) block, which converts parallel messages into a serial bit stream that can be transmitted through electrical interconnects or optical fibers between chips. In such systems, there is a distinction between on-chip communication and off-chip communication. For example, the computing elements on the chip use metal interconnects, while messages going to another chip must reach the interface with the SerDes through chip-level interconnects, where the data is converted into a bit stream and transmitted optically. In the receiving direction, the bits arrive at the optical fiber or electrical interconnect, are assembled, and then transmitted to the destination processor or memory through the metal interconnects inside the chip. A lot of energy is consumed when moving data to the SerDes within the chip and then moving it from the SerDes to other chips in the system.

[0005] In addition, the performance of the system when processing workloads is limited by memory and interconnect bandwidth. Data movement (resulting in large power consumption, poor performance, and excessive latency) exacerbates this problem, especially as AI workloads grow exponentially. Conventional digital computing environments that rely on electrical interconnects are insufficient to meet the required data movement of AI workloads. Therefore, some existing systems use hybrid electronic-photonic computing. However, these existing systems are inefficient due to large data movement distances and poor thermal environment management. Summary of the invention BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 A block diagram illustrating an exemplary memory structure for connecting to one or more circuit packages according to one or more embodiments disclosed in the present disclosure.

[0007] Figure 2 Embodiments of a memory structure suitable for connection to one or more circuit packages according to one or more embodiments disclosed in the present disclosure are shown.

[0008] Figure 3 A top view of another embodiment of a memory structure suitable for connection to one or more circuit packages is shown in accordance with one or more embodiments disclosed in the present disclosure.

[0009] Figure 4 A perspective view illustrating an embodiment of a three-dimensional memory structure suitable for connection to one or more circuit packages according to one or more embodiments disclosed in the present disclosure.

[0010] Figure 5 is a diagram illustrating an exemplary system showing an intra-chip link between two adjacent nodes in a memory structure according to one or more embodiments disclosed in the present disclosure.

[0011] Figure 6 is a diagram illustrating an exemplary system showing an inter-chip link between two adjacent nodes in different chips according to one or more embodiments disclosed in the present disclosure.

[0012] Figure 7 is a side view of a circuit package according to one or more embodiments disclosed in the present disclosure.

[0013] Figure 8 is a side view of a circuit package according to one or more embodiments disclosed in the present disclosure.

[0014] Fig. 9 is a top view of a node of a memory structure according to one or more embodiments disclosed in the present disclosure.

[0015] Fig.10 is a flow chart for using a memory structure according to one or more embodiments disclosed in the present disclosure.

[0016] Fig.11A A top view of a system-in-package (SIP) suitable for use with various embodiments is shown.

[0017] Fig. 11B Depicted is a side view of a SIP according to one or more embodiments disclosed within the present disclosure.

[0018] Fig.12 Depicts an exemplary node of a heat generating element that may be used in a photonic structure according to one or more embodiments disclosed within the present disclosure.

[0019] Fig.13A A cross-sectional view illustrating a portion of a thermal control system for an optical component according to one or more embodiments disclosed in the present disclosure.

[0020] Fig. 13B A top view of a portion of a thermal control system for an optical component is shown according to one or more embodiments disclosed in the present disclosure.

[0021] Fig.14 A cross-sectional view illustrating a portion of a SIP having the ability to thermally control optical components according to one or more embodiments disclosed in the present disclosure.

[0022] Fig.15 A top view of a SIP having the ability to thermally control optical components is shown according to one or more embodiments disclosed in the present disclosure.

[0023] Fig.16 is a flow chart illustrating operations involved in thermally controlling an optical component in accordance with one or more embodiments disclosed within the present disclosure.

[0024] Fig.17 is a flow chart illustrating operations involved in thermally controlling an optical component in accordance with one or more embodiments disclosed within the present disclosure.

[0025] Fig.18A Another side view of a SIP is shown in accordance with one or more embodiments disclosed within the present disclosure.

[0026] Fig.18B A more detailed side view of a SIP is shown in accordance with one or more embodiments disclosed within the present disclosure.

[0027] Fig.19 Another top view illustrating a portion of a thermal control system for an optical component according to one or more embodiments disclosed in the present disclosure.

[0028] Fig. 20 is a flow chart illustrating data movement within a digital circuit in a photonic structure according to one or more embodiments disclosed in the present disclosure. DETAILED DESCRIPTION

[0029] The present application discloses methods, devices and systems for thermal control (e.g., thermal control systems) of circuit packages and / or optical components connected to n-dimensional electro-photonic memory structures. With respect to circuit packages and n-dimensional electro-photonic memory structures, the circuit packages have various arrangements and are configured to receive message packets from at least one client computing element, such as a microprocessor (MPU), a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence (AI) accelerator, or another digital application-specific integrated circuit (ASIC).

[0030] Depending on the context, a photonic structure (e.g., an electro-photonic memory structure) allows low-latency and low-power data movement when moving data within and between chips. For example, the structure consists of nodes connected by optical links within and between chips. Data is moved from a source node in the structure to a destination node by moving the data between the source node and any intermediate node units until it reaches the destination node. At each node, a message router moves the data along the next hop in the path. For example, when a node receives data along an optical link, the message router performs optoelectronic conversion and electro-optical conversion to pass the data along the optical link to the next node. At the destination node, the signal is converted into electrical form and used by a processor and / or memory associated with the destination node.

[0031] As previously described, the present disclosure depicts an n-dimensional electro-photonic memory structure that improves the movement of data processed by a computing element (e.g., a client computing element). Specifically, the electro-photonic memory structure provides a hybrid electro-photonic computing environment for moving data or instructions photonically by transmitting data packets in the form of electromagnetic waves in an optical carrier (such as a waveguide or optical fiber). By transmitting data or instructions optically, the system is fast and consumes minimal power. Moreover, as further described below, the electro-photonic memory structure achieves an efficient balance of sending, receiving, converting, processing, and modifying data in the optical and electrical domains.

[0032] As described above, embodiments of the present disclosure are directed to solving one or more of the above problems and other problems in the art. For example, various systems, devices, components, methods, and approaches provide improved data movement using n-dimensional electro-optical memory structures. Specifically, embodiments of the present disclosure describe connecting a circuit package to a memory structure, which connection provides an improved hybrid electro-optical computing environment.

[0033] For example, in various embodiments, the electro-photonic memory structures achieve optimal system performance by processing workloads quickly and efficiently. For example, the electro-photonic memory structures described in this document maximize the use of the optical domain when processing workloads by minimizing the distance between data and computing power (which reduces the amount that needs to be moved when processing workloads). In some embodiments, the electro-photonic memory structures described in this document can manage the thermal environment of the hardware layer to ensure that the system operates efficiently without wasting available packaging space.

[0034] As explained in the above discussion, the present disclosure utilizes a variety of terms to describe the features and advantages of one or more embodiments. For example, this document often refers to a core particle. In this document, a core particle refers to a small or micro integrated circuit (IC) that performs one or more functions. A core particle is typically combined with other core particles on an interposer in a single package (e.g., a circuit package).

[0035] Additional details regarding exemplary embodiments of a core particle or memory structure are discussed in conjunction with the following figures. For example, Figure 1 A block diagram showing an exemplary memory structure for connecting one or more circuit packages according to one or more embodiments disclosed in the present disclosure. For example, Figure 1 The system 100 includes a server 102 and circuit packages (i.e., circuit package 104 and circuit package 106). As shown, the system 100 includes a memory structure (shown as an n-dimensional electro-optical memory structure 108) having two nodes (i.e., node 110 and node 112). Although Figure 1 A specific number of nodes and circuit packages are shown, but system 100 may include any number of nodes and circuit packages.

[0036] Figure 1 The components in FIG. 1 show various interconnections. For example, Figure 1 The interconnect shown in FIG. 1 includes a photonic channel 114. Although Figure 1 It is not explicitly shown in the , but the memory structure and circuit package typically include electronic integrated circuits (EICs) and / or photonic integrated circuits (PICs), such that each of the nodes and each of the circuit packages has at least one photonic transceiver, whose functionality resides partially in the EIC and / or partially in the PIC. This enables the photonic transceiver to send and receive data packets as modulated electromagnetic waves in the optical domain via the photonic channel 114, or to send and receive data packets as digital packets via electrical interconnects.

[0037] Various embodiments of the photonic transceiver include active or passive components in the EIC and active or passive components in the PIC that are directly joined together or stacked on top of each other, for example, in a chip-to-chip configuration. For example, a copper pillar or another electrical connector connects the active components in the EIC to the passive components in the PIC. In this way, the copper pillar bridges a gap that is typically between 2 millimeters and less than 50 microns. In these embodiments, the copper pillar bridge is substantially perpendicular to the planes of the EIC and the PIC. In addition, this direct joining, direct coupling, or stacking of electrical interconnections between electrical and optical components maximizes the bandwidth of the photonic transceiver.

[0038] Figure 2 Show Figure 1 Specifically, Figure 2 An embodiment of a server-based memory structure 290 is shown that uses circuit packaging to move data within the memory structure (eg, to move data into and out of computing elements and memory / computing resources).

[0039] As shown, system 200 includes server 102, additional memory / computing resources 206, switch 208 and circuit package 104. Server 102 includes node 110. Although not shown, system 200 and / or server 102 may include additional nodes extending in one or more dimensions. As shown, node 110 includes memory connection area 212, memory controller 232, computing connection area 214, interface controller 234 (e.g., memory and / or computing interface controller), message router 238 (i.e., router), routing controller 236, photonic interface 230 and thermal control block 242.

[0040] As shown, node 110 (eg, server 102) is connected to circuit package 104 and via switch 208, via photon channel 204. Circuit package 104 includes interposer 222 that connects core 216 and computing element 224 via interconnect 220 and / or connection region 218. Figure 2 In FIG. 2 , core 216 includes photonic interface 228, message router 226, switch 210, and thermal control block 240. In addition, as shown, circuit package 104 and server 102 are connected to additional memory / computing resources 206 via switch 208 using photonic channel 202.

[0041] In various embodiments, the circuit package 104 is connected to the server 102 and the additional memory / computing resource 206 via a photon channel (e.g., photon channel 202 and photon channel 204). In various embodiments, a switch (e.g., switch 208 or switch 210) is used to determine when the photon channel is used, thereby determining whether the circuit package 104 accesses the server-based memory structure 290 on the server 102 or accesses the additional memory / computing resource 206.

[0042] Although Figure 2 It is simplified to show a single node (i.e., node 110) on server 102, but in many embodiments, the chip on server 102 includes hundreds of nodes. In addition, a multi-chip configuration may have hundreds of thousands of nodes (or more) connected via photonic channels in an n-dimensional memory structure. In these cases, each of the nodes may have the characteristics of node 110, including memory connection area 212 and / or computing connection area 214.

[0043] Memory connection area 212 and compute connection area 214 are designed to provide a standard interface for a computing element or a memory element integrated into system 200. In various embodiments, memory connection area 212 and compute connection area 214 are configured to receive a memory element or a computing element using electrical connections such as copper wires, bump attach units, copper pillars, through silicon vias, and / or other connections.

[0044] Examples of memory elements include, but are not limited to, NAND flash memory, solid-state drive (SSD) memory, NOR flash memory, complementary metal oxide semiconductor (CMOS) memory, thin film transistor-based memory, phase change memory (PCM), storage class memory (SCM), read-only memory (ROM), random access memory (RAM), magnetoresistive RAM (MRAM), resistive RAM, static random access memory (SRAM), dynamic RAM (DRAM), synchronous dynamic random access memory (SDRAM), double data rate (DDR)-based DRAM, high bandwidth memory (HBM), and dual in-line memory module (DIMM) memory.

[0045] Examples of computing elements include, but are not limited to, a CPU, a GPU, an MPU, a tensor engine, a load unit, a storage unit, a neural compute engine, a dot product, a convolution engine, a field programmable gate array (FPGA), and / or an AI accelerator.

[0046] Circuit package 104 includes a core 216 and a connection region 218 connected via an interconnect 220. In various embodiments, core 216 has a bottom surface that is coupled to connection region 218 via an electrical connection through interposer 222. In some cases, interconnect 220 can be used as an electrical connection. In addition, in various embodiments, interconnect 220 is a standard electrical connection through interposer 222. In one or more embodiments, interconnect 220 includes a plurality of channels corresponding to a plurality of ports in memory connection region 212 or computing connection region 214.

[0047] The computing element 224 may be connected to the connection region 218 using a variety of means. The core 216 also includes a message router 226 for controlling the flow of packets between the core and the rest of the system 200. For example, the router forms a digital packet that includes a message request from the computing element and corresponding routing information. In various embodiments, the photonic interface 228 on the circuit package 104 and the photonic interface 230 on the node 110 form an optical bidirectional path for optical signals that represent digital packets and can be reconstructed and / or converted to digital form when being routed between the server 102 and the circuit package 104 to the electrical port of the message router at the final destination.

[0048] Although not in Figure 2Although not specifically shown in the figure, the photonic interface generally includes a photonic transceiver having a transmitting unit and a receiving unit. In various cases, the transmitting unit converts a digital packet into an optical signal and transmits the optical signal through a photonic channel. Similarly, the receiving unit converts the optical signal into a digital packet and transmits the optical signal through an electrical channel. For example, the photonic interface 228 in the circuit package 104 uses a transmitting unit to connect to a receiving unit in the photonic interface 230 of the node 110 via a first photonic channel, while the transmitting unit in the photonic interface 230 of the node 110 is connected to the receiving unit in the photonic interface 228 of the circuit package 104 via a second photonic channel. This enables bidirectional optical communication between the circuit package 104 and the server 102.

[0049] In some embodiments, within the router, the transmitting unit is partially in the core 216 and partially in the interposer 222. In these cases, the transmitting unit transmits the digital packet in optical form to the photonic interface through the fiber array unit (FAU) to reach the destination indicated in the routing information of the digital packet. Similarly, in various embodiments, the receiving unit is partially in the core 216 and partially in the interposer 222. For example, the receiving unit is partially in the core 216 and partially in the interposer 222 for receiving the optical signal in digital form at the router through the FAU.

[0050] In one or more embodiments, circuit package 104 requests entries stored in memory connection region 212 of node 110, and / or utilizes computing resources available in computing connection region 214. In these cases, photonic interface 230 receives the request from circuit package 104 via photonic channel 204 and converts the request into a digital packet, which is provided to memory controller 232, interface controller 234, or routing controller 236.

[0051] In various embodiments, memory controller 232 is an electrical interface, such as a Joint Electronic Device Engineering Council (JEDEC) compliant or Compute Express Link (CXL) compliant interface, which can be used to access data entries stored in memory elements connected in memory connection area 212. In one or more embodiments, interface controller 234 is an electrical interface, device, or module that controls and configures the interface of connected computing elements in compute connection area 214. In several embodiments, interface controller 234 performs configuration, handles faults, provides embodiments of algorithms to transfer data to and from the interface, and / or generates interrupt events that signal compute connection area 214 when events related to the interface occur.

[0052] Additionally, in one or more embodiments, routing controller 236 is used in memory structures where the current node is not the destination node (not shown). In these cases, routing controller 236 modifies the digital packet to update routing information before sending the digital packet to a transmission unit connected to an adjacent or next node on the route to the destination node.

[0053] In various embodiments, when the current node is not the destination node, the message router 238 uses one of its optical ports to photonically transmit the digital packet. In addition, in one or more embodiments, when computing or memory resources are used in the current node, the message router 238 outputs the digital packet along its electrical port.

[0054] Figure 2 A thermal control block is also included. For example, server 102 includes thermal control block 242 and circuit package 104 includes thermal control block 240. In various embodiments, thermal control block provides thermal control for circuit package 104 and server-based memory structure 290.

[0055] Some embodiments use thermally stable optical components, such as electro-absorption modulators (EAMs), in photonic integrated circuits (PICs). These optical components are typically manufactured to have an operating range that is typically in excess of 30 degrees Celsius. These optical components are directly coupled to active electronic components in the EIC, such as drivers, serializer / deserializer (SERDES) blocks, controllers, via copper pillars or another interconnect that can provide direct chip-to-chip bonding of the layers.

[0056] Due to the relatively small gap between active and passive components in a photonic transceiver, the heat generated by the EIC is typically radiated into the PIC and affects the thermal operating environment of the EAM. In some embodiments, the EAM is designed relative to the expected thermal behavior in the EIC. In these embodiments, the thermal impact of the EIC operating at maximum load determines the operating window of the EAM directly coupled thereto.

[0057] Thus, one of the functions of the thermal control blocks (eg, thermal control blocks 240 and 242) is to provide voltage inputs to the EAM when needed to extend the operating range of the EAM depending on the current thermal conditions the EAM is operating in. Additional details regarding the thermal control blocks are provided below.

[0058] Figure 3 The use of a memory structure to connect circuit packages is shown. As shown, Figure 3The memory structure 330 and the circuit package (i.e., the circuit package 118 and the circuit package 120) are included. The top view conceptually shows the memory structure 330. As shown, the memory structure 330 is part of the server 302 and includes a plurality of nodes 304 connected to each other via a photon channel 318. One or more nodes in the plurality of nodes 304 are also directly connected to the circuit package via a photon channel 320. In various embodiments, the photon channel includes inter-chip links and intra-chip links. Figure 5 and Figure 6 Provides more details about the photon channel. Fig. 9 Provides more details and internal components of the node.

[0059] As shown, memory structure 330 includes sixteen nodes (i.e., multiple nodes 304) arranged in a two-dimensional grid of 4x4. In other embodiments, memory structure 330 is larger in size and has additional ports or switches to realize the connection of nodes in n dimensions. In the embodiment where 4x4 grid is used for memory structure 330, each of multiple nodes 304 has at least 4 optical ports and an electrical port. In these embodiments, optical ports can realize the interconnection of all internal nodes. For example, the transmitting unit and receiving unit of adjacent nodes are optically connected by photon channels to establish a bidirectional optical connection between nodes. The nodes at the periphery of the grid can have optical ports dedicated to circuit packaging and / or can be used for inter-chip or intra-chip links to other nodes (not shown). Alternatively, if additional ports are not needed, the optical ports on the nodes (e.g., nodes have only two or three optical ports) may not be used or manufactured, such as corner nodes.

[0060] In various embodiments, each of the plurality of nodes 304 of the memory structure 330 includes one or more message routers (not shown) that are used together with the photon channel 318 to form an electro-photonic network. In these embodiments, the message routers are arranged in a two-dimensional quadrilateral array or grid. The message routers of two nodes that are adjacent to each other (e.g., in the horizontal or vertical direction) are connected by a bidirectional channel. In this way, each message router in the interior of the array includes at least four photon channel interfaces for at least four corresponding bidirectional photon channels (e.g., one photon channel interface for each of the directions that can be referred to as "north", "south", "east" and "west"). In addition, along the periphery of the array, the router only needs to have two (at the corners) or three (at the edges between the corners) photon channel interfaces serving the memory structure 330. In various embodiments, as shown with respect to the circuit package 118 and the circuit package 120, some or all of the photon channel interfaces at the corner nodes and edge nodes (which are not dedicated to the memory structure 330) are used for point-to-point connections with the circuit package.

[0061] In various embodiments, the message routers use various addressing schemes to route messages between the circuit packages and the plurality of nodes 304. Regardless of the addressing scheme, the messages may be delivered primarily or entirely through the memory structure 330 via the photonic channels 318 and / or photonic channels 320 (optical-to-electrical and electrical-to-optical conversion at each router along the path) in the PIC.

[0062] In one or more embodiments, packet data is provided between multiple nodes 304 and / or circuit packs and includes routing information to indicate its destination. For example, a signed 5-bit packet data (e.g., extracted from a header or payload of a message) provides a relative position (or distance) relative to a destination node in a horizontal direction (east / west). For another example, a signed 5-bit packet data provides a relative position (or distance) relative to a destination node in a vertical direction (north / south). In various embodiments, packet data of different sizes (e.g., number of bits) are used (e.g., depending on the number of nodes and the resulting address space size).

[0063] As the message traverses the router to reach different nodes, the routing information may be modified. For example, the horizontal or vertical coordinate of the routing information is decremented for each hop, depending on the dimension along which the message is passed. In this example, the message has reached the destination node when the packet data provided in the direction of the destination node decrements or decreases to zero. The message is then forwarded to the local electrical port of the router in the node for use by computing or memory resources. In some cases, the message is used to transmit read and write memory services between nodes or circuit packages.

[0064] In one or more embodiments, the server 302 includes a thermal control block (TC) 332. As described, the thermal control block will be described in more detail later. In various embodiments, the thermal control block responds to changes in thermal conditions of the PIC in one or all of the plurality of nodes 304. In one example, the thermal control block cycles through each of the plurality of nodes 304 and provides the node's input voltage to the PIC (when needed). For example, the thermal control block provides an input voltage sized to restore the node's EAM to peak operating conditions during each time period.

[0065] Figure 4 A higher dimensional memory structure is shown, such as a three-dimensional memory structure for connecting circuit packages. As shown in the figure, Figure 4 A perspective view of a higher dimensional memory structure 400 for connecting circuit package 118 is shown.

[0066] exist Figure 4, a higher dimensional memory structure 400 has a plurality of layers 404, including a first layer 404a and a second layer 404b. Each layer in the plurality of layers 404 includes a router 402. Specifically, the first layer 404a includes routers 402a, 402b, 402c, and 402d, and the second layer 404b includes routers 402e and 402f.

[0067] In the illustrated embodiment, router 402 includes optical ports. For example, the optical ports between routers on the first layer 404a (i.e., routers 402a-d) are enhanced by higher dimensional links 405a, 405b, 405c, and 405d. Figure 4 As shown, circuit package 118 is connected to higher dimensional memory structure 400 via one of routers 402a on first layer 404a. Furthermore, any number of additional circuit packages may be connected to any number of additional routers and ports depending on the nature and topology of higher dimensional memory structure 400.

[0068] In various embodiments, the higher dimensional memory structure 400 forms a mesh or a different shape. In addition, the higher dimensional memory structure 400 forms a wrapped mesh, a ring, a wrapped ring, or an expandable wrapped ring.

[0069] As mentioned above, Figure 5 and Figure 6 Provides more details on inter-chip and intra-chip links. Figure 5 Provides an example of an intra-chip link, while Figure 6 An example of an inter-chip link is provided.

[0070] For illustration purposes, Figure 5 An example of a photonic link connecting nodes in a memory structure (i.e., an "intra-chip link"). As shown in the figure, Figure 5 The optical engine 500 includes a first beam splitter tree 502a, a second beam splitter tree 502b, a set of optical modulators 510a, 510b, 510c and 510d, a set of corresponding waveguides (e.g., waveguides 512a, 512b, 512c and 512d), and a set of photodetectors 514a, 514b, 514c and 514d.

[0071] For on-chip optical communication, an optical engine 500 (which can be an on-chip or off-chip laser light source) outputs light 504 (e.g., carrier light) at a single wavelength (e.g., λa1). A first optical splitter tree 502a can disperse the light 504 into multiple optical paths 506, which lead to optical modulators associated with different nodes and photonic channels on the chip.

[0072] As shown in the figure, Figure 5Light is shown split and propagating along multiple optical paths 506, one of which (ie, the intermediate optical path) leads to the components shown. Other optical paths (as shown by arrows) can travel to other nodes and photonic channels (not shown) on the chip.

[0073] In various embodiments, light traveling along one of the plurality of optical paths 506 may be further split. For example, the second optical splitter tree 502b splits the light in the optical path into an additional optical path 508 to provide the light to a set of optical modulators 510a-d. In some embodiments, the second optical splitter tree is a demultiplexer (demux). As shown, a set of optical modulators 510a-d corresponds to a set of photodetectors 514a-d via a set of corresponding waveguides 512a-d.

[0074] In some embodiments, a group of optical modulators 510a-d are associated with a group of unidirectional photonic links bonded together to form a bonded group. For example, a bonded group of unidirectional photonic links extends in the same direction from one node to another in the memory structure in a unidirectional photonic channel.

[0075] In some embodiments, two such unidirectional photon channels in opposite directions between the same pair of nodes of the memory structure form an intra-chip bidirectional photon channel. For example, a set of optical modulators 510a-d represents an EAM and / or modulates light to have a single wavelength (e.g., λa1) and transmits the modulated light to photodetectors 514a-d located in different nodes of the same chip via corresponding waveguides 512a-d.

[0076] As mentioned above, Figure 6 Provides examples of chip-to-chip links. For example, Figure 6 The diagram illustrates a connection between two adjacent nodes in different chips (e.g., a first chip 600a and a second chip 600b) according to some embodiments, or a point-to-point connection (i.e., "inter-chip connection") between a memory structure and a circuit package. In various embodiments, the chip implements one or more machine learning processors and / or photonic integrated circuits (PICs).

[0077] As shown, the first chip 600a includes an optical engine 650, a splitter tree 602 that generates multiple optical paths 606, a demultiplexer 654 (DEMUX), optical modulators 656a, 656b, 656c, and 656d connected to a multiplexer 680 (mux) via different waveguides 672a, 672b, 672c, and 672d, and a grating coupler 640. The first chip 600a is connected to the second chip 600b via an optical fiber connector 642. In addition, the second chip 600b includes a grating coupler 645, a waveguide 646, a demultiplexer 682, and photodetectors 692a, 692b, 692c, and 692d connected via different waveguides 674a, 674b, 674c, and 674d.

[0078] More specifically, the first chip 600a includes a light engine 650, which can be an on-chip or off-chip laser light source. The light engine 650 provides light with multiple wavelengths (e.g., 2 to 16 wavelengths). For example, the light engine 650 provides light with four wavelengths λb1, λb2, λb3, and λb4. The optical splitter tree 602 (e.g., similar to Figure 5 The first optical splitter tree 502 of the embodiment can separate the light into multiple wavelengths between multiple optical paths 606. Although only one of the multiple optical paths 606 leading to a different node of the first chip 600a with additional components is shown, each of the multiple optical paths 606 can go to a different group of similar components.

[0079] For the optical path shown, it leads to optical modulators 656a-d associated with different photon channel interfaces within the node. For example, carrier light at wavelengths λb1, λb2, λb3, and λb4 is provided to optical modulators 656a-d associated with multiple peripheral photon channel interfaces. Before reaching the optical modulators 656a-d, the light is separated by wavelength (e.g., λb1, λb2, λb3, and λb4) by demultiplexer 654. For example, optical modulators 656a-d represent different corresponding modulators (e.g., EAMs).

[0080] In various embodiments, the optical modulators 656a-d modulate the carrier light at different wavelengths λb1, λb2, λb3, and λb4, and provide the modulated optical signals with the corresponding wavelengths to a multiplexer 680 (e.g., a wavelength division (WDM) multiplexer) on different waveguides 672a-d (e.g., via different optical links). The multiplexer 680 generates a multiplex output containing four data streams (each encoded on a separate wavelength). As shown, the multiplex output is provided to a grating coupler 640 on a single waveguide 639, where the multiplexed modulated optical signal is coupled off-chip via a first optical fiber 641.

[0081] As shown, the first chip 600a and the second chip 600b are connected via an optical fiber connector 642. Specifically, the grating coupler 640 on the first chip 600a is connected to the optical fiber connector 642 via a first optical fiber 641. The optical fiber connector 642 is connected to the grating coupler 645 of the second chip 600b via a second optical fiber 643. In this way, the first chip 600a can provide one or more optical signals to the second chip 600b and / or other chips via an inter-chip link.

[0082] As shown, the second chip 600b receives the multi-path modulated optical signal from the fiber connector 642 via the second optical fiber 643. In some embodiments, edge-coupled optical fibers may be used instead of or in addition to the fiber array unit (FAU) and the grating coupler.

[0083] In the second chip 600b, the grating coupler 645 provides the multiplexed optical signal via a single waveguide to a demultiplexer 682. The demultiplexer 682 demultiplexes the multiplexed optical signal and outputs four independent modulated signals having four different wavelengths (or a corresponding number of 2-16 wavelengths) such as λb1, λb2, λb3, and λb4. In various embodiments, the four signals are provided to photodetectors 692a-d corresponding to different wavelengths via different waveguide optical waveguides 674a-d.

[0084] In various embodiments, Figure 6 The chip in the figure represents a system-in-package (SIP) that uses wavelength division multiplexing (WDM) for optical communication between chips. For example, Figure 6 The components shown in FIG. 4 form a unidirectional photon channel between nodes of different SIPs. In some cases, two such unidirectional photon channels between the same pair of SIP nodes form an inter-chip bidirectional photon channel.

[0085] Although the embodiment discussed above is directed to the photon channels of four optical links shown in one direction and the WDM multiplexer receiving four different wavelengths, in other embodiments, two or more optical links and the WDM multiplexer receiving two or more different wavelengths can be used. In these embodiments, the demultiplexer outputs two or more different wavelengths in the same manner as described above.

[0086] In various cases, the processing elements in the EIC of one or more SIPs can be connected to an electro-photonic network using intra-chip and inter-chip photonic channels as described above (such as including one or more links in each direction). In these cases, the resulting network topology generally depends on the selection of node pairs directly connected via associated photonic channels. In fact, various exemplary topologies are possible. In addition, although the present disclosure generally refers to bidirectional photonic channels (when compared with unidirectional photonic channels, the network structure generated by bidirectional photonic channels provides greater flexibility for implementing machine learning (ML) and other computing models), in principle, electro-photonic networks can also be formed by unidirectional photonic channels. In addition, such networks can also retain many of the advantages discussed in the present disclosure (e.g., power saving due to photonic data transmission over longer distances).

[0087] Figure 7 and Figure 8 Different embodiments of circuit packages (including chips) for photonically connecting client computing elements via photon interfaces are shown. As shown in the figure, Figure 7 and Figure 8 They include a photonic structure interface core 701, a computing element 702 and a PIC interposer 704 (ie, a photonic integrated circuit interposer). Figure 7 Also included is a standard interposer 706, which is Figure 8 As described above, computing element 702 (e.g., client computing element) may represent an MPU, GPU, CPU, AI accelerator, or other digital ASIC.

[0088] also, Figure 7 and Figure 8 The photonic structure interface core 701 in the embodiment includes a router 710, a thermal control block 712, a driver 714 and an amplifier 716, the router 710 being used to form a digital packet including a message request from a computing element. The PIC interposer 704 includes a modulator 718 for sending, a photodiode 720 for receiving and a multiplexer / demultiplexer 722, the multiplexer / demultiplexer 722 being connected to a fiber array unit 724 (FAU) connected to the PIC interposer 704. As also shown in the figure, the modulator 718 and the photodiode 720 of the PIC interposer 704 are respectively connected to the driver 714 and the amplifier 716 of the photonic structure interface core 701. The modulator 718 of the PIC interposer 704 is also connected to the thermal control block 712 of the photonic structure interface core 701.

[0089] As mentioned above, Figure 7A standard interposer 706 is included. More specifically, the circuit package 700 shows a computing element 702 connected to a photonic structure interface core 701 via a connection area 708 of the standard interposer 706. As shown, the standard interposer 706 routes the connection of the computing element 702 to a router 710 of the photonic structure interface core 701 via a PIC interposer 704. In various embodiments, a thermal control block 712 (e.g., an optical thermal control block) sends input to a modulator 718 when needed.

[0090] Figure 8 A standard interposer is not included. Instead, as shown, the circuit package 800 includes a PIC interposer 704 that interfaces between the computing element 702 and the photonic structure interface core 701. For example, the PIC interposer 704 includes a connection area 709 that receives messages from the computing element 702 and provides them to a router 710 of the photonic structure interface core 701 via an electrical connection. In fact, in Figure 8 In the embodiment, the bottom surface of the photonic structure interface die 701 is electrically connected to the connection area 709 of the PIC interposer 704 .

[0091] In various embodiments, Figure 7 and Figure 8 The router 710 in each of the figures is a message router that resides partially in the PIC middleware 704 and partially in the photonic fabric interface core 701. In these embodiments, the router 710 is configured to convert optical signals into digital packets in a receiving unit and / or convert digital packets into optical signals in a transmitting unit.

[0092] By coupling with the computing element 702, the photonic fabric interface core 701 can be photonically connected (e.g., via an inter-chip or intra-chip link) to another photonic interface in another device. For example, the photonic fabric interface core 701 can photonically connect the computing element 702 to a server and / or a memory structure. In addition, although Figure 7 and Figure 8 Fiber array unit 724 is shown, but the photonic structure interface core 701 can be bidirectionally photonically connected with other devices via waveguides or other optical means. In fact, the fiber array unit facilitates bidirectional communication with connected nodes and devices (e.g., sending and receiving lasers and / or messages to photodiodes via the fiber array unit 724).

[0093] Fig. 9 The nodes of the memory structure are shown in more detail. As shown in the figure, Fig. 9A plurality of nodes are included (eg, nodes 900, 902, 904, 906, and 908), however, only node 900 is shown having internal components, elements, and connections. Thus, the description of node 900 may be applicable to the other nodes shown.

[0094] As shown, the node 900 includes various components, including a routing controller 920, a memory 922, a thermal control block 924, an electrical port 926, a message router 928, an optical port 930, a FIFO register 932, and a thermally stable optical modulation element 934. Some or all of these components have been described above. In addition, as previously described, the node 900 communicates with other nodes through one or more photon channels 940.

[0095] As shown, node 900 also includes one or more memory connection areas and / or computing connection areas (shown as connection area 912). As shown, connection area 912 includes a memory controller and / or computing controller (shown as memory / computing controller 914) and a memory and / or computing element (shown as memory / computing element 916). In various embodiments, the memory and computing connection areas receive memory elements or computing elements using standard electrical interconnect technologies (such as copper wires, bump attachment units, copper pillars, through silicon vias, etc.). In the above Figure 2 Examples of memory and / or computing elements are provided.

[0096] In one or more embodiments, the connection area 912 is coupled to a memory element (e.g., HBM) loaded with data (e.g., embedded tables) for machine learning (e.g., training and / or reasoning). For example, the circuit package is able to interact with the data in the HBM according to the requirements of the AI ​​workload it is executing. In some cases, the output of the circuit package is an optical signal converted from a digital packet, and a digital packet is formed in the core grain in response to a request for data from a computing element. In these cases, the memory structure has an inter-chip or intra-chip link to the circuit package at one of the ports of one of its external 12 nodes.

[0097] In various embodiments, a node is a destination node when it is located in a memory structure having an HBM with the requested data. In one or more embodiments, if the circuit package requests data from a destination node having a direct photonic link, a memory or compute controller (e.g., memory / compute controller 914) in node 900 is used to interact with the data.

[0098] In some embodiments, if the destination node where the data resides is not directly connected by the next FAU (or waveguide or another type of single photon link), the routing controller 920 (e.g., routing control block) in the node 900 modifies the packet and outputs the modified packet to the next node in the route toward the destination node. In these cases, the process repeats until the packet reaches the destination node, and the storage controller in the destination node can interact with the data. For example, the data in the form of an embedded table is provided to the requesting client computing device via an electrical port.

[0099] In some embodiments, node 900 also includes a computing element (e.g., a CPU, GPU, MPU, etc.). For example, interaction with the data may include using a tensor engine, a neural computing engine, and / or another type of processor in the node to perform calculations and / or convert the data. In this example, the converted data may be stored back in an HBM in a memory portion (e.g., a storage element) of connection region 912 or in another HBM in another node. In addition, this process may continue until the AI ​​workload is completed.

[0100] In various embodiments, the computing device requests data from the HGM on the server and / or converted data processed by the computing elements in the node. In these embodiments, the data is routed through a photonic interface in the node that has a direct connection to the circuit package to which the computing device is attached. For example, the data is routed from the current node to a node that shares a photonic channel with the circuit package.

[0101] In some embodiments, the request is returned to the client ASIC by retrieving the data from the HBM using the storage controller in the current node and forming a packet in the message router with routing information including data indicating the destination location. In these embodiments, the digital packet is converted into an optical signal and sent to the next node. Once routed to the destination node, the result can be sent along the photonic connection between the client computing device and the edge of the memory structure (e.g., via optical fiber and two FAUs). As previously described, when the optical signal arrives, the message router in the core can convert the result into a digital packet that can be used by the computing device.

[0102] In various embodiments, the node 900 includes a message router 928 that includes an interface having a bidirectional photon channel (not shown) via an optical port 930. In one or more embodiments, messages containing packet data arrive via the photon channel of the PIC and are received at an optical-to-electrical (OE) interface between the PIC and the message router 928. In various embodiments, as described above, the OE interface is implemented using a photodetector (e.g., a photodiode) in the PIC that converts an optical signal into an electronic signal. For example, this is done in conjunction with using associated electronic circuits in the message router 928, which may include a transimpedance amplifier (TIA), an optional gain control for normalizing signal levels, and / or a limiter for extracting a bit stream. In addition, the messages may also be buffered in electronic form in registers such as a first-in, first-out register 932.

[0103] In one or more embodiments, a routing controller 920 (e.g., a routing control block) in node 900 includes circuitry for examining received messages. For example, routing controller 920 identifies an address contained in a message header (or message payload) and determines to which port and / or destination node the message should be routed. For example, in some cases, message router 928 determines that the destination of the message is a memory 922 (e.g., a memory element in a memory connection area) on node 900. In these cases, the information is routed to electrical port 926.

[0104] In other cases, the message router 928 determines that the destination of the message is another node in the memory structure. In these cases, the message is routed to the destination node via the EO interface between the message router 928 and the PIC, where the message is converted into the optical domain for transmission via another photonic channel. In various embodiments, the EO interface is implemented using an optical modulator within the PIC and associated driver circuitry (e.g., a modulator driver) in the message router 928. Several examples of suitable modulator technologies include electro-absorption modulators (EAMs), Mach-Zehnder modulators, ring modulators, and quantum bound Stark effect EAMs (QCCE EAMs).

[0105] Fig.10 Provides more details about using the memory structure according to one or more embodiments. Specifically, Fig.10 An exemplary flow chart is shown that illustrates how data is moved in the memory structure. For ease of explanation, Fig.10 Described as a series of operations or acts 1000.

[0106] As shown, a series of actions 1000 includes an action 1010 of receiving a request in a core particle. Specifically, action 1010 may involve receiving a request in a core particle for a computation or memory controller in a destination node of a memory structure. For example, the request is a message request and / or an electrical request provided to a node in the memory structure from a computation element electrically interconnected with a circuit package including the core particle. In some cases, the core particle receives a message request from a computation element requesting access to a memory controller or a computation controller associated with a photonic interface.

[0107] As shown, a series of acts 1000 includes an act 1020 of forming a packet including the request and routing information. In some embodiments, a die of a circuit package connected to a connection region via electrical connections of an interposer forms a digital packet associated with the connection region.

[0108] In addition, the series of actions 1000 also includes an action 1030: photonically transmitting the packet as a modulated electromagnetic wave to an interface of the memory structure. For example, action 1030 may involve photonically transmitting the packet from a first optical interface of the core to a second optical interface of a node in the memory structure, the first and second interfaces being connected via optical fibers, waveguides, a mixture of optical fibers and waveguides, intra-chip or inter-chip links, other suitable optical connections and / or photon paths, or a combination thereof. For example, the packet is transferred onto an optical carrier signal by a photonic transceiver in the circuit package and transmitted to a port of the node of the memory structure connected to the circuit package. In some cases, the transmitting unit is partially in the core and partially in the interposer for optically sending / transmitting the digital packet to the photonic interface via a fiber array unit (FAU).

[0109] The series of actions 1000 also includes an action 1040 of converting the packet to digital form in an electrical port of the node. For example, the node receives the packet and converts the packet from an optical signal back to electrical form using a photonic transceiver in the node. In some cases, the routing controller sends the modified digital output to an adjacent node in the memory structure by converting the digital output to an optical signal and sending the optical signal to the adjacent node via a photonic interface of the memory structure. For example, in various cases, the receiving unit is partially in the core particle and partially in the interposer for receiving the optical signal from the FAU and providing the optical signal in digital form to the electrical portion of the core particle.

[0110] In addition, the series of actions 1000 also includes an action 1050 of determining whether the current node is a destination node. For example, a routing controller on the current node determines whether the current node is a destination for the request. If so, as shown, the series of actions 1000 includes an action 1060 of interacting with a memory or computing controller in the node. For example, an electrical port of the node is used to access a memory or interface controller associated with a memory or computing resource coupled to the node (depending on the nature of the initial request).

[0111] If action 1050 determines that the current node is not the destination node (i.e., "no"), the series of actions 1000 includes an action 1070 of modifying the packet. For example, the routing controller modifies the packet (e.g., by decrementing or changing a value in the routing information). In addition, the series of actions 1000 also includes an action 1080 of photonically transmitting the packet to the next node. For example, the electrical port sends the modified packet to the photon transceiver, converts it to an optical signal, and sends it to the next node in the memory structure. For example, the modified packet is sent along a photon link connecting the current node and the next node in the memory structure (along the path to the destination node). In addition, action 1050 is repeated until the destination node is reached.

[0112] Additional discussion of methods, apparatus, and systems (eg, thermal control systems) related to thermal control of optical components will now be provided.

[0113] As described below, the present disclosure includes a thermal control system, which includes one or more embodiments, the thermal control system includes a semiconductor having an optical layer stacked with an electrical layer, wherein the semiconductor is divided into a pure electric region and a photoelectric region. In addition, the thermal control system also includes one or more nodes in the photoelectric region, wherein each of the nodes resides in the optical layer and the electrical layer. In some embodiments, the first portion of each node resides in the optical layer and has an optical modulator or a heating element that resides in the electrical layer and radiates heat to the optical layer. The thermal control system also includes a temperature sensing region in the second portion of each node, wherein the temperature sensing region has a temperature sensor for sending a thermal signal to the pure electric region, and the thermal signal is associated with the current temperature of at least one optical modulator. In addition, the thermal control system includes a controller in the pure electric region, which has an electrical interconnection with each node, for receiving a thermal signal from the temperature sensor and sending a new voltage signal to the photoelectric region based on the thermal signal.

[0114] In some embodiments, the present disclosure includes a system-in-package (SIP) including a photonic integrated circuit (PIC), an electronic integrated circuit (EIC) having electrical connections to the PIC, a node (wherein a first portion of the node resides in the EIC and a second portion of the node resides in the PIC), a plurality of heat generating elements in the first portion of the node that radiate heat to the second portion of the node (which causes a thermal change in the second portion of the node); a plurality of optical modulators in the second portion of the node, and a temperature sensing region in the second portion of the node for sending a current temperature to a controller. In some cases, the controller sends a first signal to each of the optical modulators based on the current temperature.

[0115] In one or more embodiments, the present disclosure includes a method for controlling a thermal variable associated with a plurality of optical components. For example, the method includes applying a first signal to a positive pole of each of the plurality of optical components, and applying a second signal to a negative pole of each of the plurality of optical components. In addition, the method includes sensing a temperature of an area associated with the plurality of optical components and receiving a current temperature associated with the area. The method also includes using the current temperature to determine when to initiate thermal control of the plurality of optical components.

[0116] In various cases, when a first optical component in the optical components is an inter-chip modulator, the method includes obtaining a first voltage and sending the first voltage to an anode of the inter-chip modulator. In other embodiments, when a second optical component in the optical components is an intra-chip modulator, the method includes obtaining a second voltage and sending the second voltage to an anode of the intra-chip modulator, wherein the second voltage has a different value than the first voltage.

[0117] To further illustrate, Fig.11A Some elements and features of a portion of a system-in-package (SIP 1102) that provides a suitable environment to benefit from various embodiments are shown. For ease of reference, Fig.11A May be referred to as a multiprocessor system or SIP 1102, but in Fig.11A The various parts, components and features of SIP 1102 are not explicitly shown.

[0118] like Fig.11A As shown, SIP 1102 includes sixteen nodes 1104 arranged in a 4x4 two-dimensional grid. Each of nodes 1104 includes a heat generating element 1175 that generates heat 1180. Fig.11A1102, the number and arrangement of nodes 1104 and the type of heating elements 1175 included may vary in different embodiments of SIP 1102. In addition, SIP 1102 includes a laser light source (not shown), a photonic integrated circuit (PIC 1192), and an ASIC 1188 (e.g., a mixed signal IC). In this document, ASICs are interchangeably referred to as electronic integrated circuits (EICs).

[0119] In various embodiments, the laser light source may be implemented in the SIP 1102 or externally. When implemented in the SIP 1102, two alternative embodiments are an interposer containing several lasers that may be co-packaged with the PIC 1192 and edge-coupled to the PIC 1192, or lasers that are directly integrated into the PIC 1192 using hybrid or heterogeneous integration. Heterogeneous integration allows for lasers to be implemented directly in the silicon photonics substrate and allows for lasers of different materials such as InP (Indium Phosphide) and architectures such as quantum dot lasers. Hybrid components of lasers on the PIC 1192 may allow III-V semiconductors or other materials to be precisely attached to the PIC 1192 and coupled into waveguides implemented on the PIC 1192. If implemented externally, the connection to the SIP 1102 is made through optical coupling which may be a grating coupler and optical fiber or edge coupler.

[0120] In addition, despite Fig.11A Although not explicitly shown, SIP 1102 includes optical links and connections for one or more fiber connections. Fiber connections can be made in a variety of ways. For example, a fiber array unit is located above a grating coupler (e.g., Fig. 11B The first fiber array unit 1132a and the second fiber array unit 1132b shown in FIG. 1 ) or an edge coupler provide connection. In addition, in many embodiments, the SIP 1102 has the function of a network on chip (NOC), especially a hybrid optoelectronic network on chip (EP-NOC).

[0121] Fig. 11B A side view of the SIP 1102 is depicted and indicates an assembly format using one embodiment of a grating coupler and fiber array unit discussed further below. Note that Fig.11A 11. The ASIC 1188 and portions of the PIC 1192 used in the SIP 1102 are generally shown, and Fig.11A The optical coupler and laser light source are omitted ( Fig. 11B An omitted portion of SIP 1102 is shown).

[0122] In various embodiments, PIC 1192 provides a photonic network for interconnecting some electronic components on ASIC 1188, etc. (while some other electronic components on ASIC 1188 are electrically interconnected). Fig. 11B As shown, the electronic components of ASIC 1188 include heat generating elements 1175 that radiate heat 1180. Heat 1180 may be radiated through PIC 1192, which may cause changes in the thermal characteristics of PIC 1192. In various cases, this may occur while ASIC 1188 is executing a computing process or otherwise operating under load, performing calculations, and / or otherwise operating as intended.

[0123] In many cases, heat 1180 affects the performance of optical components in PIC 1192. For example, the optical components in PIC 1192 are sensitive to temperature changes that affect their operating characteristics. In addition, the optical components in PIC 1192 are directly coupled to ASIC 1188 in a chip-to-chip manner without using an interposer or having another means for dissipating heat over distance.

[0124] Thus, the current embodiments can stack the heat generating elements 1175 with minimal distance or spacing (typically in the micrometer range) between the optical components. The benefits of the chip-to-chip connection of the SIP 1102 include reduced latency at the expense of increased heat in the optical components. This creates an example environment suitable for various embodiments, as they would benefit from thermal control of the optical components in the PIC 1192 to maximize and / or optimize the performance of the SIP 1102. Fig.18A , Fig.18B and Fig.19 Additional details are provided regarding thermally stable optical modulators (eg, electroabsorption modulators) that operate efficiently over a range of temperatures.

[0125] As shown, the PIC 1192 includes a first fiber array unit 1132a that sends and receives optical data from a first optical fiber 1133a, and a second fiber array unit 1132b that also sends and receives optical data from a second optical fiber 1133b. For example, the first optical fiber 1133a is connected to a first node, and the second optical fiber 1133b is connected to a second node.

[0126] According to various embodiments, the heating element 1175 includes, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), a memory unit, a memory controller, a message router, a tensor engine, a digital neural network (DNN), a field programmable gate array (FPGA), and a general processing element. In some embodiments, the semiconductor may include an optical layer stacked with an electrical layer.

[0127] In many cases, both electrical signal routing and photon signal routing are used. Signal routing tasks are distributed between electrical (or electronic) paths and photon paths in different ways as described below. For example, in the present disclosure, several processors are interconnected (e.g., interconnected chip to chip or SIP to SIP) to produce a single system called an accelerator or multi-processor system. The photonic network within several processors and the optical connections, laser light sources, passive optical components, and external optical fibers on a printed circuit board (PCB) (which can be used in various combinations and configurations with other photonic elements) form the photonic structure of the accelerator and interconnect multiple processors.

[0128] Apart from Fig.11A and Fig. 11B In addition, Fig.12 An exemplary node including a heating element that can be used in a photonic structure according to one or more embodiments disclosed in the present disclosure. As shown in the figure, Fig.12 Many of the previously introduced components are included, such as node 1104 of SIP 1102, PIC 1192, heating element 1175, ASIC 1188 and their corresponding components. Additional description of the components of ASIC 1188 is provided below.

[0129] For illustration purposes, Fig.12 Node 1104 in includes DNN 1106. For example, DNN 1106 resides in ASIC 1188 and is implemented in electronic form. In some embodiments, DNN 1106 performs a convolution function or a dot product function as required by the neural network of the accelerator (such as part of the inference calculation performed by the accelerator). The multi-processor system of SIP 1102 (including DNN 1106) is a suitable configuration for various embodiments and is only for illustrative purposes and is not required. In fact, various embodiments are suitable for various environments including optical components (such as those configured for general purpose computing) that are tightly coupled to heating elements and / or EP-NOC.

[0130] like Fig.12 (and Fig.11A) As further shown, node 1104 includes a tensor engine 1108, a message router 1110, a first-level SRAM (L1SRAM 1112), and a second-level SRAM (L2SRAM 1114). In various embodiments, L1SRAM 1112 is used as a scratch pad memory for each node in node 1104, while L2SRAM 1114 has the function of a main memory for each node in node 1104 and can be physically close to DNN 1106 and tensor engine 1108 to store the weights of the machine learning model. L2SRAM 1114 can also store intermediate results that may be needed to execute the machine learning model. In one embodiment, L1SRAM 1112 is optional. In some cases, weights are used in each layer of the neural network within each SIP 1102. This can include performing inference calculations. Each layer of the neural network can be implemented by multiple nodes in node 1104 in SIP 1102, wherein each of node 1104 includes one or more neural nodes or neurons.

[0131] While operating, as the neural network processes data and / or performs more computationally intensive tasks, components of ASIC 1188 generate heat. For this purpose, DNN 1106, tensor engine 1108, message router 1110, L1SRAM 1112, and L2SRAM 1114 are referred to as heat generating elements 1175. Whether in an AI accelerator or a general purpose computer, these heat generating elements 1175 can be configured in any number of configurations suitable for ASIC 1188, which also generates heat during normal operation.

[0132] Back to Fig.11A , SIP 1102 includes optional elements such as bus interface 1122, CPU / GPU 1124, and memory controller 1126. For example, bus interface 1122 is a peripheral component interconnect express (PCIE) interface. CPU / GPU 1124 can be an advanced reduced instruction set RISC machine (ARM) core, image processor or other processing element. The external memory controller can support DRAM, NVRAM, SRAM or other types of memory.

[0133] In various embodiments, bus interface 1122 enables electrical interconnection between SIP 1102 and external components. Specifically, weights stored in L2SRAM 1114 are received from external components (such as dynamic random access memory (DRAM)) via bus interface 1122. CPU / GPU 1124 can interface with a storage device (not shown), which can be external to SIP 1102 and can process image data or perform other computing tasks. Memory controller can interface with high bandwidth memory (HBM 1189, such as Fig. 11B ), which may be external to SIP 1102 or integrated into SIP 1102. Other forms of memory, such as non-volatile memory, may be attached in a similar manner using corresponding memory controllers in the block.

[0134] In one or more embodiments, thermal controller 1128 includes one or more control circuits having electrical connections to PIC 1192 to take one or more actions and / or send one or more signals to PIC 1192. This may be, for example, in response to thermal characteristics and / or thermal changes in PIC 1192, where the signals that thermal controller 1128 may send are configured to alter operating characteristics of one or more of the optical components of PIC 1192 and / or to counteract thermal changes occurring in PIC 1192. This may typically occur when there is a change in thermal characteristics in PIC 1192 that requires some action to continue operating the optical components in a more efficient and / or enhanced manner.

[0135] Refer to Fig.12 In one or more embodiments, a message containing packet data arrives via a photonic network located on the PIC 1192 and is received at an optical / electrical interface 1134. In some embodiments, the optical / electrical interface 1134 is a photodiode or related circuitry, wherein at least a portion of the photodiode or related circuitry resides in the ASIC 1188. In various embodiments, the message is buffered electronically in a register such as a FIFO register 1136 (a "first in, first out" register). In addition, the address contained in the message header is then checked by the message router 1110, and the message router 1110 (e.g., an electronic message router) determines to which port and to which destination the message should be routed. For example, the message is routed to a destination node via the electrical / optical interface 1138, which may be a driver of an optical component, such as an optical modulator (not shown).

[0136] In the current example, the optical modulator (not shown) is close to but typically stacked below or above the driver in the electrical / optical interface 1138. For example, the stacking distance of the optical modulator from the driver in the electrical / optical interface 1138 is measured in microns.

[0137] In various embodiments, the coupling proximity between the optical modulator and the driver in the electrical / optical interface 1138 and the heat generated by the heat generating element 1175 produces radiation that changes the thermal environment of the optical components in the PIC 1192 .

[0138] about Fig.12, the optical components are not visible because they are obscured and / or stacked below the optical / electrical interface 1134 and the electrical / optical interface 1138 in the ASIC 1188. For example, a portion of the optical components stacked below the electrical / optical interface 1138 include various optical modulators. Examples of suitable modulator technologies include electro-absorption modulators (EAMs), including quantum confined Stark effect (QCSE) EAMs, or other modulators with optical absorption properties that vary depending on the thermal properties of the modulator's operating environment.

[0139] Fig.13A A cross-sectional view showing a portion of SIP 1102, Fig. 13B A top view of a portion of a SIP 1102 is shown, which may be used to thermally control one or more optical components according to various embodiments. Fig.13A , ASIC 1188 is shown as being located above or stacked on PIC 1192. Examples of nodes 1304a, 1304b, 1304c, and 1304d in ASIC 1188 are shown, and modulator drivers 1341a, 1341b, and 1341c are located in nodes 1304a, 1304b, and 1304c, respectively (e.g., ASIC nodes). Transimpedance amplifiers (TIAs 1342b, 1342c, and 1342d) are located in nodes 1304b, 1304c, and 1304d, respectively (e.g., ASIC nodes). Optical modulators 1345a, 1345b, and 1345c are fabricated in PIC 1192 and are located directly below respective instances of modulator drivers 1341a, 1341b, and 1341c.

[0140] Additionally, there are photodetectors (e.g., PDs 1346b, 1346c, and 1346d) located directly below respective instances of TIAs 1342b, 1342c, and 1342d in PIC 1192. Optical links (such as waveguides 1343ab, 1343bc, and 1343cd) provide optical pathways in PIC 1192 that are part of a photonic network for intra-chip communication between nodes 1304a, 1304b, 1304c, and 1304d within SIP 1102.

[0141] also, Fig.13A Optical coupling involves establishing connections between nodes. Optical coupling can be achieved using edge coupling, or as Fig.13A As shown, optical coupling is achieved using a fiber array unit 1132 (FAU) and optical fiber 1133 located above the PIC 1192 and providing optical input to a grating coupler 1340 in the PIC 1192. The optical fiber 1133 can be connected to an off-chip laser light source and / or a FAU of another processor that will provide optical input to the PIC 1192.

[0142] Each of the optical modulators 1345a, 1345b, and 1345c can be an optical modulator of a first optical component type 1395 or a second optical component type 1396, where the type depends on its location in the system topology. For example, a first optical component type (e.g., associated with optical modulators 1345b and 1345c) has a connection inside the PIC 1192 and is routed through a waveguide in the PIC 1192 (e.g., on-chip modulation). As shown, optical modulators 1345b and 1345c are first optical component type 1395. In addition, optical modulators of a second optical component type 1396 are edge or corner optical modulators that are (at least partially) coupled to the fiber array unit 1132 (e.g., inter-chip modulation). As shown, optical modulator 1345a has a second optical component type 1396.

[0143] In many embodiments, the differences in the hardware used to couple the first and second optical modulator types result in different thermal requirements for the two optical modulator types to operate optimally. For example, an inter-chip modulator receives and / or absorbs more light than an on-chip modulator and operates under hotter conditions when operating normally. This is (in part) because the laser light is multiplexed together on the fiber array unit 1132, so the inter-chip modulator (e.g., optical modulator 1345a) receives and / or absorbs more light than the on-chip modulator (e.g., optical modulators 1345b and 1345c). Therefore, the inter-chip controller 1300 and the on-chip controller 1305 can be used in the ASIC 1188 to operate on two different types of optical modulators (e.g., the first optical component type 1395 and the second optical component type 1396) residing in the SIP 1102.

[0144] In one or more embodiments, the laser light source may be an on-chip laser light source as described above. For example, the laser light need not be provided by the fiber array unit 1132. In various embodiments, the optical link (such as waveguide 1344 and Fig.13A Additional waveguides (not visible in the cross-sectional view) supply light received by the grating coupler 1340 to optical modulators 1345a, 1345b, and 1345c located on the PIC 1192. Although the connections between the grating coupler 1340 and the other connections between the optical modulators 1345b and 1345c are Fig.13A These connections are not explicitly shown in Fig. 13B It is shown in Fig.13A yes Fig. 13B Cross-sectional view of a portion of.

[0145] like Fig. 13BAs shown, waveguide 1344 brings the laser light source from the fiber array unit 1132 through the optional beam splitter 1347 to the beam splitter 1382a ( Fig.13A From the optical splitter 1382a in the node 1304a, one optical path is provided to the optical modulator 1345a, while another optical path is provided to the optical splitter 1382b in the node 1304b through the continuation of the waveguide 1344 ( Fig.13A From the optical splitter 1382b in the node 1304b, one optical path is provided to the optical modulator 1345b, while another optical path is provided through the continuation of the waveguide 1344 to the optical modulator 1345c in the node 1304c.

[0146] Fig. 13B Also shown are top views of waveguide 1343ab connecting optical modulator 1345a to PD 1346b, waveguide 1343bc connecting optical modulator 1345b to PD 1346c, and waveguide 1343cd connecting optical modulator 1345c to PD 1346d. Fig. 13B The top view corresponds to Fig.13A In addition to the corresponding cross-sectional diagram Fig.13A In addition to the contents shown in the cross-section diagram, Fig. 13B A top view of other optical paths in PIC 1192 is shown as another example of optical connections between various nodes in SIP 1102.

[0147] In various embodiments, such as Fig.13A and 13B As shown, ASIC 1188 is electrically coupled to PIC 1192 and includes thermal controller 1128. For example, thermal controller 1128 includes inter-chip controller 1300 (e.g., inter-chip thermal controller), intra-chip controller 1305 (e.g., intra-chip thermal controller), DC bias signal 1310, and AC swing signal 1330. In various embodiments, DC bias signal 1310 has an electrical connection 1370 to a positive terminal of one of the optical modulators.

[0148] In one or more embodiments, electrical connection 1370 is implemented with a through silicon via (TSV), a wire, or another suitable electrical connection capable of transmitting a voltage signal to the positive terminal of one of the optical modulators. In some cases, AC swing signal 1330 has an electrical connection 1375 to the negative terminal of one of the optical modulators. Additionally, in various embodiments, electrical connection 1375 is implemented with a TSV, a wire, or another suitable electrical connection capable of transmitting a voltage signal to the negative terminal of one of the optical modulators.

[0149] In many embodiments, for node-to-node communication between the first node and the second node, streaming of activations from the first node in the first SIP to the second node in the second SIP is performed using a photonic network in the PIC 1192 using optical components including modulators and photodetectors located just below the corresponding modulator drivers and TIAs on the ASIC 1188. Typically, the optical modulators and photodetectors are connected by optical pathways (e.g., waveguides) on the PIC 1192. Thus, in many cases, most or all of the node-to-node communication is not performed electronically in the ASIC 1188, but rather optically by the photonic network provided by the PIC 1192.

[0150] Furthermore, in various embodiments, on-chip optical communication is typically performed using a single wavelength of light. However, in some embodiments, on-chip optical communication is performed using multiple wavelengths of light.

[0151] Fig.14 A cross-sectional view of a portion of an exemplary SIP illustrating thermal management of an optical component according to embodiments disclosed herein. Fig.14 An exemplary node with previously introduced components is shown. For example, Fig.14 An ASIC 1188 is included having nodes 1304a, 1304b, and 1304c, with modulator drivers 1341a, 1341b, and 1341c located in respective nodes. As shown, optical modulators 1345a, 1345b, and 1345c are located directly below respective instances of modulator drivers 1341a, 1341b, and 1341c.

[0152] As shown, temperature sensors 1400, 1401, and 1402 are associated with optical modulators 1345a, 1345b, and 1345c. For example, each of temperature sensors 1400, 1401, and 1402 is capable of monitoring the temperature of a corresponding instance of optical modulator 1345a, 1345b, and 1345c and is correspondingly positioned in PIC 1192. In some embodiments, optical modulators 1345a, 1345b, and 1345c typically have a wide operating thermal range (e.g., a difference of a few degrees Celsius will have minimal impact on the performance of optical modulators 1345a, 1345b, and 1345c).

[0153] In some cases, the optical modulators 1345a, 1345b, and 1345c are manufactured to operate when the ambient temperature is at a maximum specified temperature and / or the ASIC 1188 is fully throttled to maximum power (e.g., all nodes 1304a, 1304b, and 1304c are performing at maximum load). When the ASIC 1188 is throttled, the ambient temperature may decrease and the optical modulators 1345a, 1345b, and 1345c will no longer operate optimally. In this case, taking corrective action on the thermal environment of the optical modulators 1345a, 1345b, and / or 1345c may help restore them to an optimal performance state.

[0154] In operation, the ASIC 1188 uses the optical modulators 1345a, 1345b, and 1345c to optically encode bits to transmit them photonically to a destination. For example, the following scheme is implemented to control the behavior of the optical modulators 1345a, 1345b, and 1345c to achieve consistent performance regardless of the thermal impact of the ASIC 1188. For example, an AC swing signal (e.g., a swing of + / -.9 volts) from the AC swing signal 1330 is applied to the optical modulators 1345a, 1345b, and 1345c at a first terminal. A DC bias signal from the DC bias signal 1310 is applied to a second terminal of the optical modulators 1345a, 1345b, and 1345c.

[0155] In some cases, applying a positive or negative 0.9 voltage swing signal (or other swing signals depending on how the optical modulators are constructed) from AC swing signal 1430 causes the optical modulators 1345a, 1345b, and 1345c to swing between 0.1 and -1.9 volts when combined with a default negative 1 volt DC signal (e.g., a negative DC bias voltage) sent from DC bias signal 1310. When the system is operating, thermal energy can be transferred from ASIC 1188 to PIC 1192. When ASIC 1188 is powered down, some portion of ASIC 1188 is idle, and / or the load on ASIC 1188 changes during the execution of a process, the temperature associated with optical modulators 1345a, 1345b, and 1345c also changes. Temperature sensors 1400, 1401, and 1402 continuously monitor the respective instances of optical modulators 1345a, 1345b, and 1345c. The outputs of the temperature sensors 1400 , 1401 , and 1402 are sent to the controller 1420 .

[0156] In various embodiments, the controller 1420 is a software, hardware, or firmware module (or any combination of software, hardware, or firmware modules) that implements logic capable of determining when a thermal variable (e.g., heat) deviates from an optimal range. For example, the controller 1420 utilizes a lookup table, accesses a database, uses an activation function to calculate a value, or uses some other tool in the bias determination module 1440 to determine when and how much voltage to apply to the optical modulators 1345a, 1345b, and 1345c via the DC bias signal 1310. As the temperature of the PIC 1192 changes, the temperature sensors 1400, 1401, and 1402 continue to send relevant signals to the controller 1420. Once the thermal threshold deviates sufficiently and / or the thermal condition of the optical modulators 1345a, 1345b, and 1345c requires intervention, the controller 1420 sends an output to the DC bias signal 1410 (which may cause the DC bias signal 1410 to send a different bias signal (corresponding to a different value) than the default -1 volt signal). In response, DC bias signal 1410 outputs a new bias signal and provides it as input to optical modulators 1345a, 1345b, and 1345c, thereby altering their performance.

[0157] In one or more embodiments, the new DC bias signal is obtained by the bias determination module 1440 using a table, a database, or another suitable data structure. In these embodiments, when a table is used, the table may have multiple rows and multiple columns, wherein each row has at least a first column representing a temperature and a corresponding second column representing one or more associated voltage values. The bias determination module 1440 may be used to locate, select, or otherwise determine a row corresponding to the current temperature in the table, and select, access, or otherwise obtain a corresponding new DC bias voltage signal in an associated column of the row. For example, the bias determination module 1440 uses the current temperature received from the temperature sensors 1400, 1401, and 1402, and compares the current temperature with each row in the table until a match is found. On this basis, a new voltage may be obtained by accessing an associated column having a new voltage value in the selected row. This may generate a new voltage signal, which may be sent to the photovoltaic region.

[0158] In some embodiments, the bias determination module 1440 is used to apply the current temperature to an activation function, which can calculate a product and / or multiply the current temperature by the activation function to obtain the current voltage required to be used as a new DC bias signal. For example, if the new DC bias voltage signal obtained by the bias determination module 1440 is -2 volts, the new swing signals of the optical modulators 1345a, 1345b, and 1345c will be between -2.9 volts and -1.1 volts. It should be noted that the value of the DC bias signal sent from the DC bias signal 1310 is only for exemplary purposes.

[0159] Furthermore, the DC bias signal 1410 may differ in various embodiments depending on the nature of the system, how the optical components are constructed, the type of loads the ASIC 1188 is expected to be used with, etc. For example, the amount of heat generated by the ASIC 1188, the thermal environment of the computing device including the optical components, the type of application using the computing system, the type of optical components, and other factors determine what value the DC bias signal 1410 should send, as well as what type of activation function, database, or lookup table the bias determination module 1440 utilizes, and the actual values ​​contained therein.

[0160] Typically, when the temperature decreases, the bias signal sent by the thermal signal block can be applied to cause the optical modulators 1345a, 1345b, and 1345c to absorb more light sent through the optical fiber 1133 or transmitted by the waveguide. Similarly, when the temperature increases, the bias signal sent by the thermal signal block can be changed to cause the optical modulators 1345a, 1345b, and 1345c to absorb less light sent through the optical fiber 1133 or transmitted by the waveguide. In this way, DC voltage control can be used to compensate for temperature drift. Therefore, when the controller 1420 takes measures related to thermal conditions and / or otherwise provides input to the optical modulators 1345a, 1345b, and 1345c, the temperature range of the optical modulators 1345a, 1345b, and 1345c can be extended by changing the DC bias via the DC bias signal 1410.

[0161] Fig.15 Another top view of an exemplary SIP (e.g., SIP 1102) having the ability to thermally control optical components according to various embodiments is shown. Fig.15 In the arrangement of FIG. 1 , the PIC 1192 is stacked with the ASIC 1188 having the purely electrical portion 1570 and the optoelectronic portion 1575. The PIC 1192 can be divided into a purely electrical region and an optoelectronic region. The purely electrical portion 1570 of the ASIC 1188 generally corresponds to a processing area that does not rely on photonic elements (stacked heating elements, adjacent to heating elements, and / or directly below heating elements) in the PIC 1192. Therefore, the purely electrical portion 1570 does not need to have thermal control in this area.

[0162] In various embodiments, the purely electrical portion 1570 includes an AC swing signal 1530, a controller 1520, and a DC bias signal 1510. In some cases, these blocks (e.g., the DC bias signal 1510, the controller 1520, and the AC swing signal 1530) use a CPU or other suitable processor and / or memory (not shown) in the region. In addition, for example, the controller 1520 can be a single unit or multiple controllers or control circuits and include the ability to control an optical modulator of a first optical component type 1395 using an on-chip controller 1305 and / or an optical modulator of a second optical component type 1396 using an inter-chip controller 1300.

[0163] like Fig.15 As shown, as previously described, the optical modulator of the first optical component type 1395 includes only optical connections to other neighborhoods within the node 1104 and is referred to as an on-chip optical component. Also as previously described, for example, the optical modulator of the second optical component type 1396 includes an optical connection to the edge of the node 1104, via the FAU to other chips and / or nodes. In various cases, the optical modulators of the first optical component type 1395 and the second optical component type 1396 are independently controlled by the same controller or different controllers (e.g., controller 1520).

[0164] In many cases, even when thermal conditions are the same in the relevant temperature sensing regions, the changes in the DC bias signal 1510 caused by the inter-chip controller 1300 or the intra-chip controller 1305 are typically different because the hardware providing inputs to the optical modulators of the first optical component type 1395 and the second optical component type 1396 is different. In the current example, each node has 16 EAMs, 8 of which are the first optical component type 1395 and 8 of which are the second optical component type 1396. In addition, the purely electrical portion 1570 includes communication couplings (electrical or optical couplings or both) with the two optical modulator types in the optoelectronic portion 1575 of the ASIC 1188. In this embodiment, each ASIC 1188 has 1256 EAMs, but this is not required. Other arrangements may also be used in other embodiments.

[0165] Each node also includes a temperature sensing region 1580. As shown, the PIC 1192 has sixteen instances of the temperature sensing region 1580, each instance including an optical modulator of the first optical component type 1395 and the second optical component type 1396. Typically, the spacing of the optical modulators of the first optical component type 1395 and the second optical component type 1396 is measured in millimeters or fractions of millimeters, so the temperature differences between the individual optical modulators in each node are not very different.

[0166] In some embodiments, instead of sensing the temperature at each of the optical modulators, the bias signals of sixteen optical modulators are adjusted at a time in each node (new bias signals for the inter-chip optical modulators of the first optical component type 1395 and new bias signals for the intra-chip optical modulators of the second optical component type 1396), instead of a high-resolution temperature sensor.

[0167] In some embodiments and where applicable, such as Fig.15 In the embodiment of the present invention, each of the optical components can have an associated temperature sensor. In addition, the temperature sensing area can be advantageously located on the node by utilizing the available area on the chip. To this end, the instance of the temperature sensing area 1580 does not have to be centered in the node and can be offset from the center depending on other components of the node (which also reside on the node). Fig.15 As shown, the temperature sensing region is off-center and therefore not equidistant from the four corner modulators of node 1104 .

[0168] In operation, a default version of the AC swing signal 1530 is provided at the negative pole of each of the 1256 optical modulators (e.g., the first optical component type 1395 and the second optical component type 1396) on the PIC 1192. In various embodiments, each of the 1256 optical modulators is also provided at the positive pole by the DC bias signal 1510. This produces a default action for all optical modulators 1 on the PIC 1192, enabling them to encode bits and otherwise perform photonic processing of data or packets in a typical manner.

[0169] In fact, each of the sixteen instances of temperature sensing region 1580 has an associated temperature sensor placed within that region. Each of the temperature sensors sends an output to controller 1520 in the form of data representing the current temperature in that particular instance of temperature sensing region 1580. Thus, controller 1520 of the current embodiment periodically receives sixteen signals regarding the current temperature in each instance of temperature sensing region 1580.

[0170] In various embodiments, controller 1520 includes inter-chip controller 1300 and intra-chip controller 1305. For example, inter-chip controller 1300 is configured to control thermal characteristics of an optical modulator of second optical component type 1396. In some cases, intra-chip controller 1305 is configured to control thermal characteristics of an optical modulator of first optical component type 1395. For example, assume that node 1104 sends data to controller 1520 from a temperature sensor in its temperature sensing area. In addition, controller 1520 uses bias determination module 1540, which is optionally coupled to database 1595 or other data storage.

[0171] In some embodiments, the bias determination module 1540 uses the current temperature received from the temperature sensing area 1580 of the node 1104 to determine whether an optical modulator (e.g., the first optical component type 1395 and / or the second optical component type 1396) needs to have a modified bias signal to maximize its performance according to the current thermal conditions. The bias determination module 1540 can use the database 1595 to access a table or other data structure that matches the temperature to a new bias signal for each of the first and second types of optical modulators.

[0172] In some embodiments, any suitable function or linear transformation may be used where the product of the current temperature and the activation value produces a new bias value. Then, once the new bias value is obtained from the bias determination module 1540, the inter-chip controller 1300 sends the new voltage value to the anode of each of the optical modulators of the second optical component type 1396. Similarly, the intra-chip controller 1305 sends the new voltage value to the anode of each of the optical modulators of the first optical component type 1395. Thereafter, the process repeats as the SIP 1102 operates as expected.

[0173] Fig.16 1 is a flow chart illustrating operations involved in thermal control of an optical component according to one embodiment. At operation 1600, an AC swing signal associated with the optical component is applied at a first terminal of each of the optical components in the EP-NOC. At operation 1610, a default DC bias signal associated with the optical component is applied to a second terminal of each of the optical components in the EP-NOC. In one embodiment, operations 1600 and 1610 include applying a high speed AC signal at a negative pole of each of the optical components and applying a default DC bias of a negative voltage at a positive pole of each of the optical components. In this example, the result of operations 1600 and 1610 causes the optical component to alternate between 0.1 and -1.9 volts when encoding a bit according to the applied signal.

[0174] In operation 1620, a temperature is sensed in a temperature sensing region of the EP-NOC associated with an optical component. This can include, for example, an EP-NOC having sixteen nodes / chips and sixteen optical components / nodes. In some embodiments, the temperature sensing region is located in association with the sixteen optical components of each region, but it is not necessary to place it at the same distance from each of the optical components. In some embodiments, other configurations can also be used. The temperature sensor can be any device suitable for this purpose, but because the spacing between optical modulators is relatively small, resulting in minimal temperature differences within a given node, some systems can save cost by using a less accurate temperature sensor.

[0175] In operation 1630, a signal associated with the sensed temperature is sent to a controller. In one embodiment, the controller can be implemented with a processor (such as an ARM or another series of CPUs) that is independent of the node of the photonic structure. For example, the signal represents the current temperature of the temperature sensing area. In operation 1640, the controller determines whether thermal control is required in the node based on the data received from the temperature sensing area. For example, the controller determines when to start thermal control of the optical component. For example, this can include using a bias determination module that utilizes a database, a data structure, a lookup table, and / or uses an activation function to determine whether the current temperature has a value assigned to a DC bias voltage that is different from the default DC bias voltage sent in operation 1610.

[0176] In operation 1650, if thermal control is required, a new voltage is obtained based on the current operating temperature of the temperature sensing region in operation 1660. In operation 1670, the new voltage is sent to the second terminal of the optical component associated with the temperature sensing region. If thermal control is not required in operation 1650 or after sending the new voltage in operation 1670, the process is repeated in operation 1620. The SIP continues to repeat these operations as long as there is a load applied to the ASIC in the SIP and / or the system operates as expected.

[0177] Fig.17 17 is a flow chart illustrating operations involved in thermal control of an optical modulator according to another embodiment. At operation 1700, an AC swing signal associated with an EAM is applied at a negative electrode of each of the EAMs in one node, a portion of the nodes, or all of the nodes in the EP-NOC. At operation 1705, a default DC bias signal associated with an EAM is applied at a positive electrode of each of the EAMs in one node, a portion of the nodes, or all of the nodes in the EP-NOC.

[0178] At operation 1710, a temperature is sensed in a temperature sensing region of the EP-NOC associated with the node where the EAM resides. The temperature sensor may be any device suitable for this purpose, and different resolutions are possible. At operation 1715, a signal associated with the sensed temperature is sent to a controller. In one embodiment, the controller may be in a purely electrical portion of the EP-NOC where the ASIC is stacked with the PIC, but there are no interconnected optical components in this region, so thermal control is not required. The purely electrical region may have electrical interconnection via the ASIC to a hybrid optoelectronic region where the analog components of the ASIC are stacked on top of portions of the PIC with optical components that may benefit from thermal control.

[0179] In operations 1720 and 1725, the controller determines whether thermal control is needed in the relevant nodes based on the data received from the temperature sensing area. For example, this can include determining that the inter-chip EAM, the intra-chip EAM, or both should be adjusted. Typically, the inter-chip and intra-chip EAMs have different hardware to support their operation. For example, compared with the intra-chip EAM, the inter-chip EAM can receive light with a smaller degree of separation and higher power. This difference usually causes different thermal signals to be sent to the two types of optical components when determining that the signal should be sent.

[0180] At operation 1730, the controller determines whether the inter-chip EAM requires thermal-based adjustments. If so, a new voltage is obtained at operation 1735 based on the current operating temperature in the temperature sensing region and the associated new bias signal that needs to be added to the inter-chip EAM based on the current thermal conditions. At operation 1740, the new voltage is sent to the positive electrode of the inter-chip EAM in the relevant temperature sensing region.

[0181] If the inter-chip EAM does not require thermal regulation at operation 1730 or after operation 1740, the controller determines whether the intra-chip EAM requires thermal-based regulation at operation 1745. If so, a new voltage is obtained at operation 1750 based on the current operating temperature of the temperature sensing region and the associated new bias signal that needs to be added to the intra-chip EAM based on the current thermal conditions.

[0182] At operation 1755, a new voltage is sent to the positive terminal of the on-chip EAM in the relevant temperature sensing region. Thereafter, or if at operation 1745, the on-chip EAM does not require thermal regulation, the process repeats at operation 1710. The SIP will continue to repeat these operations whenever there is a load applied to the ASIC in the SIP and / or the system is operating as expected.

[0183] As described herein, the present EP-NOC includes a novel scheme for controlling the thermal characteristics of one or more optical modulators in a receiving unit of the EP-NOC. In fact, the present document describes an EP-NOC that significantly improves the performance of a receiving unit.

[0184] Additional discussion will now be provided regarding the following items: devices, systems and methods for electro-absorption modulators (EAMs) that can provide stable operation over a wide modulation temperature range for optical components of computing devices. As described above, EAMs are semiconductor-based optical modulators that are typically used to control light sources using voltage. For example, EAMs use low voltage amounts to modulate laser beams. As previously described, EAMs are based on utilizing the Franz-Keldyshe effect to achieve electrically induced changes in optical absorption.

[0185] Depending on the context, heat generating electronic components in an ASIC vary widely in the amount of heat they generate under different loads. The optical modulation element in a PIC is designed to operate within a limited temperature range. The widely varying heat of the electronic components directly coupled to the optical modulation element has an impact that makes it an important consideration when designing optical components in a PIC that meet the required operating parameters and remain reliable under these conditions.

[0186] This becomes even more important in the context of photonic structures, where thousands of electronic components are in close proximity (e.g., within 50 microns) of corresponding optical modulation elements. While enabling direct coupling between electronic components and optical modulation elements has huge advantages in terms of computing speed and energy efficiency, varying levels of thermal impact on the PIC can also be a disadvantage.

[0187] In fact, the photonic structure is designed to have an optical modulation element that can operate efficiently within a temperature range that is consistent with the temperature range experienced by the ASIC when operating at or near maximum load. Likewise, when operating at a lower load, the amount of heat generated by the ASIC that affects the PIC is smaller, and the temperature is lower in the area where the optical modulation element operates. Therefore, it is important to have an optical modulation element that is also efficient under these lower temperature conditions.

[0188] In detail, the material and type of optical modulator used should take into account the expected temperature conditions in the PIC. The optical modulator should also take into account the temperature fluctuations indirectly caused by the idle ASIC, as well as other characteristics of the system that can cause changes in the thermal working environment of the optical modulation element. Therefore, the EAM described in this article takes these factors into account and works efficiently within a wide operating range.

[0189] In various embodiments, in order to achieve stable operation over a wide temperature range, the EAM is made of bulk semiconductor material. For example, the EAM is made of one or more materials such as pure germanium or silicon (or their alloys), or various so-called III-V materials, which mainly include indium phosphide (InP) or gallium arsenide (GaAs) material systems.

[0190] As previously mentioned, one use case for employing thermally stable optical modulation elements is to accommodate operation over a wide temperature range. Another use case includes situations involving high optical modulation amplitude (OMA) outputs, which are typical in a narrower operating range, while still being thermally stable. Optical modulation elements designed to operate over a wide temperature range typically operate in a range exceeding 30 degrees Celsius (but optical modulation elements with a narrower operating range are also feasible). Optical modulation elements designed for high OMA outputs typically operate in a range less than 30 degrees Celsius (but optical modulation elements with a wider operating range are also feasible).

[0191] As described above, the present disclosure depicts EAMs that operate over a wide temperature range. In some embodiments, the EAMs are based on a quantum confinement architecture and achieve enhanced performance in terms of higher OMA output of the EAM over a narrow temperature range. For example, EAMs based on the quantum confinement Stark effect (QCSE) achieve these results, particularly when fabricated for bulk semiconductor materials (e.g., alloys of germanium and silicon and alloys using III-V materials based on the indium phosphide and gallium arsenide systems).

[0192] In various embodiments, the EAM disclosed in this document utilizes a thermal control loop that applies a voltage (bias voltage) to the optical modulation element in response to changing thermal conditions in the PIC. In this manner, the voltage application causes the optical modulation element to operate at a thermal temperature condition close to that which it may experience under maximum load, even if the actual temperature in that region is lower and / or outside the normal thermal range of the optical modulation element (e.g., no voltage signal is provided). Furthermore, even though the temperature conditions may have exceeded the operating range of the device, the temperature range of the optical modulation element is extended via the increased voltage.

[0193] In some embodiments, the thermally stable optical modulator operates within a temperature range greater than 30 degrees Celsius. For example, the thermally stable optical modulator is an EAM that is approximately 50 microns in size and operates at a data rate between 50-115 Gbps and a power of less than 1.0 volt. In these embodiments, the EAM implements silicon photonic packaging that directly connects processors, ASICs, and memory chips. In addition, the EAM also provides optical connections within the chip and between chips. In addition, in one or more embodiments, the EAM (i.e., thermally stable optical modulator) has stable operating performance while also having a narrow (or quite narrow) operating range, which can be further increased by a thermal control loop.

[0194] In various embodiments, the EAM (i.e., thermally stable optical modulator) operates within a temperature range of less than 30 degrees Celsius. For example, as described above, the EAM is based on a quantum confinement architecture. In these cases, a higher optical OMA output from the EAM is used within a narrower temperature range (e.g., less than 30 degrees Celsius) to achieve higher performance. In addition, as described above, in some of these embodiments, the EAM is made of (e.g., composed of) a material selected from germanium, silicon, an alloy of germanium, an alloy of silicon, an InP-based III-V material, and / or a GaAs-based III-V material.

[0195] As described above, in some embodiments, an EAM (i.e., a thermally stable optical modulator) uses the quantum confined Stark effect (QCSE) for electrically induced changes in optical absorption. In this way, the EAM outputs a higher optical modulation amplitude. For example, the EAM utilizes a QCSE modulator with a high OMA to achieve a wide operating range or a substantially wide operating range, which can be further enhanced by a thermal control loop.

[0196] Additional details are now provided about the environment in which the EAM operates. More specifically, the embodiments described in this document relate to chip hardware that includes features and functions that provide one or more thermally stable optical modulation elements coupled to one or more electronic components. In one or more embodiments, the hardware is a device that includes an electronic integrated circuit (EIC) and a photonic integrated circuit (PIC). The PIC can be stacked with the EIC in a direct-coupled manner.

[0197] For illustration purposes, Fig.18A FIG. 1 shows a side view of a system-in-package (SIP). As shown in the figure, Fig.18A SIP 1102 is shown with PIC 1192 coupled to an EIC that is part of ASIC 1188. For example, SIP 1102 is stacked with the EIC in a direct-coupled fashion.

[0198] In various embodiments, PIC 1192 is a silicon photonic integrated circuit. In addition, Fig.18A Also included is HBM 1189 (High Bandwidth Memory). As described above, the components of ASIC 1188 generate heat when performing processing operations such as neural network processing and other various computing tasks.

[0199] As mentioned above, Fig.18A Also included is a SIP 1102 having a first optical fiber 1133a, a first optical fiber array unit 1132a, a second optical fiber 1133b, and a second optical fiber array unit 1132b. For example, a fiber array unit (FAU) and its corresponding optical fibers are located above the PIC 1192 and provide optical input to the PIC 1192. In various embodiments, the optical fibers are connected to an off-chip laser light source (e.g., a light engine) and / or the FAU of another processor that provides optical input to the PIC 1192.

[0200] In addition to these lines, the device may also include nodes having routers, each router having a transmit unit and a receive unit, wherein the transmit unit and the receive unit reside partially in the EIC and partially in the PIC. In various embodiments, each transmit unit includes a thermally stable optical modulator (e.g., an EAM) in the portion that resides in the PIC. Data can be optically moved in the PIC between one of the thermally stable optical modulators in the first node and one of the receive units in the second node via an optical carrier.

[0201] As described above, in one or more embodiments, the thermally stable optical modulator is an EAM that operates within a temperature range of less than 30 degrees Celsius. In this example, the thermally stable optical modulator may include a material made of (e.g., composed of) a group consisting of germanium, silicon, an alloy of germanium, an alloy of silicon, an indium phosphide (InP)-based III-V material, and a gallium arsenide (GaAs)-based III-V material. In one or more embodiments, the thermally stable optical modulator uses the quantum bound Stark effect (QCSE) for electrically induced changes in optical absorption. In addition, in various embodiments, the EAM (e.g., thermally stable optical modulator) has an output with a high optical modulation amplitude.

[0202] Fig.18B A more detailed side view of the SIP is shown. As shown, Fig.18B Included is a SIP 1102 having a first fiber array unit 1132a and coupled to an ASIC 1188. In various embodiments, the ASIC 1188 is a 5nm system on chip (SOC).

[0203] also, Fig.18B A waveguide 1344 (e.g., a channel waveguide) is shown as part of the SIP 1102. The waveguide 1344 includes a grating coupler attached to the first fiber array unit 1132a, a splitter tree 1852, and an EAM 1860 (electroabsorption modulator) having a contact 1862 with the ASIC 1188 via an attachment 1864. In various embodiments, the attachment is a column attachment, such as a 50 μm column. The waveguide 1344 also includes a photodiode 1854 attached to the ASIC 1188.

[0204] As shown, the ASIC 1188 includes an EAM driver 1866 electrically connected to the EAM 1860. In addition, the ASIC 1188 includes a TIA 1856 (transimpedance amplifier) ​​electrically connected to the photodiode 1854.

[0205] like Fig.18B As shown, in various embodiments, the ASIC is directly coupled to the PIC in a design similar to a photonic structure. Fig.18BA specific configuration for direct coupling between electronic and photonic components is shown, but many other examples are possible. For example, while copper pillar attachments connect the EAM driver to the EAM and the photodiode to the TIA, other embodiments for direct coupling (chip-to-chip packaging) may be used.

[0206] In various embodiments, the EAM is an optical modulation element that enables light to be transferred between the cathode and the anode. In addition, the EAM also provides thermal stability at over 30 degrees Celsius and enables the SIP to be directly packaged with one or more processors of an ASIC and / or memory chip. In fact, the EAM provides optical connections within the chip and between chips. In addition, the EAM can be around 50 microns in size and / or operate at a data transfer rate of 50-115 Gbps with a power of less than 1.0 volt (but up to 2.0 volts).

[0207] Fig.19 Another top view of a portion of a thermal control system for an optical component is shown according to one or more embodiments disclosed within the present disclosure. Fig.19 Included are previously introduced components such as PIC 1192, ASIC 1188, optical modulators 1345a, 1345b, and 1345c, and nodes 1304a, 1304b, 1304c, and 1304d.

[0208] As described above, in various embodiments, nodes 1304a, 1304b, 1304c, and 1304c each include a router. Furthermore, in many cases, each of the routers includes a transmitting unit and a receiving unit. For example, the transmitting unit corresponds to modulator drivers 1341b and 1341c combined with optical modulators 1345b and 1345c (e.g., EAMs). Furthermore, the receiving unit corresponds to TIAs 1342b and 1342c combined with PDs 1346b and 1346c. In fact, as Fig.19 As shown, the transmit unit and the receive unit reside partially in the EIC (eg, ASIC 1188 ) and partially in the PIC 1192 .

[0209] Furthermore, as described above, in various embodiments, each of the transmit units includes a thermally stable optical modulator (i.e., EAM) in a portion that resides in the PIC 1192. Furthermore, data is optically moved in the PIC 1192 over an optical carrier (e.g., waveguide 1344) between a thermally stable optical modulator (e.g., first EAM or optical modulator 1345a) in a first node (e.g., node 1304a) and one of the receive units (e.g., TIA 1342b and PD 1346b) in a second node (e.g., node 1304b).

[0210] Fig. 20 is a flow chart illustrating data movement within a digital circuit in a photonic structure according to one or more embodiments disclosed in the present disclosure. For ease of explanation, Fig. 20 Described as a series of operations or actions 2000.

[0211] As shown, a series of operations 2000 includes an act of providing data from a first router of a first node 2010. For example, act 2010 may involve providing data from a first router of a first node, wherein the first router includes a transmit unit that resides partially within a photonic integrated circuit (PIC) of the first node, wherein the transmit unit includes a thermally stabilized optical modulator that resides partially within an electronic integrated circuit (EIC).

[0212] As shown, a series of acts 2000 includes an act of transmitting data from a first node to a second node 2020. For example, act 2020 may involve transmitting data from the first node to the second node via an optical carrier, such as an optical channel waveguide.

[0213] As shown, the series of acts 2000 also includes an act of receiving data at a second router of the second node 2030. For example, act 2030 may include receiving data at a second router of the second node, wherein the second router includes a receiving unit that resides partially within the EIC and partially within the PIC.

[0214] Computer-readable media can be any available media that can be accessed by a general or special-purpose computer system. A computer-readable medium that stores computer-executable instructions is a non-transitory computer-readable storage medium (device). A computer-readable medium that carries computer-executable instructions is a transmission medium. Therefore, by way of example and not limitation, embodiments of the present disclosure may include at least two distinct computer-readable media: a non-transitory computer-readable storage medium (device) and a transmission medium.

[0215] Both non-transitory computer-readable storage media (devices) and transmission media can be temporarily used to store or carry software instructions in the form of computer-readable program code, which allows the execution of embodiments of the present disclosure. Non-transitory computer-readable storage media can also be used to store such software instructions persistently or permanently. Examples of non-transitory computer-readable storage media include physical memory (e.g., RAM, ROM, EPROM, EEPROM, etc.), optical disk storage (e.g., CD, DVD, HDDVD, Blu-ray, etc.), storage devices (e.g., disk storage, tape storage, floppy disk, etc.), flash memory or other solid-state storage or memory or any other non-transmission medium, which can be used to store program code in the form of computer-executable instructions or data structures and can be accessed by general-purpose or special-purpose computers, whether such program code is stored as software, hardware, firmware, or a combination thereof, or is stored in software, hardware, firmware, or a combination thereof.

[0216] A "network" or "communication network" as a whole can be defined as one or more data links that allow electronic data to be transmitted between computer systems and / or modules, engines and / or other electronic devices. When information is transferred or provided to a computing device via a communication network or other communication connection (hardwired, wireless, or a combination of hardwired and wireless), the computing device properly views the connection as a transmission medium. The transmission medium may include communication networks and / or data links, carrier waves, wireless signals, etc., which may be used to carry the desired program or template code tools or instructions in the form of computer executable instructions or data structures and may be accessed by a general purpose or special purpose computer.

[0217] Furthermore, upon reaching various computer system components, program code in the form of computer executable instructions or data structures may be automatically or manually transferred from a transmission medium to a non-transitory computer readable storage medium (or vice versa). For example, computer executable instructions or data structures received over a network or data link may be buffered in a memory (e.g., RAM) within a network interface module (NIC) and then ultimately transferred to the computer system RAM and / or a less volatile non-transitory computer readable storage medium at the computer system. Thus, it should be understood that a non-transitory computer readable storage medium may be included in a computer system component that also (or even primarily) uses a transmission medium.

[0218] The articles "a / an" and "the" mean one or more of the elements present in the preceding description. The terms "include", "comprises" and "have" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. In addition, it should be understood that the reference to "one embodiment" or "embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also contain the listed features. For example, any element described in the embodiments herein may be combined with the elements of any other embodiment described herein. As can be understood by a person of ordinary skill in the art covered by the embodiments of the present disclosure, the numbers, percentages, ratios or other values ​​described herein are intended to include the value and other values ​​of the "approximate" or "approximate" values. Therefore, the interpretation of the values ​​should be broad enough to cover values ​​that are at least close to the values ​​to perform the desired function or achieve the desired result. The values ​​include at least the expected changes in a suitable manufacturing or production process, and may include values ​​within the range of 5%, 1%, 0.1% or 0.01% of the values.

[0219] As used herein, the terms "approximately," "about," and "substantially" represent an amount that is close to a stated amount but still performs a desired function or achieves a desired result. For example, the terms "approximately," "about," and "substantially" may refer to an amount that is within 5%, 1%, 0.1%, or 0.01% of a stated amount. In addition, it should be understood that any directions or reference frames in the foregoing description are only relative directions or movements. For example, any references to "up" and "down," or "above" or "below," only describe the relative position or movement of the associated elements.

[0220] Although the subject matter of the present invention has been described with specific language of structural features and / or methodological actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Instead, the specific features and actions described above are disclosed as example forms of implementing the claims.

[0221] Industrial Applicability

[0222] Item 1. A circuit package comprising: an interposer having a connection area for receiving a computing element; a core connected to the connection area via an electrical connection of the interposer, the core used to form a digital packet associated with the connection area; and a transmitting unit, the transmitting unit being partially in the core and partially in the interposer, for optically transmitting the digital packet to a photonic interface via a fiber array unit (FAU).

[0223] Item 2. The circuit package of Item 1, further comprising a receiving unit, the receiving unit being partially in the core and partially in the interposer, for receiving the optical signal from the FAU and providing the optical signal in digital form to the electrical portion of the core.

[0224] Clause 3. The circuit package of Clause 1, wherein the core receives a message request from the computing element requesting access to a memory controller or a computing controller associated with the photonic interface.

[0225] Item 4. A circuit package according to Item 3, wherein the core grain includes a router that receives the message request from the computing element via the electrical connection of the interposer; and the router in the core grain forms the digital packet, which includes the message request from the computing element and routing information for the message request indicating the destination of the requested memory controller or the computing controller.

[0226] Clause 5. The circuit package of clause 4, wherein the transmitting unit sends the message request in the optical form to the photonic interface through the FAU according to the routing information.

[0227] Clause 6. The circuit package of Clause 1, wherein the on-die router comprises the transmit unit and the receive unit.

[0228] Clause 7. The circuit package of Clause 1, wherein the photonic interface is part of an electro-photonic memory structure comprising a plurality of nodes.

[0229] Clause 8. The circuit package of Clause 1, wherein the interposer is a photonic integrated circuit interposer (PIC interposer); and the die has a bottom surface coupled to the connection region of the PIC interposer via the electrical connection.

[0230] Item 9. The circuit package of Item 1, wherein the interposer is a standard interposer connected to a PIC interposer; the core particle has a bottom surface coupled to the PIC interposer, the bottom surface coupled to the connection area of ​​the standard interposer; and the electrical connection passes through the PIC interposer and the standard interposer.

[0231] Item 10. A memory structure comprising: a plurality of nodes connected via a photonic channel; a connection area of ​​each of the plurality of nodes, which is used to receive a corresponding computing element; a message router in each of the plurality of nodes, the router having an electrical port for receiving a digital input from an optical receiving unit and providing a digital output to an optical transmitting unit; a routing controller in each of the plurality of nodes, the routing controller being used to generate a modified digital input based on the digital input and to provide the modified digital input as a modified digital output to the electrical port when a current node of the plurality of nodes is not a destination node; and a storage controller or a computing controller in each node, the storage controller or the computing controller being used to receive the digital output from the electrical port at the connection area when the current node is the destination node.

[0232] Item 11. A memory structure according to Item 10, wherein: a first node among the multiple nodes has a first optical transmitting unit connected to a second optical receiving unit in a second node via a first photon channel; and the second node has a second optical transmitting unit connected to the first optical receiving unit in the first node via a second photon channel.

[0233] Clause 12. The memory structure of Clause 11, wherein the first photonic channel and the second photonic channel comprise intra-chip links or inter-chip links.

[0234] Clause 13. The memory structure of Clause 10, wherein the memory controller or the compute controller provides data to the electrical port in response to interacting with the connection region.

[0235] Clause 14. The memory structure of clause 10, wherein modifying the digital input comprises modifying routing information of a packet comprising a message request and the routing information.

[0236] Clause 15. The memory structure of Clause 14, wherein modifying the routing information for the packet comprises decrementing a value in the routing information corresponding to a position of the destination node of the plurality of nodes in the memory structure.

[0237] Clause 16. A memory structure as described in clause 10, wherein the routing controller sends the modified digital output to an adjacent node in the memory structure by: converting the digital output to an optical signal; and sending the optical signal to the adjacent node via a photonic interface of the memory structure.

[0238] Item 17. A method of using a memory structure, comprising: receiving in a core a request for a compute controller or a memory controller in a destination node of the memory structure; forming a packet including the request and routing information for the request; photonically transmitting the packet from a first optical interface of the core to a second optical interface of a node in the memory structure, the first and second optical interfaces being connected via optical fibers; converting the packet into digital form in an electrical port of the node; based on determining that the node in the memory structure is the destination node, interacting with the requested memory controller or the requested compute controller in the destination node; and based on determining that the node in the memory structure is not the destination node, photonically transmitting the packet to a next node.

[0239] Clause 18. The method of clause 17, further comprising: based on determining that the node in the memory structure is not the destination node, modifying the packet to update the routing information for the request.

[0240] Clause 19. The method of clause 18, wherein photonically transmitting the packet to the next node comprises converting the digital form back to photon form after modifying the packet and before providing the packet to the next node.

[0241] Clause 20. The method of Clause 17, wherein the request is received from a computing element electrically interconnected with a circuit package including the core.

[0242] Item 21. A thermal control system comprising: a semiconductor having an optical layer stacked with an electrical layer, the semiconductor being divided into a purely electric region and a photoelectric region; one or more nodes in the photoelectric region, each of the one or more nodes residing in the optical layer and the electrical layer, a first portion of each of the one or more nodes residing in the optical layer and having at least one optical modulator and one or more heating elements residing in the electrical layer and radiating heat to the optical layer; a temperature sensing region in a second portion of each of the one or more nodes, the temperature sensing region having a temperature sensor therein for sending a thermal signal to the purely electric region, the thermal signal being associated with a current temperature of the at least one optical modulator; and a controller in the purely electric region, the controller having an electrical interconnection with each of the one or more nodes to receive the thermal signal from the temperature sensor and send a new voltage signal to the photoelectric region based on the thermal signal.

[0243] Clause 22. The thermal control system of Clause 21, wherein the controller comprises a control circuit comprised of hardware, software, or firmware.

[0244] Clause 23. The thermal control system of Clause 21, wherein the at least one optical modulator is selected from the group consisting of an electro-absorption modulator (EAM) and a quantum confined Stark effect (QCSE) electro-absorption modulator.

[0245] Clause 24. The thermal control system of Clause 21, wherein the new voltage signal is a negative DC bias voltage associated with a value of the thermal signal.

[0246] Clause 25. The thermal control system of Clause 21, wherein the at least one optical modulator has a positive pole and a negative pole and wherein the controller sends an AC swing signal to the negative pole and sends the new voltage signal to the positive pole.

[0247] Clause 26. The thermal control system of Clause 21, further comprising a table containing a plurality of voltage values ​​associated with a plurality of temperatures, wherein the controller selects a voltage value for the new voltage signal using the table and the current temperature.

[0248] Clause 27. The thermal control system of Clause 21, further comprising a function for calculating the new voltage signal using a product of the current temperature and an activation function.

[0249] Clause 28. A thermal control system according to Clause 21, wherein the one or more heat-generating elements are selected from a group consisting of a central processing unit (CPU), a graphics processing unit (GPU), a memory unit, a message router, a tensor engine, a digital neural network, a field programmable gate array (FPGA), and a processing element.

[0250] Item 29. A system-in-package (SIP) comprising: a photonic integrated circuit (PIC); an electronic integrated circuit (EIC) having an electrical connection to the PIC; a node having a first portion of the node residing in the EIC and a second portion of the node residing in the PIC; a plurality of heat generating elements in the first portion of the node, the heat generating elements radiating heat to the second portion of the node, thereby causing thermal changes in the second portion of the node; a plurality of optical modulators in the second portion of the node; and a temperature sensing area in the second portion of the node, the temperature sensing area being used to send a current temperature to a controller, wherein the controller sends a first signal to each of the plurality of optical modulators based on the current temperature.

[0251] Clause 30. The SIP of clause 29, wherein the first signal is a DC bias voltage signal.

[0252] Clause 31. The SIP of clause 29, wherein each of the plurality of optical modulators comprises a negative pole and a positive pole, and wherein the first signal is sent to the positive pole of each of the plurality of optical modulators.

[0253] Clause 32. The SIP of clause 31, wherein the controller is further configured to send a second signal to the cathode of each of the plurality of optical modulators, the second signal comprising an AC swing signal.

[0254] Clause 33. The SIP of Clause 29, wherein the controller comprises control circuitry comprised of hardware, software, or firmware.

[0255] Clause 34. The SIP of Clause 29, wherein the plurality of optical modulators are selected from the group consisting of electro-absorption modulators (EAMs) and quantum confined Stark effect (QCSE) electro-absorption modulators.

[0256] Clause 35. The SIP of clause 31, wherein the controller sends an AC swing signal to the negative terminals of the plurality of optical modulators.

[0257] Clause 36. The SIP of clause 29, further comprising a table containing a plurality of voltage values ​​associated with a plurality of temperatures, wherein the controller selects a voltage value for the first signal using the table and the current temperature.

[0258] Clause 37. The SIP of Clause 29, further comprising a function for calculating the first signal using a product of the current temperature and an activation function.

[0259] Clause 38. A SIP according to clause 29, wherein the plurality of heat generating elements are selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), a memory unit, a message router, a tensor engine, a digital neural network, a field programmable gate array (FPGA), and a processing element.

[0260] Clause 39. The SIP of Clause 29, wherein the temperature sensing region is off-center within the node.

[0261] Item 40. A method for controlling thermal variables associated with multiple optical components, comprising: applying a first signal to a negative electrode of each of the multiple optical components; applying a second signal to a positive electrode of each of the multiple optical components; sensing a temperature in an area associated with the multiple optical components; receiving a current temperature associated with the area; using the current temperature, determining when to initiate thermal control of the multiple optical components; and wherein, when a first optical component among the multiple optical components is an inter-chip modulator, obtaining a first voltage and sending the first voltage to the positive electrode of the inter-chip modulator; when a second optical component among the multiple optical components is an intra-chip modulator, obtaining a second voltage and sending the second voltage to the positive electrode of the intra-chip modulator, the second voltage having a different value from the first voltage.

[0262] Clause 41. The method of clause 40, wherein determining when to initiate the thermal control of the plurality of optical components is performed using control circuitry.

[0263] Clause 42. The method of clause 40, wherein the second signal is a DC bias voltage signal.

[0264] Clause 43. The method of clause 40, wherein the first signal comprises an AC swing signal.

[0265] Clause 44. The method of clause 41, wherein the control circuit comprises hardware, software, or firmware.

[0266] Clause 45. The method of Clause 41, wherein the plurality of optical components are selected from the group consisting of electro-absorption modulators (EAMs) and quantum confined Stark effect (QCSE) electro-absorption modulators.

[0267] Clause 46. The method of Clause 40, further comprising a table containing a plurality of voltage values ​​associated with a plurality of temperatures, wherein determining when to initiate the thermal control of the plurality of optical components further comprises accessing the table.

[0268] Clause 47. The method of clause 46, wherein determining when to initiate the thermal control of the plurality of optical components further comprises comparing the current temperature to the plurality of temperatures.

[0269] Clause 48. The method of Clause 47, wherein sending the first voltage and the second voltage comprises selecting one or more rows in the table and obtaining values ​​from one or more columns associated with the one or more rows.

[0270] Item 49. The method according to Item 40 further includes one or more functions, wherein sending the first voltage to the positive pole of the inter-chip modulator and sending the second voltage to the positive pole of the intra-chip modulator includes calculating the first voltage and the second voltage by multiplying the current temperature with an activation function.

[0271] Clause 50. A device comprising: an electronic integrated circuit (EIC); a photonic integrated circuit (PIC) stacked in a manner directly coupled to the EIC; and a plurality of nodes having routers, each of the routers comprising a transmit unit and a receive unit, wherein the transmit unit and the receive unit reside partially in the EIC and partially in the PIC, wherein each transmit unit includes a thermally stable optical modulator in the portion residing in the PIC, and wherein data is optically moved in the PIC between the thermally stable optical modulator in a first node and the receive unit in a second node via an optical carrier.

[0272] Item 51. A device according to Item 50, wherein the thermally stable optical modulator operates within a temperature range greater than 30 degrees Celsius and is composed of a material selected from germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs).

[0273] Clause 52. The device of clause 51, wherein the thermally stable optical modulator is an electro-absorption modulator (EAM) that uses the Franz-Caldesci effect for electrically induced changes in optical absorption.

[0274] Clause 53. The device of clause 50, wherein the thermally stable optical modulator is an EAM that operates within a temperature range of less than 30 degrees Celsius.

[0275] Clause 54. The apparatus of clause 53, wherein the thermally stable optical modulator is an EAM comprised of a material selected from the group consisting of germanium, silicon, alloys of germanium, alloys of silicon, InP-based III-V materials, and GaAs-based III-V materials.

[0276] Clause 55. The device of clause 53, wherein the thermally stable optical modulator uses a quantum confined Stark effect (QCSE) for electrically induced changes in optical absorption.

[0277] Item 56. A device according to Item 50, wherein the thermally stable optical modulator has an output end, the output end has a high optical modulation amplitude and is composed of a material selected from the group consisting of germanium, silicon, alloys of germanium, alloys of silicon, InP-based III-V materials and GaAs-based III-V materials.

[0278] Clause 57. The device of Clause 56, wherein the thermally stable optical modulator uses a QCSE for electrically induced changes in optical absorption.

[0279] Clause 58. A device according to clause 50, wherein the thermally stable optical modulator is configured to operate stably over a wide temperature range and is composed of a material selected from the group consisting of germanium, silicon, alloys of germanium, alloys of silicon, InP-based III-V materials, and GaAs-based III-V materials.

[0280] Article 59. A method for moving data within a digital circuit in a photonic structure, comprising: providing data from a first router at a first node, wherein the first router includes a transmitting unit that resides partially within a photonic integrated circuit (PIC) of the first node, wherein the transmitting unit includes a thermally stable optical modulator that resides partially within an electronic integrated circuit (EIC); transmitting the data from the first node to the second node via an optical carrier; and receiving the data at a second router at the second node, wherein the second router includes a receiving unit that resides partially within the EIC and partially within the PIC.

[0281] Clause 60. The method of clause 59, wherein the thermally stable optical modulator is an EAM optical modulator, which is an electro-absorption modulator (EAM) that uses the Franz-Caldesci effect for electrically induced changes in optical absorption.

[0282] Clause 61. The method of clause 60, wherein the thermally stable optical modulator is an EAM that operates within a temperature range of less than 30 degrees Celsius.

[0283] Clause 62. The method of clause 60, wherein the EIC is directly coupled to the PIC.

[0284] Clause 63. The method of Clause 62, wherein the EAM on the PIC is thermally stable within 50 microns of the EIC.

[0285] Clause 64. The method of clause 59, wherein the first node and the second node are the same node.

[0286] Clause 65. The method of clause 59, wherein the first node and the second node are different nodes.

[0287] Clause 66. The method of Clause 59, wherein the thermally stable optical modulator uses a quantum confined Stark effect (QCSE) for electrically induced changes in optical absorption.

[0288] Clause 67. The method of Clause 59, wherein the thermally stable optical modulator has an output having a high optical modulation amplitude.

[0289] Clause 68. The method of Clause 67, wherein the thermally stable optical modulator uses a QCSE for electrically induced changes in optical absorption.

[0290] Item 69. A method according to any one of items 59-68, wherein the thermally stable optical modulator operates within a temperature range greater than 30 degrees Celsius and is composed of a material selected from germanium, silicon, an alloy of germanium, an alloy of silicon, a III-V material based on indium phosphide (InP), or a III-V material based on gallium arsenide (GaAs).

[0291] Clause 70. The method of clause 59, wherein the EIC operates on a digital application specific integrated circuit (ASIC).

Claims

1. A system comprising: A circuit package comprising: an interposer having a connection area for receiving a computing element; a core particle connected to the connection area via an electrical connection of the interposer, the core particle being used to form a packet associated with the connection area; and a transmitting unit, the transmitting unit being partly in the core particle and partly in the interposer, for providing the packet in an optical form; a first photon channel connected to the circuit package at a first end for receiving the packet from the transmitting unit; and A memory structure has a plurality of nodes connected by a second photon channel, the first photon channel being connected at a second end to at least one of the plurality of nodes.

2. The system according to claim 1 further comprises a receiving unit, which is partially in the core and partially in the interposer, for receiving an optical signal via the first photon channel and providing the optical signal in digital form to the electrical part of the core.

3. A system according to any one of claims 1 or 2, wherein: The core particle receives a message request from the computing element requesting access to a memory controller or a computing controller associated with the memory structure.

4. The system of claim 3, wherein: The core particle includes a router that receives the message request from the computing element via the electrical connection of the interposer; as well as The router in the core particle forms a packet including the message request from the computing element and routing information for the message request indicating a destination of the requested memory controller or the computing controller.

5. The system according to claim 4, wherein: The transmitting unit sends the message request in the optical form through the first photon channel based on the routing information.

6. The system according to any one of claims 1 to 5, wherein: The router on the chip includes the transmitting unit and the receiving unit.

7. The system according to any one of claims 1 to 6, wherein: The first photonic channel is part of an electro-photonic memory structure including a plurality of nodes.

8. The system according to any one of claims 1 to 7, wherein: The interposer is a photonic integrated circuit interposer, i.e., a PIC interposer; and The die has a bottom surface coupled to the connection region of the PIC interposer via the electrical connection.

9. The system according to any one of claims 1 to 8, wherein: The interposer is a standard interposer connected to a PIC interposer; The core particle has a bottom surface coupled to the PIC interposer, the bottom surface coupled to the connection area of ​​the standard interposer; as well as The electrical connections pass through the PIC interposer and the standard interposer.

10. A memory structure comprising: Multiple nodes connected via photon channels; a connection region in each of the plurality of nodes for receiving a corresponding computing element; a message router in each of the plurality of nodes, the router having an electrical port for receiving a digital input from an optical receive unit and providing a digital output to an optical transmit unit; a routing controller in each of the plurality of nodes, the routing controller to generate a modified digital input from the digital input and provide the modified digital input as a modified digital output to the electrical port when a current node of the plurality of nodes is not a destination node; as well as A storage controller or a computing controller in each node is configured to receive the digital output from the electrical port at the connection region when the current node is the destination node.

11. The memory structure of claim 10, wherein: A first node of the plurality of nodes has a first optical transmitting unit connected to a second optical receiving unit in a second node via a first photon channel; and The second node has a second optical transmitting unit connected to the first optical receiving unit in the first node via a second photonic channel.

12. The memory structure according to claim 11, wherein: The first photon channel and the second photon channel include intra-chip links or inter-chip links.

13. The memory structure according to any one of claims 10 to 12, wherein: The memory controller or the compute controller provides data to the electrical port in response to interacting with the connection area.

14. The memory structure according to any one of claims 10 to 13, wherein: Modifying the digital input includes modifying routing information of a packet including a message request and the routing information.

15. The memory structure of claim 14, modifying the routing information for the packet comprises decrementing a value in the routing information corresponding to a location of the destination node of the plurality of nodes in the memory structure.

16. The memory structure according to any one of claims 10 to 15, wherein: The routing controller transmits the modified digital output to an adjacent node in the memory structure by: converting the digital output into an optical signal; and The optical signal is transmitted to the neighboring node via a photonic interface of the memory structure.

17. A method of using a memory structure, comprising: receiving, in a core particle, a request to a compute controller or a memory controller in a destination node of the memory structure; forming a packet including the request and routing information for the request; photonically transmitting the packet from a first optical interface of the core to a second optical interface of a node in the memory structure, the first optical interface and the second optical interface being connected via an optical fiber; converting the packet to digital form in an electrical port of the node; based on determining that the node in the memory structure is the destination node, interacting with the compute controller or the memory controller in the destination node; as well as Based on determining that the node in the memory structure is not the destination node, photonically sending the packet to a next node.

18. The method according to claim 17, further comprising: Based on determining that the node in the memory structure is not the destination node, modifying the packet to update the routing information for the request.

19. The method according to claim 18, wherein: Photonically sending the packet to the next node includes converting the digital form back to photon form after modifying the packet and before providing the packet to the next node.

20. The method according to any one of claims 17 to 19, wherein: The request is received from a computing element electrically interconnected with a circuit package including the core particle.

21. A thermal control system comprising: A semiconductor having an optical layer stacked with an electrical layer, the semiconductor being divided into a purely electrical region and a photovoltaic region; one or more nodes in the optoelectronic region, each of the one or more nodes residing in the optical layer and the electrical layer, a first portion of each of the one or more nodes residing in the optical layer and having at least one optical modulator and one or more heat generating elements residing in the electrical layer and radiating heat to the optical layer; a temperature sensing region in the second portion of each of the one or more nodes, the temperature sensing region having a temperature sensor therein for transmitting a thermal signal to the electric-only region, the thermal signal being associated with a current temperature of the at least one optical modulator; as well as A controller in the electric-only region, the controller having an electrical interconnection with each of the one or more nodes, is configured to receive the thermal signal from the temperature sensor and transmit a new voltage signal to the photovoltaic region based on the thermal signal.

22. The thermal control system of claim 21, wherein: The controller includes a control circuit composed of hardware, software or firmware.

23. A thermal control system according to any one of claims 21 or 22, wherein: The at least one optical modulator is selected from the group consisting of an electro-absorption modulator, EAM, and a quantum confined Stark effect (QCSE) electro-absorption modulator.

24. The thermal control system according to any one of claims 21 to 23, wherein: The new voltage signal is a negative DC bias voltage associated with the value of the thermal signal.

25. The thermal control system according to any one of claims 21 to 24, wherein: The at least one optical modulator has a positive pole and a negative pole and wherein the controller transmits an AC swing signal to the negative pole and transmits the new voltage signal to the positive pole.

26. The thermal control system of any one of claims 21-25, further comprising a table including a plurality of voltage values ​​associated with a plurality of temperatures, wherein the controller selects a voltage value for the new voltage signal using the table and the current temperature.

27. The thermal control system of any one of claims 21-26, further comprising a function for calculating the new voltage signal using a product of the current temperature and an activation function.

28. The thermal control system according to any one of claims 21 to 27, wherein: The one or more heat generating elements are selected from the group consisting of a central processing unit CPU, a graphics processing unit GPU, a memory unit, a message router, a tensor engine, a digital neural network, a field programmable gate array FPGA and a processing element.

29. A system-in-package (SIP), comprising: Photonic integrated circuit is PIC; an electronic integrated circuit or EIC having electrical connections to the PIC; a node having a first portion of the node residing in the EIC and a second portion of the node residing in the PIC; a plurality of heat generating elements in the first portion of the node, the plurality of heat generating elements radiating heat to the second portion of the node, thereby causing a thermal change in the second portion of the node; a plurality of optical modulators in said second portion of said node; as well as A temperature sensing region in the second portion of the node is configured to transmit a current temperature to a controller, wherein the controller transmits a first signal to each of the plurality of optical modulators based on the current temperature.

30. The SIP of claim 29, wherein: The first signal is a DC bias voltage signal.

31. A SIP according to any one of claims 29 or 30, wherein Each of the plurality of optical modulators includes a negative pole and a positive pole, and wherein the first signal is transmitted to the positive pole of each of the plurality of optical modulators.

32. The SIP of claim 31, wherein: The controller is also configured to transmit a second signal to the negative electrode of each of the plurality of optical modulators, the second signal comprising an AC swing signal.

33. A SIP according to any one of claims 29-32, wherein: The controller includes a control circuit composed of hardware, software or firmware.

34. A SIP according to any one of claims 29-33, wherein: The plurality of optical modulators are selected from the group consisting of electro-absorption modulators (EAMs) and quantum confined Stark effect (QCSE) electro-absorption modulators.

35. A SIP according to any one of claims 31-34, wherein The controller transmits an AC swing signal to the negative electrodes of the plurality of optical modulators.

36. The SIP of any one of claims 29-35, further comprising a table including a plurality of voltage values ​​associated with a plurality of temperatures, wherein the controller selects a voltage value for the first signal using the table and the current temperature.

37. The SIP of any one of claims 29-36, further comprising a function for calculating the first signal using the product of the current temperature and an activation function.

38. A SIP according to any one of claims 29-37, wherein The plurality of heat generating elements are selected from the group consisting of a central processing unit CPU, a graphics processing unit GPU, a memory unit, a message router, a tensor engine, a digital neural network, a field programmable gate array FPGA and a processing element.

39. A SIP according to any one of claims 29-38, wherein The temperature sensing region is off-center within the node.

40. A method for controlling thermal variables associated with a plurality of optical components, comprising: applying a first signal to a cathode of each of the plurality of optical components; applying a second signal to an anode of each of the plurality of optical components; sensing a temperature in an area associated with the plurality of optical components; receiving a current temperature associated with the zone; using the current temperature, determining when to initiate thermal control of the plurality of optical components; as well as wherein when a first optical component of the plurality of optical components is an inter-chip modulator, obtaining a first voltage and transmitting the first voltage to a positive electrode of the inter-chip modulator; When a second optical component among the plurality of optical components is an on-chip modulator, a second voltage is obtained and transmitted to a positive electrode of the on-chip modulator, the second voltage having a different value from the first voltage.

41. The method of claim 40, wherein: A control circuit is used to determine when to initiate the thermal control of the plurality of optical components.

42. The method according to any one of claims 40 or 41, wherein: The second signal is a DC bias voltage signal.

43. The method according to any one of claims 40 to 42, wherein: The first signal comprises an AC swing signal.

44. The method according to any one of claims 41 to 43, wherein: The control circuit includes hardware, software or firmware.

45. The method according to any one of claims 41 to 44, wherein: The plurality of optical components are selected from the group consisting of electro-absorption modulators (EAMs) and quantum confined Stark effect (QCSE) electro-absorption modulators.

46. ​​The method of any one of claims 40-45, further comprising a table comprising a plurality of voltage values ​​associated with a plurality of temperatures, wherein determining when to initiate the thermal control of the plurality of optical components further comprises accessing the table.

47. The method of claim 46, wherein: Determining when to initiate the thermal control of the plurality of optical components further includes comparing the current temperature to the plurality of temperatures.

48. The method of claim 47, wherein: Transmitting the first voltage and the second voltage includes selecting one or more rows in the table and obtaining values ​​from one or more columns associated with the one or more rows.

49. The method according to any one of claims 40-48 further includes one or more functions, wherein transmitting the first voltage to the positive pole of the inter-chip modulator and transmitting the second voltage to the positive pole of the inter-chip modulator include calculating the first voltage and the second voltage by multiplying the current temperature with an activation function.

50. An apparatus comprising: Electronic integrated circuits are EICs; A photonic integrated circuit, i.e., a PIC, stacked in a manner directly coupled to the EIC; as well as A plurality of nodes having routers, each of the routers comprising a transmit unit and a receive unit, wherein the transmit unit and the receive unit reside partially in the EIC and partially in the PIC, wherein each transmit unit comprises a thermally stable optical modulator in the portion residing in the PIC, and wherein data is optically moved in the PIC between the thermally stable optical modulator in a first node and a receive unit in a second node via an optical carrier.

51. The apparatus of claim 50, wherein: The thermally stable optical modulator operates over a temperature range greater than 30 degrees Celsius and is composed of a material selected from germanium, silicon, alloys of germanium, alloys of silicon, III-V materials based on indium phosphide (InP), or III-V materials based on gallium arsenide (GaAs).

52. The apparatus of claim 51, wherein: The thermally stable optical modulator is an electro-absorption modulator, EAM, which uses the Franz-Caldesci effect to achieve electrically induced changes in optical absorption.

53. The apparatus according to any one of claims 50 to 52, wherein: The thermally stable optical modulator is an EAM that operates within a temperature range of less than 30 degrees Celsius.

54. The apparatus of claim 53, wherein: The thermally stable optical modulator is an EAM composed of a material selected from the group consisting of germanium, silicon, alloys of germanium, alloys of silicon, InP-based III-V materials, and GaAs-based III-V materials.

55. The apparatus of claim 53, wherein: The thermally stable optical modulator exploits the quantum trapped Stark effect, or QCSE, for electrically induced changes in optical absorption.

56. The apparatus of any one of claims 50 to 55, wherein: The thermally stable optical modulator has an output end having a high optical modulation amplitude and is composed of a material selected from the group consisting of germanium, silicon, alloys of germanium, alloys of silicon, InP-based III-V materials, and GaAs-based III-V materials.

57. The apparatus of claim 56, wherein: The thermally stable optical modulator uses QCSE for electrically induced changes in optical absorption.

58. The apparatus of any one of claims 50 to 57, wherein: The thermally stable optical modulator is configured to operate stably over a wide temperature range and is composed of a material selected from the group consisting of germanium, silicon, alloys of germanium, alloys of silicon, InP-based III-V materials, and GaAs-based III-V materials.

59. A method of moving data within a digital circuit in a photonic structure, comprising: providing data from a first router of a first node, wherein the first router comprises a transmit unit residing partially within a photonic integrated circuit (PIC) of the first node, wherein the transmit unit comprises a thermally stable optical modulator residing partially within an electronic integrated circuit (EIC); transferring the data from the first node to the second node via an optical carrier; as well as The data is received at a second router of the second node, wherein the second router includes a receiving unit that resides partially within the EIC and partially within the PIC.

60. The method of claim 59, wherein: The thermally stable optical modulator is an EAM optical modulator, which is an electro-absorption modulator (EAM) that uses the Franz-Caldesci effect for electrically induced changes in optical absorption.

61. The method of claim 60, wherein: The thermally stable optical modulator is an EAM that operates within a temperature range of less than 30 degrees Celsius.

62. The method according to any one of claims 60 or 61, wherein: The EIC is directly coupled to the PIC.

63. The method of claim 62, wherein: The EAM on the PIC is thermally stable within 50 microns of the EIC.

64. The method according to any one of claims 59 to 63, wherein: The first node and the second node are the same node.

65. The method according to any one of claims 59 to 64, wherein: The first node and the second node are different nodes.

66. The method according to any one of claims 59 to 65, wherein: The thermally stable optical modulator exploits the quantum trapped Stark effect, QCSE, for electrically induced changes in optical absorption.

67. The method according to any one of claims 59 to 66, wherein: The thermally stable optical modulator has an output having a high optical modulation amplitude.

68. The method of claim 67, wherein: The thermally stable optical modulator uses QCSE for electrically induced changes in optical absorption.

69. The method according to any one of claims 59 to 68, wherein: The thermally stable optical modulator operates over a temperature range greater than 30 degrees Celsius and is composed of a material selected from germanium, silicon, alloys of germanium, alloys of silicon, III-V materials based on indium phosphide (InP), or III-V materials based on gallium arsenide (GaAs).

70. The method of claim 59, wherein: The EIC operates on a digital application specific integrated circuit ASIC.

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