Voltage domain GPIO control

Abstract

An integrated circuit (100) includes an input / output (I / O) interface (104), a first domain circuit (108), and a second domain circuit (110). The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second domain circuit is coupled to a second voltage domain and is configured to generate a bit value for a control bit in the control bits, generate a multi-bit identifier (ID) for the control bit, and transmit the bit value and the multi-bit ID. The first domain circuit is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, identify the control bit from the multi-bit ID, and configure the control bit of the I / O interface with the bit value.

Description

Technical Field

[0001] The present disclosure relates generally to integrated circuits, and more particularly to cross-supply voltage domain signal propagation in integrated circuits. Background Art

[0002] A general purpose input-output (GPIO) port of an integrated circuit is typically supplied by a voltage level that is different from the supply voltage of other circuits of the integrated circuit, and thus the interface between the GPIO circuit and the other circuits may be accomplished through a level shifter circuit.

[0003] In "General Purpose Input / Output (GPIO)" (Balachandran and Sasang (2009)), the authors claim that the need for flexibility in data input and output is essential for creating adaptability in microprocessor communications, and that the use of general-purpose input / output (GPIO) enables open communication between devices at the embedded level. These pins available on the processor can be programmed to accept input or provide output to external devices based on user expectations and application requirements. The variable methods of data processing implemented on these pins, such as ADC conversion and interrupt handling, provide an ideal alternative for multi-input applications.

[0004] US Patent 6,487,687 discloses a voltage level shifter with testable cascode devices. According to one embodiment, the level shifter includes a plurality of cascode devices and switches a first output driver according to the values ​​of a data input and an enable input.

[0005] U.S. Patent No. 11,128,300 discloses a level shifter circuit with an intermediate power domain and a method of operating the same. The level shifter circuit includes an input circuit, an output circuit, and an intermediate circuit. The input circuit is coupled to receive an input signal from a first voltage domain operating at a first supply voltage and generate a first intermediate signal. The intermediate circuit receives the first intermediate signal and generates a second intermediate signal. The output circuit receives the intermediate signal and provides an output signal to a second voltage domain operating at a second supply voltage different from the first supply voltage. A voltage multiplexer is configured to provide one of the first supply voltage or the second supply voltage to the intermediate circuit depending on the state of the input signal. Summary of the Invention

[0006] Embodiments described herein provide an integrated circuit (IC) comprising an input / output (I / O) interface, a first domain circuit, and a second domain circuit. The I / O interface is coupled to a first voltage domain and is configurable by a set of control bits. The second domain circuit is coupled to a second voltage domain and is configured to generate a bit value for a control bit in the control bits, generate a multi-bit identifier (ID) for the control bit, and transmit the bit value and the multi-bit ID. The first domain circuit is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, identify the control bit from the multi-bit ID, and configure the control bit of the I / O interface with the bit value.

[0007] In some embodiments, the IC further includes a plurality of level shifters configured to transmit the bit value and the multi-bit ID from the second domain circuit to the first domain circuit. In one embodiment, the number of level shifters designated to transmit the multi-bit ID is less than the number of control bits.

[0008] In a disclosed embodiment, the IC further includes a second I / O interface coupled to the first voltage domain, the second domain circuitry is further configured to transmit a second bit value, and the first domain circuitry is configured to configure a control bit of the second I / O interface with the second bit value. In another embodiment, the first domain circuitry includes a plurality of storage elements configured to retain respective bit values ​​of the control bits.

[0009] In yet another embodiment, the second domain circuitry includes one or more processor cores configured to communicate with an I / O interface.In yet another embodiment, a maximum voltage of the first voltage domain exceeds an operating voltage of the second voltage domain by at least five times.

[0010] According to the embodiments described herein, an integrated circuit (IC) is further provided, comprising a plurality of input / output (I / O) interfaces, a first domain circuit, and a second domain circuit. The I / O interfaces are coupled to a first voltage domain and are each configurable by a corresponding set of control bits. The second domain circuit is coupled to a second voltage domain and is configured to generate corresponding bit values ​​for the control bits, generate an indication specifying a subset of one or more of the I / O interfaces to be configured with the bit values, and transmit the bit values ​​and the indication. The first domain circuit is coupled to the first voltage domain and is configured to receive the bit values ​​and the indication, identify the subset of I / O interfaces from the indication, and configure the I / O interfaces in the subset with the bit values.

[0011] According to the embodiments described herein, an integrated circuit (IC) is also provided, comprising a plurality of input / output (I / O) interfaces, a first domain circuit, and a second domain circuit. The I / O interfaces are coupled to a first voltage domain and are each configurable by a corresponding set of control bits. The second domain circuit is coupled to a second voltage domain and comprises (i) a plurality of processing cores and (ii) a control circuit configured to control at least one of the I / O interfaces by generating a bit value for a control bit in the control bits, generating a multi-bit identifier (ID) for the control bit, and transmitting the bit value and the multi-bit ID. The first domain circuit is coupled to the first voltage domain and is configured to receive the multi-bit ID, identify the control bit from the multi-bit ID, and configure the control bit of the I / O interface with the bit value.

[0012] According to embodiments described herein, a method is further provided that includes operating an input / output (I / O) interface coupled to a first voltage domain and configurable by a set of control bits. Using second domain circuitry coupled to a second voltage domain, generating a bit value for a control bit in the control bits, generating a multi-bit identifier (ID) for the control bit, and transmitting the bit value and the multi-bit ID. Using first domain circuitry coupled to the first voltage domain, receiving the bit value and the multi-bit ID, identifying the control bit from the multi-bit ID, and configuring the control bit of the I / O interface using the bit value.

[0013] According to embodiments described herein, a method is also provided that includes operating a plurality of input / output (I / O) interfaces coupled to a first voltage domain and each configurable by a corresponding set of control bits. Using second domain circuitry coupled to a second voltage domain, generating corresponding bit values ​​for the control bits, generating an indication specifying a subset of one or more of the I / O interfaces to be configured with the bit values, and transmitting the bit values ​​and the indication. Using first domain circuitry coupled to the first voltage domain, receiving the bit values ​​and the indication, identifying the subset of the I / O interfaces from the indication, and configuring the I / O interfaces in the subset with the bit values.

[0014] The present disclosure will be more fully understood from the following detailed description of embodiments of the present disclosure in conjunction with the accompanying drawings, in which: BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a block diagram schematically illustrating the structure of an integrated circuit (IC) according to an embodiment of the present disclosure;

[0016] Figure 2 is a block diagram schematically illustrating a GPIO pad circuit according to an embodiment of the present disclosure;

[0017] Figure 3A is a block diagram schematically illustrating a bit-serial GPIO configuration in an IC according to an embodiment of the present disclosure;

[0018] Figure 3B is a block diagram schematically illustrating a GPIO control register according to an embodiment of the present disclosure;

[0019] Figure 4 is a block diagram schematically illustrating a bit-parallel GPIO configuration in an IC according to an embodiment of the present disclosure;

[0020] Figure 5 is a block diagram schematically illustrating a GPIO configuration in a system on chip (SoC) according to an embodiment of the present disclosure;

[0021] Figure 6A is a flow chart schematically illustrating a method for cross-voltage domain bit-serial GPIO configuration in an IC according to an embodiment of the present disclosure;

[0022] Figure 6B is a flow chart schematically illustrating a method for cross-voltage domain parallel GPIO configuration in an IC according to an embodiment of the present disclosure;

[0023] Figure 7 is a diagram schematically illustrating various types of systems that may include any of the circuits, devices, or systems discussed above according to embodiments of the present disclosure; and

[0024] Figure 8 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Overview

[0026] To achieve higher speeds and lower power consumption, high-density integrated circuits (ICs) typically use a low-voltage power supply (e.g., 0.6V) for the logic core. However, for inputs and outputs (I / O), a higher voltage power supply (e.g., 1.8V, 3.3V, or higher) is often used to comply with existing inter-IC interface specifications. We refer to circuits operating on the I / O power supply as Vdd1 domain circuits, and core and other circuits operating on the core power supply as Vdd2 domain circuits (an integrated circuit may have additional Vdd domains for various types of circuits).

[0027] The I / O circuits used in ICs vary in functionality. Some I / O circuits are input-only, others are output-only, and still others are bidirectional input / output circuits. Input circuits sometimes have a Schmidt configuration and / or a resistive pull-up or pull-down (other configurations may be used, some of which are described below). Integrated circuits sometimes include configurable general-purpose I / O (GPIO) circuits that can typically be set to the desired functionality during IC initialization (e.g., by a processor in the IC). Such GPIOs can be configured by multiple control bits (e.g., nine or eleven bits).

[0028] To transfer the voltage level of an external signal to the IC core, the Vdd1 domain signal from the I / O circuit must be voltage-shifted to Vdd2. Conversely, to transfer a Vdd2 logic signal from the IC core to an external signal, a voltage shift from Vdd2 to Vdd1 is required. (The conductors through which external signals are input to the IC core are called bit input conductors; the conductors through which external signals are output from the IC core are called bit output conductors. Bit input and bit output conductors are collectively referred to as bit lines.)

[0029] Additional level shifters are required when a processor or other circuitry in the core programs the I / O circuit configuration.

[0030] However, voltage level shifters are typically large, consume significant power, and in some cases, present reliability bottlenecks. For an example voltage shifter, see U.S. Patent 8,502,317, which describes a level shifter circuit for an integrated circuit having one or more inputs operating in a first voltage domain and a signal output operating in a second voltage domain.

[0031] According to embodiments of the present disclosure, circuits and methods are provided for programming GPIOs in integrated circuits using a small number of voltage level shifters. GPIOs are also referred to herein as "GPIO devices," "I / O buffers," or "I / O interfaces." All of these terms are used interchangeably herein.

[0032] In the disclosed bit-serial programming implementation, the vdd2 circuit encodes the identifier (ID) of the selected GPIO control bit to be programmed; simultaneously, the logic core transmits the value to be programmed on the corresponding bit-out wires for multiple (e.g., all) GPIOs. The logic core can also transmit a write pulse, which is voltage-level shifted and used as a write input for multiple (e.g., all) registers. In some implementations, the vdd1 decoder converts the bit ID into a one-hot bus, where the set bit indicates the selected control register bit. In one implementation, the bit-in wire can be used to read the contents of the selected control register bit for multiple (e.g., all) GPIOs.

[0033] The disclosed technique enables programming of GPIOs using a reduced number of voltage shifters, thereby reducing IC size and power consumption.

[0034] In the disclosed bit-parallel programming implementation, the VDD2 circuit transmits the entire contents to be programmed in the GPIO control register. In parallel, the logic core transmits instructions on the BITOUT wires specifying a subset of one or more GPIOs to be programmed. The bit-parallel implementation can be more efficient than the bit-serial implementation when the number of groups of GPIOs with the same configuration is less than the number of control register bits.

[0035] Description of Example Implementations

[0036] The I / O buffers of high-density integrated circuits typically operate at a supply voltage that is much higher than the voltage of the core power supply. For example, while the core operating voltage may be 0.6V, the I / O supply voltage may be as high as 5V to 10V (e.g., 6V). When using configurable general-purpose I / O (GPIO) buffers that are programmed during initialization or during other configuration sequences, the core (typically the processor within the core) transfers configuration data to the GPIO buffers through a series of voltage-level translators ("voltage shifters") that are typically large, consume significant power, and reduce IC reliability.

[0037] Figure 1 1 is a block diagram schematically illustrating the structure of an integrated circuit (IC) 100 according to an embodiment of the present disclosure. IC 100 includes pads 102 coupled to external circuitry (not shown), GPIO buffers 104 (also referred to as I / O interfaces) coupled to the pads, and core logic 106. In an embodiment, core logic 106 may include any digital circuitry, including, for example, one or more processors.

[0038] In one embodiment, IC 100 may include two or more power domains, each domain including circuits powered by a different power input; these domains are typically isolated from each other (e.g., to avoid bipolar latch-up). IC 100 includes a Vdd1 power domain 108 and a Vdd2 power domain 110. GPIO buffer 104 is powered by vdd1 and, therefore, resides in vdd1 domain 108. In some embodiments, Vdd1 is defined so that the output and input signals of IC 100 will conform to inter-chip communication standards; logic core 106 is Vdd2 power domain 110; in an embodiment, Vdd2 is optimized for high speed, compatible with fast thin oxide gates used in high-density semiconductor devices. (In some embodiments, IC 100 may have additional power domains for other purposes.)

[0039] according to Figure 1 In the example embodiment shown, each GPIO buffer in GPIO buffer 104 is controlled by a corresponding configuration register 112; in some embodiments, the configuration register can configure the GPIO buffer as an input buffer, an output buffer, or a bidirectional input and output buffer; in one embodiment, the configuration register configures the drive strength of the output buffer, and in other embodiments, can configure the Schmitt input buffer (see Figure 2 , other GPIO buffer configuration options will be described below.) When the configuration registers control the GPIO buffers, the configuration registers are in the Vdd1 domain 108.

[0040] In an embodiment, to transfer data between the Vdd domains, a voltage level shifter is used (the reader is referred to U.S. Patent 8,502,317 for an example voltage domain level shifter). In some embodiments, the maximum voltage of the vdd1 domain exceeds the operating voltage of the vdd2 domain by at least five times. Typically, voltage level shifters are large, consume a lot of power, and reduce the reliability (e.g., life expectancy) of the integrated circuit. Figure 1 In the example embodiment shown in , voltage level shifter 114 translates signals transmitted from the Vdd2 circuit to the Vdd1 circuit, and translates signals transmitted from the Vdd1 circuit (eg, GPIO buffer 104) to the Vdd2 circuit in the opposite direction.

[0041] The voltage level shifter 114 converts the signal generated by the input buffer of the GPIO buffer 104 (referred to as the input bit line) to the Vdd2 voltage domain, and converts the Vdd2 domain signal output by the logic core 106 (referred to as the bit line output) to the Vdd1 domain input of the output buffer of the GPIO buffer 104. (The bit line input and bit line output are collectively referred to as "bit line". Figure 1 In the figure, the vdd1 domain bit line and the vdd2 domain bit line are both represented as "bit lines.")

[0042] When logic core 106 configures a GPIO buffer, it transfers the configuration data to configuration register 112. The number of configuration bits can be large; for example, if there are 200 GPIO buffers and each GPIO buffer has nine configuration bits, the total number of program bits can be 1800. Figure 1 In the example embodiment shown in , the number of voltage level shifters conveying GPIO programming data is significantly lower than the number of configuration bits.

[0043] In one embodiment, IC 100 includes Vdd2-I / O configuration circuit 116, which can encode configuration data. The Vdd2-I / O configuration circuit transmits the encoded configuration data to voltage level shifter 114 and inputs the corresponding Vdd1 domain signal to Vdd1-I / O configuration circuit 118, which decodes the encoded data and programs configuration register 112 in response to the decoded data. As will be described below (see Figures 3 and Figure 5 ), so the number of level shifters required is significantly lower than the number of programming bits.

[0044] In an embodiment, the bit lines that the logic core passes to or receives from the pads are also coupled to the vdd2 I / O configuration circuit, and the vdd1 I / O configuration circuit programs configuration register 112 in response to data passed directly to the vdd1 I / O configuration circuit by the vdd2 I / O circuit (through the voltage level shifter) and in response to data passed by the vdd2 I / O configuration circuit over the bit lines.

[0045] Figure 1 The configuration of integrated circuit 100 shown and described above is an example cited for conceptual clarity. In alternative embodiments, other configurations may be used. For example, GPIO buffer groups may exist in more than one Vdd domain. In some embodiments, some of the GPIO buffers may have fixed configurations and no configuration registers.

[0046] Figure 2 2 is a block diagram schematically illustrating a GPIO pad circuit 200 according to an embodiment of the present disclosure. The GPIO pad circuit includes an output buffer 202, an input buffer 204, and a pad 206. The pad is coupled to the output buffer and the input buffer; the output buffer is coupled to a bit-out conductor 208, and the input buffer is coupled to a bit-in conductor 210.

[0047] according to Figure 2In the example embodiment shown, the output buffer 202 receives six control inputs: (i) a strong active pull-up input 212 connected to control the output buffer to connect the strong pull-up device to the pad 206; (ii) a weak active pull-up input 214 connected to control the output buffer to connect the weak pull-up device to the pad; (iii) a fixed slew rate active pull-up input 215 connected to control the output buffer to connect the positive fixed slew rate circuit to the pad. pad (the fixed slew rate circuit is configured to produce a linear v(t) slope); (iv) connecting a strong active pull-down input 218, which controls an output buffer to connect the strong pull-down device to the pad; (v) connecting a weak active pull-down input 222, which controls an output buffer to connect the weak pull-down device to the pad; and (vi) connecting a fixed slew rate active pull-down input 215, which controls an output buffer to connect the negative fixed slew rate circuit to pad 206.

[0048] The input buffer 204 receives an activate Schmitt trigger input 224 which sets the input buffer into a Schmitt trigger configuration (where the transition threshold for a rising edge at the input signal is higher than the threshold for a falling edge).

[0049] GPIO buffer 200 is also configured to couple passive pull-up and pull-down devices to pad 206. Connecting passive pull-up input 226 closes electronic switch 228, which couples the Vdd supply to the pad through pull-up resistor 230. Similarly, connecting passive pull-down input 232 closes electronic switch 234, which couples the Vss supply (e.g., ground) to the pad through pull-down resistor 236.

[0050] Therefore, according to Figure 2 In the example embodiment shown, the GPIO buffer can be set to one of a variety of configurations by controlling nine inputs.

[0051] exist Figure 2The configuration of the GPIO buffer 200 shown in and described above is an example cited for conceptual clarity. In alternative embodiments, other GPIO configurations may be used. For example, in one embodiment, the GPIO may have additional control inputs (e.g., for connecting a pull-up or pull-down device of medium strength); in another embodiment, the GPIO may have fewer control inputs (e.g., a single weak or strong control may be used to define the strength of both the pull-up device and the pull-down device). In other embodiments, the GPIO may be controlled by more inputs that allow additional and / or different functionality. In yet other embodiments, a smaller number of inputs are used, thereby having reduced and / or different functionality.

[0052] Figure 3A is a block diagram schematically illustrating a bit-serial GPIO configuration in IC 100 according to an embodiment of the present disclosure.

[0053] IC 100 includes vdd1 domain pad circuits 300; each pad circuit includes pad 102 and GPIO 104 (both at Figure 1 To control GPIO operation, the pad circuit 300 also includes a control register 302 (described below with reference to Figure 3B describe).

[0054] I / O buffer 104 is connected to the I / O buffer 104 by voltage level shifter 118 ( Figure 1 ) are connected to the bit input and bit output ports of the vdd2 I / O configuration circuit 304.

[0055] To program or read a single bit of control register 302 (in all or some of the pad circuits in pad circuit 300), vdd2 I / O control circuit 304 outputs the bit ID of the bit to be programmed. (For example, if control register 112 includes nine bits, the bit ID can be a four-bit signal, where 0x0000 represents bit 0, 0x0001 represents bit 1, and so on.) The vdd2 I / O configuration circuit also includes a write output and a read output; to program or read a control register bit, the vdd2 I / O configuration circuit transmits a pulse on the write or read output, respectively.

[0056] The bit ID, write output, and read output are input to a voltage level shifter 306 which converts vdd2 to the write and read conductors, and vdd2 bit ID to the corresponding vdd1 write, read, and bit ID signals.

[0057] The vdd1 domain bit ID, read signal, and write signal are connected to all pad circuits 300. A set of voltage level shifters 118 converts the vdd1 domain input and output signals to Vdd2 domain bit input and bit output signals.

[0058] When a write signal is received, the control register 302 is configured to write the logic value present in the vdd1 domain bit output conductor to the flip-flop corresponding to the input ID. When a read signal is received, the control register drives the vdd1 domain bit input conductor with the data stored in the flip-flop corresponding to the input ID. The Vdd1-vdd2 voltage level shifter 118 translates data to be written to the flip-flop from the vdd2 domain to the vdd1 domain, and translates data read from the flip-flop from the vdd1 domain to the vdd2 domain.

[0059] Thus, using a small number of voltage shifters, all control register bits can be read and written; for any number of GPIO buffers (since all GPIOs are written simultaneously), the number of write pulses to configure all n bits of all GPIOs is n; and the number of read pulses to read all n register bits of all GPIOs is again n.

[0060] Figure 3B 1 is a block diagram schematically illustrating a pad circuit 300 according to an embodiment of the present disclosure. The pad circuit includes a pad 102, an I / O buffer 104 (both in Figure 1 3 ). The control register 302 includes control bits stored in the flip-flop 350 to control the configuration of the I / O buffer 104. Figure 3B In the example embodiment shown in FIG, there are nine flip-flops 350 to configure the nine control inputs of the I / O buffer 104 (e.g., Figure 2 nine control inputs as described).

[0061] The pad circuit 300 also includes a read and write decoder 351 that drives the write bus (w1 to w9) and the read bus (R0 to R9). When the write input is set, the read and write decoders each drive one of the write bus conductors to the ID input high; conversely, when the read input is high, the read and write decoders drive one of the read bus conductors high according to ID (in some embodiments, the write input signal is a write pulse, and the selected write bus conductor is pulsed).

[0062] Flip-flop 350 is a D-type flip-flop with a clock input and a data input. The D inputs of all nine flip-flops are connected to the bit output conductor, while the clock inputs of the flip-flops are connected to the corresponding write bus conductor output by decoder 351. Therefore, when a pulse is present on one of the write bus conductors, the corresponding flip-flop will latch the bit output data.

[0063] The output of flip-flop 350 is wired to the input of tri-state buffer 352, and the output of tri-state buffer is connected to the bit input signal. The enable input of buffer 352 is connected to the read bus conductor. Therefore, when read and write decoder 351 asserts one of the read bus conductors, the corresponding tri-state buffer 352 will drive the logic value of the corresponding flip-flop on the bit input conductor.

[0064] In some embodiments, to avoid contention on the bit input conductors, a multiplexer is added to pad circuit 300 that selects the drive source for the bit input conductors from one of flip-flops 350 or (if no read bus conductor is active) from input buffer 204 in response to the read bus conductors; in other embodiments, control register 302 forces the input buffers of I / O buffer 104 to a closed state (e.g., disabling the buffers' bit input drive) when any of the read bus conductors is active.

[0065] exist Figure 3A and Figure 3B The configuration of IC 100 including pad circuit 300 shown in FIG and described herein is cited as an example. In alternative embodiments, other configurations may be used. For example, in some embodiments, decoder 351 transmits a single hot pulse (e.g., nine bits) on the register select bus and transmits a single write signal; if the write is valid, control register 302 will always read register data onto the bus input wire and write the register bit from the bit output. In an embodiment, there is a single decoder 351 shared by all or some of the I / O circuits in I / O circuit 300.

[0066] In other embodiments of the present disclosure, a single write pulse can be used to write all bits of a GPIO control register. This is useful when there are a small number of configurations for all GPIOs in an IC (e.g., one set of outputs, one set of Schmitt inputs, and one set of non-Schmitt inputs).

[0067] Figure 4 is a block diagram schematically illustrating a bit-parallel GPIO configuration in IC 100 according to an embodiment of the present disclosure. Vdd2 I / O configuration circuitry 402 drives a vdd2 control register bus (including the desired values ​​for all control register bits) and a write enable signal, which is coupled to a voltage level shifter 404; the voltage level shifter generates a corresponding vdd1 domain control register data bus and a corresponding vdd1 write enable signal.

[0068] The Vdd2 I / O configuration circuit 402 also transmits a write pulse on the bit output wire of the GPIO buffer to which the control register bus should be written.

[0069] IC 100 includes pad circuits 406, each of which includes a pad 102 and an I / O buffer 104 ( Figure 1 ); and a bit-parallel programmable control register 408, the bit-parallel programmable control register being configured to write to all register bits in parallel in response to a write pulse on the bit output wire.

[0070] Therefore, all GPIO buffers of an IC with the same configuration can be programmed with a single write pulse.

[0071] For simplicity, Figure 4 The example embodiment shown in does not show circuitry for reading the control register bits. In some embodiments, the bits do not need to be read; in other embodiments, a circuit similar to that described above with reference to FIG. Figure 3A and Figure 3B The described read mechanism can be used to serially read the bits. In other embodiments, a read bus and read enable are added, and the control bits (of a single GPIO at a time) can be read in parallel.

[0072] exist Figure 4 The configuration of IC 100 shown in FIG and described above is cited as an example. In alternative embodiments, other configurations may be used. For example, a write enable may be set on the bit output wire, while a write pulse may be transmitted in parallel to all GPIO buffers.

[0073] Figure 5 is a block diagram schematically illustrating a GPIO configuration in a system on a chip (SoC) 500 according to an embodiment of the present disclosure. In an embodiment, SoC 500 may include any kind of digital and analog circuitry, including but not limited to one or more central processing units (CPUs), graphics processor units (GPUs), digital signal processors (GPUs), wireless modems, neural networks, and many other circuits. Figure 5 In the example embodiment shown, SoC 500 includes a plurality of processing cores 502 .

[0074] SoC 500 includes two voltage domains—a Vdd1 voltage domain for communicating with external circuits and a Vdd2 voltage domain for processing core 502. In one embodiment, the Vdd1 voltage is substantially higher than Vdd2. In an exemplary embodiment, the Vdd1 voltage may be 5V to 10V, while Vdd2 may be 0.6V (in some embodiments, an intermediate voltage shifter shifts the 0.6V signal to an intermediate 0.8V domain). In some embodiments, SoC 500 may include additional Vdd domains for circuits that may require other operating voltages.

[0075] To communicate data with external circuitry (e.g., integrated circuits) outside the SoC (not shown), the processor 502 is coupled to a vdd2 domain GPIO control circuit 504 that communicates input and output between the processing core and the external circuitry. The GPIO control circuit transmits and receives the vdd2 bit line to the I / O circuit 104 (via a vdd1-vdd2 voltage level shifter that converts the vdd2 bit line to the vdd1 bit line (and vice versa). Figure 1 ), which in turn communicates with external circuits.

[0076] The I / O circuits 104 are controlled by vdd1 domain I / O control registers 510. Each I / O control register has multiple bits to control multiple (e.g., nine or eleven) functions of the corresponding I / O circuit. To configure the I / O control registers, the GPIO control circuit 504 transmits common GPIO configuration control signals (vdd2 domain) to the vdd1-vdd2 voltage level shifter, which converts these signals into corresponding vdd1 group GPIO configuration control signals.

[0077] In some embodiments, the GPIO configuration control signal includes a bit ID indicating one of an I / O control register bit, a write signal, and a read signal (similar to the above reference to Figure 3A In other embodiments, the GPIO configuration control signal may include a control bit value and a write enable indication (similar to Figure 4 mechanism); in other embodiments, any other suitable combination of configuration information may be used.

[0078] In some embodiments, the vdd1 GPIO configuration control signal is input to a vdd1 configuration decode circuit, which outputs a vdd1 GPIO configuration bus. In other embodiments, the GPIO configuration bus comprises a one-hot bus that indicates the bit of the I / O control register to be programmed (concurrently for all I / O control registers). In other embodiments, all bits of the I / O control register will be programmed concurrently, and the GPIO configuration bus indicates the programmed value for all bits. In one embodiment, configuration decode circuit 508 is not used; instead, the GPIO configuration bus comprises a vdd1 common configuration control.

[0079] The GPIO configuration bus is input to the I / O control registers 510. Each I / O control register includes a flip-flop for storing I / O buffer control bits and read / write logic for writing to and reading from the flip-flop in response to the decoded GPIO configuration bus and the bit output signal. In some embodiments, the decoded GPIO configuration bus indicates the control register bit to be programmed, and for each control register, the bit output signal indicates the logic value to be programmed. In other embodiments, the decoded GPIO configuration bus indicates the values ​​to be programmed into all bits of the control register, and the bit output line indicates whether the corresponding control register should be programmed. In one embodiment, the GPIO configuration bus includes a vdd2 write pulse that is converted by a vdd1-vdd2 voltage shifter into a vdd1 write pulse; the GPIO configuration bus includes a write pulse that is subsequently used to time writes to the register. In another embodiment, the write pulse is transmitted on the bit output line, and in other embodiments, a combination of the write pulse and a write enable signal may be used to transmit this combination on the GPIO configuration bus and / or the bit output signal.

[0080] In some embodiments, the GPIO control circuitry can read the configuration control register. In one embodiment, the GPIO transmits a vdd2 read signal; a vdd1-vdd2 voltage shifter converts the read signal to a vdd1 read signal, which the configuration decoder circuitry transmits to the I / O control register. In one embodiment, the I / O control register transmits stored configuration data on a bit input line; in another embodiment, the stored configuration data is transmitted on a GPIO configuration bus.

[0081] Figure 5 The configuration of SoC 500 shown and described above is an example cited for conceptual clarity only. In alternative embodiments, other configurations may be used. For example, in some embodiments, there may be more than one configuration decoding circuit, each controlling the configuration of a separate group of physically adjacent GPIOs. In one embodiment, the I / O control registers are configured concurrently for all control register bits, while being read one bit at a time.

[0082] Bit-parallel versus bit-serial considerations

[0083] To choose between bit-serial and bit-parallel I / O configuration implementations, consider the following:

[0084] In terms of programming time, programming the control registers of all GPIOs takes n write cycles using a bit-serial implementation and m write cycles using a bit-parallel implementation, where n is the number of control register bits and m is the number of I / O circuits.

[0085] According to the voltage level shifter, in a bit serial implementation, the vdd2 circuit uses log2n wires (rounded to the nearest integer) to transmit the bit identifier ID, while in a bit parallel implementation, a bus of n vdd2 wires is used.

[0086] Finally, in a bit-parallel implementation, reading of the control register bits is more complex.

[0087] Figure 6A FIG6 is a flowchart 600 schematically illustrating a method for cross-voltage domain bit-serial GPIO configuration in an IC according to an embodiment of the present disclosure. The flowchart consists of a vdd2 I / O configuration circuit 304, a voltage level shifter 118, a voltage level shifter 306, and a decoder 308 (all in FIG6). Figure 3A ) is executed.

[0088] The flowchart begins at the encode control register next bit ID operation 602, where the vdd2 I / O configuration circuit outputs the bit ID corresponding to the next control register bit to be programmed (starting with the first bit). Next, at the transfer bit value operation 604, the vdd2 I / O configuration circuit transfers the logic value to be programmed to the selected control register bit on the bit output wires for all GPIOs.

[0089] At voltage shift operation 606, the voltage level shifter then creates a vdd1 version of the bit ID and bit value. At decode operation 608, decoder 306 decodes the bit ID and generates a one-hot bus in which one of the wires corresponding to the control register bit to be programmed is set, while all other bits are cleared. Next, at set control bit operation 610, the control registers of all GPIOs use the data input on the bit output wire to program the register bit corresponding to the set wire of the one-hot bus.

[0090] Finally, in operation 612, which is repeated until the end, the I / O configuration circuit checks whether more control register bits need to be programmed. If so, the flowchart re-enters operation 602 to program the next control register bit. If, in operation 612, the I / O configuration circuit determines that no more bits are to be programmed, the flowchart ends.

[0091] Figure 6B 650 is a flowchart schematically illustrating a method for parallel GPIO configuration of a cross voltage domain in an IC according to an embodiment of the present disclosure. The flowchart is composed of I / O configuration circuit 402, voltage level shifters 118, 404, and control register 408 ( Figure 4 )implement.

[0092] The flowchart begins at a transfer control bit value operation 652, where the I / O configuration circuitry transfers the contents of a control register for a group of GPIOs that should be identically configured (all bits in parallel). Next, at a transfer write indication operation 654, the I / O configuration circuitry transfers an indication (e.g., a logic high) on the bit conductors corresponding to the GPIOs that should be programmed.

[0093] Voltage level shifters 118 and 404 then convert the contents of the vdd1 bit output conductor and the control bus to corresponding vdd2 signals at voltage shift operation 656 .

[0094] Next, the corresponding bit output conductor instructs each of the written I / O configuration registers to write the contents of the control bus to all of its flip-flops in parallel.

[0095] Finally, in operation 660, which is repeated until the end, the I / O configuration circuit checks whether more GPIOs of the same configuration need to be programmed. If so, the flowchart re-enters operation 652 to program the next group of GPIOs. If, in operation 660, the I / O configuration circuit determines that no GPIO groups need to be programmed, the flowchart ends.

[0096] exist Figure 6A and Figure 6B The configurations of the flowcharts 600, 650 shown in FIG. 6 and described above are example configurations cited for clarity. In alternative embodiments, other configurations may be used. In some embodiments, the flowcharts are controlled by dedicated circuitry; in other embodiments, the flowcharts may be controlled by a processor (e.g., Figure 5 3, Figure 4 and Figure 5 between the various units shown in .

[0097] In one embodiment, a hybrid flow chart may be used that programs some of the GPIOs bit-serially and programs other GPIOs in a bit-parallel manner; in another embodiment, some of the bits are programmed serially and other bits are programmed in parallel.

[0098] Although the embodiments described herein are primarily directed to cross-power domain GPIO programming, the methods and systems described herein may also be used in other applications where configuration data is communicated between power domains.

[0099] Figure 7700 is a diagram schematically illustrating various types of systems that may include any of the circuits, devices, or systems discussed above according to embodiments of the present disclosure. Systems or devices 700 that may incorporate or otherwise utilize one or more of the techniques described herein may be used in a wide variety of fields. For example, system or device 700 may be used as part of the hardware of a system such as a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a television 750 (or a set-top box coupled to a television).

[0100] Similarly, the disclosed elements can be used in a wearable device 760, such as a smartwatch or a health monitoring device. In many embodiments, a smartwatch can implement a variety of different functions—for example, access to email, cellular service, a calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0101] The system or device 700 may also be used in a variety of other contexts. For example, the system or device 700 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 770. Furthermore, the system or device 700 may be implemented in a wide range of dedicated everyday devices, including devices 780 commonly found in homes, such as refrigerators, thermostats, security cameras, and the like. The interconnection of such devices is commonly referred to as the "Internet of Things" (IoT). Components may also be implemented in various modes of transportation. For example, the system or device 700 may be used in control systems, guidance systems, entertainment systems, and the like for various types of vehicles 790.

[0102] Figure 7 The applications shown in the figure are merely exemplary and are not intended to limit potential future applications of the disclosed system or device. Other example applications include, but are not limited to, portable gaming devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0103] The present disclosure has described various example circuits in detail above. It is intended that the present disclosure encompass not only embodiments including such circuit systems, but also computer-readable storage media including design information specifying such circuit systems. Thus, the present disclosure is intended to support claims covering not only apparatuses including the disclosed circuit systems, but also storage media that specify the circuit systems in a format identified by a manufacturing system configured to produce hardware (e.g., integrated circuits) including the disclosed circuit systems. Claims to such storage media are intended to cover, for example, entities that produce a circuit design but do not themselves manufacture the design.

[0104] Figure 8 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, semiconductor manufacturing system 820 is configured to process design information 815 stored on non-transitory computer-readable medium 610 and manufacture integrated circuit 830 based on design information 815.

[0105] The non-transitory computer-readable storage medium 810 may include any of various suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 810 may be an installation medium, such as a CD-ROM, floppy disk, or tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, magnetic media, for example, a hard drive or optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 610 may also include other types of non-transitory memory or a combination thereof. The non-transitory computer-readable storage medium 810 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0106] Design information 815 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, and the like. Design information 815 may be used by semiconductor manufacturing system 820 to manufacture at least a portion of integrated circuit 830. The format of design information 815 may be identified by at least one semiconductor manufacturing system 820. In some embodiments, design information 815 may also include one or more cell libraries that specify the synthesis, layout, or both of integrated circuit 830. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies the cell library elements and their connectivity. Design information 815, when obtained separately, may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 815 may specify the circuit elements to be manufactured, but not their physical layout. In such cases, design information 815 may need to be combined with layout information to actually manufacture the specified circuit system.

[0107] In various embodiments, integrated circuit 830 may include one or more custom macrocells, such as memory, analog or mixed-signal circuits, and the like. In such cases, design information 815 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to Graphics Data System II (GDSII) or any other suitable format.

[0108] Semiconductor manufacturing system 620 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 820 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0109] In various embodiments, integrated circuit 830 is configured to operate according to the circuit design specified by design information 815, which may include performing any of the functionality described herein. For example, integrated circuit 830 may include Figure 1 、 Figure 2 Figure 3 Figure 4 and Figure 5 Any of the various elements shown in . In addition, integrated circuit 830 can be configured to perform the various functions described herein in conjunction with other components. In addition, the functionality described herein can be performed by multiple connected integrated circuits.

[0110] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0111] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). An embodiment is different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a specific embodiment," etc., do not necessarily refer to the same embodiment. Numerous possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of this disclosure.

[0112] This disclosure may discuss potential advantages that may result from the disclosed embodiments. Not all implementations of these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. Indeed, there are many reasons why an implementation falling within the scope of the claims may not exhibit some or all of the disclosed advantages. For example, a particular implementation may include additional circuitry outside the scope of this disclosure that, in combination with one of the disclosed embodiments, negates or mitigates one or more of the disclosed advantages. Furthermore, suboptimal design implementation of a particular implementation (e.g., a particular implementation technique or tool) may also negate or mitigate the disclosed advantages. Even assuming a specific implementation of the technique, the realization of an advantage may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, inputs provided to a particular implementation may prevent one or more of the problems addressed by this disclosure from occurring in a particular situation, and as a result, the benefits of its solution may not be realized. In light of the possible existence of factors external to this disclosure, it is expressly stated that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Rather, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from this disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantages often depends on technical realities of additional factors.

[0113] Unless otherwise stated, the embodiments are non-restrictive. That is, the disclosed embodiments are not intended to limit the scope of claims drafted based on this disclosure, even when only a single example is described with respect to a particular feature. The embodiments disclosed herein are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art knowing the beneficial effects of this disclosure.

[0114] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be formulated during the prosecution of this application (or an application claiming priority thereto) directed to any such combination of features. Specifically, with reference to the appended claims, features of dependent claims may, where appropriate, be combined with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may, where appropriate, be combined.

[0115] Thus, while the appended dependent claims can be drafted such that each dependent claim is dependent on a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0116] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0117] ***

[0118] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0119] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim, without accompanying context, does not exclude additional instances of that item. A "plurality" of an item refers to a group of two or more of the items.

[0120] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0121] The terms "include" and "including" and their forms are open ended and mean "including, but not limited to."

[0122] When the term "or" is used in this disclosure with respect to a list of options, unless the context provides otherwise, it will generally be understood to be used in an inclusive sense. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either, but not both, x or y" make it clear that "or" is used in an exclusive sense.

[0123] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in that list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0124] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0125] The phrase "based on" or "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based solely on the specified factors or on the specified factors as well as other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover embodiments in which A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0126] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrases do not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with or independent of the specified factors. That is, the effect may be responsive to only those factors, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is the factor that triggers the performance of A or triggers a particular result of A. The phrase does not exclude that the performance of A may also be responsive to some other factor, such as C. The phrase also does not exclude that the performance of A may be performed in response to B and C in combination. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0127] ***

[0128] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Thus, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, a memory storing executable program instructions, etc. The phrase is not used herein to refer to an intangible thing.

[0129] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0130] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA could be "configurable to" perform that function. After being appropriately programmed, the FPGA could then be considered "configured to" perform the particular function.

[0131] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0132] Different “circuits” may be described in this disclosure. These circuits constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits can be custom designed or taken from a standard library. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits.

[0133] Thus, the disclosed circuits / units / components and other elements illustrated in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of that circuit. For example, a particular "decode unit" may be described as performing the function of "processing an instruction's opcode and routing that instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible architectures for the circuit.

[0134] In various embodiments, as discussed in the preceding paragraphs, the arrangement of circuits, units, and other elements defined by the functions or operations they are configured to implement, with respect to one another and the manner in which such circuits / units / components interact, forms a microarchitectural definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitectural definition. Thus, a microarchitectural definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitectural definition. That is, a person skilled in the art, armed with a microarchitectural definition provided in accordance with the present disclosure, can, without undue experimentation and with the application of ordinary skill, implement the structure by decoding a description of the circuits / units / components in a hardware description language (HDL) such as Verilog or VHDL. HDL descriptions are often expressed in a manner that can be visualized as functional. However, for those skilled in the art, the HDL description is a means for translating the structure of a circuit, unit, or component into the next level of implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce the integrated circuit. Some hardware circuits, or portions thereof, may also be custom designed in the schematic editor and captured into the integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between the transistors and the circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA) and implemented in the FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to situations where the circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at a different stage in the circuit implementation process.

[0135] The fact that many different low-level combinations of circuit elements can be used to achieve the same specifications of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell libraries available for a particular project, and so on. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0136] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Consequently, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. An integrated circuit IC, comprising: an input / output (I / O) interface coupled to the first voltage domain and configurable by a set of control bits; a second domain circuit coupled to the second voltage domain and configured to generate a bit value for a control bit of the control bits, generate a multi-bit identifier (ID) for the control bit, and transmit the bit value and the multi-bit ID; and A first domain circuit is coupled to the first voltage domain and is configured to receive the bit value and the multi-bit ID, identify the control bit from the multi-bit ID, and configure the control bit of the I / O interface with the bit value. 2 . The IC of claim 1 , further comprising a plurality of level shifters configured to transfer the bit value and the multi-bit ID from the second domain circuit to the first domain circuit. 3 . The IC of claim 2 , wherein the number of the level shifters allocated for transmitting the multi-bit ID is smaller than the number of the control bits.

4. The IC of any one of claims 1 to 3, further comprising a second I / O interface coupled to the first voltage domain, wherein the second domain circuitry is further configured to send a second bit value, and the first domain circuitry is configured to configure the control bit of the second I / O interface with the second bit value. 5 . The IC of claim 1 , wherein the first domain circuit comprises a plurality of storage elements configured to hold respective bit values ​​of the control bits.

6. The IC of any one of claims 1 to 3, wherein the second domain circuitry comprises one or more processor cores configured to communicate with the I / O interface.

7. The IC of any one of claims 1 to 3, wherein a maximum voltage of the first voltage domain exceeds an operating voltage of the second voltage domain by at least five times.

8. An integrated circuit (IC), comprising: a plurality of input / output (I / O) interfaces coupled to the first voltage domain and each configurable by a corresponding set of control bits; a second domain circuit coupled to a second voltage domain and configured to generate a corresponding bit value for the control bit, generate an indication specifying a subset of one or more of the I / O interfaces to be configured with the bit value, and transmit the bit value and the indication; and A first domain circuit is coupled to the first voltage domain and is configured to receive the bit value and the indication, identify the subset of I / O interfaces from the indication, and configure the I / O interfaces in the subset with the bit value. 9 . The IC of claim 8 , further comprising a plurality of level shifters configured to transfer the bit value and the indication from the second domain circuit to the first domain circuit.

10. The IC of claim 8 or 9, wherein the first domain circuit comprises a plurality of storage elements configured to hold the respective bit values ​​of the control bits.

11. The IC of claim 8 or 9, wherein the second domain circuitry comprises one or more processor cores configured to communicate with the I / O interface.

12. The IC of claim 8 or 9, wherein a maximum voltage of the first voltage domain exceeds an operating voltage of the second voltage domain by at least five times.

13. A method comprising: operating an input / output (I / O) interface coupled to the first voltage domain and configurable by a set of control bits; generating, using second domain circuitry coupled to a second voltage domain, a bit value for a control bit of the control bits, generating a multi-bit identifier (ID) for the control bit, and transmitting the bit value and the multi-bit ID; as well as Using first domain circuitry coupled to the first voltage domain, the bit value and the multi-bit ID are received, the control bit is identified from the multi-bit ID, and the control bit of the I / O interface is configured with the bit value. 14 . The method of claim 13 , further comprising transferring the bit value and the multi-bit ID from the second domain circuit to the first domain circuit using a plurality of level shifters. 15 . The method of claim 14 , wherein the number of the level shifters allocated for transmitting the multi-bit ID is smaller than the number of the control bits.

16. The method according to any one of claims 13 to 15, further comprising: a second I / O interface operatively coupled to the first voltage domain; transmitting a second bit value using the second domain circuit; as well as The control bits of the second I / O interface are configured with the second bit value using the first domain circuitry.

17. The method of any one of claims 13 to 15, further comprising using a plurality of storage elements in the first domain circuit to hold respective bit values ​​of the control bits.

18. The method of any one of claims 13 to 15, wherein generating and transmitting the bit value and the multi-bit ID comprises communicating with the I / O interface using one or more processor cores in the second domain circuitry.

19. The method of any one of claims 13 to 15, wherein a maximum voltage of the first voltage domain exceeds an operating voltage of the second voltage domain by at least five times.

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