Instruction set system and CPU system based on RISC architecture

Abstract

The invention discloses an instruction set system and a CPU (central processing unit) system based on an RISC (Reduced Instruction Set Computer) architecture, which are applied to a system of the RISC architecture. Instruction set coding is in a 32-bit equal-length instruction set coding format and comprises an operation code field with variable length, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit number field, an immediate number field, a process field, a time counting field and a mode field. The operation code fields with different bit lengths are combined with at least one field in the fields, or all the operation code fields form different instruction coding format types, and the operation code fields are used for executing preset operation instructions. Compared with the traditional instruction set operation, the method can be realized by needing fewer instructions, so that the instruction execution times are reduced, the operation speed is improved, complex operation can be realized by only needing one instruction, the occupied storage space is reduced, the programming difficulty is reduced, and the program performance is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of processor microstructure, and in particular to an instruction set system and a CPU system based on a RISC architecture. Background Art

[0002] In the process of continuous development of computer technology, the instruction set system plays a vital role as the basis for the operation of computer processors. As an important part of the computer structure system, instruction set technology is currently divided into two categories according to the technical characteristics of instruction sets: Complex Instruction Set Computing (CISC) and Reduced Instruction Set Computing (RISC).

[0003] Traditional CISC dominated the early development of computers, but with the advancement of technology, some of its inherent defects gradually emerged. The CISC instruction set system has an irregular instruction length and a complex instruction format, which requires more hardware resources and time for the processor to decode and execute instructions, thus affecting the performance and efficiency of the system.

[0004] In certain complex computing tasks, RISC instruction set systems may require more instruction combinations to complete the work, which increases the difficulty of programming. For example, in the operation instructions, 16-bit operands are usually operated on each other. If the high 8 bits need to be operated separately, shifting, separate logical operations, and separate assignment combinations are required to achieve this. Combination control requires a lot of space for calculations, low operating efficiency, and is cumbersome and complicated for developers. Summary of the invention

[0005] The present invention provides an instruction set system and a CPU system based on a RISC architecture, which improve the degree of program parallelism and reduce the need for a large number of combinations to realize program operation, thereby reducing the storage space occupied by the program, thereby reducing the difficulty of programming and improving program performance.

[0006] According to one aspect of the present invention, there is provided an instruction set system based on a RISC architecture, which is applied to a system with a RISC architecture, and the instruction set system comprises: instruction set encoding; the instruction set encoding is a 32-bit equal-length instruction set encoding format, including an opcode field of indefinite length, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field, a process field, a time count field and a mode field; an instruction encoding format type consisting of opcode fields of different bit lengths combined with at least one of the above fields, or all consisting of opcode fields, for executing preset operation instructions.

[0007] Optionally, the instruction set encoding includes at least 8 instruction encoding format types, namely a first instruction encoding format, a second instruction encoding format, a third instruction encoding format, a fourth instruction encoding format, a fifth instruction encoding format, a sixth instruction encoding format, a seventh instruction encoding format and an eighth instruction encoding format, each instruction encoding format type is composed of different combinations of fields in an opcode field, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field process field, a time count field and a mode field of different bit lengths to execute different preset operation instructions.

[0008] Optionally, the first instruction encoding format includes a 4-bit opcode field, a 4-bit bit field, a 13-bit address offset field, a 10-bit first register index field and a 1-bit pointer field; the first instruction encoding format is used to execute the following preset operation instructions: encode a conditional jump instruction that reads the bit field in the register to determine whether to jump to the offset address and whether to increase or change the PC pointer.

[0009] Optionally, the second instruction encoding format includes a 4-bit opcode field, a 1-bit storage field, a 16-bit immediate field, a 10-bit first register index field and a 1-bit return field; the second instruction encoding format is used to execute the following preset operation instructions: encoding immediate arithmetic and logical operation instructions that determine whether to return after executing the instruction based on register values ​​and immediate numbers as operands, operation storage addresses and return fields.

[0010] Optionally, the third instruction encoding format includes a 6-bit operation code field, a 10-bit first register index field and a 1-bit return field; the third instruction encoding format is used to execute the following preset operation instructions: encoding a control transfer instruction that increases the PC pointer according to the register value and determines whether to return to the address after executing the instruction according to the return field.

[0011] Optionally, the fourth instruction encoding format includes a 6-bit opcode field, a 4-bit process field, a 10-bit time count field and a 1-bit return field; the fourth instruction encoding format is used to execute the following preset operation instructions: encode a thread instruction that enters the program with the time count field of the process field.

[0012] Optionally, the fifth instruction encoding format includes a 6-bit opcode field, a 1-bit storage field, a 2-bit mode field, a 10-bit first register index field, a 10-bit first register index field and a 1-bit return field; the fifth instruction encoding format is used to execute the following preset operation instructions: encoding a plurality of combinational arithmetic and logic operation instructions that use the first register index field as the source register and the second register index field as the target register, determine the mode according to the mode field to perform operations and set the storage address to store the results, and determine whether to return after executing the instruction according to the return field.

[0013] Optionally, the sixth instruction encoding format includes a 6-bit operation code field, a 1-bit storage field, a 2-bit mode field, a 4-bit bit field, a 10-bit first register index field and a 1-bit return field; the sixth instruction encoding format is used to execute the following preset operation instructions: encoding a multi-state displacement instruction with a register and a bit field of the required number of displacements and a displacement mode, setting a storage address to store the result and judging whether to return after executing the instruction based on the return field.

[0014] Optionally, the seventh instruction encoding format includes an operation code field consisting of a 6-bit length and an address offset field consisting of a 13-bit length, and the eighth instruction encoding format includes an operation code field consisting of a 6-bit length; the seventh instruction encoding format is used to execute the following preset operation instructions: the encoding includes an unconditional jump instruction with a register as the base address and the operation code field as the offset; the eighth instruction encoding format is used to execute the following preset operation instructions: the encoding includes program return instructions, miscellaneous instructions and system special operation instructions.

[0015] According to another aspect of the present invention, a RISC architecture-based CPU system is provided, the system comprising a RISC architecture-based CPU and an instruction set system based on the RISC architecture as described in any embodiment of the present invention, the CPU being used to run the RISC architecture-based instruction set system.

[0016] The technical solution of the embodiment of the present invention is applied to a system with a RISC architecture, and the instruction set system includes: instruction set encoding; the instruction set encoding is a 32-bit equal-length instruction set encoding format, including an opcode field of indefinite length, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field, a process field, a time count field, and a mode field; the opcode field of different bit lengths is combined with at least one of the above fields, or all of the opcode fields are composed of different instruction encoding format types, which are used to execute preset operation instructions. Compared with traditional instruction set operations, fewer instructions are required to implement, the number of instruction executions is reduced, the operation speed is improved, only one instruction is needed to implement complex operations, and the storage space occupied is reduced, thereby reducing the programming difficulty and improving the program performance.

[0017] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 It is a schematic diagram of the encoding format of an instruction set system based on RISC architecture provided by the present invention;

[0020] Figure 2 It is a schematic diagram of a coding format of a first instruction coding format in an instruction set system based on a RISC architecture provided by the present invention;

[0021] Figure 3 It is a schematic diagram of a coding format of a second instruction coding format in an instruction set system based on a RISC architecture provided by the present invention;

[0022] Figure 4 It is a schematic diagram of the encoding format of a third instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention;

[0023] Figure 5 It is a schematic diagram of the encoding format of a fourth instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention;

[0024] Figure 6It is a schematic diagram of the encoding format of the fifth instruction encoding format in an instruction set system based on RISC architecture provided by the present invention;

[0025] Figure 7 It is a schematic diagram of the encoding format of the sixth instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention;

[0026] Figure 8 It is a schematic diagram of the encoding format of the seventh instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention;

[0027] Fig. 9 It is a schematic diagram of the encoding format of the eighth instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention;

[0028] Fig.10 It is a structural schematic diagram of a CPU system based on RISC architecture provided by the present invention. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] Figure 1It is a schematic diagram of the encoding format of an instruction set system based on a RISC architecture provided by the present invention, wherein Type1-Type8 represent different instruction encoding format types. Applied to a system with a RISC architecture, the instruction set system includes: instruction set encoding, the instruction set encoding is a 32-bit equal-length instruction set encoding format, including an opcode field of variable length, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field, a process field, a time count field, and a mode field; an opcode field of different bit lengths combined with at least one of the above fields, or all of which are composed of opcode fields, and different instruction encoding format types are used to execute preset operation instructions.

[0032] Among them, instruction set encoding refers to binary encoding of instructions. The instruction set encoding format of 32 bits of equal length means that each instruction is represented by a 32-bit binary number, and different bit segments represent different instruction information, such as operation code, register index, address offset, etc. The operation code field is used to specify the type of operation to be performed. The operation code determines the specific function of the instruction, such as addition, subtraction, jump, etc. The register index field is used to specify the number of the register. The first register index field and the second register index field are used to specify the first and second registers that the operation instruction needs to operate, respectively. Through the index value, the CPU can access a specific register to obtain an operand or store an operation result. The address offset field is used to indicate the offset of the address in addressing instructions. The pointer field refers to the PC pointer field, that is, the program counter pointer, which is used to store the address of the next instruction to be executed. It will be adjusted according to specific rules when executing a jump instruction, etc. The return field is used for the return operation during the execution of the instruction set. The storage field is used to determine the storage location of the operation instruction. The bit field is used to specify the bit or number of bits of the accessed operand. It can be used to judge conditions in jump instructions and to indicate the number of displacements in shift instructions. The immediate field is used to store immediate values ​​and directly provide operands for instruction operations without obtaining them from registers. The process field is used to provide the number of operation processes for process instructions and is used to manage and control processes in the system. The time count field is used to count process instructions, for example, to record the time of process execution or specific counting information. The mode field is used to determine the specific mode of instruction execution. In calculation instructions, different calculation methods are determined, such as the high 8 bits, low 8 bits or 6 bits of the operand; in displacement instructions, which mode of displacement operation is used. Instruction encoding format type refers to different instruction encoding methods composed of opcode fields of different bit lengths combined with at least one field in other fields, or all composed of opcode fields. Different encoding format types correspond to different instruction functions and operations. Preset operation instructions refer to various pre-set instructions, which are represented and executed through instruction set encoding. Various computer operations such as arithmetic operations, logical operations, and control flow transfer can be implemented based on preset operation instructions.

[0033] Optionally, the first register index field Ga is a fixed 10-bit length, indicating that the operation instruction needs to operate the index value of the first register, which is used to specify that the CPU access one of the 1024 registers to obtain the first operand or to store the operation result.

[0034] Optionally, the second register index field Gb is a fixed 10-bit length, indicating that the operation instruction needs to operate the index value of the first register, and is used to specify that the CPU access one of the 1024 registers to obtain the second operand.

[0035] Specifically, the first register index field Ga and the second register index field Gb are both fixed 10 bits in length. This means that the range they can represent is sufficient to specify that the CPU access one of up to 1024 registers. For example, by encoding these 10 bits differently, a specific register can be accurately located. When executing an operation instruction, Ga is used to specify the register that obtains the first operand or the register that stores the operation result. Similarly, Gb is used to specify the register that obtains the second operand.

[0036] Optionally, the address offset field Offset is a fixed 13-bit length, and the address offset Offset represents the address offset of addressing instructions (including jump instructions and memory access instructions), and is used to provide an address offset for jump instructions or memory access instructions to generate a target address.

[0037] Specifically, the address offset field Offset is a fixed 13-bit length. It is used to represent the address offset, and by combining with other address information, the target address can be generated. For example, in a jump instruction, Offset can determine the offset of the new address to jump to relative to the current address, thereby realizing the control flow transfer of the program. In a memory access instruction, Offset can be used to determine the offset of the memory address to be accessed relative to a certain base address.

[0038] Optionally, the PC pointer field C is a fixed 1-bit length, indicating that the PC instruction is operated to increase and store the current address, and is used by the CPU to determine whether the jump instruction needs to increase the PC value or keep the PC value unchanged and store the current address.

[0039] Specifically, the PC pointer field C is a fixed 1-bit length. When the CPU executes a jump instruction, the PC pointer field C is used to determine whether to increase the PC value or keep the PC value unchanged. If the C bit is a specific value, it may mean that the PC value needs to be increased to point to the address of the next instruction; if it is another value, it means that the current PC value remains unchanged. In addition, the C bit is also used to store the current address so that it can be restored to the previous execution position when necessary.

[0040] Optionally, the return field R is a fixed 1-bit length, indicating that the operation instruction returns to the previous level PC instruction minus one level, which is used for instruction set return.

[0041] Specifically, the return field R is a fixed 1-bit length. During the execution of the instruction set, when it is necessary to return to the previous level, the R bit comes into play. If the R bit is set to a specific value, the operation instruction will return to the previous level PC instruction and decrease one level to implement the return operation of the program. The return field R can ensure that the program can correctly return to the call point and continue execution during function calls and nested instruction execution.

[0042] Optionally, the storage field D is a fixed 1-bit length, indicating whether the operation instruction is stored in the first operand or a general register, and is used for calculating whether the result of the instruction or the displacement instruction is stored in the first operand or a general register.

[0043] Specifically, the storage field D is a fixed 1-bit length. In a calculation instruction or a displacement instruction, the D bit is used to determine whether the storage result is stored in the first operand or a general register. If the D bit is in one state, the result will be stored in the location specified by the first operand; if it is in another state, it will be stored in a general register.

[0044] Optionally, the bit field Bit is a fixed 4-bit length, indicating the bit number or number of the access operand, and is used to determine the bit in a jump instruction or the number of displacements in a shift instruction.

[0045] Specifically, the bit field Bit is a fixed 4-bit length. In a jump instruction, the bit field can be used to determine conditions, such as determining whether to jump based on a specific bit state. In a shift instruction, the Bit field indicates the number of shifts, which determines how many bits the operand needs to be shifted. By encoding the 4 bits of the bit field differently, different shift quantities and conditional judgments can be achieved.

[0046] Optionally, the immediate field Imm is a fixed 16-bit length, and the immediate field Imm is used to directly provide operands for instruction operations.

[0047] Specifically, the immediate field Imm is a fixed 16-bit length. The immediate field is used to directly provide operands for instruction operations. In some instructions, an immediate value may be required as an operand for calculation instead of being obtained from a register. The Imm field can store a 16-bit value and directly participate in the operation of the instruction, thereby improving the flexibility and efficiency of the instruction.

[0048] Optionally, the process field Thalt code is a fixed 4-bit length, and the process field Thalt code is used to provide an operation process number for the process instruction.

[0049] Specifically, the process field Thalt code can specify a specific process number or status so that the CPU can manage and control different processes.

[0050] Optionally, the time count field Timeout is a fixed 4-bit length, and the process field Thalt code is used for process instruction counting.

[0051] Specifically, the time count field is also used for process instruction counting, and can help the CPU perform time management and resource allocation by recording the process execution time or specific count information.

[0052] Optionally, the mode field Mode is a fixed 2-bit length, indicating that the instruction set has a total of 4 modes, which are used in calculation instructions to use the high 8 bits of two operands for calculation, the low 8 bits for calculation, or 16-bit calculation, or the high 8 bits of the first operand for the low 8 bits of the second operand. Or used in displacement instructions to use the displacement mode.

[0053] Specifically, in a calculation instruction, the Mode field can determine whether to use the upper 8 bits of the two operands for calculation, the lower 8 bits for calculation, or the 16 bits for calculation, or to use the upper 8 bits of the first operand to operate on the lower 8 bits of the second operand. In a displacement instruction, the Mode field can be used to determine which mode of displacement operation to use. By selecting different modes, different calculation and displacement requirements can be met, improving the flexibility and adaptability of the instruction set.

[0054] Optionally, the instruction set encoding includes at least 8 instruction encoding format types, namely a first instruction encoding format, a second instruction encoding format, a third instruction encoding format, a fourth instruction encoding format, a fifth instruction encoding format, a sixth instruction encoding format, a seventh instruction encoding format and an eighth instruction encoding format, each instruction encoding format type is composed of different combinations of fields in an opcode field, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field process field, a time count field and a mode field of different bit lengths to execute different preset operation instructions.

[0055] Specifically, in a system based on the RISC architecture, the design of the instruction set encoding is intended to achieve efficient instruction execution and flexible function expansion. The instruction set encoding includes at least eight different instruction encoding format types, namely the first to eighth instruction encoding formats. Each instruction encoding format type is composed of different field combinations in the opcode field, the first register index field, the second register index field, the address offset field, the pointer field, the return field, the storage field, the bit field, the immediate field, the process field, the time count field and the mode field. The various instruction encoding format types generated by the combination of different fields can realize a rich variety of preset operation instructions, providing the system with powerful computing and control capabilities.

[0056] Optional, Figure 2The present invention provides a schematic diagram of the encoding format of the first instruction encoding format in an instruction set system based on a RISC architecture, wherein the first instruction encoding format includes a 4-bit operation code field, a 4-bit median field, a 13-bit address offset field, a 10-bit first register index field and a 1-bit pointer field; the first instruction encoding format is used to execute the following preset operation instructions: encoding a conditional jump instruction that reads the median field in a register to determine whether to jump to an offset address and whether to increase or change a PC pointer.

[0057] Specifically, when the preset operation instruction is a conditional jump instruction, the register to be conditionally judged is first determined according to the first register index field Ga. Then the value of a single bit specified by the bit field Bit in the register is read as a basis for determining whether to jump. If the value of the bit satisfies the preset jump condition (for example, jump when the bit is 1), the target address to jump to is calculated in combination with the address offset field Offset and the current PC value. Finally, the change in the PC value after the jump can be determined according to the value of the PC pointer field C. If the C bit is a specific value, the PC value increases and points to the address of the next instruction; if the C bit is another value, the PC value remains unchanged.

[0058] To summarize, the first instruction encoding format is based on the fact that one instruction can complete the operations of judging, jumping and modifying the PC value. Compared with the traditional single-bit judgment and jumping that require multiple instructions, it reduces the number of instruction executions and improves the computing speed. Only one instruction is needed to implement complex operations, reducing the occupied storage space.

[0059] Optional, Figure 3 This is a schematic diagram of the encoding format of the second instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention. The second instruction encoding format includes a 4-bit operation code field, a 1-bit storage field, a 16-bit immediate field, a 10-bit first register index field and a 1-bit return field; the second instruction encoding format is used to execute the following preset operation instructions: encoding an immediate arithmetic and logical operation instruction that determines whether to return after executing the instruction based on register values ​​and immediate numbers as operands, operation storage addresses and return fields.

[0060] Among them, different encodings of the opcode field can correspond to different arithmetic or logical operations, such as addition, subtraction, and, or, etc. The storage field determines the storage location of the operation result. If the storage field D is in a state (such as 0), it means that the result is stored in the register corresponding to the first operand, that is, the register specified by the first register index word Ga. If the storage field D is in another state (such as 1), it means that the result is stored in a general register. The immediate value can be a specific value, such as an integer, a constant, etc., and the corresponding operation is performed with the value in the register during the operation. The first register index field Ga is used to specify the register involved in the operation. Through this index value, the CPU can accurately access a specific register and take out a value from it as another operand to participate in the operation. For example, in an addition operation, the value in the register is added to the immediate value in the immediate field Imm. The return field is used to determine whether to return after executing the instruction. If the return field R is in a state (such as 0), it means that it will not return after executing the instruction, and the program continues to execute the next instruction. If the return field R is in another state (such as 1), it means that the instruction will be returned to the previous level after execution.

[0061] Specifically, when the preset operation instruction is an immediate operation bit operation instruction: first determine the specific arithmetic or logic operation to be performed according to the operation code field Opcode. Then, take out a value from the register specified by the first register index field Ga as an operand. At the same time, get the immediate number from the immediate field Imm as another operand. Then, perform the corresponding arithmetic or logic operation according to the operation code, for example, the addition operation is to add the value in the register to the immediate number. Finally, decide whether to store the operation result in the register (the register specified by Ga) or the general register according to the value of the storage field D. And, determine whether to return to the previous level after executing the instruction according to the value of the return field R.

[0062] In summary, the second instruction encoding format directly uses immediate data to participate in the operation, without the need to read additional data from the memory, which improves the operation efficiency. At the same time, one instruction can complete multiple steps from operand acquisition, operation to result storage and return judgment, reducing the time and space overhead of instruction execution.

[0063] Optional, Figure 4 This is a schematic diagram of the encoding format of the third instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention. The third instruction encoding format includes an operation code field with a length of 6 bits, a first register index field with a length of 10 bits, and a return field with a length of 1 bit; the third instruction encoding format is used to execute the following preset operation instructions: encoding a control transfer instruction that increases a PC pointer according to a register value and determines whether to return an address after executing the instruction according to the return field.

[0064] Among them, the opcode is used to specify the specific operation type of the instruction. Different opcodes can correspond to different control transfer methods, such as unconditional transfer, conditional transfer, etc.

[0065] Specifically, when the preset operation instruction is a control transfer instruction, first, it can be determined that this is a control transfer instruction based on the operation code field Opcode, and the specific transfer method can be determined. Then, the value in the register specified by the first register index field Ga is read. Next, the value in the register is subjected to a specific operation with the current value of the program counter (PC), such as adding the value in the register to the PC, thereby realizing the operation of increasing the PC value according to the register value, and transferring the program control to the corresponding new address. Finally, the value of the return field R is used to determine whether to return to the address after executing the instruction. If a return is required, it may be necessary to save information such as the current execution status so that it can be restored and returned at the appropriate time.

[0066] In summary, the third instruction encoding format can achieve a more flexible control flow by using the value in the register to determine the address of the program control transfer, and can dynamically change the transfer target address according to different operating conditions to adapt to various complex program logics.

[0067] Optional, Figure 5 This is a schematic diagram of the encoding format of the fourth instruction encoding format in an instruction set system based on a RISC architecture provided according to the present invention. The fourth instruction encoding format includes an operation code field of 6 bits, a process field of 4 bits, a time count field of 10 bits and a return field of 1 bit; the fourth instruction encoding format is used to execute the following preset operation instructions: encode a thread instruction that enters a program with the time count field of the process field.

[0068] Among them, in the fourth instruction encoding format, the opcode is used to specify the specific operation type of the instruction. Different opcodes can correspond to different thread operation modes, such as starting a thread, switching a thread, etc. The process field Thalt code is used to specify a specific process or thread state. For example, different process field values ​​can represent different thread priorities, thread types and other information to help the CPU determine how to handle the thread. When executing thread instructions, the time count field Timeout can represent the thread's execution time limit, waiting time, etc.

[0069] Specifically, when the preset operation instruction is a thread instruction, first determine that this is a thread-related instruction based on the operation code field Opcode, and determine the specific thread operation mode. Then, read the value of the process field Thalt code to determine the state or attribute of the current thread. For example, determine the priority, type, etc. of the current thread based on the value of the process field. Next, check the value of the time count field Timeout. Compare the Timeout value with the preset time value to determine whether the time count value field exceeds the preset value. If the value of the time count field does not exceed the preset value, the thread may continue to execute or wait. If the value of the time count field exceeds the preset value, according to the specific requirements of the thread instruction, the corresponding operation may be triggered, such as switching to another thread, performing thread scheduling, etc. Finally, determine whether to return or perform other specific operations after executing the instruction based on the value of the return field R.

[0070] In summary, the fourth instruction encoding format can accurately control the execution time of the thread through the time count field, avoiding the thread occupying system resources for a long time or causing deadlock and other problems. By setting the process field and the return field, it is possible to flexibly manage threads according to different thread states and requirements. By reasonably setting the time count field and the process field, the utilization rate of system resources can be improved, ensuring that each thread can be executed at the right time, and improving the overall performance of the system.

[0071] Optional, Figure 6 The present invention is a schematic diagram of the encoding format of the fifth instruction encoding format in an instruction set system based on a RISC architecture, wherein the fifth instruction encoding format includes an operation code field of 6 bits, a storage field of 1 bit, a mode field of 2 bits, a first register index field of 10 bits, a second register index field of 10 bits and a return field of 1 bit; the fifth instruction encoding format is used to execute the following preset operation instructions: encoding a plurality of combinational arithmetic and logic operation instructions, which uses the first register index field as a source register and the second register index field as a target register, determines the mode according to the mode field to perform operations and sets a storage address to store results, and determines whether to return after executing the instruction according to the return field.

[0072] Among them, in the fifth instruction encoding format, the opcode is used to specify the specific operation type of the instruction. The mode field determines the specific mode for performing arithmetic and logical operations. If the value of the mode field is a state (such as 00), it means that the upper 8 bits of the source register (specified by Ga) and the target register (specified by Gb) are used for operation. At this time, the CPU will take out the upper 8-bit values ​​from the source register and the target register respectively to perform the corresponding arithmetic and logical operations. If the value of the mode field is another state (such as 01), it means that the lower 8 bits of the source register and the target register are used for operation. Similarly, the CPU will extract the corresponding lower 8-bit value for operation. If the value of the mode field is a third state (such as 10), it means that the 16 bits of the source register and the target register are used for operation, that is, the value of the entire register is operated. If the value of the mode field is a fourth state (such as 11), it means that the upper 8 bits of the source register and the lower 8 bits of the target register are used for operation.

[0073] Specifically, when the preset operation instruction is a multi-combination arithmetic logic operation instruction, first, determine the specific arithmetic logic operation type to be performed according to the operation code field Opcode. Then determine the source register and the target register through the first register index fields Ga and Gb. Next, determine the operation mode according to the value of the mode field Mode. If it is a high 8-bit operation mode, take out the high 8-bit values ​​from the source register and the target register respectively for operation. If it is a low 8-bit operation mode, extract the corresponding low 8-bit value for operation. If it is a 16-bit operation mode, operate on the value of the entire register. If it is a source high 8-bit and target low 8-bit operation mode, take out the high 8-bit of the source register and the low 8-bit of the target register respectively for operation. After the operation is completed, it can be decided whether to store the result in the source register or the general register according to the value of the storage field D. Finally, determine whether to return to the previous level after executing the instruction according to the value of the return field R.

[0074] In summary, the fifth instruction encoding format can realize a variety of different arithmetic logic operation modes through different settings of the mode field to meet different computing needs. Through the combination of several fields of specific lengths, complex multi-combination arithmetic logic operation functions are realized, the complexity of the instructions is reduced, and it is convenient for the hardware to realize fast instruction decoding and execution.

[0075] Optional, Figure 7The present invention provides a schematic diagram of the encoding format of the sixth instruction encoding format in an instruction set system based on a RISC architecture. The sixth instruction encoding format includes an operation code field of 6 bits, a storage field of 1 bit, a mode field of 2 bits, a digit field of 4 bits, a first register index field of 10 bits and a return field of 1 bit. The sixth instruction encoding format is used to execute the following preset operation instructions: encoding a multi-state displacement instruction using a register and a digit field of the number of displacements required and a displacement mode, setting a storage address to store a result and judging whether to return after executing the instruction according to a return field.

[0076] Specifically, the sixth instruction encoding format can be used to execute displacement instructions. The execution process of the displacement instruction determines the displacement basis with the register and the bit field. Specifically, a register can be determined according to the first register index field Ga, and then combined with the number of displacements specified in the bit field Bit to provide basic data for the displacement operation. When the preset operation instruction is a displacement instruction, the displacement method can be determined according to the mode field. If the mode field Mode indicates that it is a loop without carry, the data is moved in a loop when it is shifted, and the carry is not considered. When it is indicated that it is a loop with carry, the carry situation will be considered in the process of the circular displacement. If the non-circular filling is 0 or 1, then when the non-circular displacement is not carried out, it is 0 or 1 according to the specific situation. Next, the storage address is set, and the storage address can be set to a register or a general register. Then, the value of the return field R is used to determine whether the result or status is returned after the displacement instruction is executed.

[0077] In summary, the sixth instruction encoding format can implement a variety of different displacement operations through one instruction encoding format, thereby reducing the space occupied by the instruction in the memory.

[0078] Optional, Figure 8 This is a schematic diagram of the encoding format of the seventh instruction encoding format in an instruction set system based on a RISC architecture provided by the present invention. The seventh instruction encoding format includes an operation code field of 6 bits and an address offset field of 13 bits. The seventh instruction encoding format is used to execute the following preset operation instructions: the encoding includes an unconditional jump instruction with a register as the base address and an operation code field as the offset.

[0079] Specifically, when executing an unconditional jump instruction, the processor first finds the register used as the base address and reads the value therein. Then, the Offset is added to the value of the base address register to obtain a new target address. The processor will immediately interrupt the current instruction execution process and jump to the new target address to continue executing the program. The instruction set system based on the RISC architecture of the unconditional jump instruction is consistent with the instruction set system based on the RISC architecture described in any of the above embodiments. The specific structure and function of the instruction set system based on the RISC architecture will not be repeated here.

[0080] Optional, Fig. 9 This is a schematic diagram of the encoding format of the eighth instruction encoding format in an instruction set system based on a RISC architecture provided according to the present invention. The eighth instruction encoding format includes an operation code field consisting of a 6-bit length. The eighth instruction encoding format is used to execute the following preset operation instructions: the encoding includes a program return instruction, miscellaneous instructions and system special operation instructions.

[0081] Specifically, the CPU instruction set system based on RISC architecture for return instructions, miscellaneous instructions and system special operation instructions is consistent with the CPU instruction set system based on RISC architecture described in any of the above embodiments. The specific structure and functions of the CPU instruction set system based on RISC architecture will not be repeated here.

[0082] Based on the same concept, in one embodiment, Fig.10 The present invention provides a schematic diagram of a RISC-based CPU system, wherein the CPU system includes a RISC-based CPU and an instruction set system based on the RISC architecture as described in any of the above embodiments, and the CPU is used to run the instruction set system based on the RISC architecture.

[0083] In this embodiment, the instruction set system based on the RISC architecture is consistent with the above-mentioned instruction set system based on the RISC architecture. The specific structure and function can refer to the above-mentioned instruction set system based on the RISC architecture, which will not be repeated here.

[0084] In this embodiment, the CPU system based on RISC architecture includes a CPU of RISC architecture and an instruction set system based on RISC architecture, and the CPU is used to run the instruction set system based on RISC architecture. The instruction set system includes: instruction set encoding, the instruction set encoding is a 32-bit equal-length instruction set encoding format, including an opcode field of variable length, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field, a process field, a time count field and a mode field; an opcode field of different bit lengths combined with at least one of the above fields, or all of which are composed of opcode fields, and different instruction encoding format types are used to execute preset operation instructions.

[0085] It should be noted that the above-mentioned CPU system embodiment and the instruction set system embodiment based on RISC architecture belong to the same concept. The specific implementation process is detailed in the instruction set system embodiment based on RISC architecture, and the technical features in the PU instruction set system embodiment based on RISC architecture are correspondingly applicable in the CPU system embodiment, which will not be repeated here.

[0086] The technical solution of the embodiment of the present invention is applied to a system with a RISC architecture, and the instruction set system includes: instruction set encoding; the instruction set encoding is a 32-bit equal-length instruction set encoding format, including an opcode field of indefinite length, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field, a process field, a time count field, and a mode field; the opcode field of different bit lengths is combined with at least one of the above fields, or all of the opcode fields are composed of different instruction encoding format types, which are used to execute preset operation instructions. Compared with traditional instruction set operations, fewer instructions are required to implement, the number of instruction executions is reduced, the operation speed is improved, only one instruction is needed to implement complex operations, and the storage space occupied is reduced, thereby reducing the programming difficulty and improving the program performance.

[0087] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0088] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An instruction set system based on RISC architecture, characterized in that: Applied to a system of RISC architecture, the instruction set system comprises: instruction set encoding; The instruction set encoding is a 32-bit equal-length instruction set encoding format, including an opcode field of variable length, a first register index field, a second register index field, an address offset field, a pointer field, a return field, a storage field, a bit field, an immediate field, a process field, a time count field and a mode field; it is composed of opcode fields of different bit lengths combined with at least one of the above fields, or all of which are composed of opcode fields. Different instruction encoding format types are used to execute preset operation instructions.

2. The system according to claim 1, characterized in that The instruction set encoding includes at least 8 instruction encoding format types, namely the first instruction encoding format, the second instruction encoding format, the third instruction encoding format, the fourth instruction encoding format, the fifth instruction encoding format, the sixth instruction encoding format, the seventh instruction encoding format and the eighth instruction encoding format. Each instruction encoding format type is composed of different field combinations of operation code fields, first register index fields, second register index fields, address offset fields, pointer fields, return fields, storage fields, bit fields, immediate field process fields, time count fields and mode fields with different bit lengths to execute different preset operation instructions.

3. The system according to claim 2, characterized in that The first instruction encoding format includes a 4-bit operation code field, a 4-bit number of bits field, a 13-bit address offset field, a 10-bit first register index field and a 1-bit pointer field; The first instruction encoding format is used to execute the following preset operation instructions: encoding a conditional jump instruction that reads a median field in a register to determine whether to jump to an offset address and whether to increase or leave a PC pointer unchanged.

4. The system according to claim 2, characterized in that The second instruction encoding format includes an operation code field of 4 bits, a storage field of 1 bit, an immediate field of 16 bits, a first register index field of 10 bits, and a return field of 1 bit; The second instruction encoding format is used to execute the following preset operation instructions: encoding an immediate arithmetic and logic operation instruction that determines whether to return after executing the instruction based on register values ​​and immediate numbers as operands, operation storage addresses, and return fields.

5. The system according to claim 2, characterized in that The third instruction encoding format includes an operation code field of 6 bits, a first register index field of 10 bits, and a return field of 1 bit; The third instruction encoding format is used to execute the following preset operation instructions: encoding a control transfer instruction that increases a PC pointer according to a register value and determines whether to return to an address after executing the instruction according to a return field.

6. The system according to claim 2, characterized in that The fourth instruction encoding format includes an operation code field of 6 bits, a process field of 4 bits, a time count field of 10 bits, and a return field of 1 bit. The fourth instruction encoding format is used to execute the following preset operation instruction: encoding a thread instruction that enters a program with a time count field of a process field.

7. The system according to claim 2, characterized in that The fifth instruction encoding format includes an operation code field of 6 bits, a storage field of 1 bit, a mode field of 2 bits, a first register index field of 10 bits, a first register index field of 10 bits, and a return field of 1 bit; The fifth instruction encoding format is used to execute the following preset operation instructions: encoding a plurality of combinational arithmetic and logic operation instructions that use the first register index field as the source register, the second register index field as the target register, determine the mode to perform operations and set the storage address to store the results according to the mode field, and determine whether to return after executing the instruction according to the return field.

8. The system according to claim 2, characterized in that The sixth instruction encoding format includes an operation code field of 6 bits, a storage field of 1 bit, a mode field of 2 bits, a number of bits field of 4 bits, a first register index field of 10 bits, and a return field of 1 bit. The sixth instruction encoding format is used to execute the following preset operation instructions: encoding a multi-state displacement instruction using a register and a bit field of the required number of displacements and a displacement mode, setting a storage address to store the result and judging whether to return after executing the instruction based on a return field.

9. The system according to claim 2, characterized in that The seventh instruction encoding format includes an operation code field of 6 bits and an address offset field of 13 bits, and the eighth instruction encoding format includes an operation code field of 6 bits; The seventh instruction encoding format is used to execute the following preset operation instructions: the encoding includes an unconditional jump instruction with a register as the base address and an operation code field as the offset; The eighth instruction encoding format is used to execute the following preset operation instructions: the encoding includes program return instructions, miscellaneous instructions and system special operation instructions.

10. A CPU system based on RISC architecture, characterized in that: The system comprises a CPU of RISC architecture and an instruction set system based on RISC architecture as claimed in any one of claims 1 to 9, wherein the CPU is used to run the instruction set system based on RISC architecture.

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