On-orbit integrated circuit aging fault diagnosis method and diagnosis system

Abstract

The invention provides an in-orbit integrated circuit aging fault diagnosis method and diagnosis system, and relates to the technical field of integrated circuit design, and the method comprises the steps: ground training: collecting characteristic parameters, carrying out the characteristic parameter processing based on an SPI protocol algorithm, a digital signal recovery fixed-point decimal algorithm, a wavelet transform filtering algorithm and a deviation standardization algorithm, and carrying out the fault diagnosis; constructing an aging failure fault data set, training through a back propagation algorithm to obtain feed-forward neural network parameters, and transplanting the feed-forward neural network parameters to a feed-forward neural network constructed based on Pytorch and a feed-forward neural network constructed based on FPGA for joint testing; and in-orbit testing: data enters a data buffer area, training data is provided for a learning training module, feedforward neural network parameters are periodically updated by using an exponential weighted moving average algorithm, and the feedforward neural network parameters are transplanted to a feedforward neural network established based on Pytorch and a feedforward neural network established by an FPGA for joint testing. Continuous learning of on-orbit data is realized, and the method adapts to irregular periodic electromagnetic influence of a space environment.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit design, and more specifically, to an on-orbit integrated circuit aging fault diagnosis method and diagnosis system. Background Art

[0002] Integrated circuit performance degradation is one of the key issues affecting the reliability of spacecraft systems. When the feature size enters the deep submicron, effects such as hot carrier injection, negative bias temperature instability, time-dependent dielectric breakdown, and electromigration will cause the performance of metal oxide semiconductor field effect transistors to degrade, the threshold voltage to increase, the circuit delay to increase, and the circuit speed to decrease. Severe degradation may also lead to timing violations, resulting in logical function errors and circuit failures, with catastrophic consequences. Various types of aging failures have become the main failure mechanism of large-scale integrated circuits. Due to the increased integration of integrated circuits, the detection cost (power consumption, area, and detection time) of traditional fault diagnosis methods is getting larger and larger. In addition, the high performance, miniaturization, heterogeneous integration, structural diversification of system integration, and the need to reduce costs in aerospace applications make it difficult for traditional detection methods to meet the high reliability requirements of aerospace applications. The technical solutions for detecting integrated circuit aging failures in the prior art are: (1) The Chinese invention patent with publication number CN118690706A discloses a simulation method and device for integrated circuit aging effects, which relates to the field of integrated circuit technology and is used to optimize the simulation process of integrated circuit aging effects and realize efficient aging effect simulation. The simulation method for integrated circuit aging effects includes: obtaining description parameters of device node waveforms, which are used to characterize information of node waveforms. Then, the corresponding aging model is called according to the description parameters, and the aging model analyzes the description parameters to obtain an approximate aging primitive function of the node waveform. The target aging simulation time is set, and the aging simulation results of the corresponding device are calculated in combination with the fitting parameters of the aging model.

[0003] (2) A Chinese invention patent with publication number CN103116121A discloses a circuit aging test method based on a self-oscillating loop, which is characterized by: selecting an aging characteristic path set T in the circuit to be tested based on static timing analysis and path correlation; maintaining an odd number of logical negations on each path to be tested in the aging characteristic path set T to form a self-oscillating loop; using a test generation method for fixed-type faults to generate a test vector, excite the self-oscillating loop, and generate a test level signal; sampling the self-oscillating loop through a counter to obtain a circuit aging characteristic value and measure the aging degree of the circuit to be tested.

[0004] However, for the integrated circuit components of satellites in orbit, it is difficult to fully simulate the space environment through ground testing. This is because satellites in orbit are subject to periodic influences from nearby celestial bodies during operation. These influences come from solar activity, cosmic rays, and magnetic field changes of other planets. Therefore, an integrated circuit aging diagnosis method that can achieve continuous learning in orbit is needed. Summary of the invention

[0005] To solve the above problems, the technical solution adopted in this application is an on-orbit integrated circuit aging fault diagnosis method, including: Ground training: The acquisition device acquires and converts the characteristic parameters of the module to be tested, and the characteristic parameters are processed based on the characteristic parameter processing module including the SPI protocol algorithm, the digital signal recovery fixed-point decimal algorithm, the wavelet transform filtering algorithm and the deviation normalization algorithm. The neural network aging failure fault data set is constructed according to the measured aging failure parameters after the characteristic parameter processing. The feedforward neural network parameters are obtained through training with the learning training module based on the back propagation algorithm, and the feedforward neural network parameters are transplanted to the feedforward neural network built based on Pytorch and the feedforward neural network built based on FPGA for joint testing; On-orbit test: After feature parameter processing, the data first enters the data buffer that contains the aging failure data set of the ground-trained neural network. The training data is provided from the data buffer to the learning and training module based on the back-propagation algorithm. The feedforward neural network parameters are periodically updated using the exponentially weighted moving average algorithm. The feedforward neural network parameters are transplanted to the feedforward neural network built based on Pytorch and the feedforward neural network built based on FPGA for joint testing.

[0006] Optionally, the feedforward neural network constructed by FPGA includes a double hidden layer feedforward neural network with a 5-2-4-2 structure, whose input layer inputs current and temperature parameters processed by the characteristic parameter processing module, and whose output layer outputs normal and aging failure.

[0007] Optionally, the digital signal recovery fixed-point decimal algorithm includes converting the digital signal converted by the acquisition device into a universal binary number representing the true value of the characteristic parameter based on the conversion principle of the successive approximation analog / digital converter using an inverse formula, and the inverse formula is: ; Where s12-s1 represents the 12-bit digital signal output, V in Indicates input voltage, V in- Indicates the minimum range of input voltage, V ref Indicates the reference voltage.

[0008] Optionally, the wavelet transform filtering algorithm includes using Daubechies wavelet as a wavelet basis to perform multi-scale decomposition of the signal processed by the digital signal recovery fixed-point decimal algorithm into wavelet coefficients through continuous wavelet transform, setting a hard threshold to remove noise in the wavelet coefficients, and reconstructing the signal using the denoised wavelet coefficients.

[0009] Optionally, the data buffer is a fixed-size buffer of a queue structure, and data is periodically extracted from the buffer for model training.

[0010] Optionally, the exponentially weighted moving average algorithm includes initializing an exponentially weighted moving average variable for each parameter in the model, calculating the exponentially weighted moving average gradient, updating the model parameters using the exponentially weighted moving average gradient, and controlling the learning rate according to the performance of the validation set.

[0011] Optionally, controlling the learning rate includes setting a sliding window to store the feedforward neural network training accuracy to build a data buffer, adding new accuracy data to the data buffer, calculating the mean and standard deviation of the data in the buffer, setting a mean control lower limit and a standard deviation control upper limit, and increasing the learning rate when the mean is lower than the mean control lower limit or the mean decreases and the standard deviation is higher than the standard deviation control upper limit.

[0012] Optionally, the learning rate is increased by exponential increase and sudden restart. The learning rate first increases exponentially to 0.1, and then suddenly restarts to 0.001. It is determined whether the accuracy reaches the mean control lower limit, and the process of exponential increase and sudden restart is repeated until the accuracy reaches the mean upper limit.

[0013] Optionally, the aging failure includes four types: hot carrier injection, negative bias temperature instability, time-dependent dielectric breakdown, and electromigration.

[0014] The present application also provides an on-orbit integrated circuit aging fault diagnosis system, which is suitable for performing integrated circuit aging fault diagnosis using any of the above-mentioned integrated circuit aging fault diagnosis methods.

[0015] The beneficial effects of the on-orbit integrated circuit aging fault diagnosis method and diagnosis system provided by the present application are: 1. This on-orbit integrated circuit aging fault diagnosis system is implemented based on FPGA. The overall system structure is simple, low cost, low power consumption, fast detection speed, and high detection accuracy. The neural network algorithm is trained on the PC side. After the training is completed, the parameters are solidified into the FPGA neural network algorithm module, thereby reducing the length of training time and resource consumption, improving diagnostic accuracy, and reducing the power consumption of the overall system. The fault diagnosis algorithm is implemented using a neural network. Compared with traditional diagnostic methods, it greatly reduces the complexity of the diagnostic system. At the same time, it can detect a variety of aging faults and reduce the detection cycle. At the same time, the diagnostic accuracy can reach 99%.

[0016] 2. Basic detection capabilities are provided by ground training results. During on-orbit training, actual on-orbit data is obtained and added to the data buffer that already contains the ground training neural network aging failure data set. Training data is provided from the data buffer to the learning and training module based on the back propagation algorithm. The exponentially weighted moving average algorithm is used to periodically update the feedforward neural network parameters to achieve continuous learning of on-orbit data and adapt to the irregular periodic electromagnetic influences of the space environment. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art.

[0018] Figure 1 This is the overall structure diagram of the system; Figure 2 Design a block diagram for the fault diagnosis algorithm; Figure 3 This is the structural diagram of the fault diagnosis; Figure 4 The simulation waveform of 12-bit serial digital signal receiving multiple SPI transmission cycles in sequence; Figure 5 Simulation diagram of the algorithm for recovering fixed-point decimals from digital signals; Figure 6 This is a simulation diagram of the deviation normalization algorithm; Figure 7 This is a simulation diagram of the feedforward neural network function. DETAILED DESCRIPTION

[0019] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0020] Ground test part: like Figure 1-Figure 3 As shown in the figure, a neural network-based on-orbit integrated circuit aging fault diagnosis system is built on FPGA (Field-Programmable Gate Array) using the idea of ​​system framework construction, software implementation, hardware implementation, and experimental verification. The specific implementation method is to use aerospace FPGA as the chip to be tested, collect the characteristic parameters (current, temperature) of the chip to be tested, and the failure diagnosis system analyzes the characteristic parameters to diagnose the aging status of the chip to be tested.

[0021] The on-orbit integrated circuit aging fault diagnosis system is aimed at the aging of aerospace FPGA. The test system is implemented based on FPGA and uses 12-bit SAR ADCSAR ADC (Successive Approximation Register Analog-to-Digital Converter, successive approximation analog-to-digital converter) to collect 4 currents of the system under test and DS18B20 (digital temperature sensor, operating temperature range: -55°C to +125°C, operating voltage range: 3.0V~5.5V). Collect 1 temperature of the system under test. Some current parameters are used as characteristic parameter inputs of the failure diagnosis system to diagnose the failure state of the system under test. The fault injection number information, current parameters, temperature parameters and diagnosis results are written into the FIFO core of the FPGA.

[0022] The board to be tested includes the core chip to be tested, acquisition devices and other peripheral circuits. The types of aging failures of the chip to be tested include hot carrier injection (hereinafter referred to as HCI), negative bias temperature instability (hereinafter referred to as NBTI), time-dependent dielectric breakdown (hereinafter referred to as TDDB), and electromigration (hereinafter referred to as EM). The failure diagnosis system is based on FPGA design. The failure diagnosis algorithm includes a characteristic parameter processing module and a feedforward neural network module. The characteristic parameter processing module adopts SPI protocol algorithm, digital signal recovery fixed-point decimal algorithm, wavelet transform filtering algorithm and deviation normalization algorithm. The algorithm design steps of the on-orbit integrated circuit aging fault diagnosis method are as follows: Step 1: Determine the transmission protocol between the ADC acquisition signal in the acquisition device of the board under test and the FPGA of the aging failure diagnosis module, and design the SPI receiving protocol using the Verilog hardware description language; Step 1 is as follows: SPI protocol uses unidirectional transmission, the master device is the SPI interface module based on FPGA, and the slave device is the ADC in the acquisition device of the board to be tested, which collects the current signal of the aerospace FPGA to be tested. The SPI interface module provides the clock SCK and chip select CS, and the ADC data output SDO and the data input SDI of the SPI interface algorithm module are defined as MISO. The ADC serially outputs a 12-bit digital signal, and the falling edge of the chip select signal CS is ready for conversion and output.

[0023] Figure 4The simulation waveform of the 12-bit serial digital signal for sequentially receiving multiple SPI transmission cycles is input as the clock signal SCK, the chip select signal CS_N, and the data input (for the receiving module) MISO. rxd_data is a 12-bit digital signal that changes in each SCK cycle. The rising edge of CS_N resets and the falling edge receives the serial digital signal. It changes once in each SCK cycle, and receives serial data bit by bit from high to low. rxd_temp is a 12-bit digital signal that changes in each transmission cycle (one ADC conversion cycle and one sampling cycle are one transmission cycle). The value of rxd_data is obtained after the ADC conversion cycle ends. rxd_flag is the end flag signal, indicating that the data reception of a transmission cycle is completed, indicating that the analysis system has obtained a characteristic parameter value. A sample (training sample and test sample) of the analysis system requires multiple characteristic parameter values. data1~data5 are 5 characteristic parameters of a sample, which are received sequentially from data1 to data5. Done1~Done5 respectively indicate that the reception of the 5 characteristic parameters is completed. data1~data5 obtain the value of rxd_temp before the end of each transmission cycle of ADC.

[0024] Step 2: The characteristic parameters of the measurement system are collected and converted by ADC and transmitted to the failure analysis system through the SPI protocol interface. The digital signal output by the ADC conversion principle is parsed into a fixed-point decimal representing the true value by the digital signal recovery fixed-point decimal algorithm. The digital signal recovery fixed-point decimal algorithm is designed using the Verilog hardware description language to obtain a universal binary number representing the true value of the characteristic parameter.

[0025] Step 2 is as follows: The conversion process of the analog signal to the 12-bit digital signal is performed bit by bit from the highest bit to the lowest bit, and one clock pulse converts one bit. Assume that the 12-bit digital signal outputs are s12~s1 respectively, and the initial value of the input voltage Vin is set to Vin- (minimum range). In the first clock pulse of the conversion process, Vin and Vin- + Vref / 2 are compared. If Vin is greater than the latter, s12 is high, otherwise s12 is low; in the second clock pulse of the conversion process, Vin and Vin- + (s12 * Vref) / 2+ (s11 * Vref) / 4 are compared. If Vin is greater than the latter, s11 is high, otherwise s11 is low. Similarly, the level values ​​of s10~s1 are output in sequence. The inverse formula for restoring the true value of a fixed-point decimal from a digital signal is shown below: .

[0026] Figure 5This is the simulation diagram of the algorithm for restoring the fixed-point decimal 1.65 from the digital signal. The input in is a 12-bit digital signal, and the output out is the real value of the digital signal restored by the module. From the highest bit to the lowest bit, out is a fixed-point number consisting of a 1-bit sign bit, 7-bit integer bits, and 24-bit decimal bits. Done is the conversion completion signal. When the digital signal is 12'h800, it means that the real value of the power supply current sampled by the ADC is 1.65, and the corresponding binary 32'h01a66600 is equal to the theoretical value 32'h01a66600, which conforms to the inverse algorithm and the error meets the requirements.

[0027] Step three is as follows: Based on the conversion principle of the successive approximation analog / digital converter, reverse thinking is used to deduce the recovery algorithm to obtain a universal binary number representing the true value of the characteristic parameter.

[0028] Step 3: Use wavelet transform filtering algorithm to filter the noise of the collected aging fault characteristic parameters of the chip under test, and use Verilog hardware description language to design the wavelet transform filtering algorithm.

[0029] The wavelet transform filtering algorithm includes using Daubechies wavelet as the wavelet basis through continuous wavelet transform, decomposing the signal processed by the digital signal recovery fixed-point decimal algorithm into wavelet coefficients at multiple scales, setting a hard threshold to remove noise in the wavelet coefficients, and reconstructing the signal with the denoised wavelet coefficients.

[0030] Step three is as follows: Using Daubechies wavelet as the wavelet basis, through continuous wavelet transform, the signal processed by the digital signal recovery fixed-point decimal algorithm is decomposed into wavelet coefficients at multiple scales, and the hard threshold is set to remove the noise in the wavelet coefficients, and the denoised wavelet coefficients are used to reconstruct the signal. Daubechies wavelet has a high degree of time localization ability and can detect local characteristics in the signal, especially transient characteristics or unstable signals in temperature, current, voltage and electromagnetic wave data. In order to cope with the simplified fault diagnosis module, continuous wavelet transform is adopted in the case of less data source to enhance the sensitivity to changes in time and identify small changes in temperature and electromagnetic wave detection.

[0031] The advantages of wavelet transform filtering in processing voltage and current signals are mainly reflected in its excellent localization characteristics and its ability to provide signal information in both the time domain and the frequency domain. This means that wavelet transform can effectively analyze the local characteristics of the signal, such as mutation points and singular points, and can capture the characteristics of the signal at different frequency levels through multi-scale analysis. In terms of processing voltage and current signals, it provides higher flexibility, local feature representation capabilities, multi-scale analysis capabilities, and adaptability to mutation and singular signals.

[0032] Step 4: Use Verilog hardware description language to design a deviation normalization algorithm to reduce the order of magnitude difference between parameters in the same sample, which can eliminate the impact of singular sample data (parameters with a large order of magnitude difference from most parameters in the sample) on the analysis results.

[0033] Step 4 is as follows: adopt normalization to design a deviation normalization algorithm. The goal of data normalization is to uniformly map the five characteristic parameter values ​​of each sample to the interval [-1,1]. The benefit of normalization is to reduce the order of magnitude difference of each element in the sample, thereby improving the convergence speed and calculation accuracy. The formula for deviation normalization is as follows: ; Where x i represents the i-th data point or feature value in the original data set; x mean represents the mean of the original data set, that is, the average value of all data points; x max Represents the maximum value in the original data set, that is, the largest data point in the data set; x min Represents the minimum value in the original data set, that is, the smallest data point in the data set; X i * Represents the i-th data point or eigenvalue after deviation normalization.

[0034] Figure 6 This is the simulation diagram of the deviation normalization algorithm. In the simulation waveform, clk and rst_n are the clock and reset signals respectively, start is the start signal, data_in1~data_in5 are the input parameter samples, data_out1~data_out5 are the results after data deviation normalization, and done is the completion signal of deviation normalization. The input sample parameters of deviation standardization are decimal 1, 2, 3, 4, and 5 respectively; the average value is calculated to be 3, and the corresponding binary fixed-point number (the highest bit is the sign bit, the middle 7 bits are integer bits, and the lower 24 bits are decimal bits) is 32'03000000; the maximum and minimum values ​​are calculated to be 5 and 1 respectively, and the corresponding binary fixed-point numbers are 32'05000000 and 32'01000000 respectively; the decimal outputs after deviation standardization are -0.5, -0.25, 0, 0.25, and 0.5 respectively, and their corresponding 32-bit fixed-point decimal places are 32'h80800000, 32'h80400000, 32'h00000000, 32'h00400000, and 32'h00800000.

[0035] Step 5. Use the feedforward neural network algorithm as the failure diagnosis system algorithm, take the 5-way feature parameters processed by steps 1 to 4 as sample input, and obtain the aging failure type through feedforward neural network diagnosis. Use Verilog hardware description language to design the feedforward neural network algorithm.

[0036] Step 5 is as follows: Design a double hidden layer feedforward neural network with a 5-2-4-2 structure. The neural network inputs IN1~IN5 are the FPGA current and temperature parameters after data preprocessing; the outputs are OUT1 and OUT2, which are normal and aging failure, respectively. Aging failure includes HCI, NBTI, TDDB and EM; Classify by the output value of the output layer node, using the Softmax function. If Softmax(OUT1)>Softmax(OUT2), it is normal, otherwise it is aging failure. The Softmax function normalizes the vector, highlights the largest value and suppresses other components far below the maximum value. The output values ​​of all output nodes are taken as an array, and the Softmax function is used to calculate this array to obtain the Softmax function value of each element in the array. The function value represents the contribution rate of each element to the array classification. For the neural network, the number of output nodes represents the number of classification types, and the output node with the largest contribution represents the number of classifications. The neurons in the feedforward neural network widely use the ReLU calculation formula f(x)=max(0,x), which means that it only needs to compare the input value with zero to determine the output. This simple logic makes ReLU extremely cheap in terms of latency when calculating, which significantly improves the overall processing speed of the network. Since the calculation of the ReLU activation function does not involve multiplication, division or other complex mathematical operations, it can significantly reduce the required hardware resources during implementation.

[0037] Figure 7 This is a simulation diagram of the feedforward neural network function. datain1~datain5 are the five input parameters IN1~IN5 of the sample. The simulation waveforms OUT1_1~OUT1_2, OUT2_1~OUT2_4, OUT3_1~OUT3_2 are the outputs of each neuron node in the first hidden layer, the second hidden layer, and the output layer. Done1, Done2, and Done3 are the end marks of the feedforward operation.

[0038] Step 6. Use the Python-based Pytorch toolkit to design a neural network training platform. The neural network training platform includes a neural network learning and training module based on the BP algorithm and a feedforward neural network built based on Pytorch. Both the BP neural network and the feedforward neural network use the same architecture as the feedforward neural network designed on the FPGA side. Use the Pycharm built-in tool PYQT5 to design the main control GUI for the joint test of the FPGA and neural network training platform, and pass the feedforward neural network parameters (weights, biases) trained in Pytorch to the feedforward neural network built on the FPGA.

[0039] Step six is ​​as follows: construct a neural network aging failure fault data set based on the measured aging failure parameters (current, temperature) of the tested FPGA, convert data samples into tensor arrays and tensor arrays into variable vectors, and the input layer of the neural network designed by Pytorch only receives input variables of variable type; use the gradient descent algorithm for training; determine the number of neural network layers, the number of nodes in each layer, the activation function of each layer of neurons, the initial learning rate and the initial weight bias parameters based on the structural framework of the feedforward neural network; prepare the data as training sets and test sets based on the measured FPGA irradiation failure data, including HCI, NBTI, TDDB, EM and normal, and use torch.utils.data.DataLoader for batch loading; use PyTorch's nn.Module class to define the BP neural network structure; the neural network training process includes determining the number of training rounds, outputting predicted values, and calculating the error between predicted values ​​and expected values, and updating weights and bias parameters based on the error. Use the PyQt5 toolkit to perform relevant configurations in Pycharm, add external tools Qt Designer and PyUIC; import Python's serial library, extract functions related to serial port transmission (serial port initialization, opening and closing serial ports, serial port receiving, serial port sending, etc.); import the code of the BP neural network training algorithm based on the Pytorch library, and integrate it into functions corresponding to receiving training / test samples, BP algorithm training neural network, extracting and sending network parameters, Pytorch feedforward neural network analysis test samples, etc. FPGA burns the feedforward neural network parameters, sends the network parameters to the FPGA on the main control GUI on the PC, and transplants them into the FPGA feedforward neural network.

[0040] Step 7: Under the condition of fault injection, the main control GUI is used to jointly test the board under test, FPGA and neural network training platform, so as to conduct a simulated aging failure test, verify the feasibility of the failure diagnosis system and obtain the diagnosis accuracy of the failure diagnosis system; Step seven is as follows: the board 1 to be tested continuously runs the specified program in a normal interference-free environment; periodically samples and restores the characteristic parameter values ​​at 400 sampling moments, a total of 400 samples, and records the label as 0 outside the system as a normal state test sample; label 1 indicates normal. Boards 2 to be tested, 3 to be tested, 4 to be tested, and 5 to be tested use failed devices under HCI, NBTI, TDDB and EM aging effects respectively, and continuously run the specified program; each board to be tested periodically samples and restores the characteristic parameter values ​​at 100 sampling moments, a total of 400 samples, and records the label as 2 outside the system as aging failure state test samples. The aging failure diagnosis of the board to be tested requires the collection of the current and temperature parameters of the aerospace FPGA to be tested as characteristic parameters, and the characteristic parameters of 5 time points are periodically collected as a sample. As the master device of the SPI transmission protocol, the FPGA generates the clock and chip select signals of the ADC and transmits them to the ADC; after the ADC collects the characteristic parameters of the aerospace FPGA to be tested and converts them into digital signals, it is transmitted to the FPGA through the SPI protocol. If the high level of the ADC's digital I / O port (clock, chip select signal, and digital signal output) is inconsistent with the high level of the I / O port provided by the FPGA development board, a level conversion unit needs to be added for the transmission between the two. After the fault diagnosis system is turned on, the system performs periodic aging fault detection on the aerospace FPGA to be tested. A total of 800 aging failure samples were detected, of which 795 were successfully detected, with an accuracy rate of 99%.

[0041] On-orbit testing part: In the outer space environment, the data after feature parameter processing first enters the data buffer that contains the aging failure fault data set of the ground-trained neural network. The training data is provided from the data buffer to the learning and training module based on the back propagation algorithm, and the feedforward neural network parameters are periodically updated using the exponentially weighted moving average algorithm. The feedforward neural network parameters are transplanted to the feedforward neural network built based on Pytorch and the feedforward neural network built based on FPGA for joint testing.

[0042] The data buffer is a fixed-size buffer in a queue structure, and data is periodically extracted from the buffer for model training. For a geosynchronous orbit satellite, its operating period is equal to the Earth's rotation period, which is about 23 hours, 56 minutes and 4 seconds. The satellite remains stationary relative to a certain point on the Earth's surface. The operating period of a low-Earth orbit satellite is usually around 90 minutes, depending on the orbital altitude and inclination. The operating period of a polar orbit satellite is also related to the orbital altitude, but is usually between 90 minutes and 120 minutes. Determine the period for extracting data for model training based on the actual application.

[0043] After the storage capacity of the data buffer is exhausted, the early data is deleted according to the first-in-first-out principle. That is, when new data arrives, the oldest data is replaced by the new data. No additional logic is required to control the flow of data, which avoids memory allocation and recycling at runtime, reduces memory fragmentation, has significant advantages in maintenance, and is adaptable to applicable scenarios where on-orbit training equipment changes periodically with environmental changes.

[0044] The exponentially weighted moving average algorithm includes initializing the exponentially weighted moving average variable for each parameter in the model, calculating the exponentially weighted moving average gradient, using the exponentially weighted moving average gradient to update the model parameters, and controlling the learning rate according to the performance of the validation set. The exponentially weighted moving average algorithm can provide an immediate response to data, has high computational efficiency, does not require a large amount of historical data, can handle missing values ​​and non-uniformly spaced data, and by giving more weight to recent data, the exponentially weighted moving average algorithm can capture the latest changes in the data, thereby providing more accurate predictions.

[0045] Initialize an exponentially weighted moving average variable: For each parameter in the model, initialize an exponentially weighted moving average variable, typically set to 0 or the initial value of the parameter at the beginning of training.

[0046] Calculate the Exponentially Weighted Moving Average (EWMA) gradient: Update the EWMA variable (denoted as EWMA_gradient) using the following formula: EWMA_gradient=λ·current_gradient+(1-λ)·EWMA_gradient previous Among them, λ is the smoothing parameter (0<λ<1), current_gradient is the gradient calculated from the current batch of data, and EWMA_gradient previous is the EWMA gradient after the last update.

[0047] Update model parameters: Use EWMA gradient to update model parameters: θ new =θ old -α·EWMA_gradient; Among them, θ old are the old model parameters, θ new is the updated model parameter, α is the learning rate, which controls the step size of parameter update.

[0048] Controlling the learning rate includes setting a sliding window to store the training accuracy of the feedforward neural network to build a data buffer, adding new accuracy data to the data buffer, calculating the mean and standard deviation of the data in the buffer, setting the mean control lower limit and the standard deviation control upper limit, and increasing the learning rate when the mean is lower than the mean control lower limit or the mean decreases and the standard deviation is higher than the standard deviation control upper limit.

[0049] The learning rate is increased by exponential increase and sudden restart. The learning rate first increases exponentially to 0.1, and then suddenly restarts to 0.001 to determine whether the accuracy reaches the mean control lower limit. The process of exponential increase and sudden restart is repeated until the accuracy reaches the mean upper limit. This helps to reduce the algorithm calculation amount and reduce the system complexity.

[0050] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A method for diagnosing aging faults of integrated circuits on track, characterized in that: include: Ground training: The acquisition device acquires and converts the characteristic parameters of the module to be tested, and the characteristic parameters are processed based on the characteristic parameter processing module including the SPI protocol algorithm, the digital signal recovery fixed-point decimal algorithm, the wavelet transform filtering algorithm and the deviation normalization algorithm. The neural network aging failure fault data set is constructed according to the measured aging failure parameters after the characteristic parameter processing, and the feedforward neural network parameters are obtained through training by the learning and training module based on the back propagation algorithm. The feedforward neural network parameters are transplanted to the feedforward neural network built based on Pytorch and the feedforward neural network built based on FPGA for joint testing; On-orbit test: After feature parameter processing, the data first enters a data buffer that contains a data set of aging failures of a ground-trained neural network. Training data is provided from the data buffer to the learning and training module based on the back-propagation algorithm. The feedforward neural network parameters are periodically updated using an exponentially weighted moving average algorithm. The feedforward neural network parameters are transplanted to a feedforward neural network built based on Pytorch and a feedforward neural network built based on FPGA for joint testing.

2. The on-orbit integrated circuit aging fault diagnosis method according to claim 1, characterized in that: The feedforward neural network constructed by the FPGA includes a double hidden layer feedforward neural network with a 5-2-4-2 structure, wherein the input layer inputs current and temperature parameters processed by a characteristic parameter processing module, and the output layer outputs normal and aging failure.

3. The on-orbit integrated circuit aging fault diagnosis method according to claim 2, characterized in that: The digital signal recovery fixed-point decimal algorithm includes using an inverse formula to convert the digital signal converted by the acquisition device into a universal binary number representing the true value of the characteristic parameter based on the conversion principle of a successive approximation analog / digital converter. The inverse formula is: ； Where s12-s1 represents the 12-bit digital signal output, V in Indicates input voltage, V in- Indicates the minimum range of input voltage, V ref Indicates the reference voltage.

4. The on-orbit integrated circuit aging fault diagnosis method according to claim 3, characterized in that: The wavelet transform filtering algorithm includes using Daubechies wavelet as wavelet basis through continuous wavelet transform, performing multi-scale decomposition of the signal processed by the digital signal recovery fixed-point decimal algorithm into wavelet coefficients, setting a hard threshold to remove noise in the wavelet coefficients, and reconstructing the signal of the denoised wavelet coefficients.

5. The on-orbit integrated circuit aging fault diagnosis method according to claim 3, characterized in that: The data buffer is a fixed-size buffer of a queue structure, and data is periodically extracted from the buffer for model training.

6. The on-orbit integrated circuit aging fault diagnosis method according to claim 5, characterized in that: The exponentially weighted moving average algorithm includes initializing an exponentially weighted moving average variable for each parameter in the model, calculating an exponentially weighted moving average gradient, using the exponentially weighted moving average gradient to update the model parameters, and controlling the learning rate according to the performance of the validation set.

7. The on-orbit integrated circuit aging fault diagnosis method according to claim 6, characterized in that: The controlling learning rate includes setting a sliding window to store the accuracy of feedforward neural network training to build a data buffer, adding new accuracy data to the data buffer, calculating the mean and standard deviation of the data in the buffer, setting a mean control lower limit and a standard deviation control upper limit, and increasing the learning rate when the mean is lower than the mean control lower limit or the mean decreases and the standard deviation is higher than the standard deviation control upper limit.

8. The on-orbit integrated circuit aging fault diagnosis method according to claim 7, characterized in that: The increase in learning rate is performed by exponential increase and sudden restart. The learning rate first increases exponentially to 0.1, and then suddenly restarts to 0.

001. It is determined whether the accuracy rate reaches the mean control lower limit, and the process of exponential increase and sudden restart is repeated until the accuracy rate reaches the mean upper limit.

9. The on-orbit integrated circuit aging fault diagnosis method according to claim 6, characterized in that: The aging failures include four types: hot carrier injection, negative bias temperature instability, time-dependent dielectric breakdown, and electromigration.

10. An on-orbit integrated circuit aging fault diagnosis system, characterized by: The method for diagnosing integrated circuit aging faults according to any one of claims 1 to 9 is suitable for diagnosing integrated circuit aging faults.

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