Error correction method, memory system and memory controller

Abstract

The embodiment of the invention provides an error correction method of a memory system, the memory system and a memory controller. The error correction method comprises the following steps: after hard decision decoding on first hard read data fails, obtaining corresponding first soft data according to the first hard read data and cached second hard read data; the first hard read data is read by the memory system according to the first hard read voltage; the second hard read data is read by the memory system according to the second hard read voltage before the first hard read data is read; performing first soft decision decoding according to the first soft data and the first hard read data, or performing the first soft decision decoding according to the first soft data and the second hard read data; the first hard read voltage is one of a plurality of reread voltages corresponding to the read command; the second hard read voltage is the initial read voltage or the reread voltage except the first hard read voltage in the plurality of reread voltages.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to an error correction method for a memory system, a memory system, and a memory controller. Background Art

[0002] With the development of storage technology, 3D NAND flash memory (Flash) has evolved from single-level cells (SLC) that can store 1 bit of information and double-level cells (DLC) that can store 2 bits of information to triple-level cells (TLC) that can store 3 bits of information, and even quadruple-level cells (QLC) that can store 4 bits of information; and the number of stacked layers is increasing. Faced with memory devices with increasing numbers of layers and storage bits, in order to enhance the reliability of data stored in the memory devices, low-density parity check (LDPC) is usually used for error correction when reading data. However, as the structure of 3D NAND Flash becomes more complex and more data is stored, the error types it contains become more and more complex. Sampling the current error correction method has a slow error correction speed and reduced efficiency, which seriously affects the reading rate. Summary of the invention

[0003] In view of this, embodiments of the present application provide an error correction method for a memory system, a memory system, and a memory controller, which can improve the error correction rate.

[0004] In a first aspect, an embodiment of the present application provides an error correction method for a memory system, the method comprising:

[0005] After a hard decision decoding of the first hard read data fails, corresponding first soft data is obtained according to the first hard read data and the cached second hard read data; wherein the first hard read data is read by the memory system according to the first hard read voltage; and the second hard read data is read by the memory system according to the second hard read voltage before reading the first hard read data;

[0006] Performing a first soft decision decoding according to the first soft data and the first hard read data, or performing a first soft decision decoding according to the first soft data and the second hard read data;

[0007] The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

[0008] In the above solution, the method further includes:

[0009] caching the first hard read data;

[0010] After the first soft decision decoding fails, reading third hard read data according to a third hard read voltage; and performing the hard decision decoding on the third hard read data;

[0011] After the hard decision decoding of the third hard read data fails, obtaining corresponding second soft data according to the cached first hard read data and the third hard read data;

[0012] performing the first soft decision decoding according to the second soft data and the first hard read data, or performing the first soft decision decoding according to the second soft data and the third hard read data;

[0013] The third hard read voltage is one of the plurality of re-read voltages except the first hard read voltage and the second hard read voltage.

[0014] In the above scheme, the method also includes: when one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold, the first stage of error correction code ECC error correction is ended.

[0015] In the above solution, obtaining the corresponding first soft data according to the first hard read data and the cached second hard read data includes: performing an XOR operation on the first hard read data and the second hard read data to obtain the first soft data.

[0016] In the above solution, the method further includes:

[0017] Whether to perform first soft decision decoding based on the first soft data and the first hard read data or to perform first soft decision decoding based on the first soft data and the second hard read data is selected according to the first number of error bits included in the first hard read data and the second number of error bits included in the second hard read data.

[0018] In the above scheme, the number of error bits included in the hard read data is measured by a comprehensive weight, and the larger the comprehensive weight is, the more error bits the hard read data includes; the selecting whether to perform first soft decision decoding according to the first soft data and the first hard read data, or to perform first soft decision decoding according to the first soft data and the second hard read data according to the first number of error bits included in the first hard read data and the second number of error bits included in the second hard read data comprises:

[0019] Obtaining a first comprehensive weight corresponding to the first hard read data;

[0020] Obtaining a second comprehensive weight corresponding to the second hard read data;

[0021] comparing a first comprehensive weight corresponding to the first hard read data with a second comprehensive weight corresponding to the second hard read data;

[0022] When the comparison result includes that the first comprehensive weight is less than the second comprehensive weight, performing a first soft decision decoding according to the first soft data and the first hard read data;

[0023] When the comparison result includes that the first comprehensive weight is greater than the second comprehensive weight, performing a first soft decision decoding according to the first soft data and the second hard read data;

[0024] When the comparison result includes that the first comprehensive weight is equal to the second comprehensive weight, a first soft decision decoding is performed according to the first soft data and the first hard read data, or a first soft decision decoding is performed according to the first soft data and the second hard read data.

[0025] In the above solution, the method further includes:

[0026] After performing a first soft decision decoding according to the first soft data and the first hard read data or performing a first soft decision decoding according to the first soft data and the second hard read data, deleting the cached second hard read data;

[0027] After performing the first soft decision decoding according to the second soft data and the first hard read data, or performing the first soft decision decoding according to the second soft data and the third hard read data, the cached first hard read data is deleted.

[0028] In the above solution, the method further includes:

[0029] After the first stage of ECC error correction fails, the second stage of ECC error correction is performed, wherein:

[0030] The second stage of ECC error correction includes: performing at least one second soft decision decoding.

[0031] In the above solution, the method further includes:

[0032] Determining a set of soft read voltages; the set of soft read voltages includes an optimal read voltage and a plurality of soft re-read voltages having a certain offset relative to the optimal read voltage;

[0033] Reading fourth hard read data and third soft data according to a soft read voltage in the set of soft read voltages; and performing the second soft decision decoding according to the fourth hard read data and the third soft data;

[0034] Wherein, when one of the following situations occurs: the second soft decision decoding is successful, and the number of soft read retries reaches a second set threshold, the second stage of ECC error correction is terminated.

[0035] In the above solution, the method further includes:

[0036] After the ECC error correction in the second stage fails, the independent NAND redundant array RAIN error correction in the third stage is performed.

[0037] In the above solution, the method further includes:

[0038] After the RAIN error correction in the third stage fails, indication information for indicating the error correction failure is output.

[0039] In the above solution, the method further includes:

[0040] When one of the following situations occurs: the ECC error correction of the first stage is successful, the ECC error correction of the second stage is successful, or the RAIN error correction of the third stage is successful, the successfully corrected read data is output.

[0041] In the above scheme, the voltage interval between each read voltage in the set of soft read voltages is the same as the voltage interval between the hard read voltages in a set of hard read voltages used to perform the hard decision decoding, wherein the set of hard read voltages includes the initial read voltage and the multiple re-read voltages.

[0042] In a second aspect, an embodiment of the present application further provides a memory system, including: a memory device, for storing data;

[0043] A memory controller, coupled to the memory device, configured to: after a hard decision decoding of first hard read data fails, obtain corresponding first soft data according to the first hard read data and cached second hard read data; wherein the first hard read data is read by the memory system according to a first hard read voltage; and the second hard read data is read by the memory system according to a second hard read voltage before reading the first hard read data;

[0044] Performing a first soft decision decoding according to the first soft data and the first hard read data, or performing a first soft decision decoding according to the first soft data and the second hard read data;

[0045] The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

[0046] In the above solution, the memory controller includes: a processor, a memory, a hard decoder and a soft decoder, wherein;

[0047] The processor is configured to: read the first hard read data from the memory device according to the first hard read voltage; read the second hard read data according to the second hard read voltage before reading the first hard read data; and cache the second hard read data to the memory;

[0048] The hard decoder is used to: perform the hard decision decoding on the first hard read data;

[0049] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data according to the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; send the first soft data to the soft decoder;

[0050] The soft decoder is used to perform first soft decision decoding according to the first soft data and the first hard read data, or to perform first soft decision decoding according to the first soft data and the second hard read data.

[0051] In the above solution, the memory is also used to cache the first hard read data;

[0052] The processor is further configured to: read third hard read data according to a third hard read voltage after the first soft decision decoding fails;

[0053] The hard decoder is further used to: perform the hard decision decoding on the third hard read data;

[0054] The processor is further configured to: after the hard decision decoding of the third hard read data fails, obtain corresponding second soft data according to the cached first hard read data and the third hard read data;

[0055] The soft decoder is further configured to: perform the first soft decision decoding according to the second soft data and the first hard read data, or perform the first soft decision decoding according to the second soft data and the third hard read data.

[0056] In the above scheme, the processor is also used to: determine whether one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold; if so, end the first stage of error correction code ECC error correction.

[0057] In the above scheme, the soft decoder is also used to: perform the second stage of ECC error correction after the first stage of ECC error correction fails, wherein the second stage of ECC error correction includes: performing at least one second soft decision decoding; wherein, in one of the following situations: the second soft decision decoding is successful, the number of soft read retries reaches a second set threshold, the second stage of ECC error correction is terminated.

[0058] In the above scheme, the memory controller further includes: a RAIN error corrector, which is used to: perform the independent NAND redundant array RAIN error correction in the third stage after the ECC error correction in the second stage fails;

[0059] The processor is further used to: after the RAIN error correction in the third stage fails, output indication information for characterizing the decoding failure; in one of the following situations: the ECC error correction in the first stage is successful, the ECC error correction in the second stage is successful, and the RAIN error correction in the third stage is successful, output the read data that has been successfully decoded.

[0060] In a third aspect, an embodiment of the present application further provides a memory controller, comprising: a processor, a memory, a hard decoder and a soft decoder, wherein;

[0061] The processor is configured to: read first hard read data from a memory device coupled to the memory controller according to a first hard read voltage; read second hard read data from the memory device according to a second hard read voltage before reading the first hard read data; and cache the second hard read data to the memory;

[0062] The hard decoder is used to: perform hard decision decoding on the first hard read data;

[0063] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data according to the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; send the first soft data to the soft decoder;

[0064] The soft decoder is used to: perform a first soft decision decoding according to the first soft data and the first hard read data, or perform a first soft decision decoding according to the first soft data and the second hard read data;

[0065] The processor is further used to: determine whether one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold; if so, end the first stage of ECC error correction;

[0066] The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

[0067] The embodiment of the present application provides an error correction method for a memory system, a memory system and a memory controller. The error correction method includes: after a hard decision decoding of a first hard read data fails, obtaining corresponding first soft data according to the first hard read data and the cached second hard read data; wherein the first hard read data is read by the memory system according to a first hard read voltage; the second hard read data is read by the memory system according to a second hard read voltage before reading the first hard read data; performing a first soft decision decoding according to the first soft data and the first hard read data, or performing a first soft decision decoding according to the first soft data and the second hard read data; wherein the first hard read voltage is one of a plurality of reread voltages having a certain offset from the initial read voltage; the second hard read voltage is the initial read voltage or a reread voltage of the plurality of reread voltages other than the first hard read voltage. The error correction method provided by the embodiment of the present application, when performing a read operation on the memory system, adds a first soft decision decoding after the hard decision decoding of the reread fails, thereby utilizing the high error correction capability of the soft decision decoding to improve the error correction speed, thereby improving the reading speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In the drawings, which are not necessarily drawn to scale, the same reference numerals may describe similar components in different views. The same numerals with different letter suffixes may represent different instances of similar components. The drawings generally illustrate various embodiments discussed in this document by way of example and not limitation.

[0069] Figure 1 A schematic diagram of an exemplary system having a memory system provided for an embodiment of the present application;

[0070] Figure 2a A schematic diagram of an exemplary memory card having a memory system provided by an embodiment of the present application;

[0071] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system provided for an embodiment of the present application;

[0072] Figure 3 A schematic diagram of an exemplary memory including a peripheral circuit provided in accordance with an embodiment of the present application;

[0073] Figure 4 A schematic diagram of the structure of a memory string, a word line, and a bit line in a memory provided by an embodiment of the present application;

[0074] Figure 5 A cross-sectional schematic diagram of a memory array including NAND memory strings provided in one embodiment of the present application;

[0075] Figure 6 A schematic diagram of an exemplary memory including a memory array and a peripheral circuit provided for an embodiment of the present application;

[0076] Figure 7 A schematic diagram of a process for an error correction method for a memory system provided in an embodiment of the present application Figure 1 ;

[0077] Figure 8 A second flowchart of an error correction method for a memory system provided in accordance with an embodiment of the present application;

[0078] Fig. 9 A flowchart of an error correction method for a memory system provided in accordance with an embodiment of the present application Figure 3 ;

[0079] Fig.10 An exemplary schematic diagram of soft decision decoding provided by an embodiment of the present application;

[0080] Fig.11 A schematic diagram of a process for an error correction method for a memory system provided in an embodiment of the present application Figure 4 ;

[0081] Fig.12 A flowchart of an error correction method for a memory system provided in accordance with an embodiment of the present application Figure 5

[0082] Fig.13 A schematic diagram of the ECC error correction process of the first stage of the error correction method provided in one embodiment of the present application;

[0083] Fig.14 A schematic diagram of the structure of a memory system provided in one embodiment of the present application. DETAILED DESCRIPTION

[0084] The exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. On the contrary, these embodiments are provided to more thoroughly understand the present application and to fully convey the scope disclosed in the present application to those skilled in the art.

[0085] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present application, some technical features well known in the art are not described: that is, all features of the actual embodiments not described here, and known functions and structures are not described in detail.

[0086] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0087] It should be understood that when an element or layer is referred to as "on ... ", "adjacent to ... ", "connected to ", "coupled to " or "coupled to" other elements or layers, it can be directly on other elements or layers, adjacent to, connected to or coupled to other elements or layers, or there can be intermediate elements or layers. On the contrary, when an element is "directly on ... ", "directly adjacent to ... ", "directly connected to " or "directly coupled to" other elements or layers, there is no intermediate element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teaching of the present application, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. When discussing a second element, component, region, layer or section, it does not necessarily mean that the first element, component, region, layer or section must be present.

[0088] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0089] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0090] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0091] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is taken as an example for description.

[0092] The embodiments of the present application are further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0093] Figure 1 A block diagram of an exemplary system having a memory system is shown. Figure 1 In the embodiment, the system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory system therein. Figure 1As shown, the electronic device 100 may include a host 108 and a memory system 102, wherein the host 108 may include a processor, such as a central processing unit (CPU) or a system on chip (SoC), wherein the system on chip may be, for example, an application processor (AP). The host 108 also includes at least one operating system (OS) that can generally manage and control functions and operations performed in the host 108. The OS can enable the host 108 coupled to the memory system 102 and the user who needs and uses the memory system 102 to interoperate. The OS can support functions and operations corresponding to the user's request, such as but not limited to, depending on whether the type of the host 102 is a removable host, the OS can be classified into a general operating system and a mobile operating system, wherein the general operating system may include a personal operating system and an enterprise operating system, the personal operating system may be an operating system including Windows and Chrome for general purposes to support services; the enterprise operating system may be an operating system including Windows Server, Linux, Unix, etc., which is dedicated to ensuring and supporting higher performance. The mobile operating system may refer to an operating system for services or functions for mobility (e.g., power saving function). Generally, the mobile operating system may be an operating system such as Android, iOS, Windows Mobile, etc. In some embodiments, the host 108 may include multiple OSs; correspondingly, the host 108 may run multiple operating systems related to the memory system 102. In other embodiments, the host 108 converts the user's request into one or more commands, and transmits the one or more commands to the memory system 102, so that the memory system 102 performs operations related to the one or more commands.

[0094] The memory system 102 can operate or perform specific functions or perform various internal operations in response to a request from the host 108. In some embodiments, the memory system 102 can store data accessed by the host 108. The memory system 102 can be used as a main memory system or an auxiliary memory system of the host 108. The memory system 102 can be electrically connected and communicated with the host 108 according to a corresponding protocol. The memory system 102 can be implemented and packaged into different types of terminal electronic products, such as but not limited to: solid state drive (SSD), multimedia card (MMC), embedded MMC (eMMC), reduced size MMC (RSMMC), micro MMC, secure digital (SD) card, mini SD, micro SD, universal serial bus (USB) storage device, universal flash memory (UFS) device, compact flash (CF) card, smart media (SM) card and memory stick, etc.

[0095] In some embodiments, the memory system 102 may also be configured as part of, for example, a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured in a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured in a home network, one of various electronic devices configured in a computer network, one of various electronic devices configured in a telematics network, a radio frequency identification (RFID) device, or one of various components configured in a computing system.

[0096] Return as Figure 1 As shown, the memory system 102 may have one or more memory devices 104 and a memory controller 106. The memory controller 106 may respond to a request from a host 108, and thereby control the memory device 104. For example, the memory controller 106 may read data from the memory device 104 and transmit the read data to the host 108; it may also receive data to be stored from the host 108, and store the data to be stored in the memory device 104. In other words, the memory controller 106 is capable of controlling the write (or programming) operation, read operation, erase operation, background operation, and the like of the memory device 104. And the memory system 102 may be implemented and packaged into different types of terminal electronic products. In the example Figure 2aIn one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host 108 in the embodiment. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0097] Among them, the memory device 104 may include a non-volatile memory, which can retain the data stored therein even if power is not supplied. The memory device 104 may also include a volatile storage memory. The device 104 can store data provided from the host 108 through a write operation; the memory device 104 can also provide the stored data to the host 108 through a read operation. In an embodiment of the present application, the memory device 104 may include any disclosed memory, such as a volatile memory device of a dynamic random access memory (DRAM) and a static RAM (SRAM), or a non-volatile memory device such as a read-only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM or ReRAM), and a flash memory (e.g., a three-dimensional NAND flash memory).

[0098] Figure 3 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1300. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0099] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible memory states and can therefore store one bit of data. For example, the first memory state "0" may correspond to a first voltage range, and the second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a two-bit memory cell (MLC) that can store more than one bit of data in more than four memory states. For example, an MLC can store two bits per memory cell, three bits per memory cell (also known as a three-bit memory cell (TLC), four bits per cell (also known as a four-bit memory cell (QLC), or five bits per cell (also known as a five-bit memory cell (PLC). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0100] like Figure 3As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0101] like Figure 3As shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at the half-memory block level, at the quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data unit for programming operations. The size of one page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in one memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates.

[0102] refer to Figure 3 as well as Figure 4 Each memory cell 306 of the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (eg, the top selection transistor (TSG) 312).

[0103] Specifically, refer to Figure 4 , the memory device may include one or more memory strings 308 (refer to Figure 4 As shown by the middle arrow, each memory string may include an upper selection transistor SST corresponding to an upper selection transistor gate line SSL, a ground selection transistor GST corresponding to a lower selection transistor gate line GSL, and a plurality of storage cells located between the upper selection transistor and the ground selection transistor, and each memory string is respectively connected to a corresponding bit line BL and a unified common source line.

[0104] Here, reference Figure 4, the word line coupled to the selected page is the selected word line (Sel.WL), the selected word line can be any word line among multiple word lines in the memory, and the other word lines are unselected word lines (Usel.WL) or virtual word lines (Dummy WL); the bit lines BL in the memory are divided into two parts, one part of the bit lines is connected to the memory cells in the lowest state (i.e., erased state) among the memory cells coupled to the selected word line, recorded as the first bit line (BL_min), and the other part of the bit lines is connected to the memory cells in the lowest state (i.e., erased state) and the memory cells that have reached the target state among the memory cells coupled to the selected word line, recorded as the second bit line (BL_other). In actual operation, a target memory cell among multiple memory cells can be selected by selecting the corresponding word line and bit line to perform corresponding read and program operations.

[0105] Figure 5 3 shows a cross-sectional schematic diagram of an exemplary memory array 301 including NAND memory strings 308 according to some aspects of the present disclosure. Figure 5 As shown, the NAND memory string 308 may include a stacked structure 510, which includes a plurality of gate layers 511 and a plurality of insulating layers 512 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 511 and the insulating layers 512. The gate layers 511 and the insulating layers 512 may be alternately stacked, and two adjacent gate layers 511 are separated by a layer of insulating layer 512. The number of pairs of gate layers 511 and insulating layers 512 in the stacked structure 510 may determine the number of memory cells included in the memory array 301.

[0106] The constituent material of the gate layer 511 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 511 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 511 includes a doped polysilicon layer. Each gate layer 511 may include a control gate surrounding a memory cell. The gate layer 511 at the top of the stacked structure 510 may extend laterally as an upper selection gate line 513, the gate layer 511 at the bottom of the stacked structure 510 may extend laterally as a lower selection gate line 514, and the gate layer 511 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer 503.

[0107] In some embodiments, the stacked structure 510 may be disposed on a substrate 501. The substrate 501 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0108] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 510. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0109] Return to reference Figure 3 , the peripheral circuit 302 may be coupled to the memory array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 6 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 604, a column decoder / bit line driver 606, a row decoder / word line driver 608, a voltage generator 610, a control logic 612, a register 614, an interface 616, and a data bus 618. It should be understood that in some examples, it may also include Figure 6 Additional peripheral circuits not shown.

[0110] The page buffer / sense amplifier 604 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 612. In one example, the page buffer / sense amplifier 604 may store a page of programming data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 604 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 604 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 606 may be configured to be controlled by the control logic 612 and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 610.

[0111] The row decoder / word line driver 608 may be configured to be controlled by the control logic 612 and select / deselect the memory block 304 of the memory array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 608 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 610. In some embodiments, the row decoder / word line driver 608 may also select / deselect and drive the BSG line 315 and the TSG line 313. The row decoder / word line driver 608 may be configured to perform a programming operation on the memory cell 306 coupled to the selected word line(s) 318. The voltage generator 610 may be configured to be controlled by the control logic 612 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boost voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0112] The control logic 612 may be coupled to each peripheral circuit described above and configured to control the operation of each peripheral circuit. The register 614 may be coupled to the control logic 612 and include a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 616 may be coupled to the control logic 612 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 612, and to buffer status information received from the control logic 612 and relay them to the host. The interface 616 may also be coupled to the column decoder / bit line driver 606 via a data bus 618 and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 301 or relay or buffer data from the memory array 301.

[0113] In 3NAND memory devices, single-bit cell (SLC) occupies a certain share in the memory market due to its advantages of fast read and write speed, high reliability and long service life; while two-bit cell (MLC), three-bit cell (TLC) and four-bit cell (QLC) have become the development trend of the memory market due to their higher storage density and larger storage capacity.

[0114] However, as the number of storage bits of the memory cell increases and the number of stacked layers increases, the types of errors it contains become more and more complex. The error correction process commonly used at present (including: first performing hard decision error correction; when error correction fails, then performing soft decision error correction; when error correction fails, finally performing independent NAND redundant array error correction) takes a long time to correct, which seriously affects the reading rate.

[0115] Based on one or more of the above problems, an embodiment of the present application provides an error correction method for a memory system. In the hard decision error correction stage, after the reread hard decision decoding fails, a first soft decision decoding is added, thereby utilizing the high error correction capability of the soft decision decoding to increase the error correction speed and thereby increase the reading speed.

[0116] See also Figure 7 , Figure 7 A flowchart of an error correction method for a memory system provided in accordance with an embodiment of the present application is provided.

[0117] Specifically, the error correction method may include:

[0118] S701: after a hard decision decoding of first hard read data fails, obtaining corresponding first soft data according to the first hard read data and cached second hard read data;

[0119] S702: Performing a first soft decision decoding according to the first soft data and the first hard read data, or performing a first soft decision decoding according to the first soft data and the second hard read data;

[0120] The first hard read data is read by the memory system according to a first hard read voltage; the second hard read data is read by the memory system according to a second hard read voltage before reading the first hard read data;

[0121] The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

[0122] It should be noted that the memory system can be any of the memory systems described above, which has one or more functions described above. The technical solution described here is that after the hard decision decoding of the first hard read data fails, a first soft decision decoding is added, and the high error correction capability of the soft decision decoding is used to speed up the error correction speed.

[0123] Here, the first hard read data may be obtained by the memory system according to the first hard read voltage; and the first hard read voltage may be one of a plurality of re-read voltages having a certain offset from the initial read voltage. Here, the initial read voltage may refer to the first voltage value used for the read operation when performing hard decision error correction, wherein the initial read voltage may be preset in the memory system based on experience. The initial read voltage may be the same as or different from the reference voltage in the retry read table (RRT).

[0124] It should be noted that RRT is a table containing multiple voltage offsets, each of which is relative to a reference voltage. These voltage offsets can be implemented by the hardware circuits in the memory, for example, by setting these voltage offsets through registers contained in the memory. In other words, all read voltages are obtained according to the RRT table to obtain the required voltage offset, and then superimposed with the reference voltage (including the superposition of the sign, that is, if the voltage offset is negative, the final read voltage is less than the reference voltage) to obtain the required voltage value, which is then applied to the corresponding word line.

[0125] That is, in the hard decision error correction stage, the initial read voltage in a set of hard read voltages (including the initial read voltage and a plurality of re-read voltages) used can be obtained according to the RRT, wherein when its voltage offset is 0, the initial read voltage is numerically the same as the reference voltage; when its voltage offset is not 0, the initial read voltage is numerically different from the reference voltage. And the plurality of re-read voltages are a set of voltage values ​​with a certain offset from the initial read voltage based on the initial read voltage, wherein the offset here may be different from or the same as the interval of the voltage offset in the aforementioned RRT.

[0126] Table 1 RRT

[0127]

[0128] For example, as shown in Table 1, it is an RRT corresponding to a TLC type storage cell provided in an embodiment of the present application. Rd1 to Rd7 in Table 1 represent voltage offsets between different data states; each column represents a set of voltage offsets of adjacent programming states relative to the corresponding reference voltage, wherein the set of voltage offsets includes a positive offset that increases in a direction greater than the reference voltage and a negative offset that decreases in a direction less than the reference voltage. For example, for Rd7, +V1, +V2, +V3, +V4 are positive offsets, wherein the values ​​of V1, V2, V3, and V4 increase in sequence; -V5 to -V11 are negative offsets, wherein the values ​​of V5 to V11 decrease in sequence.

[0129] Based on the above Table 1, a group of hard read voltages used in the embodiment of the present application is illustrated. The initial read voltage contained therein may have no offset relative to the reference reference voltage in the RRT table, that is, taking Rd7 as an example. The offset of the initial read voltage relative to the reference reference voltage is 0, that is, the value corresponding to the first row in Table 1. The initial read voltage may also be offset by +V1 from the reference reference voltage in the RRT table, in which case the initial read voltage is the sum of the reference reference voltage and V1. The other hard read voltages in the group of hard read voltages except the initial read voltage are distributed on both sides of the initial read voltage, and the offset of each hard read voltage relative to the initial read voltage may be different from or the same as the offset in the RRT.

[0130] The first soft data required for the first soft decision decoding may be obtained according to the first hard read data and the cached second hard read data. Specifically, in some embodiments, obtaining the corresponding first soft data according to the first hard read data and the cached second hard read data may include: performing an XOR operation on the first hard read data and the second hard read data to obtain the first soft data.

[0131] Here, the second hard read data may be read by the memory system according to a second hard read voltage, wherein the second hard read voltage may be the initial read voltage or a reread voltage among the plurality of reread voltages except the first hard read voltage, and the second hard read data is read before the first hard read data. If the first hard read voltage is the first reread after the initial read voltage, then the second hard read voltage is the initial read voltage; if the first hard read voltage is not the first reread after the initial read voltage, then the second hard read voltage is a reread voltage among the plurality of reread voltages except the first hard read voltage.

[0132] Figure 7 The described technical solution is to add a first soft decision decoding after the hard decision decoding fails. At this time, the first soft read data required in the first soft decision decoding does not need to be read from the memory in the memory system, but is obtained by XOR calculation based on the two hard read data cached above, which saves time. Furthermore, the decoding ability of the first soft decision decoding is higher than that of the hard decision decoding, and the probability of successful decoding is higher, so that the number of re-reads can be saved, which further saves time and improves the reading rate.

[0133] In some embodiments, Figure 8 As shown, the method may also include:

[0134] S703: Cache the first hard read data;

[0135] S704: after the first soft decision decoding fails, reading third hard read data according to a third hard read voltage; and performing the hard decision decoding on the third hard read data;

[0136] S705: after the hard decision decoding of the third hard read data fails, obtaining corresponding second soft data according to the cached first hard read data and the third hard read data;

[0137] S706: Perform the first soft decision decoding according to the second soft data and the first hard read data, or perform the first soft decision decoding according to the second soft data and the third hard read data;

[0138] The third hard read voltage is one of the plurality of re-read voltages except the first hard read voltage and the second hard read voltage.

[0139] It should be noted that the ability of soft decision decoding is higher than that of hard decision decoding. In actual application, if there are many error bits in the read data, the first soft decision decoding performed only once cannot be successfully decoded. Therefore, the first hard read data is cached for later use. After the first soft decision fails, the third hard read voltage is used to reread once to read the third hard read data; then, the third hard read data is hard-decision decoded, and after the hard decision decoding of the third hard read data fails, the first soft decision decoding is added again, wherein the soft data used in the first soft decision decoding this time is the second soft data calculated by the XOR between the third hard read data and the cached first hard read data.

[0140] In actual application, the method may further include:

[0141] In one of the following situations: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold, the first stage of ECC error correction is terminated.

[0142] It should be noted that the error correction code (ECC, Error Correcting Code) correction of the first stage mentioned here can be understood as the aforementioned hard decision error correction stage including the first soft decision decoding. That is to say, the error correction method provided by the embodiment of the present application adds a soft decision decoding after the hard decision decoding fails during the rereading of the hard decision error correction stage, and the soft data required for the soft decision decoding is obtained by using the cached hard read data, so as to shorten the decoding time by using the high decoding ability of the soft decision decoding, thereby reducing the reading time and improving the reading efficiency. It should be understood that when the hard decision decoding is successful or the first soft decision decoding is successful, not only the ECC error correction of the first stage ends, but also the entire error correction process ends, because the read data has been corrected and is correct data. Furthermore, the ECC error correction of the first stage will not be executed indefinitely. When the number of hard read retries reaches the first set threshold, the ECC error correction of the first stage will also end, and enter the next stage of error correction or output the indication information of error correction failure. That is, the first stage of ECC error correction can be terminated when one of the following occurs: the hard decision decoding is successful, the first soft decision decoding is successful, or the number of hard read retries reaches a first set threshold. Here, the first set threshold can be determined by the designer according to actual conditions.

[0143] For the aforementioned step 702, specifically selecting the first hard read data or the second hard read data, and performing the first soft decision decoding together with the first soft data, in some embodiments, such as Fig. 9 As shown, the method may also include:

[0144] S7021: Based on a first number of error bits contained in the first hard read data and a second number of error bits contained in the second hard read data, select whether to perform a first soft decision decoding based on the first soft data and the first hard read data, or to perform a first soft decision decoding based on the first soft data and the second hard read data.

[0145] That is, according to the number of error bits contained in the first hard read data and the second hard read data, it is selected whether to perform the first soft decision decoding according to the first soft data and the first hard read data, or to perform the first soft decision decoding according to the first soft data and the second hard read data. Specifically, when the first number is greater than the second number, the first soft decision decoding is selected according to the first soft data and the second hard read data; when the first number is less than the second number, the first soft decision decoding is selected according to the first soft data and the first hard read data; when the first number is equal to the second number, the first soft decision decoding is selected according to the first soft data and the first hard read data, or the first soft decision decoding is selected according to the first soft data and the second hard read data. This is because the more error bits the hard read data contains, the lower the probability of it being correctly corrected. Therefore, when performing the first soft decision decoding, the hard read data containing fewer error bits should be selected as the reference read data for the first soft decision decoding. It should be understood that the information input to the next stage decoder by the soft decision decoding can be a log-likelihood ratio (LLR), that is, the so-called soft data. The soft data is a kind of probability information of different decision reliability, which is used to measure the reliability of the decision. Therefore, it is necessary to have a read data as a benchmark, and the soft data is used to measure its reliability.

[0146] For an understanding of soft decision decoding, see Fig.10 .exist Fig.10 In the example, it is assumed that the first hard read data read by the first hard read voltage is 100; the second hard read data read by the second hard read voltage is 110; correspondingly, the first soft data is 010. At this time, if the data is read based on the first hard read data, then the bit that is "0" in the first soft data indicates that the reliability of the bit in the first hard read data is relatively high. In other words, the judgment of the bit is closer to the truth. For example, Fig.10In the example, the data is read based on the first hard read data, and the leftmost bit is "1", while the number corresponding to the bit in the first soft data is "0". Therefore, the reliability of the bit is relatively high, that is, a strong "1". Similarly, the number of the first soft data corresponding to the middle bit in the first hard read data is "1", so the reliability of the middle bit is weak, that is, weak '1' or '0'; the rightmost bit in the first hard read data is a strong "0". The data is read based on the second hard read data, and the analysis is similar, which will not be repeated here. As for whether to select the first hard read data or the second hard read data, the above has described how to select, and the implementation method is also specifically given later.

[0147] In actual application, the number of error bits included in the hard read data is measured by a syndrome weight value, and the larger the syndrome weight value is, the more error bits the hard read data includes; the first number of error bits included in the first hard read data and the second number of error bits included in the second hard read data are selected as to whether to perform a first soft decision decoding according to the first soft data and the first hard read data, or to perform a first soft decision decoding according to the first soft data and the second hard read data, such as Fig.11 As shown, it may include:

[0148] S1101: Obtain a first comprehensive weight corresponding to the first hard read data;

[0149] S1102: Obtain a second comprehensive weight corresponding to the second hard read data;

[0150] S1103: Compare a first comprehensive weight corresponding to the first hard read data with a second comprehensive weight corresponding to the second hard read data;

[0151] S1104: When the comparison result includes that the first comprehensive weight is less than the second comprehensive weight, performing first soft decision decoding according to the first soft data and the first hard read data;

[0152] S1105: When the comparison result includes that the first comprehensive weight is greater than the second comprehensive weight, performing first soft decision decoding according to the first soft data and the second hard read data;

[0153] S1106: When the comparison result includes that the first comprehensive weight is equal to the second comprehensive weight, perform a first soft decision decoding according to the first soft data and the first hard read data, or perform a first soft decision decoding according to the first soft data and the second hard read data.

[0154] It should be noted that the number of error bits contained in the hard read data can be measured by the syndrome weight value, wherein a larger syndrome weight value indicates that the hard read data contains a larger number of error bits. In some embodiments, the syndrome weight value corresponding to the hard read data can be assigned to the obtained hard read data by the memory controller when the hard read data is obtained, and the more error bits the hard read data contains, the larger the assigned value. In some embodiments, a mapping relationship table between error bits and comprehensive weights can be pre-stored in the memory controller, and when the hard read data is obtained, the number of error bits contained therein is counted, and then the values ​​are assigned according to the mapping relationship table. That is, the above-described method of obtaining the first comprehensive weight corresponding to the first hard read data and the method of obtaining the second comprehensive weight corresponding to the second hard read data can refer to the above-described method of assigning values ​​using the mapping relationship table. It can also be a dynamic assignment, for example, the comprehensive weight corresponding to the first hard read data is randomly assigned, and then the second hard read data is compared with the number of error bits contained in the first hard read data. If the number of error bits of the second hard read data is greater than the number of error bits contained in the first hard read data, the comprehensive weight assigned to the second hard read data is greater than the random assignment; otherwise, if it is less than, the comprehensive weight assigned to the second hard read data is less than the random assignment; if it is equal to, the comprehensive weight assigned to the second hard read data is equal to the random assignment; then, when assigning the comprehensive weight of the hard read data obtained later, it needs to be compared with the number of error bits contained in each previous hard read data, and then assigned according to the comparison result.

[0155] Here, it is necessary to obtain the first comprehensive weight corresponding to the first hard read data and the second comprehensive weight corresponding to the second hard read data; then, compare the first comprehensive weight corresponding to the first hard read data with the second comprehensive weight corresponding to the second hard read data, and select whether to perform the first soft decision decoding according to the first soft data and the first hard read data, or to perform the first soft decision decoding according to the first soft data and the second hard read data according to the comparison result. Specifically, when the comparison result includes that the first comprehensive weight is less than the second comprehensive weight, the first soft decision decoding is performed according to the first soft data and the first hard read data; when the comparison result includes that the first comprehensive weight is greater than the second comprehensive weight, the first soft decision decoding is performed according to the first soft data and the second hard read data; when the comparison result includes that the first comprehensive weight is equal to the second comprehensive weight, the first soft decision decoding is performed according to the first soft data and the first hard read data, or the first soft decision decoding is performed according to the first soft data and the second hard read data.

[0156] In order to save storage space of the memory of the memory controller, in some embodiments, the method may further include:

[0157] After performing a first soft decision decoding according to the first soft data and the first hard read data or performing a first soft decision decoding according to the first soft data and the second hard read data, deleting the cached second hard read data;

[0158] After performing the first soft decision decoding according to the second soft data and the first hard read data, or performing the first soft decision decoding according to the second soft data and the third hard read data, the cached first hard read data is deleted.

[0159] That is, hard read data that is not needed subsequently is deleted to save memory space.

[0160] In some embodiments, the method may further include:

[0161] After the first stage of ECC error correction fails, the second stage of ECC error correction is performed, wherein:

[0162] The second stage of ECC error correction includes: performing at least one second soft decision decoding.

[0163] In some embodiments, performing the second soft decision decoding includes:

[0164] Determining a set of soft read voltages; the set of soft read voltages includes an optimal read voltage and a plurality of soft re-read voltages having a certain offset relative to the optimal read voltage;

[0165] Reading fourth hard read data and third soft data according to a soft read voltage in the set of soft read voltages; and performing the second soft decision decoding according to the fourth hard read data and the third soft data;

[0166] In one of the following situations: the second soft decision decoding is successful, or the number of soft read retries reaches a second set threshold, the second stage of ECC error correction is terminated.

[0167] It should be noted that after the first stage of ECC error correction fails, there will be other error correction measures, such as at least one second soft decision decoding. Here, the second soft decision decoding and the aforementioned first soft decision decoding algorithm can be the same or different, for example, the second soft decision decoding can be a confidence propagation algorithm; or the first soft decision decoding can be a confidence propagation algorithm, and the second soft decision decoding can be a minimum sum algorithm. Regardless of whether the algorithms of the first soft decision decoding and the second soft decision decoding are the same, the biggest difference between the two is that the soft data and reference read data used are different. Specifically, the first soft data used by the first soft decision decoding is obtained based on the logical operation of the cached hard read data; and the third soft data used by the second soft decision decoding is data read from the memory based on the set soft read voltage, that is, the third soft data is the data fed back to the memory controller by the memory in response to the soft read voltage applied by the memory controller, rather than calculated in the memory controller using the cached hard read data; furthermore, the reference read data used by the first soft decision decoding is one of the cached hard read data; and the reference read data used by the second soft decision decoding is data read from the memory based on the aforementioned optimal read voltage.

[0168] The above description of performing at least one second soft decision decoding is also to increase the probability of correctly reading data. The process of performing the second soft decision decoding each time may include the following steps: determining a set of soft read voltages; the set of soft read voltages may include: an optimal read voltage and a plurality of soft re-read voltages with a certain offset relative to the optimal read voltage; wherein the optimal read voltage may be obtained according to the aforementioned RRT table, specifically, the RRT table may be traversed to obtain an optimal voltage offset; then the optimal voltage offset is superimposed on the reference reference voltage to form an optimal read voltage; under the optimal read voltage, the number of error bits contained in the obtained reference read data is the least. In some embodiments, the voltage interval between each soft read voltage in the set of soft read voltages may be the same as the voltage interval between the hard read voltages in the set of hard read voltages used to perform the hard decision decoding, wherein the set of hard read voltages includes the initial read voltage and the plurality of re-read voltages. In other embodiments, the voltage interval between each soft read voltage in the set of soft read voltages may also be different from the voltage interval between the hard read voltages in the set of hard read voltages. The specific method of performing soft decision decoding has been described above and will not be repeated here.

[0169] When the second soft decision decoding is successful and the number of soft read retries reaches one of the second preset thresholds, the second stage of ECC error correction is terminated. The second preset threshold is also manually set according to actual conditions and can be the same as or different from the first preset threshold. Here, the number of soft read retries can refer to the number of times the second soft decision decoding is performed.

[0170] In some embodiments, the method may further include:

[0171] After the ECC error correction in the second stage fails, the independent NAND redundant array RAIN error correction in the third stage is performed.

[0172] In some embodiments, the method may further include:

[0173] After the RAIN error correction in the third stage fails, indication information for indicating the error correction failure is output.

[0174] In some embodiments, the method further comprises:

[0175] When one of the following situations occurs: the ECC error correction of the first stage is successful, the ECC error correction of the second stage is successful, or the RAIN error correction of the third stage is successful, the successfully corrected read data is output.

[0176] It should be noted that, in more extreme cases, after both the first-stage ECC error correction and the second-stage ECC error correction fail, the third-stage independent NAND redundant array RAIN error correction can be enabled. If it still fails, an indication message representing the error correction failure is output; the indication message can be one of the following: sound, image, text, symbol, and any combination of the above. In the event of one of the following situations: the first-stage ECC error correction is successful, the second-stage ECC error correction is successful, and the third-stage RAIN error correction is successful, the successfully corrected read data is output, that is, no matter which stage, if the error correction is successful, the successfully corrected read data can be output.

[0177] In order to understand this application, Fig.12 As shown, it shows a schematic diagram of an error correction process of a memory system provided by an embodiment of the present invention.

[0178] The specific process includes:

[0179] S1201: First stage ECC error correction.

[0180] Among them, Fig.13 As shown, the first stage of ECC error correction includes: initial reading; hard decision decoding of the initial read data; if the initial reading fails, the first rereading and hard decision decoding are performed; if the first rereading fails, the first soft decision decoding is performed; and then, and the next decoding is performed when the decoding fails. If one of the rereading times reaches the first set threshold, the hard decision decoding is successful, or the first soft decision decoding is successful, the first stage of ECC error correction is terminated.

[0181] S1202: Second stage ECC error correction.

[0182] The second stage of ECC error correction includes: at least one second soft decision decoding. The similarities and differences with the first soft decision have been described in detail above and will not be repeated here.

[0183] S1203: The third stage of RAIN error correction.

[0184] Wherein, after the RAIN error correction in the third stage fails, indication information for indicating the error correction failure is output; when the RAIN error correction in the third stage succeeds, the successfully corrected read data is output.

[0185] The error correction method provided in the embodiment of the present application adds a soft decision decoding after each reread hard decision decoding fails in the first stage ECC error correction process (hard decision error correction), and utilizes the high decoding capability of the soft decision decoding to speed up the error correction process and improve the reading efficiency.

[0186] Based on the aforementioned inventive concept, the present application embodiment further provides a memory system, see Fig.14 , Fig.14 A structural block diagram of a memory system is shown. The memory system 140 includes: a memory device 1401, for storing data;

[0187] A memory controller 1402, coupled to the memory device, for: after a hard decision decoding of first hard read data fails, obtaining corresponding first soft data according to the first hard read data and cached second hard read data; wherein the first hard read data is read by the memory system according to a first hard read voltage; and the second hard read data is read by the memory system according to a second hard read voltage before reading the first hard read data;

[0188] Performing a first soft decision decoding according to the first soft data and the first hard read data, or performing a first soft decision decoding according to the first soft data and the second hard read data;

[0189] The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

[0190] In some embodiments, the memory controller 1402 may include: a processor 1423, a memory 1427, a hard decoder 1425 and a soft decoder 1426, wherein;

[0191] The processor is configured to: read the first hard read data from the memory device according to the first hard read voltage; read the second hard read data according to the second hard read voltage before reading the first hard read data; and cache the second hard read data to the memory;

[0192] The hard decoder is used to: perform the hard decision decoding on the first hard read data;

[0193] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data according to the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; send the first soft data to the soft decoder;

[0194] The soft decoder is used to perform first soft decision decoding according to the first soft data and the first hard read data, or to perform first soft decision decoding according to the first soft data and the second hard read data.

[0195] In some embodiments, the memory is further used to cache the first hard read data;

[0196] The processor is further configured to: read third hard read data according to a third hard read voltage after the first soft decision decoding fails;

[0197] The hard decoder is further used to: perform the hard decision decoding on the third hard read data;

[0198] The processor is further configured to: after the hard decision decoding of the third hard read data fails, obtain corresponding second soft data according to the cached first hard read data and the third hard read data;

[0199] The soft decoder is further configured to: perform the first soft decision decoding according to the second soft data and the first hard read data, or perform the first soft decision decoding according to the second soft data and the third hard read data.

[0200] In some embodiments, the processor is also used to: determine whether one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold; if so, end the first stage of error correction code ECC correction.

[0201] In some embodiments, the soft decoder is further used to: after the first stage ECC error correction fails, perform a second stage ECC error correction, wherein the second stage ECC error correction includes: performing at least one second soft decision decoding;

[0202] In one of the following situations: the second soft decision decoding is successful, or the number of soft read retries reaches a second set threshold, the second stage of ECC error correction is terminated.

[0203] In some embodiments, the memory controller further includes: a RAIN error corrector 1428, configured to: perform a third stage of independent NAND redundant array RAIN error correction after the second stage of ECC error correction fails;

[0204] The processor is further used to: after the RAIN error correction in the third stage fails, output indication information for characterizing the decoding failure; in one of the following situations: the ECC error correction in the first stage is successful, the ECC error correction in the second stage is successful, and the RAIN error correction in the third stage is successful, output the read data that has been successfully decoded.

[0205] It should be noted that Fig.14 In the memory system 140 shown, the memory controller 1402 is used to control the memory device 1401 to perform various operations, such as read and write operations. Here, the memory controller 1402 and the memory device 1401 can be coupled in any suitable manner. In the embodiment of the present application, the memory device 1401 can be a semiconductor memory for storing data in a non-volatile manner, such as a NAND type memory. Fig.14 As shown, the memory system 140 is connected to the host 141, and the host 141 can be an electronic device such as a personal computer, a mobile terminal, etc. Among them, the host I / F 1421 outputs the command, valid data (write data), etc. received from the host 141 to the internal bus 1420, and sends the valid data (read data) read from the memory device 1401, the response from the control unit 1423, etc. to the host 141. Among them, the host I / F 1421 includes but is not limited to at least one of the following: universal serial bus (USB), multimedia card (MMC), high-speed peripheral component interconnect (PCI-e or PCIe), small computer system interface (SCSI), serial SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (PATA), small computer system interface (SCSI), enhanced small disk interface (ESDI) and electronic integrated drive (IDE). In some embodiments, the host I / F 1421 is a component of the memory system for exchanging data with the host 108, which can be implemented by firmware called host interface layer (HIL).

[0206] The memory I / F 1422 controls the process of writing valid data to the memory device 1401 and the process of reading from the memory device 1401 based on the instruction of the control unit 1423. The control unit 1423 controls the memory system 140 as a whole, and the control unit 1423 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. The control unit 1423 performs control according to the command received from the host 141 via the host I / F 1421. For example, the control unit 1423 instructs the memory I / F 1422 to write valid data and parity data to the memory device 1401 according to the command from the host 141. In addition, the control unit 1423 instructs the memory I / F 1422 to read valid data and parity data from the memory device 1401 according to the command from the host 141. Among them, the memory I / F 1422 can be implemented as a component for exchanging data with the memory device 104 through firmware called a flash interface layer (FIL, Flash Interface Layer).

[0207] The error correction (ECC) module 1424 includes a hard decision decoder 1425, a soft decision decoder 1426 and a RAIN decoder 1428, and their respective functions have been described above and will not be repeated here.

[0208] The data buffer 1427 temporarily stores valid data received from the host 141 before storing it in the memory device 1401 , and temporarily stores data read from the memory device 1401 before sending it to the host 141 .

[0209] The memory 1427 may also be a working memory of the memory controller 1402, configured to store data for driving the memory controller 1402. More specifically, when the memory controller 1402 controls the memory device 1401 in response to a request from the host 141, the memory 1427 may store firmware driven by the processor of the control unit 1423 and data required to drive the firmware (e.g., metadata). The memory 1427 may also be a buffer memory of the memory controller 1401, configured to temporarily store write data transmitted from the host 141 to the memory device 1401 and read data transmitted from the memory device 1401 to the host 141. The memory 1427 may include a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, and a mapping buffer / cache for storing write data and read data. The memory 1427 may be implemented using a volatile memory. The memory 1427 may be implemented using a static random access memory (SRAM), a dynamic random access memory (DRAM), or both.

[0210] Although Fig.14The memory 1427 is shown to be included in the memory controller 1402, but the present application is not limited thereto. In an embodiment, the memory 1427 may be included outside the memory controller 1402, and the memory controller 1402 may input and output data to the memory 1427 through a separate memory interface (not shown).

[0211] Based on the aforementioned inventive concept, an embodiment of the present application further provides a memory controller, which may include: a processor, a memory, a hard decoder and a soft decoder, wherein;

[0212] The processor is configured to: read first hard read data from a memory device coupled to the memory controller according to a first hard read voltage; read second hard read data from the memory device according to a second hard read voltage before reading the first hard read data; and cache the second hard read data to the memory;

[0213] The hard decoder is used to: perform hard decision decoding on the first hard read data;

[0214] The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data according to the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; send the first soft data to the soft decoder;

[0215] The soft decoder is used to: perform a first soft decision decoding according to the first soft data and the first hard read data, or perform a first soft decision decoding according to the first soft data and the second hard read data;

[0216] The processor is further used to: determine whether one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold; if so, end the first stage of ECC error correction;

[0217] The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

[0218] It should be noted that the memory controller described here is included in the aforementioned memory system. Therefore, the structure of the memory controller and the operations related to the error correction method provided in the embodiment of the present application have been described in detail above and will not be repeated here.

[0219] The above description is intended to be illustrative, not restrictive. For example, the above examples (or one or more aspects thereof) can be used in combination with each other. Other embodiments can be used, such as those available to those skilled in the art when reading the above description. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the above detailed description, various features can be combined together to simplify the application. This should not be interpreted as meaning that the disclosed features that are not claimed for protection are essential to any claim. On the contrary, the disclosed subject matter may be less than all the features of a specific disclosed embodiment. Therefore, the attached claims are thus incorporated into the detailed description, wherein each claim is independently used as a separate embodiment, and it is expected that these embodiments can be combined with each other in various combinations or permutations. The scope of the present application should be determined with reference to the attached claims and the full scope of the equivalents given by these claims.

Claims

1. A memory system error correction method, characterized in that: The method comprises: After a hard decision decoding of the first hard read data fails, corresponding first soft data is obtained according to the first hard read data and the cached second hard read data; wherein the first hard read data is read by the memory system according to the first hard read voltage; and the second hard read data is read by the memory system according to the second hard read voltage before reading the first hard read data; performing a first soft decision decoding according to the first soft data and the first hard read data, or performing a first soft decision decoding according to the first soft data and the second hard read data; The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

2. The error correction method according to claim 1, characterized in that: The method further comprises: caching the first hard read data; After the first soft decision decoding fails, reading third hard read data according to a third hard read voltage; and performing the hard decision decoding on the third hard read data; After the hard decision decoding of the third hard read data fails, obtaining corresponding second soft data according to the cached first hard read data and the third hard read data; performing the first soft decision decoding according to the second soft data and the first hard read data, or performing the first soft decision decoding according to the second soft data and the third hard read data; The third hard read voltage is one of the plurality of re-read voltages except the first hard read voltage and the second hard read voltage.

3. The error correction method according to claim 2, characterized in that: The method further comprises: In one of the following situations: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold, the first stage of ECC error correction is terminated.

4. The error correction method according to claim 1, characterized in that: The obtaining corresponding first soft data according to the first hard read data and the cached second hard read data comprises: An XOR operation is performed on the first hard read data and the second hard read data to obtain the first soft data.

5. The error correction method according to claim 1, characterized in that: The method further comprises: Whether to perform first soft decision decoding based on the first soft data and the first hard read data or to perform first soft decision decoding based on the first soft data and the second hard read data is selected according to the first number of error bits included in the first hard read data and the second number of error bits included in the second hard read data.

6. The error correction method according to claim 5, characterized in that: The number of error bits included in the hard read data is measured by a comprehensive weight, and the greater the comprehensive weight, the greater the number of error bits included in the hard read data; the selecting whether to perform first soft decision decoding according to the first soft data and the first hard read data, or to perform first soft decision decoding according to the first soft data and the second hard read data according to the first number of error bits included in the first hard read data and the second number of error bits included in the second hard read data, comprises: Obtaining a first comprehensive weight corresponding to the first hard read data; Obtaining a second comprehensive weight corresponding to the second hard read data; comparing a first comprehensive weight corresponding to the first hard read data with a second comprehensive weight corresponding to the second hard read data; When the comparison result includes that the first comprehensive weight is less than the second comprehensive weight, performing a first soft decision decoding according to the first soft data and the first hard read data; When the comparison result includes that the first comprehensive weight is greater than the second comprehensive weight, performing a first soft decision decoding according to the first soft data and the second hard read data; When the comparison result includes that the first comprehensive weight is equal to the second comprehensive weight, a first soft decision decoding is performed according to the first soft data and the first hard read data, or a first soft decision decoding is performed according to the first soft data and the second hard read data.

7. The error correction method according to claim 2, characterized in that: The method further comprises: After performing a first soft decision decoding according to the first soft data and the first hard read data or performing a first soft decision decoding according to the first soft data and the second hard read data, deleting the cached second hard read data; After performing the first soft decision decoding according to the second soft data and the first hard read data, or performing the first soft decision decoding according to the second soft data and the third hard read data, the cached first hard read data is deleted.

8. The error correction method according to claim 3, characterized in that: The method further comprises: After the first stage of ECC error correction fails, the second stage of ECC error correction is performed, wherein: The second stage of ECC error correction includes: performing at least one second soft decision decoding.

9. The error correction method according to claim 8, characterized in that: Executing the second soft decision decoding includes: Determine a set of soft read voltages; the set of soft read voltages includes an optimal read voltage and a plurality of soft re-read voltages having a certain offset relative to the optimal read voltage; Reading fourth hard read data and third soft data according to a soft read voltage in the set of soft read voltages; and performing the second soft decision decoding according to the fourth hard read data and the third soft data; Wherein, when one of the following situations occurs: the second soft decision decoding is successful, and the number of soft read retries reaches a second set threshold, the second stage of ECC error correction is terminated.

10. The error correction method according to claim 9, characterized in that: The method further comprises: After the ECC error correction in the second stage fails, the independent NAND redundant array RAIN error correction in the third stage is performed.

11. The error correction method according to claim 10, characterized in that: The method further comprises: After the RAIN error correction in the third stage fails, indication information for indicating the error correction failure is output.

12. The error correction method according to claim 10, characterized in that: The method further comprises: When one of the following situations occurs: the ECC error correction of the first stage is successful, the ECC error correction of the second stage is successful, or the RAIN error correction of the third stage is successful, the successfully corrected read data is output.

13. The error correction method according to claim 9, characterized in that: The voltage intervals between the read voltages in the set of soft read voltages are the same as the voltage intervals between the hard read voltages in a set of hard read voltages used to perform the hard decision decoding, wherein the set of hard read voltages includes the initial read voltage and the plurality of re-read voltages.

14. A memory system, characterized in that: include: A memory device for storing data; A memory controller, coupled to the memory device, configured to: after a hard decision decoding of first hard read data fails, obtain corresponding first soft data according to the first hard read data and cached second hard read data; wherein the first hard read data is read by the memory system according to a first hard read voltage; and the second hard read data is read by the memory system according to a second hard read voltage before reading the first hard read data; Performing a first soft decision decoding according to the first soft data and the first hard read data, or performing a first soft decision decoding according to the first soft data and the second hard read data; The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

15. The memory system according to claim 14, characterized in that: The memory controller comprises: a processor, a memory, a hard decoder and a soft decoder, wherein; The processor is configured to: read the first hard read data from the memory device according to the first hard read voltage; read the second hard read data according to the second hard read voltage before reading the first hard read data; and cache the second hard read data to the memory; The hard decoder is used to: perform the hard decision decoding on the first hard read data; The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data according to the first hard read data and the cached second hard read data; send the first hard read data or the second hard read data to the soft decoder; send the first soft data to the soft decoder; The soft decoder is used to perform first soft decision decoding according to the first soft data and the first hard read data, or to perform first soft decision decoding according to the first soft data and the second hard read data.

16. The memory system according to claim 15, characterized in that: The memory is further used to cache the first hard read data; The processor is further configured to: read third hard read data according to a third hard read voltage after the first soft decision decoding fails; The hard decoder is further used to: perform the hard decision decoding on the third hard read data; The processor is further configured to: after the hard decision decoding of the third hard read data fails, obtain corresponding second soft data according to the cached first hard read data and the third hard read data; The soft decoder is further configured to: perform the first soft decision decoding according to the second soft data and the first hard read data, or perform the first soft decision decoding according to the second soft data and the third hard read data.

17. The memory system according to claim 16, wherein: The processor is also used to: determine whether one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold; if so, end the first stage of error correction code ECC error correction.

18. The memory system according to claim 17, characterized in that: The soft decoder is further configured to: after the ECC error correction of the first stage fails, perform the ECC error correction of the second stage, wherein the ECC error correction of the second stage includes: performing at least one second soft decision decoding; Wherein, when one of the following situations occurs: the second soft decision decoding is successful, and the number of soft read retries reaches a second set threshold, the second stage of ECC error correction is terminated.

19. The memory system according to claim 18, wherein: The memory controller further includes: a RAIN error corrector, configured to: perform a third-stage independent NAND redundant array RAIN error correction after the second-stage ECC error correction fails; The processor is further used to: after the RAIN error correction in the third stage fails, output indication information for characterizing the decoding failure; in one of the following situations: the ECC error correction in the first stage is successful, the ECC error correction in the second stage is successful, and the RAIN error correction in the third stage is successful, output the read data that has been successfully decoded.

20. A memory controller, characterized in that: include: processor, memory, hard decoder and soft decoder, among which; The processor is configured to: read first hard read data from a memory device coupled to the memory controller according to a first hard read voltage; and before reading the first hard read data, read second hard read data from the memory device according to a second hard read voltage; and caching the second hard read data into the memory; The hard decoder is used to: perform hard decision decoding on the first hard read data; The processor is further configured to: after the hard decision decoding of the first hard read data fails, obtain corresponding first soft data according to the first hard read data and the cached second hard read data; sending the first hard read data or the second hard read data to the soft decoder; sending the first soft data to the soft decoder; The soft decoder is used to: perform a first soft decision decoding according to the first soft data and the first hard read data, or perform a first soft decision decoding according to the first soft data and the second hard read data; The processor is further used to: determine whether one of the following situations occurs: the hard decision decoding is successful, the first soft decision decoding is successful, and the number of hard read retries reaches a first set threshold; if so, end the first stage of ECC error correction; The first hard read voltage is one of a plurality of re-read voltages having a certain offset from an initial read voltage; and the second hard read voltage is the initial read voltage or a re-read voltage among the plurality of re-read voltages except the first hard read voltage.

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