Display panel, preparation method thereof and display device

Abstract

The invention provides a display panel, a preparation method thereof and a display device, and belongs to the technical field of display. In the display panel, a side edge wire is connected with a first surface wire through an electrode structure, and further passes through a first surface and a side surface in sequence to extend to a second surface. The electrode structure comprises at least one layer of conductive pattern and at least one passivation layer, wherein the conductive pattern and the passivation layer are sequentially stacked in the direction away from the substrate, and the passivation layer is located on the side, away from the substrate, of each layer of conductive pattern. The first included angle between any passivation layer and the bearing surface of the substrate is smaller than or equal to the second included angle between the conductive pattern close to the substrate and the bearing surface of the substrate, so that the problem that a film layer climbs and falls off due to the fact that the included angle is too large due to the influence of a preparation process can be avoided, and it can be ensured that the product yield is good.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Mini light emitting diode (mini LED) has gradually become the mainstream of the market due to its advantages such as self-luminescence, high brightness and small size. It can be used in two scenarios: direct display or backlight.

[0003] In the related art, large-size display products including mini LEDs often include multiple spliced ​​display panels. Considering the impact of the seam on the display, the driver chip is currently set on the back of the display panel, and the light-emitting element and electrode structure are set on the front of the display panel, and the side wiring is set on the side of the display panel, and one end of the side wiring is electrically connected to the light-emitting element through the electrode structure, and the other end of the side wiring is extended to the back through the front and side in turn to be electrically connected to the driver chip, so that the driver chip and the light-emitting element are indirectly transferred, thereby driving the light-emitting element to emit light. In addition, the current electrode structure generally includes a buffer layer, a conductive pattern and a passivation layer stacked in sequence.

[0004] However, due to the influence of the manufacturing process, peeling is prone to occur between adjacent film layers in the current electrode structure, which leads to a poor yield of display products. Summary of the invention

[0005] Provided are a display panel and a method for manufacturing the same, and a display device, which can solve the problem of poor yield of display products caused by easy shedding between adjacent film layers in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, the display panel comprising:

[0007] A substrate having a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area;

[0008] A first surface wiring located in a display area of ​​the first surface, an electrode structure located in a peripheral area of ​​the first surface, and a side wiring located on at least one side surface of the plurality of side surfaces;

[0009] One end of the side wiring is electrically connected to the electrode structure, and the other end of the side wiring sequentially passes through the first surface and the at least one side surface and extends to the second surface, and the electrode structure is also electrically connected to the first surface wiring;

[0010] Furthermore, the electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on a side of each conductive pattern away from the substrate, and a first angle between any one of the at least one passivation layer and the supporting surface of the substrate is less than or equal to a second angle between the conductive pattern of the at least one conductive pattern close to the substrate and the supporting surface of the substrate.

[0011] Optionally, the first angle is equal to the second angle, and the angle is 0; and the electrode structure includes:

[0012] A first conductive pattern, a first passivation layer, and a second passivation layer sequentially stacked in a direction away from the substrate;

[0013] a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern;

[0014] and a protection layer located in the through hole and covering the first conductive pattern.

[0015] Optionally, the first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; the electrode structure includes:

[0016] A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate;

[0017] a through hole penetrating the second passivation layer and exposing the second conductive pattern;

[0018] a protection layer located in the through hole and covering the second conductive pattern;

[0019] a transfer hole penetrating the first passivation layer and exposing the first conductive pattern, the second conductive pattern being transferred to the first conductive pattern through the transfer hole, and the transfer hole being away from the at least one side surface relative to the through hole;

[0020] And, a spacer layer located between the first conductive pattern and the first passivation layer, the orthographic projection of the spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the spacer layer is greater than the thickness of any other film layer in the electrode structure.

[0021] Optionally, a third angle between the spacer layer and the supporting surface of the substrate is smaller than the second angle, and the first angle is equal to the third angle;

[0022] Furthermore, the first angles between each passivation layer and the bearing surface of the substrate are equal, and the fourth angle between the second conductive pattern and the bearing surface of the substrate is equal to the first angle.

[0023] Optionally, the thickness of the spacer layer is greater than 3 microns.

[0024] Optionally, the material of the spacing layer includes: resin material.

[0025] Optionally, the electrode structure further includes:

[0026] A third passivation layer is located between the first conductive pattern and the spacer layer, and the via hole also penetrates the third passivation layer to expose the first conductive pattern.

[0027] Optionally, the first surface routing includes: a first routing layer and a second routing layer stacked in sequence in a direction away from the substrate;

[0028] Wherein, a first conductive pattern layer included in the electrode structure is located in the same layer as the first wiring layer;

[0029] The electrode structure includes two layers of conductive patterns, namely, a first conductive pattern and a second conductive pattern stacked in sequence. The first conductive pattern and the first routing layer are located in the same layer, and the second conductive pattern and the second routing layer are located in the same layer.

[0030] Optionally, the thickness of the protective layer included in the electrode structure is greater than the thickness of the through hole, and the material of the protective layer includes: metal material.

[0031] Optionally, the material of the protective layer includes: nickel and / or gold.

[0032] Optionally, in the electrode structure, at least one layer of the conductive pattern includes: a plurality of sub-conductive patterns stacked sequentially in a direction away from the substrate.

[0033] Optionally, in the electrode structure, at least one layer of the conductive pattern comprises: three layers of sub-conductive patterns stacked in sequence in a direction away from the substrate;

[0034] Furthermore, the materials of the three-layer sub-conductive pattern include, in sequence: metal molybdenum, metal copper and metal molybdenum; or metal molybdenum-niobium, metal copper and metal molybdenum-niobium.

[0035] Optionally, the at least one layer of conductive patterns includes: a conductive pattern in the at least one layer of conductive patterns that is close to a side of the substrate.

[0036] Optionally, in the electrode structure, the thickness of at least one passivation layer is greater than 2000 angstroms and less than or equal to 4000 angstroms.

[0037] Optionally, the at least one passivation layer includes: a passivation layer on a side of the at least one passivation layer away from the substrate.

[0038] In another aspect, a method for preparing a display panel is provided, for preparing the display panel as described in the above aspect; the method comprises:

[0039] Providing a substrate, wherein the provided substrate has a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area;

[0040] A first surface wiring is formed in a display area of ​​the first surface, and an electrode structure is formed in a peripheral area of ​​the first surface, wherein the electrode structure is electrically connected to the first surface wiring;

[0041] forming a side wiring on at least one side surface among the plurality of side surfaces, electrically connecting one end of the side wiring to the electrode structure, and extending the other end of the side wiring to the second surface through the first surface and the at least one side surface in sequence;

[0042] Among them, the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on the side of each conductive pattern away from the substrate, and the first angle between any passivation layer in the at least one passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern in the at least one conductive pattern close to the substrate and the supporting surface of the substrate.

[0043] Optionally, the first angle is equal to the second angle, and the angle is 0; and an electrode structure is formed in a peripheral area of ​​the first surface, comprising:

[0044] Forming a first conductive pattern, a first passivation layer, and a second passivation layer sequentially stacked in a direction away from the substrate on one side of the substrate;

[0045] forming a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern;

[0046] And, a protection layer covering the first conductive pattern is formed in the through hole.

[0047] Optionally, the first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; an electrode structure is formed in a peripheral area of ​​the first surface, comprising:

[0048] A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate;

[0049] forming a through hole penetrating the second passivation layer and exposing the second conductive pattern;

[0050] forming a protection layer covering the second conductive pattern in the through hole;

[0051] forming a via hole penetrating the first passivation layer and exposing the first conductive pattern, wherein the via hole is formed away from the at least one side surface relative to the through hole;

[0052] Connecting the second conductive pattern to the first conductive pattern through the connecting hole;

[0053] A spacer layer is formed between the first conductive pattern and the first passivation layer, and the orthographic projection of the formed spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the formed spacer layer is greater than the thickness of any other film layer in the electrode structure.

[0054] Optionally, forming a first surface wiring in the display area of ​​the first surface includes: forming a film of a conductive material in a corresponding area, and then forming the first surface wiring in the display area of ​​the first surface by using a yellow light process;

[0055] Forming a side wiring on at least one of the plurality of side surfaces comprises: forming a film of a conductive material in a corresponding area, and then forming the side wiring on at least one of the plurality of side surfaces by a laser etching process.

[0056] In another aspect, a display device is provided, the display device comprising: a power supply component, and the display panel as described in the above aspect;

[0057] Wherein, the power supply component is coupled to the display panel and is used to supply power to the display panel.

[0058] In summary, the beneficial effects brought about by the technical solution provided by the embodiments of the present disclosure may at least include:

[0059] A display panel and a method for manufacturing the same, as well as a display device are provided. In the display panel, the side wiring is connected to the first surface wiring through an electrode structure, and further extends to the second surface through the first surface and the side surface in sequence. The electrode structure includes at least one layer of conductive patterns stacked in sequence in a direction away from the substrate and at least one layer of passivation layer located on the side of each layer of conductive patterns away from the substrate. Since the first angle between any layer of passivation layer and the bearing surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate and the bearing surface of the substrate, it is possible to avoid the problem of excessive angle caused by the influence of the preparation process, thereby causing the film layer to climb and fall off, and ensure a good product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0061] Figure 1 is a schematic diagram of the front structure of a display panel provided by an embodiment of the present disclosure;

[0062] Figure 2 is Figure 1 A cross-sectional schematic diagram of a display panel based on the structure shown;

[0063] Figure 3 is Figure 1 A cross-sectional schematic diagram of another display panel based on the structure shown;

[0064] Figure 4 is a film layer structure diagram of an electrode structure in a display panel provided by an embodiment of the present disclosure;

[0065] Figure 5 It is a film layer structure diagram of an electrode structure in a display panel in the related art;

[0066] Figure 6 is Figure 4 A top view of a display panel shown based on the structure shown;

[0067] Figure 7 is Figure 6 A cross-sectional schematic diagram of another display panel based on the structure shown;

[0068] Figure 8 is a schematic structural diagram of a pixel in a display panel provided by an embodiment of the present disclosure;

[0069] Fig. 9is a schematic diagram of a SEM slice of a display panel provided by an embodiment of the present disclosure;

[0070] Fig.10 is a schematic diagram of a process for forming a conductive pattern provided by an embodiment of the present disclosure;

[0071] Fig.11 is a film layer structure diagram of another electrode structure in a display panel provided by an embodiment of the present disclosure;

[0072] Fig.12 is a film layer structure diagram of an electrode structure in another display panel provided by an embodiment of the present disclosure;

[0073] Fig.13 is a film layer structure diagram of a first wiring layer in a display panel provided by an embodiment of the present disclosure;

[0074] Fig.14 is a schematic diagram of an SEM slice of another display panel provided by an embodiment of the present disclosure;

[0075] Fig.15 is a schematic diagram of an SEM slice of another display panel provided by an embodiment of the present disclosure;

[0076] Fig.16 is a flow chart of a method for preparing a display panel provided by an embodiment of the present disclosure;

[0077] Fig.17 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0078] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0079] Figure 1 It is a structural schematic diagram of a display panel provided in an embodiment of the present disclosure. Figure 2 is Figure 1 A cross-sectional view of a display panel in the mm' direction is shown based on FIG. Figure 3 is Figure 1 Another cross-sectional view of a display panel in the mm' direction is shown based on FIG. Figures 1 to 3 It can be seen that the display panel recorded in the embodiment of the present disclosure includes:

[0080] Substrate 01. The substrate 01 has a first surface A and a second surface B opposite to each other, and a plurality of side surfaces C connecting the first surface A and the second surface B, and the first surface A includes a display area A1 and a peripheral area A2 closer to the side surface C than the display area A1. For example, Figure 1 The illustrated substrate 01 has four side surfaces C.

[0081] Optionally, the peripheral area A2 may be as follows Figure 1 As shown, the peripheral area A2 is located around the rectangular display area A1, surrounding the display area A1; or, in some embodiments, the peripheral area A2 may also partially surround the display area A1, such as the peripheral area A2 may be located Figure 1 The lower side of the rectangular display area A1 is shown. The present disclosure embodiment does not limit this. In addition, the display area A1 and the peripheral area A2 can be as follows Figure 1 Alternatively, in some embodiments, the display area A1 and the peripheral area A2 may also be circular or elliptical. The embodiments of the present disclosure do not limit this. Figure 1 As shown, the shape of the peripheral area A2 and the shape of the display area A1 can be regular shapes; or, in some embodiments, the shape of the peripheral area A2 and the shape of the display area A1 can also be irregular shapes. Of course, to ensure the display effect, the area of ​​the display area A1 is generally larger than the area of ​​the peripheral area A2.

[0082] Continue to combine Figures 1 to 3 It can also be seen that the display panel recorded in the embodiment of the present disclosure further includes:

[0083] The first surface wiring L1 located in the display area A1 of the first surface A, the electrode structure 02 located in the peripheral area A2 of the first surface A, and the side wiring L2 located on at least one side surface C of the plurality of side surfaces C. For example, Figure 1 In the display panel shown, at least one side surface C is two opposite side surfaces among the four side surfaces. One end of the side line L2 is electrically connected to the electrode structure 02, and the other end of the side line L2 sequentially passes through the first surface A and at least one side surface C and extends to the second surface B, and the electrode structure 02 is also electrically connected to the first surface line L1.

[0084] Optional, continue to refer to Figures 1 to 3 It can also be seen that the display panel recorded in the embodiment of the present disclosure may also include a plurality of light-emitting elements L01 located in the display area A1 and an external circuit board located on the second surface B. The first surface trace L1 may also be electrically connected to the light-emitting element L01, and the side trace L2 may also be electrically connected to the external circuit board when extending to the second surface B. Thus, the purpose of switching the external circuit board to the light-emitting element L01 is achieved, so that the external circuit board can reliably drive the light-emitting element L01 to emit light.

[0085] Optionally, in some embodiments, Figure 2As shown, the portion of the side routing L2 located on the second surface B may have a fan-out line structure, and its free end extending through the first surface A and at least one side surface C to the second surface B may be electrically connected to the gold finger structure of the external circuit board, thereby achieving the purpose of connecting the external circuit board to the light-emitting element L01 through the side routing L2 and the first surface routing L1 in sequence.

[0086] Or, in other embodiments, Figure 3 As shown, the display panel recorded in the embodiment of the present disclosure may also include: a second surface routing line L3 located on the second surface B. The second surface routing line L3 may have a fan-out line structure, and one end of the second surface routing line L3 having the fan-out line structure may be electrically connected to the gold finger structure of the external circuit board, and the other end of the second surface routing line L3 may be electrically connected to the side routing line L2, so as to achieve the purpose of connecting the external circuit board to the light-emitting element L01 through the second surface routing line L3, the side routing line L2 and the first surface routing line L1 in sequence. That is, in some other embodiments, the free end of the side routing line L2 extending to the second surface B through the first surface A and at least one side surface C may be electrically connected to the second surface routing line L3 on the second surface B, so as to be indirectly electrically connected to the external circuit board through the second surface routing line L3.

[0087] Optionally, the display panel may include a plurality of first surface routing lines L1, a plurality of electrode structures 02, a plurality of side routing lines L2, and a plurality of second surface routing lines L3. The plurality of first surface routing lines L1 may be connected to the plurality of electrode structures 02 in a one-to-one correspondence, that is, each first surface routing line L1 is electrically connected to an electrode structure 02, and each first surface routing line L1 is electrically connected to a different electrode structure 02. The plurality of side routing lines L2 may be connected to the plurality of electrode structures 02 in a one-to-one correspondence, and may be connected to the plurality of second surface routing lines L3 in a one-to-one correspondence. That is, each side routing line L2 is electrically connected to an electrode structure 02 and a second surface routing line L3, respectively, and each side routing line L2 is electrically connected to a different electrode structure 02 and a different second surface routing line L3.

[0088] Optional, combined Figure 2 In the disclosed embodiment, the first surface wiring L1 and the electrically connected electrode structure 02 can be an integrated structure; the second surface wiring L3 and the electrically connected side wiring L2 can be an integrated structure. In this way, the process can be simplified and the cost can be saved.

[0089] Optionally, the light-emitting element L01 includes but is not limited to mini LED, (organic light-emitting diode, OLED) and micro light-emitting diode (micro light-emitting diode, micro LED). The size of the mini LED is between OLED and micro LED, which is about 100 to 200 microns (μm). The embodiment of the present disclosure is described by taking the light-emitting element L01 as a mini LED as an example.

[0090] It should be noted that, under the premise that the light-emitting element L01 located in the display area A1 in the first surface A emits light, it can be known that the first surface A is the light-emitting surface of the display panel, and correspondingly, the second surface B opposite to the first surface A is the backlight surface of the display panel. Optionally, in the embodiment of the present disclosure, the first surface A as the light-emitting surface can also be referred to as the front side, and the second surface B as the backlight surface can be referred to as the back side. Correspondingly, the first surface trace L1 located on the first surface A can also be referred to as the front trace, and the second surface trace L3 located on the second surface B can be referred to as the back trace. Based on the above embodiment, it can be known that the embodiment of the present disclosure is to transfer the binding area between the light-emitting element L01 and the external circuit board to the back side of the display panel, and realize the binding connection between the light-emitting element L01 and the external circuit board through the front + side + back lines, which is often used in scenarios where all four sides of direct display products can be spliced ​​to avoid the seam affecting the display uniformity of the product.

[0091] In addition, in some embodiments, the front wiring can be made by yellow light process, and the side wiring and the back wiring can be made by laser etching process, and the process under this embodiment can be called a single-sided back plate (BP) process. Alternatively, in some embodiments, both the front wiring and the back wiring can be made by yellow light process, and only the side wiring is made by laser etching process, and the process under this embodiment can be called a double-sided BP process. The embodiments of the present disclosure do not limit the panel preparation process.

[0092] exist Figures 1 to 3 Based on the structure shown, continue to refer to Figure 4 It can be seen from the film layer structure diagram that in the display panel provided by the embodiment of the present disclosure, the electrode structure 02 located in the peripheral area A2 includes:

[0093] A buffer layer 021, at least one conductive pattern 022, and at least one passivation layer 023 located on a side of each conductive pattern 022 away from the substrate 01 and stacked sequentially in a direction away from the substrate 01.

[0094] Among them, the first angle α1 between any passivation layer 023 in the at least one passivation layer 023 and the bearing surface of the substrate 01 is less than or equal to (that is, not greater than) the second angle α2 between the conductive pattern 022 close to the substrate 01 in the at least one conductive pattern 022 and the bearing surface of the substrate 01. That is, in the embodiment of the present disclosure, even if the conductive pattern 022 close to the substrate 01 is thicker, has a steeper slope, and has a larger angle with the substrate 01 due to the influence of the preparation process and the film layer material, the slope of other film layers located on the side of the conductive pattern 022 with a steeper slope away from the substrate 01 can still be set to be smaller, and the angle with the substrate 01 is smaller, so as to avoid peeling between film layers.

[0095] Optionally, in some embodiments, the electrode structure 02 may further include a wiring protection layer located on at least one side surface C and covering the side wiring L2 to protect the side wiring L2, play a role in electrical insulation and water-proof oxygen corrosion, and prevent the side wiring L2 from being damaged by the outside world, causing peeling, disconnection, or oxidation. In some embodiments, the wiring protection layer is, for example, a protective adhesive layer or an ink layer.

[0096] In summary, an embodiment of the present disclosure provides a display panel. In the display panel, the side wiring is connected to the first surface wiring through the electrode structure, and also extends to the second surface through the first surface and the side surface in sequence. Wherein, the electrode structure includes at least one layer of conductive pattern stacked in sequence in a direction away from the substrate and at least one passivation layer located on the side of each conductive pattern away from the substrate. Because the first angle between any passivation layer and the bearing surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate and the bearing surface of the substrate, it is possible to avoid the problem of the angle being too large due to the influence of the preparation process, thereby causing the film layer to climb and fall off, and ensure a good product yield.

[0097] As an optional implementation, the first angle α1 between any passivation layer 023 and the bearing surface of the substrate 01 can be smaller than the second angle α2 between the conductive pattern 022 close to the substrate 01 and the bearing surface of the substrate 01, and the first angle α1 and the second angle α2 can both be greater than 0 and less than 90 degrees. On this basis, Figure 4 As shown, in this implementation, the electrode structure 02 may include:

[0098] 1. A first conductive pattern 022a, a first passivation layer 023a, a second conductive pattern 022b, and a second passivation layer 023b are sequentially stacked in a direction away from the substrate 01, and the orthographic projection of the first conductive pattern 022a on the substrate 01 can be located within the orthographic projection of the second conductive pattern 022b on the substrate 01. The electrode structure 02 may include two conductive patterns 022 and two passivation layers 023.

[0099] Optionally, the thickness of the first conductive pattern 022a is generally between 1.8 μm and 2.8 μm, such as 2 μm; the thickness of the first passivation layer 023a and the second passivation layer 023b is generally between 2000 angstroms. to Between, such as The thickness of the second conductive pattern 022 b is generally between 0.6 μm and 0.9 μm, such as 0.9 μm. It should be noted that in the embodiment of the present disclosure, the thickness direction may be a direction perpendicular to the bearing surface of the substrate 01 .

[0100] 2. A through hole K1 penetrating the second passivation layer 023b and exposing the second conductive pattern 022b.

[0101] 3. The protective layer 024 located in the through hole K1 and covering the second conductive pattern 022b. The protective layer 024 can be used to protect the second conductive pattern 022b exposed to the outside to prevent water vapor in the air from corroding the second conductive pattern 022b.

[0102] 4. A transfer hole K2 penetrates the first passivation layer 023a and exposes the first conductive pattern 022a. The second conductive pattern 022b is transferred to the first conductive pattern 022a through the transfer hole K2. The first conductive pattern 022a and the second conductive pattern 022b transferred to each other can also be called a transfer portion included in the electrode structure 02.

[0103] It should be noted that the transfer hole K2 can be away from at least one side surface C relative to the through hole K1. Figure 4 As shown, the through hole K1 may be close to at least one side surface C, and the orthographic projection of the through hole K1 on the substrate 01 does not overlap with the orthographic projection of the first conductive pattern 022 a on the substrate 01 , and they are spaced apart from each other.

[0104] exist Figure 4 Based on Figure 5It can be seen from the film layer structure diagram shown that: at present, the electrode structure 02 located in the peripheral area A2 generally includes: a buffer layer 021, a first conductive pattern 022a, a first passivation layer 023a, a second conductive pattern 022b, and a second passivation layer 023b stacked in sequence in a direction away from the substrate 01. That is, the first passivation layer 023a is directly overlapped on the side of the first conductive pattern 022a away from the substrate 01. There is a structure in which the first passivation layer 023a and the second conductive pattern 022b climb the first conductive pattern 022a at the transfer hole K2 of the transfer part. Since the thickness of the first passivation layer 023a and the second conductive pattern 022b is relatively thin (e.g., 0.4μm and 0.9μm, respectively), and the thickness of the first conductive pattern 022a is relatively thick (e.g., 2μm), the first passivation layer 023a and the second conductive pattern 022b have a poor coverage problem at the climbing part of the first conductive pattern 022, which may cause peeling between the film layers or even film breakage in severe cases.

[0105] In the present disclosure embodiment, continue to refer to Figure 4 It can be seen from the film layer structure diagram that in the display panel recorded in the embodiment of the present disclosure, the electrode structure 02 may include, in addition to the above film layers, also include:

[0106] 5. A spacer layer 025 located between the first conductive pattern 022a and the first passivation layer 023a.

[0107] The orthographic projection of the spacer layer 025 on the substrate 01 may be located within the orthographic projection of the first passivation layer 023a on the substrate 01, and covers the side surface C in contact with the buffer layer 021 and the top surface away from the buffer layer 021 in the first conductive pattern 022a, and the thickness of the spacer layer 025 may be greater than the thickness of any other film layer in the electrode structure 02. For example, the thickness of the spacer layer 025 may be greater than 3 μm, such as in some embodiments, the thickness of the spacer layer 025 may be 4 μm.

[0108] That is, in the disclosed embodiment, a spacer layer 025 may be provided to wrap around the edge of the first conductive pattern 022a, so that the step of the second conductive pattern 022b is formed by the spacer layer 025, rather than being directly formed by the first passivation layer 023a. Since the thickness of the spacer layer 025 is relatively thick, on the one hand, better coverage can be achieved at the slope of the first conductive pattern 022a, without the risk of film breakage; on the other hand, the angle α3 between it and the bearing surface of the substrate 01 can be made smaller, that is, the slope is relatively gentle, which is more suitable for covering and wrapping thinner film layers. On this basis, the first angle α1 between any passivation layer 023 and the bearing surface of the substrate 01 can be made smaller than the second angle α2 between the conductive pattern 022 close to the substrate 01 and the bearing surface of the substrate 01, thereby preventing the first passivation layer 023a and the second conductive pattern 022b from climbing the steep slope of the first conductive pattern 022a. That is, a gentle slope can be formed by the thicker spacer layer 025, which facilitates the coverage of the first passivation layer 023a and the second conductive pattern 022b, thereby improving the peeling defect caused by the first passivation layer 023a and the second conductive pattern 022b at the transfer via K2.

[0109] That is, in the embodiment of the present disclosure, the third angle α3 between the spacer layer 025 and the bearing surface of the substrate 01 may also be smaller than the second angle α2. Furthermore, in some embodiments, the first angle α1 between any passivation layer 023 and the bearing surface of the substrate 01 may also be equal to the third angle α3. Furthermore, the first angle α1 between each passivation layer 023 and the bearing surface of the substrate 01 is equal, and the fourth angle (not marked in the figure) between the second conductive pattern 022b and the bearing surface of the substrate 01 may also be equal to the first angle α1. In this way, better coverage between adjacent film layers can be further ensured to avoid peeling between film layers.

[0110] Optionally, in the embodiment of the present disclosure, the material of the spacer layer 025 can be a resin material with a relatively thick thickness and a smooth surface. Figure 5 Marked area Q1. In the area Q1, at the boundary of the transfer hole K2 where the first conductive pattern 022a and the second conductive pattern 022b are transferred in the current display panel, there is a structure where the first passivation layer 023a, the second conductive pattern 022b, the second passivation layer 023b and other film layers climb the side of the first conductive pattern 022a. The embodiment of the present disclosure introduces a thicker spacer layer 025 between the first conductive pattern 022a and the first passivation layer 023a to better cover the side of the first conductive pattern 022a, so that the subsequent second conductive pattern 022b and the second passivation layer 023b and other film layers can maintain good coverage at the side climbing of the spacer layer 025, thereby better improving the peeling problem between the film layers.

[0111] Optional, Figure 6 shows a front schematic diagram of a display panel, Figure 4 for Figure 6 Cross-sectional view of the structure shown in the nn' direction. Figure 7 Shows Figure 6 Cross-sectional view of the structure shown in the kk' direction.

[0112] Combination Figure 6 and Figure 7 It can be seen that the display area A1 on the front of the display panel provided by the embodiment of the present disclosure may include: a buffer layer 021, a first wiring layer M1, a first resin layer Resin1, a first passivation layer 023a, a second wiring layer M2, a second resin layer Resin2, and a second passivation layer 023b stacked in sequence in a direction away from the substrate 01. The first wiring layer M1 and the second wiring layer M2 may be used to form a plurality of front wiring lines L1.

[0113] And, continue to refer to Figure 6 It can be seen that in the display panel provided by the embodiment of the present disclosure, the first resin layer Resin1 in the display area A1 can be extended to the peripheral area A2 as the spacer layer 025 of the electrode structure 02. That is, in the embodiment of the present disclosure, the resin layer is not only located in the display area A1 on the front side, but also in the peripheral area A2 on the front side, and overlaps with the orthographic projection of the electrode structure 02 on the substrate 01. Figure 4 As shown, the resin layer also covers the side of the first conductive pattern 022a and does not block the transfer hole K2. In this way, the subsequent second conductive pattern 022b and the second passivation layer 023b can maintain good coverage at the side slope of the spacer layer 025, thereby improving the peeling problem between the film layers. Figure 5 In the display panel of the related art, the first resin layer Resin1 is only located in the display area A1 on the front side, and does not extend to the peripheral area A2. That is, in the related art, the orthographic projection of the first resin layer Resin1 on the substrate 01 and the orthographic projection of the first conductive pattern 022a on the substrate 01 do not overlap, and the resin layer is far away from at least one side surface C relative to the electrode structure 02. Therefore, the above-mentioned film peeling problem is very likely to occur in area Q1.

[0114] Optionally, in some embodiments, continue to refer to Figure 6It can be seen that the minimum distance d2_min between the side of the spacer layer 025 close to at least one side surface C and the side of the electrode structure 02 close to at least one side surface C is generally about 105 μm, and the maximum distance d2_max between the side of the spacer layer 025 close to at least one side surface C and the side of the electrode structure 02 close to at least one side surface C is generally about 170 μm.

[0115] Optionally, in some embodiments, Figure 6 Based on Figure 1 and Figure 8 As can be seen from the partial schematic diagram of a display panel shown in FIG. 1 , the display panel described in the embodiment of the present disclosure may include: Figure 1 The plurality of pixels P arranged in an array as shown in the figure may be arranged in N rows and M columns, each pixel P includes at least three sub-pixels SP of different colors and a driving element for driving each sub-pixel SP to emit light, and each sub-pixel SP includes at least one light-emitting element L01. The light-emitting element L01 and the driving element may be located as shown in FIG. Figure 7 The second passivation layer 023 b is shown at a side away from the substrate 01 .

[0116] For example, Figure 8 As shown, the embodiment of the present disclosure is described by taking each pixel P including three sub-pixels SP, and each sub-pixel SP including one light-emitting element L01 as an example. The three light-emitting elements L01 in the figure are arranged in three rows, and the light-emitting elements L01 in the three rows can be the first color (e.g., red) light-emitting element L01, the second color (e.g., green) light-emitting element L01 and the first color (e.g., blue) light-emitting element L01 from top to bottom.

[0117] Optionally, in some embodiments, the second wiring layer M2 may further form a plurality of connection pads (not shown in the figure), and the plurality of connection pads may be used to electrically connect the light emitting element L01 and the driving element. For example, the pins of the light emitting element L01 and the pins of the driving element may be electrically connected to the corresponding connection pads through a welding material S (such as solder, tin-silver-copper alloy or tin-copper alloy, etc.), and as Figure 7 As shown, a protective layer 024 as described in the above embodiment is also provided on the connection pad. The pins of the light-emitting element L01 can be electrically connected to the two connection pads through the via holes penetrating the second passivation layer 023b and the second resin layer Resin2, and the pins of the driving element can be connected to the six connection pads through the via holes penetrating the second passivation layer 023b and the second resin layer Resin2, so that the light-emitting element L01 can emit light under the signal transmitted by the signal line and the control of the driving element.

[0118] Optionally, in some embodiments, continue to refer to Figure 6 and Figure 7It can be seen that the front wiring L1 formed by the first wiring layer M1 may include a data line Dm, a first positive signal line Hm1, a second positive signal line Hm2, a reference signal line Vm and a scan signal switching line Cn. The front wiring L1 formed by the second wiring layer M2 may include a plurality of scan signal lines Sn, each of which may be electrically connected to a scan signal switching line Cn. In addition, the driving element may be electrically connected to the cathode of the light-emitting element L01 in each sub-pixel SP driven by it, at least one data signal line Dm among the plurality of data lines, at least one scan signal line Sn among the plurality of scan lines, and at least one reference signal line Vm among the plurality of reference signal lines. The driving element may be configured to write the signal of the data signal line Dm into the sub-pixels SP of different colors in a time-sharing manner under the control of the scan signal line Sn, wherein the reference signal line Vm is used to provide a negative signal to the driving element so as to form a current path between the driving element and the light-emitting element L01. That is, under the drive of the signal transmitted by the front wiring L1, the light-emitting element L01 can emit light reliably.

[0119] Optionally, in some embodiments, continue to refer to Figure 8 It can also be seen that the driving element may have a first signal terminal O1, a second signal terminal O2, a third signal terminal O3, a fourth signal terminal O4, a fifth signal terminal O5 and a sixth signal terminal O6. Among them, the first signal terminal O1 is connected to the cathode - of the first color light emitting element L01, the second signal terminal O2 is connected to the cathode - of the second color light emitting element L01, the third signal terminal O3 is connected to the cathode - of the third color light emitting element L01, the fourth signal terminal O4 is electrically connected to the data signal line Dm, the fifth signal terminal O5 is connected to the scanning signal line Sn, and the sixth signal terminal O6 is connected to the reference signal line Vm. The anode + of the first color light emitting element L01 is connected to the second anode signal line Hm2, the anode + of the second color light emitting element L01 is connected to the first anode signal line Hm1, and the anode + of the third color light emitting element L01 is connected to the first anode signal line Hm1. The scanning signal line Sn is connected to the scanning signal adapter line Cn.

[0120] Based on the above embodiment records, Fig.10 FIG. 2 shows a microscope photo of a display panel after a spacer layer 025 is provided to cover the side of the first conductive pattern 022a. Fig.10 It can be seen that for the current Figure 5 For the solution shown in the figure, the first passivation layer 023a has a larger angle at the climbing position of the first conductive pattern 022a, generally averaging 69.8 degrees, and the maximum angle may even reach 77.4 degrees. Figure 4After the solution shown, the angle at the climbing position is significantly reduced, which can be reduced to an average of about 35 degrees, and the maximum value is about 41.2 degrees, which is not too large. It can be seen that the angle is reduced by about 35 degrees, so the slope can be reduced to half of the original, ensuring that the first passivation layer 023a can better cover the first conductive pattern 022a.

[0121] Taking the angle profile of a conductive pattern (eg, the first conductive pattern 022a located in the same layer as the first wiring layer M1) as an example, Fig. 9 The definition of the angle profile of any film layer in the embodiment of the present disclosure is as follows: In the preparation process, first, a film layer such as Fig. 9 The conductive film layer shown in step (1) in the above process is formed; then a patterned photoresist (PR) can be disposed on the side of the conductive film layer away from the substrate 01; then the patterned PR is used to perform exposure, development, etching and other processes on the conductive film layer to pattern the conductive film layer to obtain the desired conductive pattern. Due to the anisotropy of etching, a conductive pattern with an angle profile as shown in step (2) is finally formed. For example, in combination with Fig. 9 It can also be seen that the final angle profile can satisfy: tan(profile)=h / x, where x=x1-x2.

[0122] Among them, X1 is the lateral etching amount at the Po1 point of the conductive pattern, also known as the top lateral etching amount, which is mainly related to the strength of the adhesion between the conductive film layer and the PR; h refers to the thickness of the conductive film layer, which is determined by the coating process; X2 refers to the lateral etching amount at the Po2 point of the conductive pattern, which belongs to the unilateral etching bias (CD bias), which is related to the etching time, etching solution concentration, conductive film layer material, and the adhesion between the conductive film layer and the photoresist PR. It can be seen that the formed angle profile is related to the top lateral etching amount, CD bias and the thickness of the conductive film layer. Under the same etching conditions, the greater the thickness of the conductive film layer, the greater the angle profile of the formed conductive pattern; conversely, the smaller the thickness of the conductive film layer, the smaller the angle profile of the formed conductive pattern. That is, the angle profile of the formed conductive pattern is positively correlated with the thickness of the conductive film layer. Under the premise that the thickness of the conductive film layer is fixed, the angle profile of the conductive pattern can be changed by adjusting the top lateral etching amount and CD bias.

[0123] It should be noted that, combined with Fig.10 The microscope photo shown in FIG. 1 takes the third angle α3 between the spacer layer 025 and the supporting surface of the substrate 01 as an example to illustrate the angle measurement method recorded in the embodiment of the present disclosure. It can be seen that the spacer layer 025 is not as Fig. 9 Like the metal pattern in the figure, the side of the section of the spacer layer 025 is a straight line segment, and the side of the section of the spacer layer 025 is a curved line segment, and each point on the curved line segment has a corresponding tangent line. Therefore, the angle between each film layer and the bearing surface of the substrate 01 recorded in the embodiment of the present disclosure can refer to: the angle profile of the line connecting the highest point Po1 and the lowest point Po2 of the curved line segment. In addition, the highest point Po1 is not as Fig.10 The point Po3 in the curve segment with the largest distance from the substrate 01 is not the point where the tangent slope of each point on the curve segment changes suddenly (that is, the point where the slope changes the most), as shown in FIG. Fig.10 The point Po1 shown can also be defined as the highest point of the side in the cross section of the spacer layer 025 .

[0124] Optional, combined Fig.11 It can be seen from the film layer structure diagram of another display panel that the electrode structure 02 recorded in the embodiment of the present disclosure may also include:

[0125] The third passivation layer 023c is located between the first conductive pattern 022a and the spacer layer 025, and the transfer hole K2 can penetrate the third passivation layer 023c to expose the first conductive pattern 022a. By providing the third passivation layer 023c between the spacer layer 025 and the first conductive pattern 022a on the basis of providing the spacer layer 025, the first conductive pattern 022a can be protected.

[0126] It should be noted that Fig.11 The structure shown and Figure 4 The structure shown can be considered as two parallel implementations proposed based on the above optional implementation (that is, the first angle α1 and the second angle α2 can both be greater than 0 and less than 90 degrees). That is, in some embodiments, it can be as follows Figure 4 As shown, the electrode structure 02 includes a first conductive pattern 022a, a spacer layer 025, a first passivation layer 023a, a second conductive pattern 022b, and a second passivation layer 023b stacked in sequence; in other embodiments, it can be as follows Fig.11 As shown, the electrode structure 02 includes a first conductive pattern 022a, a third passivation layer 023c, a spacer layer 025, a first passivation layer 023a, a second conductive pattern 022b and a second passivation layer 023b which are stacked in sequence.

[0127] As another optional implementation: the first angle α1 between any passivation layer 023 and the bearing surface of the substrate 01 can be equal to the second angle α2 between the conductive pattern 022 close to the substrate 01 and the bearing surface of the substrate 01, and the angles of the first angle α1 and the second angle α2 can both be 0. That is, any passivation layer 023 and the conductive pattern 022 close to the substrate 01 can be parallel to the substrate 01. On this basis, Fig.12 As shown, in this implementation, the electrode structure 02 may include:

[0128] 1. The first conductive pattern 022a, the first passivation layer 023a and the second passivation layer 023b are sequentially stacked in a direction away from the substrate 01. That is, the electrode structure 02 may include a conductive pattern 022 and two passivation layers 023.

[0129] 2. A through hole K1 penetrating the first passivation layer 023a and the second passivation layer 023b and exposing the first conductive pattern 022a. As described in the above embodiment, the through hole K1 may be close to at least one side surface C. Generally, the distance between the side edge of the through hole K1 close to the at least one side surface and the boundary of the at least one side surface is about 11 μm.

[0130] 3. A protection layer 024 located in the through hole K1 and covering the first conductive pattern 022a.

[0131] In this alternative implementation, it can be considered that the second conductive pattern 022b described in the above embodiment is cancelled, and a layer of the first conductive pattern 022a is directly used as a binding terminal to be electrically connected to the side trace L2. Figure 3 and Fig.11 It can be seen that, compared with the above-mentioned optional implementation method, the other implementation method reduces the setting of the transfer hole for connecting the first conductive pattern 022a and the second conductive pattern 022b, that is, there is no need to set a transfer part, so correspondingly, the structure in which the second conductive pattern 022b is set on the side of the first conductive pattern 022a mentioned in the above embodiment does not exist, which essentially solves the peeling problem between film layers caused by the climbing setting.

[0132] Optional, reference Figure 6 and Figure 7 It can be seen that the first surface routing L1 recorded in the embodiment of the present disclosure may include: a first routing layer M1 and a second routing layer M2 stacked in sequence in a direction away from the substrate 01 .

[0133] On this basis, combined with Figure 4It can be seen from the film layer structure diagram that in the above optional implementation, the electrode structure 02 recorded in the embodiment of the present disclosure includes a first conductive pattern 022a and a second conductive pattern 022b stacked in sequence, in which the first conductive pattern 022a and the first wiring layer M1 are located on the same layer, and the second conductive pattern 022b and the second wiring layer M2 are located on the same layer. Fig.11 It can be seen from the film layer structure diagram that in the above another optional implementation, the electrode structure 02 recorded in the embodiment of the present disclosure includes a first conductive pattern 022a which is located in the same layer as the first wiring layer M1.

[0134] It should be noted that being located in the same layer may refer to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are made of the same material and are formed through the same composition process. In this way, the manufacturing process and manufacturing costs can be saved, and the manufacturing efficiency can be accelerated.

[0135] It should also be noted that, as described in the above embodiment, the thickness of the first wiring layer M1 is generally greater than the thickness of the second wiring layer M2, so the above-mentioned electrode structure 02 is set to only include another optional implementation method of the first conductive pattern 022a located on the same layer as the first wiring layer M1. Compared with an optional implementation method including the first conductive pattern 022a and the second conductive pattern 022b located on the same layer as the first wiring layer M1 and the second wiring layer M2, respectively, the overall thickness of the film layer of the electrode structure 02 near at least one side surface C is thicker, generally about 1.1μm thick. For example, for the above optional implementation method, the electrode structure 02 near at least one side surface C mainly includes: buffer layer 021+first passivation layer 023a+second conductive pattern 022b (that is, second wiring layer M2)+second passivation layer 023b. For the above-mentioned alternative implementation, the electrode structure 02 near at least one side surface C mainly includes: buffer layer 021 + first passivation layer 023a + first conductive pattern 022a (that is, first wiring layer M1) + second passivation layer 023b. In addition, another buffer layer may be included on the side of the second passivation layer 023b close to the substrate 01. The thicker the thickness, the more unfavorable the subsequent edge grinding process.

[0136] Optional, combined Figure 4 , Fig.11 and Fig.12It can also be seen that in the electrode structure 02 described in the embodiment of the present disclosure, the thickness of the protective layer 024 can be greater than the thickness of the through hole K1 in which it is located. For example, the thickness of the protective layer 024 can be about 3 to 4 μm.

[0137] Optionally, the material of the protection layer 024 may include: a metal material. For example, the material of the protection layer 024 may include: nickel and / or gold.

[0138] It should be noted that the peeling improvement method described in the above embodiment can be considered as an improvement method from the design perspective. The following embodiment proposes another improvement method from the process perspective:

[0139] First, in the embodiment of the present disclosure, the film structure of at least one layer of the conductive pattern 022 in the electrode structure 02 can be improved to reduce the slope, thereby improving the film coverage effect and improving the film peeling problem.

[0140] Optional, such as Fig.13 As shown, in the electrode structure 02 described in the embodiment of the present disclosure, at least one layer of conductive pattern 022 may include: multiple layers of sub-conductive patterns 0221 stacked in sequence in a direction away from the substrate 01 .

[0141] For example, Fig.13 In the electrode structure 02 shown, at least one conductive pattern 022 includes: three layers of sub-conductive patterns 0221 stacked in sequence in a direction away from the substrate 01. In addition, in the disclosed embodiment, the materials of the three-layer sub-conductive pattern 0221 may include: metal molybdenum Mo, metal copper Cu and metal molybdenum Mo in sequence, that is, a Mo / Cu / Mo structure; or metal molybdenum niobium MoNb, metal copper Cu and metal molybdenum niobium MoNb, that is, a MoNb / Cu / MoNb structure. Optionally, the thickness of each layer in the Mo / Cu / Mo structure may be: and The thickness of each layer in the MoCuMo structure can be and Here, the thickness and material are only schematic illustrations.

[0142] Optionally, in the embodiment of the present disclosure, the at least one layer of conductive pattern 022 may include: a conductive pattern 022 on the side close to the substrate 01 in the at least one layer of conductive pattern 022 included in the electrode structure 02. For example, the first conductive pattern 022a (that is, the first routing layer M1) recorded in the above embodiment. Of course, in some other embodiments, the at least one layer of conductive pattern 022 may also include: a conductive pattern 022 on the side away from the substrate 01 in the at least one layer of conductive pattern 022 included in the electrode structure 02, such as the second conductive pattern 022b recorded in the above embodiment. Accordingly, in the embodiment of the present disclosure, the first conductive pattern 022a may also be referred to as the Cu1 layer, and the second conductive pattern 022b may also be referred to as the Cu2 layer.

[0143] It should be noted that in current display panels, the first wiring layer M1 structure usually includes at most Mo / Cu stacked in sequence in a direction away from the substrate 01. Figure 5 , a first passivation layer 023a is directly disposed on one side of the first conductive pattern 022a located on the same layer as the first wiring layer M1. Due to the influence of the material, the adhesion between the first passivation layer 023a and the metal copper Cu is poor, and peeling is also prone to occur. However, the disclosed embodiment improves the structure of the first wiring layer M1 and sets it to include Mo / Cu / Mo or MoNb / Cu / MoNb stacked in sequence in the direction away from the substrate 01, which can directly reduce the angle between the first conductive pattern 022a located on the same layer as the first wiring layer M1 and the bearing surface of the substrate 01, and reduce the slope of the first conductive pattern 022a, thereby facilitating the coverage of the film layer on the side of the first conductive pattern 022a away from the substrate 01, ensuring the coverage integrity of the first passivation layer 023a at the climbing part of the first conductive pattern 022a, and improving the peeling problem of the film layer.

[0144] For example, on the basis of the structure that the first wiring layer M1 (that is, the first conductive pattern 022a) includes sequentially stacked Mo / Cu, the thickness of the Mo / Cu structure is respectively and For example, Fig.14 A schematic diagram of SEM slices is shown; on the basis of the first wiring layer M1 including a structure of Mo / Cu / Mo stacked in sequence, the thickness of the Mo / Cu / Mo structure is respectively and For example, Fig.15 Another microscope photo is shown. Fig.14 and Fig.15 It can be seen that the angle α2 of the first conductive pattern 022a currently only including the Mo / Cu structure is about 71 degrees, while the angle α2 of the first conductive pattern 022a including the Mo / Cu / Mo structure in the embodiment of the present disclosure can be reduced to 32.6 degrees. The angles here are only schematic illustrations. In addition, Fig.14 and Fig.15 The PRs provided on one side of the first conductive pattern 022a are also shown.

[0145] Optionally, the materials and thicknesses of other film layers are described as follows: the materials of the buffer layer 021 and the passivation layer 022 may include silicon nitride SiNx and / or silicon oxide SiOx. The thickness of the buffer layer 021 may be approximately to As a general rule,

[0146] Secondly, in the disclosed embodiment, at least one passivation layer 023 in the electrode structure 02 may be thicker to improve the coverage of the passivation layer 023 and improve the subsequent film peeling problem caused by the step difference of the first conductive pattern 022a.

[0147] Optionally, in the electrode structure 02, the thickness of at least one passivation layer 023 may be greater than and less than or equal to For example, the thickness of at least one passivation layer 023 may be set to

[0148] Optionally, the at least one passivation layer 023 with a larger thickness may include: the passivation layer 023 on the side away from the substrate 01 in the at least one passivation layer 023. For example, the second passivation layer 023b described in the above embodiment. Of course, in some other embodiments, the at least one passivation layer 023 with a larger thickness may also include the passivation layer 023 on the side close to the substrate 01, such as the first passivation layer 023a described in the above embodiment. In this way, the film coverage can also be improved and the film peeling problem can be improved.

[0149] Based on the above-mentioned embodiments, it can be known that the embodiments of the present disclosure can improve the peeling problem of the film layer by adding a spacer layer or directly eliminating the transfer hole from the design end, and can also improve the film layer structure and / or film layer thickness from the process end to improve the peeling problem of the film layer, thereby ultimately ensuring a good product yield.

[0150] In summary, an embodiment of the present disclosure provides a display panel. In the display panel, the side wiring is connected to the first surface wiring through the electrode structure, and also extends to the second surface through the first surface and the side surface in sequence. Wherein, the electrode structure includes at least one layer of conductive pattern stacked in sequence in a direction away from the substrate and at least one passivation layer located on the side of each conductive pattern away from the substrate. Because the first angle between any passivation layer and the bearing surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate and the bearing surface of the substrate, it is possible to avoid the problem of the angle being too large due to the influence of the preparation process, thereby causing the film layer to climb and fall off, and ensure a good product yield.

[0151] Fig.16 1 is a flow chart of a method for preparing a display panel provided by an embodiment of the present disclosure, which is used to prepare a display panel as described in the above embodiment of the present disclosure. Fig.16 As shown, the method includes:

[0152] Step 1601: Provide a substrate, wherein the provided substrate has a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area.

[0153] Step 1602, forming a first surface routing in the display area of ​​the first surface, and forming an electrode structure in the peripheral area of ​​the first surface, the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on the side of each conductive pattern away from the substrate, and a first angle between any passivation layer in the at least one passivation layer and the bearing surface of the substrate is less than or equal to a second angle between the conductive pattern in the at least one conductive pattern close to the substrate and the bearing surface of the substrate.

[0154] Step 1603, forming a side routing on at least one side surface among the multiple side surfaces, and electrically connecting one end of the side routing to the electrode structure, extending the other end of the side routing to the second surface through the first surface and at least one side surface in sequence, and electrically connecting the electrode structure to the first surface routing.

[0155] Among them, the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern and at least one passivation layer located on the side of each conductive pattern away from the substrate, and the first angle between any passivation layer in the at least one passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate in the at least one conductive pattern and the supporting surface of the substrate.

[0156] As an optional implementation: Figure 4As shown, in the formed electrode structure 02, the first angle α1 may be smaller than the second angle α2, and the first angle α1 and the second angle α2 may both be greater than 0 and less than 90 degrees. In this implementation, in the above step 1602, forming the electrode structure in the peripheral area of ​​the first surface may include the following steps:

[0157] a1. A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate on one side of the substrate, and the orthographic projection of the first conductive pattern on the substrate is located within the orthographic projection of the second conductive pattern on the substrate.

[0158] b1. Forming a through hole penetrating the second passivation layer and exposing the second conductive pattern.

[0159] c1. Forming a protection layer covering the second conductive pattern in the through hole.

[0160] d1. Forming a via hole penetrating the first passivation layer and exposing the first conductive pattern, wherein the formed via hole is away from at least one side surface relative to the through hole.

[0161] e1. Connect the second conductive pattern to the first conductive pattern through the connecting hole.

[0162] f1. A spacer layer is formed between the first conductive pattern and the first passivation layer, and the orthographic projection of the formed spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the formed spacer layer is greater than the thickness of any other film layer in the electrode structure.

[0163] As another optional implementation: Fig.12 As shown, in the formed electrode structure 02, the first angle α1 is equal to the second angle α2, and the first angle α1 and the second angle α2 may both be 0. In this implementation, in the above step 1602, forming the electrode structure in the peripheral area of ​​the first surface may include the following steps:

[0164] a2. Forming a first conductive pattern, a first passivation layer, and a second passivation layer that are sequentially stacked in a direction away from the substrate on one side of the substrate.

[0165] b2. Form a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern.

[0166] c2. Form a protection layer covering the first conductive pattern in the through hole.

[0167] Optionally, as described in the above embodiment, in the above step 1602, forming a first surface routing in the display area of ​​the first surface may include: forming the first surface routing in the display area of ​​the first surface using a yellow light process. Forming a side edge routing on at least one side surface of the plurality of side surfaces may include: forming a side edge routing on at least one side surface of the plurality of side surfaces using a laser etching process. Optionally, as described in the above embodiment, in some embodiments, a second surface routing may also be formed on the second surface to electrically connect the side edge routing to an external circuit board located on the second surface. And, forming a second surface routing on the second surface may include: forming a second surface routing on the second surface using a yellow light process or a laser etching process.

[0168] Among them, the process of using yellow light process to form front and back routing, and using laser etching process to form side routing can be called double-sided BP process; the process of using yellow light process to form front routing, and using laser etching process to form side and back routing can be called single-sided BP process.

[0169] Optional, with Fig.11 Taking the film layer structure shown, that is, one of the above optional implementations as an example, the following embodiment briefly describes the preparation process of the display panel:

[0170] 1) A buffer layer 021 can be formed on the provided substrate 01. Optionally, the substrate 01 provided here can be a glass substrate; and the buffer layer 021 can be formed by a magnetron sputtering process, and the thickness of the buffer layer 021 can be about

[0171] 2) Next, a Cu1 layer, i.e., a first conductive pattern 022a, can be formed on the side of the buffer layer 021 away from the substrate 01. Optionally, the first conductive pattern 022a can be formed by a process such as magnetron sputtering, cleaning, coating, baking, photo exposure, development, hard baking, etching, and lift-off, and the thickness of the first conductive pattern 022a is about 2 μm.

[0172] 3) Next, a third passivation layer 023c may be formed on the side of the Cu1 layer away from the substrate 01. Optionally, the third passivation layer 023c may be formed by a magnetron sputtering process, or, in some embodiments, may be formed by chemical vapor deposition (CVD). The thickness of the third passivation layer 023c formed here may be approximately

[0173] 4) Next, a spacer layer 025 may be formed on the side of the third passivation layer 023c away from the substrate 01. Optionally, the material of the spacer layer 025 may include a resin material, and the spacer layer 025 may be formed through a coating, photo and develop process, and the thickness of the formed spacer layer 025 may be about 4 μm.

[0174] 5) Next, a first passivation layer 023a may be formed on the side of the spacer layer 025 away from the substrate 01. Similarly, the first passivation layer 023a may be formed by a magnetron sputtering process or a chemical vapor deposition process, and the thickness of the first passivation layer 023a may be about Afterwards, the first passivation layer 023 a may be etched by an etching process to form a via hole K1 exposing the first conductive pattern 022 a .

[0175] 6) Next, a Cu2 layer, i.e., a second conductive pattern 022b, can be formed on the side of the first passivation layer 023a away from the substrate 01. Similarly, the second conductive pattern 022b can also be formed by magnetron sputtering, Cleaning, Coating, Baking, Photo, Develop, Hardbaking, Etch, and Lift-off processes, and the thickness of the formed second conductive pattern 022b can be about 0.9 μm.

[0176] 7) Next, a second passivation layer 023b may be formed on the side of the second conductive pattern 022b away from the substrate 01. Similarly, the second passivation layer 023b may also be formed by a magnetron sputtering process or a chemical vapor deposition process. It should be noted that, in some embodiments, the second passivation layer 023b may also include two passivation sublayers stacked in sequence in a direction away from the substrate 01, and may also include a resin layer located between the two passivation sublayers. The thickness of the passivation sublayers may be respectively and The thickness of the resin layer may be about 2 μm. At this point, the front side process is completed.

[0177] 8) Place the second surface of the substrate horizontally with the second surface facing upward, and at least form a backside wiring and a wiring protection layer on the second surface. Optionally, the thickness of the backside wiring can be about The thickness of the routing protection layer can be approximately The material of the back wiring may include Cu, and the material of the wiring protection layer may include a transparent conductive material, such as indium tin oxide (ITO). Finally, a magnetron sputtering process or a chemical vapor deposition process as described in the above embodiment may be used to form a layer with a thickness of about 100 nm on the wiring protection layer. The passivation protection layer 023b is patterned to expose the partial surface of the stacked structure composed of the back wiring and / or wiring protection layer. At this point, the back process is completed. After the back process is completed, the second flip can be performed, the first surface of the substrate is placed horizontally with the first surface facing upward, and the second passivation layer 023b is etched by a dry etching process to expose the partial surface of the electrode structure, and a protection layer 024 is set on the exposed surface.

[0178] 9) Make side traces to connect the electrode structure with the corresponding back traces.

[0179] It should be noted that the above process flow is only a schematic description and does not limit the display panel structure described in the embodiment of the present disclosure.

[0180] In summary, the embodiments of the present disclosure provide a method for preparing a display panel. In the display panel prepared by the method, the side wiring is connected to the first surface wiring through the electrode structure, and also extends to the second surface through the first surface and the side surface in sequence. Wherein, the electrode structure includes at least one layer of conductive patterns stacked in sequence in a direction away from the substrate and at least one passivation layer located on the side of each conductive pattern away from the substrate. Because the first angle between any passivation layer and the bearing surface of the substrate is less than or equal to the second angle between the conductive pattern close to the substrate and the bearing surface of the substrate, it is possible to avoid the problem of the angle being too large due to the influence of the preparation process, thereby causing the film layer to climb and fall off, and ensure a good product yield.

[0181] Fig.17 Schematic diagram of a display device provided by an embodiment of the present disclosure. Fig.17 As shown, the display device includes: a power supply component J1, and a display panel 00 as described in the above embodiment.

[0182] The power supply component J1 is coupled to the display panel 00 and is used to supply power to the display panel 00 .

[0183] Optionally, the display device may be any product or component having a display function, such as a mini LED display device, an OLED display device or a micro LED display device.

[0184] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should be the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs.

[0185] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are merely used to distinguish different components.

[0186] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0187] Words such as “include” or “comprising” and the like mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0188] “Up”, “down”, “left” or “right” etc. are only used to indicate relative position relationship. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0189] "And / or" indicates that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects before and after are in an "or" relationship.

[0190] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel comprises: A substrate having a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area; A first surface wiring located in a display area of ​​the first surface, an electrode structure located in a peripheral area of ​​the first surface, and a side wiring located on at least one side surface of the plurality of side surfaces; One end of the side wiring is electrically connected to the electrode structure, and the other end of the side wiring sequentially passes through the first surface and the at least one side surface and extends to the second surface, and the electrode structure is also electrically connected to the first surface wiring; Furthermore, the electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on a side of each conductive pattern away from the substrate, and a first angle between any one of the at least one passivation layer and the supporting surface of the substrate is less than or equal to a second angle between the conductive pattern of the at least one conductive pattern close to the substrate and the supporting surface of the substrate.

2. The display panel according to claim 1, characterized in that: The first angle is equal to the second angle, and the angle is 0; the electrode structure includes: A first conductive pattern, a first passivation layer, and a second passivation layer sequentially stacked in a direction away from the substrate; a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern; and a protection layer located in the through hole and covering the first conductive pattern.

3. The display panel according to claim 1, characterized in that: The first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; the electrode structure includes: A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate; a through hole penetrating the second passivation layer and exposing the second conductive pattern; a protection layer located in the through hole and covering the second conductive pattern; a transfer hole penetrating the first passivation layer and exposing the first conductive pattern, the second conductive pattern being transferred to the first conductive pattern through the transfer hole, and the transfer hole being away from the at least one side surface relative to the through hole; And, a spacer layer located between the first conductive pattern and the first passivation layer, the orthographic projection of the spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the spacer layer is greater than the thickness of any other film layer in the electrode structure.

4. The display panel according to claim 3, characterized in that: A third angle between the spacer layer and the supporting surface of the substrate is smaller than the second angle, and the first angle is equal to the third angle; Furthermore, the first angles between each passivation layer and the bearing surface of the substrate are equal, and the fourth angle between the second conductive pattern and the bearing surface of the substrate is equal to the first angle.

5. The display panel according to claim 3, characterized in that: The thickness of the spacer layer is greater than 3 microns.

6. The display panel according to claim 3, characterized in that: The material of the spacer layer includes: resin material.

7. The display panel according to claim 3, characterized in that: The electrode structure further comprises: A third passivation layer is located between the first conductive pattern and the spacer layer, and the via hole also penetrates the third passivation layer to expose the first conductive pattern.

8. The display panel according to any one of claims 2 to 7, characterized in that: The first surface routing includes: a first routing layer and a second routing layer stacked in sequence in a direction away from the substrate; Wherein, a first conductive pattern layer included in the electrode structure is located in the same layer as the first wiring layer; Alternatively, the electrode structure includes two layers of conductive patterns, namely, a first conductive pattern and a second conductive pattern stacked sequentially, wherein the first conductive pattern and the first routing layer are located in the same layer, and the second conductive pattern and the second routing layer are located in the same layer.

9. The display panel according to any one of claims 2 to 7, characterized in that: The thickness of the protection layer included in the electrode structure is greater than the thickness of the through hole, and the material of the protection layer includes: metal material.

10. The display panel according to claim 9, characterized in that: The material of the protection layer includes: nickel and / or gold.

11. The display panel according to any one of claims 1 to 7, characterized in that: In the electrode structure, at least one layer of the conductive pattern comprises: a plurality of sub-conductive patterns stacked in sequence in a direction away from the substrate.

12. The display panel according to claim 11, characterized in that: In the electrode structure, at least one layer of the conductive pattern comprises: three layers of sub-conductive patterns stacked in sequence in a direction away from the substrate; Furthermore, the materials of the three-layer sub-conductive pattern include, in sequence: metal molybdenum, metal copper and metal molybdenum; or metal molybdenum-niobium, metal copper and metal molybdenum-niobium.

13. The display panel according to claim 11, characterized in that: The at least one layer of conductive patterns includes: a conductive pattern close to one side of the substrate in the at least one layer of conductive patterns.

14. The display panel according to any one of claims 1 to 7, characterized in that: In the electrode structure, the thickness of at least one passivation layer is greater than 2000 angstroms and less than or equal to 4000 angstroms.

15. The display panel according to claim 14, characterized in that: The at least one passivation layer comprises: a passivation layer on a side of the at least one passivation layer away from the substrate.

16. A method for preparing a display panel, characterized in that: Used for preparing a display panel as claimed in any one of claims 1 to 15; the method comprising: Providing a substrate, wherein the provided substrate has a first surface and a second surface opposite to each other, and a plurality of side surfaces connecting the first surface and the second surface, wherein the first surface includes a display area and a peripheral area surrounding the display area; A first surface wiring is formed in a display area of ​​the first surface, and an electrode structure is formed in a peripheral area of ​​the first surface, wherein the electrode structure is electrically connected to the first surface wiring; Forming a side wiring on at least one side surface among the plurality of side surfaces, one end of the side wiring is electrically connected to the electrode structure, and the other end of the side wiring sequentially passes through the first surface and the at least one side surface and extends to the second surface; Among them, the formed electrode structure includes: a buffer layer located on one side of the substrate and stacked in sequence in a direction away from the substrate, at least one conductive pattern, and at least one passivation layer located on the side of each conductive pattern away from the substrate, and the first angle between any passivation layer in the at least one passivation layer and the supporting surface of the substrate is less than or equal to the second angle between the conductive pattern in the at least one conductive pattern close to the substrate and the supporting surface of the substrate.

17. The method according to claim 16, characterized in that The first angle is equal to the second angle, and the angle is 0; an electrode structure is formed in the peripheral area of ​​the first surface, including: Forming a first conductive pattern, a first passivation layer, and a second passivation layer sequentially stacked in a direction away from the substrate on one side of the substrate; forming a through hole penetrating the first passivation layer and the second passivation layer and exposing the first conductive pattern; And, a protection layer covering the first conductive pattern is formed in the through hole.

18. The method according to claim 16, characterized in that The first angle is smaller than the second angle, and both angles are greater than 0 and less than 90 degrees; an electrode structure is formed in the peripheral area of ​​the first surface, including: A first conductive pattern, a first passivation layer, a second conductive pattern, and a second passivation layer are sequentially stacked in a direction away from the substrate, and an orthographic projection of the first conductive pattern on the substrate is located within an orthographic projection of the second conductive pattern on the substrate; forming a through hole penetrating the second passivation layer and exposing the second conductive pattern; forming a protection layer covering the second conductive pattern in the through hole; forming a via hole penetrating the first passivation layer and exposing the first conductive pattern, wherein the via hole is formed away from the at least one side surface relative to the through hole; Connecting the second conductive pattern to the first conductive pattern through the connecting hole; A spacer layer is formed between the first conductive pattern and the first passivation layer, and the orthographic projection of the formed spacer layer on the substrate is located within the orthographic projection of the first passivation layer on the substrate, and covers the side surface of the first conductive pattern in contact with the buffer layer and the top surface away from the buffer layer, and the thickness of the formed spacer layer is greater than the thickness of any other film layer in the electrode structure.

19. A display device, characterized in that: The display device comprises: a power supply component, and a display panel according to any one of claims 1 to 15; Wherein, the power supply component is coupled to the display panel and is used to supply power to the display panel.

Images