Channel decoding method, confidence information transmission circuit and reconfigurable chip architecture

Abstract

The invention provides a channel decoding method, a confidence information transmission circuit and a reconfigurable chip architecture, and relates to the field of wireless communication, and the method comprises the steps: determining an aggregation level according to computing power information and / or information amount related to a to-be-decoded bit sequence under the condition that the to-be-decoded bit sequence is received; the aggregation level is used for indicating the number of nodes of synchronous iteration; therefore, the speed of synchronous transmission of the confidence information is flexibly adjusted; according to the aggregation level, iteratively calculating confidence information alternately transmitted between each check node and each variable node; and decoding the bit sequence to be decoded according to the confidence information of each variable node to obtain target information. Therefore, the confidence information which needs to be transmitted is determined by performing synchronous calculation on the confidence information received by the plurality of nodes, so that on one hand, the calculation process is simplified, the decoding reconstruction speed is improved, and on the other hand, the decoding performance is improved.

Description

Technical Field

[0001] The present application relates to the field of wireless communication technology, and in particular to a channel decoding method, a trust information transmission circuit and a reconfigurable chip architecture. Background Art

[0002] In the existing channel decoding schemes, the transmission of confidence information mainly relies on the sum-product algorithm, the minimum sum algorithm, the normalized minimum sum algorithm, the minimum sum algorithm with offset, etc. However, the use of the above algorithms to transmit confidence information has the problems of cumbersome calculation process during decoding and poor decoding performance. Summary of the invention

[0003] The embodiments of the present application provide a channel decoding method, a trust information transmission circuit and a reconfigurable chip architecture, which solve the problems of cumbersome calculation process and poor decoding performance of the current decoding method.

[0004] In a first aspect, to achieve the above-mentioned object, an embodiment of the present application provides a channel decoding method, including:

[0005] When receiving a bit sequence to be decoded, determining an aggregation level according to computing power information and / or an amount of information related to the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration;

[0006] Iteratively calculating the confidence information alternately transmitted between each check node and each variable node according to the aggregation level;

[0007] The to-be-decoded bit sequence is decoded according to the confidence information of each of the variable nodes to obtain target information.

[0008] Optionally, according to the aggregation level, iteratively calculating the confidence information alternately transmitted between each check node and each variable node includes:

[0009] When calculating the confidence information transmitted from the first node to the second node, determining, according to the check matrix, a plurality of third nodes that transmit the confidence information to the second node, wherein the first node and the second node are of different types, and the first node and the third nodes are of the same type;

[0010] According to the aggregation level, the confidence information received by the plurality of third nodes and the confidence information received by the first node are synchronously iterated to obtain the confidence information transmitted by the first node to the second node.

[0011] Optionally, according to the aggregation level, synchronously iterating the confidence information received by the plurality of third nodes and the confidence information received by the first node to obtain the confidence information transmitted by the first node to the second node includes:

[0012] Generate an iterative operation sequence according to the confidence information received by the plurality of third nodes and the confidence information received by the first node, wherein the confidence information received by the first node is the last information of the iterative operation sequence;

[0013] According to the aggregation level, synchronous iterative operation is performed on the information in the iterative operation sequence to obtain confidence information transmitted by the first node to the second node.

[0014] Optionally, generating an iterative operation sequence according to the confidence information received by the plurality of third information and the confidence information received by the first node includes:

[0015] When the number of the plurality of third nodes is an integer multiple of the difference between the aggregation level and 1, sorting the confidence information received by the third nodes and the confidence information received by the first node to obtain the iterative operation sequence;

[0016] When the number of the plurality of third nodes is not an integer multiple of the difference between the aggregation level and 1, preset confidence information is constructed, and the confidence information received by the plurality of third nodes, the preset confidence information and the confidence information received by the first node are sorted to obtain an iterative operation sequence; wherein the preset confidence information is located after the confidence information received by the plurality of third nodes.

[0017] Optionally, performing synchronous iterative operation on the information in the iterative operation sequence according to the aggregation level to obtain the confidence information transmitted by the first node to the second node includes:

[0018] The i-th confidence information in the iterative operation sequence is operated in sequence with the N-1 confidence information before the i-th confidence information to obtain a first operation result, and the i-th confidence information is updated to the first operation result; wherein, i=k*(N-1)+1, k is a positive integer, and N is the aggregation level.

[0019] Optionally, operating the i-th confidence information in the iterative operation sequence with N-1 confidence information before the i-th confidence information comprises:

[0020] Based on the Jacobi function, construct an operational relational expression for N pieces of confidence information for operation;

[0021] The Taylor series is used to perform linear fitting on the operational relationship.

[0022] Optionally, performing linear fitting on the operational relational expression using Taylor series includes:

[0023] Sorting the N pieces of confidence information to obtain a first value region that meets a preset convergence condition;

[0024] Selecting an expansion point for fitting in the first value range;

[0025] The operation relation is linearly fitted by performing Taylor series expansion at the expansion point.

[0026] In a second aspect, in order to achieve the above-mentioned object, an embodiment of the present application provides a confidence information transmission circuit, which is applicable to the confidence information calculation process in the channel decoding method as described in the first aspect, including:

[0027] An information calculator, used for calculating the received N pieces of confidence information;

[0028] a first selector, connected to the information calculator, for performing segmented selection on the calculation result of the information calculator;

[0029] A post-calculator, connected to the first selector, is used to operate on multiple results obtained by segmented selection, and calculate the operation results with the Nth confidence information to update the Nth confidence information.

[0030] Optionally, the post-calculator comprises:

[0031] A processor, connected to the first selector, and configured to respectively calculate the results of the selection of each segment;

[0032] A first adder is connected to the processor and is used to accumulate each operation result output by the processor and the Nth confidence information.

[0033] Optionally, the processor includes:

[0034] A positive detector, connected to the first selector, for performing a positive operation on the results of each segment selection respectively;

[0035] A memory, used for storing a parameter lookup table;

[0036] a multiplier connected to the positive detector and configured to perform a multiplication operation on an output result of the positive detector and a first parameter found in the parameter lookup table;

[0037] The second adder is connected to the multiplier and is used to perform an addition operation on an output result of the multiplier and a second parameter found in the parameter lookup table.

[0038] Optionally, the confidence information transmission circuit further includes:

[0039] A second selector is connected to the first adder, and is used for inputting the Nth confidence information into the second adder.

[0040] In a third aspect, in order to achieve the above-mentioned object, an embodiment of the present application provides a reconfigurable chip architecture, applicable to the channel decoding method as described in the first aspect, including:

[0041] A control unit, configured to determine an aggregation level according to computing power information and / or an amount of information related to the bit sequence to be decoded when receiving the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration;

[0042] A decoding intermediate variable unit, used for iteratively calculating the confidence information alternately transmitted between each check node and each variable node according to the aggregation level;

[0043] The node updating unit is used to decode the to-be-decoded bit sequence according to the confidence information of each of the variable nodes to obtain target information.

[0044] Optionally, the decoding intermediate variable unit includes:

[0045] The decoding intermediate variable unit includes an aggregation unit and a sliding control unit that cooperate with each other;

[0046] The aggregation level unit is used to control the number of units that transmit the confidence information at a time according to the aggregation level, and to perform confidence information calculation according to the number of units that transmit the confidence information at a time;

[0047] The sliding control unit is used to set the calculation unit that needs to be skipped according to the information sent by the aggregation level unit.

[0048] Optionally, the node updating unit includes:

[0049] A check node updating unit, used to update the check node according to the confidence information output by the decoding intermediate variable unit;

[0050] The variable node updating unit is used to update the variable nodes according to the confidence information output by the decoding intermediate variable unit, and decode the to-be-decoded bit sequence according to the confidence information of each of the variable nodes to obtain target information.

[0051] Optionally, the reconfigurable chip architecture further includes:

[0052] A memory is connected to the control unit, the decoding intermediate variable unit and the node updating unit respectively, and is used to store the log-likelihood ratio of the to-be-decoded bit sequence, the target information and the check matrix.

[0053] The beneficial effects of the above technical solution of the present application are as follows:

[0054] The channel decoding method of the embodiment of the present application, first, when receiving the bit sequence to be decoded, determines the aggregation level according to the computing power information and / or the amount of information related to the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration; in this way, the speed of synchronous transmission of the confidence information is flexibly adjusted based on the amount of calculation; secondly, according to the aggregation level, iteratively calculates the confidence information alternately transmitted between each check node and each variable node; in this way, the calculation process of the confidence information is simplified, and the decoding reconstruction speed can be improved, and finally, the bit sequence to be decoded is decoded according to the confidence information of each variable node to obtain the target information. In this way, the confidence information received by all nodes is used to determine the confidence information transmitted between the variable node and the check node, thereby improving the decoding performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 Tanner graph for LDPC decoding;

[0056] Figure 2 A schematic diagram of a flow chart of a channel decoding method according to an embodiment of the present application;

[0057] Figure 3 A schematic diagram of a trust information transmission circuit according to an embodiment of the present application;

[0058] Figure 4 A schematic diagram of a reconfigurable chip architecture according to an embodiment of the present application. DETAILED DESCRIPTION

[0059] In order to make the technical problems, technical solutions and advantages to be solved by the present application clearer, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0060] It should be understood that the references to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present application. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0061] In the various embodiments of the present application, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0062] Additionally, the terms "system" and "network" are often used interchangeably herein.

[0063] In the embodiments provided in the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and / or other information.

[0064] Before describing the embodiments of the present application, the relevant technical points are first described:

[0065] 1. Low Density Parity Check Codes (LDPC)

[0066] One of the most notable features of the check matrix of LDPC codes is that the check matrix of LDPC codes is very sparse. The proportion of non-zero elements in the check matrix of LDPC codes decreases as the code length increases, and it has a typical sparse characteristic. Theoretical analysis can prove that the sparse characteristic of the check matrix is ​​one of the important reasons for the excellent performance of LDPC codes, which allows decoding to be carried out effectively when the code length is long.

[0067] 2. LDPC code decoding algorithm

[0068] The decoding algorithms of LDPC codes can be divided into hard decision decoding algorithms and soft decision decoding algorithms. The former is the bit flipping (BF) decoding algorithm, which has low complexity and is easy to implement in hardware, but has poor decoding performance and is only applicable to communication systems with excellent channel quality; the latter refers to the belief propagation (BP) decoding algorithm based on a posteriori probability calculation, which has performance close to the maximum likelihood decoding algorithm and is widely used. The iterative decoding algorithm of LDPC codes is relatively simple to implement, and its complexity is linear with the code length, which is conducive to hardware implementation.

[0069] 2.1 Hard Decision Decoding Algorithm

[0070] Assume that the signal transmission information sequence is X = {x0, x1, ..., x n-1}, the received information sequence after passing through the channel is Y = {y0,y1,...,y n-1}. The decoding process is as follows:

[0071] (1) First, determine the channel transmission message and obtain the bit sequence;

[0072] (2) Substitute the result of step (1) into the verification equation for calculation. If the verification equation holds, stop the iteration and the decoding is successful. Otherwise, find the variable node with the largest number of invalid values ​​and flip all its bits uniformly.

[0073] (3) If the verification equation in step (2) does not hold, substitute the flipped judgment result into the verification equation again, calculate its verification result, and repeat step (2) until all verification equations hold or the maximum number of iterations is reached.

[0074] The problem with this algorithm is that after a certain iteration, if there are multiple nodes with the largest number of invalid nodes, they will flip at the same time, resulting in a high error rate. At present, some studies have proposed some improvements to the BF algorithm, such as adding certain weights to variable nodes, but the performance is average. Therefore, this algorithm is only suitable for situations with good channel conditions such as optical fiber communication.

[0075] 2.2 Soft Decision Decoding Algorithm

[0076] The soft decision decoding algorithm of LDPC code is a research hotspot in communication system. The decoding of LDPC code is an iterative algorithm based on probability message passing (MP), and its implementation in logarithmic domain is usually called Sum Product Algorithm (SPA).

[0077] Here, the mean is 0 and the variance is σ 2 The additive white Gaussian noise channel (AWGN) is analyzed by taking the case of BPSK modulation as an example. The dimension of the check matrix H is M×N. Assume that the signal transmission information sequence is X={x0,x1,...,x n-1}, the received information sequence after passing through the channel is Y = {y0,y1,...,y n-1}, l max is the maximum number of iterations. Figure 1 In the example, v is a variable node and c is a check node. The related concepts are defined as follows:

[0078] M(j) represents the set of check nodes linked to variable node j;

[0079] N(i) represents the set of variable nodes linked to check node i;

[0080] N(i)\j means N(i) after removing element j;

[0081] M(j)\i means M(j) after removing element i;

[0082] It is a modulo 2 and operation;

[0083] Channel initial reception information represents the probability that the transmission variable xj takes the value a∈{1,-1};

[0084] Check Node c i To variable node v j The verification information sent is used Indicates that the variable node v j To the check node c i The variable information transmitted is used express.

[0085] 2.2.1、The steps of LDPC code soft decision decoding are as follows:

[0086] (1) Initialization: l = 0, initialize the information of each LDPC code check node and variable node, and initialize the receiving value of the channel

[0087] (2) Iterative message update and delivery:

[0088] Step 1 (check node update): For check node c i Connected variable node v j , j∈N(i), send verification information one by one Variable node v j To receive information and the initial value of the channel Based on the correction

[0089] Step 2 (variable node update): For variable node v j Each check node c connected i , i∈M(j), transmit variable information one by one Check Node c i To receive information Based on the correction

[0090] (3) Judgment and decoding attempt:

[0091] Each variable node v j Receiving information and the initial value received by the channel Calculated based on And for the variable node v j Make a decision and get the decoding result. Order decision codeword otherwise The resulting decision codeword is x = [x1, x2, ..., x N ], if the decoding check formula is satisfied, the iterative decoding stops, the decoding is successful, and x is output as the decoding result, otherwise it returns to step (2) to continue execution. max , terminate the decoding operation.

[0092] In the above steps, during the first iteration, check node c i For other variable nodes v j of The message is unknown, and the variable message value it transmits is calculated with equal probability, that is, Initialized to 0.

[0093] For the LDPC decoding algorithm, the update calculation operation of the above iterative decoding varies with the different metrics of message transmission. In general, the common sum-product decoding algorithm metrics are divided into two types: probability-based and log-likelihood ratio-based. The sum-product decoding algorithm based on probability measurement requires multipliers for information transmission between nodes, which is not easy to implement in hardware. Therefore, the embodiment of this application focuses on introducing and using the sum-product decoding algorithm based on log-likelihood ratio measurement.

[0094] Under the sum-product decoding algorithm of log-likelihood ratio measure, Initialized to 0. The initial probability of the prior information of xj = a is In the decoding iteration process, information is transmitted in the form of log likelihood ratio (LLR). When updating the calculation, addition operation is used instead of multiplication operation of probability measure, and normalization is not required. The common information update formula is as follows:

[0095] f j =L(x j |y j )=log(P(x j =0|y j ) / P(x j =1|y j ))=2y j / σ 2

[0096]

[0097] The value of the log-likelihood ratio measure of the decoded symbol received information is:

[0098]

[0099] When making a decoding decision, if Q j If ≥0, the received signal judgment is 1, otherwise it is 0.

[0100] 2.2.2 Common LLR-SPA Algorithms

[0101] (1) Sum-product algorithm based on Tanh rule

[0102]

[0103] (2) Sum-product algorithm based on Gallager function

[0104]

[0105] (3) Sum-product algorithm based on Jacobian function

[0106] The aforementioned Tanh rule can also be expressed as follows:

[0107]

[0108] The above transformation is called Jacobian transformation. i , there is c variable node v j Connected to it, the input variable information is Two auxiliary set definitions are proposed: and

[0109] Variable information that can be entered using auxiliary sets Get output information and We can get:

[0110]

[0111] The update formula of the check node is transformed into:

[0112]

[0113] Simply put, this algorithm is essentially a forward-backward recursive decoding algorithm for a single parity-check code.

[0114] In general, the sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, which makes it difficult to implement in hardware.

[0115] 2.2.3 Minimum Sum Algorithm

[0116] In order to reduce the complexity of LDPC decoding implementation, relevant researchers simplified the complex check node processing flow in the sum-product algorithm, eliminated this type of nonlinear function, and obtained the classic minimum sum (MS) algorithm, which only performs addition and comparison operations when calculating the check node information update, which is conducive to hardware implementation. The understanding of these simplified algorithms can be inspired by the analysis of the Jacobian algorithm.

[0117] The MS algorithm simplifies the information processing of the check nodes in the sum-product decoding algorithm as follows:

[0118]

[0119] Applying this approximation to the iterative decoding process of LDPC, the check node update information calculation formula is transformed into

[0120]

[0121] According to the above formula, the MS algorithm can perform decoding operations with only the minimum sign and amplitude of the information transmitted by the node. The method for finding the minimum value can generally use the binary tree method. The MS algorithm verifies that the node information update is only based on the sign of the transmitted information and the minimum modulus value, which greatly simplifies the complexity of hardware implementation. However, the amplitude of many variable information transmissions is ignored during the decoding process, resulting in performance loss. In order to compensate for the performance loss, scholars have proposed corresponding offset measures, namely the Normalized Min Sum (NMS) decoding algorithm and the Offset Min Sum (OMS) algorithm as improvements.

[0122] 2.2.4 Normalized Minimum Sum Algorithm

[0123] The Normalized Min Sum (NMS) decoding algorithm is an improved decoding algorithm based on the MS algorithm. The minimum value of the transmitted information in the check node information update can be multiplied by a value α less than 1. At this time, the formula for updating the check node information is:

[0124]

[0125] From the perspective of optimization, α should change with different decoding environments and iteration times to obtain the optimal decoding result. However, for the convenience of implementation, common NMS algorithms usually use α as a constant, and its value can be estimated using the density evolution (DE) method.

[0126] 2.2.5 Minimum Sum Algorithm with Offset

[0127] The Offset Min Sum (OMS) algorithm is an improved decoding algorithm based on the MS algorithm. The minimum value obtained by transferring information in the check node information update can be subtracted by a value β. At this time, the formula for updating the check node information is:

[0128]

[0129] From the perspective of optimization, β should change with different decoding environments and iteration times to obtain the best decoding result. However, for the convenience of implementation, the common OMS algorithm usually takes β as a constant. The improvement of this method over the NMS algorithm is that information with an amplitude less than β will be set to zero, and the impact on the update of the variable node in the next iteration will be ignored.

[0130] It can be seen that the MS algorithm, OMS algorithm and NMS algorithm only need the channel reception value as input, and do not require channel-related information.

[0131] 2.3. From the above content, we can know that:

[0132] The sum-product decoding algorithm contains nonlinear functions such as hyperbolic functions, which makes it difficult to implement in hardware.

[0133] The minimum sum algorithm verifies that node information is updated only by the sign of the transmitted information and the minimum modulus value, which greatly simplifies the complexity of hardware implementation. However, the amplitude of many variable information transmissions is ignored during the decoding process, resulting in performance loss.

[0134] The normalized minimum sum decoding algorithm is based on the minimum sum algorithm to obtain the minimum value of the transmitted information in the check node information update multiplied by a value less than 1, but since more channel information is omitted, there is still room for improvement in performance.

[0135] The minimum sum decoding algorithm with offset is based on the minimum sum algorithm to obtain the minimum value of the transmitted information in the check node information update minus an offset value, but since more channel information is omitted, there is still room for improvement in performance.

[0136] Based on the above situation, if Figure 2 As shown, an embodiment of the present application provides a channel decoding method, including:

[0137] Step 201, when receiving a bit sequence to be decoded, determining an aggregation level according to computing power information and / or information amount related to the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration;

[0138] In this step, firstly, the bit sequence to be decoded is a sequence transmitted through a channel after the transmitting device encodes the information to be transmitted, for example, the bit sequence to be decoded is an LDPC code, a fountain code, a polarization (POLAR) code, etc.; secondly, the computing power information is the current computing power of the chip (decoder), for example, the computing power information includes computing power overhead, that is, power consumption; thirdly, the amount of information related to the bit sequence to be decoded is related to the confidence value of the decoded data.

[0139] Here, it should be noted that, on the one hand, the computing power information is positively correlated with the aggregation level, that is, the greater the computing power overhead, the greater the aggregation level; specifically, when the current computing power overhead of the decoding chip is large, that is, the power consumption is high, in order to reduce the chip power consumption overhead, a large-span aggregation level is adopted, that is, more computing units are skipped to achieve more confidence information transmission; conversely, when the current computing power overhead of the chip is small and the power consumption is low, a small-span aggregation level can be adopted to improve the decoding accuracy; on the other hand, the amount of information related to the bit sequence to be decoded is negatively correlated with the aggregation level, that is, the greater the amount of information, the smaller the aggregation level; specifically, the decoder analyzes the decoding confidence information, and for the case where the confidence information is distributed relatively evenly, that is, the overall value fluctuation or the variance and standard deviation are lower than a certain threshold, it means that the current amount of information is small and the values ​​of each information value are similar. At this time, a large-span aggregation level is adopted, that is, more computing units are skipped to achieve more confidence information transmission. Conversely, when the confidence information distribution is relatively dispersed, it means that the current confidence information contains a large amount of information. At this time, a small-span aggregation level is adopted to achieve more accurate decoding operations.

[0140] In this step, the aggregation level is determined based on the computing power information and / or the amount of information related to the bit sequence to be decoded, so that the number of nodes for synchronous iteration is flexibly adjusted based on the power consumption of the decoding chip and / or the amount of information based on the confidence information, thereby reducing the complexity of the calculation while ensuring the decoding performance.

[0141] Step 202, iteratively calculating the confidence information alternately transmitted between each check node and each variable node according to the aggregation level;

[0142] In this step, the confidence information alternately transmitted between the check node and the variable node is the check node update information and the variable node update information. For example, in this step, the confidence information of multiple check nodes can be synchronously iterated based on the aggregation level to reduce the number of iterations.

[0143] Here, it should be noted that before iteratively calculating the confidence information alternately transmitted between each check node and each variable node, the confidence information of each check node and each variable node is first initialized. Specifically, the initialized confidence information of each variable node is the LLR of each bit of the bit sequence to be decoded, and the initialized confidence information of each check node is 0; then, each variable node sends its initialized confidence information to the connected check node; each check node updates the received confidence information through the synchronous iteration method in this step.

[0144] This step calculates the confidence information based on the aggregation level, and realizes the calculation of the confidence information of multiple nodes at the same time, and then iterates with other nodes until the confidence information of all relevant nodes (nodes connected to the same node) are involved in the calculation; in this way, on the one hand, the accuracy of the calculated confidence information can be ensured; on the other hand, the complexity of the calculation is simplified.

[0145] Step 203: Decode the to-be-decoded bit sequence according to the confidence information of each variable node to obtain target information.

[0146] In this step, the target information is the decoding result of the to-be-decoded bit sequence.

[0147] Here, it should be noted that when calculating the confidence information, the confidence information of all nodes is comprehensively considered, rather than just transmitting the confidence information symbol and the minimum modulus value as in the minimum sum algorithm, so that the decoding performance can be improved.

[0148] The channel decoding method of the embodiment of the present application, first, when receiving the bit sequence to be decoded, according to the computing power information and / or the amount of information related to the bit sequence to be decoded, determines the aggregation level for indicating the number of nodes for synchronous iteration; thus, the speed of synchronous transmission of the confidence information is flexibly adjusted based on the amount of calculation; secondly, according to the aggregation level, iteratively calculates the confidence information alternately transmitted between each check node and each variable node; thus, the calculation process of the confidence information is simplified, and finally, the bit sequence to be decoded is decoded according to the confidence information of each variable node to obtain the target information. Thus, the confidence information received by all nodes is used to determine the confidence information transmitted between the variable node and the check node, thereby improving the decoding performance.

[0149] As an optional implementation, step 202, iteratively calculating the confidence information alternately transmitted between each check node and each variable node according to the aggregation level, includes:

[0150] When calculating the confidence information transmitted from the first node to the second node, multiple third nodes that transmit the confidence information to the second node are determined according to the check matrix, wherein the first node and the second node are of different types, and the first node and the third node are of the same type; for example, the first node and the third node are both check nodes, and the second node is a variable node.

[0151] Here, it should be noted that in the check node, each row corresponds to a check equation (also called a check node), each column corresponds to a bit of the codeword (also called a variable node), and in the check matrix, an element is 1, indicating that the check node corresponding to the row where the element is located is connected to the variable node corresponding to the column where the element is located; therefore, when the second node is a variable node, the first node and the plurality of third nodes are nodes corresponding to the row where the "1" element is located in the column corresponding to the second node. Therefore, in this step, a plurality of third nodes connected to the second node are selected based on the check matrix.

[0152] According to the aggregation level, the confidence information received by the plurality of third nodes is synchronously iterated with the confidence information received by the first node to obtain the confidence information transmitted by the first node to the second node.

[0153] In this step, synchronous iteration means that when the first node is updated, the first node is updated based on the iterative calculation of the third node. Specifically, during the iterative calculation process, three or more nodes may be calculated each time.

[0154] Simply put, this step is to update the first node based on the confidence information received by multiple third nodes. In this way, the node is updated based on multiple variable information to avoid the loss of decoding performance. In addition, the node is updated in a synchronous iterative manner, which reduces the number of iterations and reduces the complexity of hardware implementation.

[0155] As a specific implementation, according to the aggregation level, the confidence information received by the plurality of third nodes is synchronously iterated with the confidence information received by the first node to obtain the confidence information transmitted by the first node to the second node, including:

[0156] Generate an iterative operation sequence according to the confidence information received by the plurality of third information and the confidence information received by the first node, wherein the confidence information received by the first node is the last information of the iterative operation sequence;

[0157] Here, the second node is taken as a variable node, and the first node and the third node are check nodes. Assume that the first node is C1, and the third nodes are C2, C3, C4, C6, C7, C8, C9, C 12 , the second node is V1, then, in this step, the multiple third nodes can be sorted first, for example, in ascending order of subscripts, then the iterative operation sequence is: {C2, C3, C4, C6, C7, C8, C9, C 12 , V1}. Here, each symbol in the iterative operation sequence represents the confidence information received by the corresponding node.

[0158] According to the aggregation level, synchronous iterative operation is performed on the information in the iterative operation sequence to obtain the confidence information transmitted by the first node to the second node.

[0159] For example, if the aggregation level is 3, the synchronous iterative operation of this step is to first operate on C2, C3, and C4 to update C4, then operate on the updated C4, C6, and C7 to update C7, then operate on the updated C7, C8, and C9 to update C9, and finally, operate on the updated C9, C8, and C9. 12 , V1 is operated to update V1, wherein the updated V1 is the confidence information that the first node needs to transmit to the second node.

[0160] As a more specific implementation, generating an iterative operation sequence according to the confidence information received by the plurality of third nodes and the confidence information received by the first node includes:

[0161] When the number of the plurality of third nodes is an integer multiple of the difference between the aggregation level and 1, sorting the confidence information received by the third nodes and the confidence information received by the first node to obtain an iterative operation sequence;

[0162] When the number of the plurality of third nodes is not an integer multiple of the difference between the aggregation level and 1, a plurality of preset confidence information is constructed, and the confidence information received by the plurality of third nodes, the preset confidence information, and the confidence information received by the first node are sorted to obtain an iterative operation sequence; wherein the preset confidence information is located after the confidence information received by the plurality of the third nodes, that is, the elements in the iterative operation sequence are, in sequence, the confidence information of the third nodes, the preset confidence information, and the confidence information of the first node.

[0163] It should be noted here that in this more specific implementation method, by judging the relationship between the third node and the aggregation level and determining whether it is necessary to fictitiously preset the confidence information based on the relationship between the two, the number of elements in the final iterative operation sequence can meet the requirements of the aggregation level in each operation, thereby being able to reuse the iterative calculation unit and reduce resource overhead. At the same time, the confidence information of all third nodes can participate in the operation to ensure better decoding performance. In addition, the preset confidence information is fictitious node information with a value of -99.

[0164] As a specific implementation, according to the aggregation level, synchronously iteratively operating the information in the iterative operation sequence to obtain the confidence information transmitted by the first node to the second node includes:

[0165] The i-th confidence information in the iterative operation sequence is operated in sequence with the N-1 confidence information before the i-th confidence information to obtain a first operation result, and the i-th confidence information is updated to the first operation result; wherein, i=k*(N-1)+1, k is a positive integer, and N is the aggregation level.

[0166] In this specific implementation, the ith confidence information is updated by using the calculation of the N-1 confidence information before the ith confidence information, and the updated ith confidence information is used for iterative calculation, and finally the last confidence information in the iterative calculation sequence (confidence information of the first node) is updated. Thus, compared with the one-by-one iteration method, this specific implementation method reduces the number of iterations, simplifies the complexity of hardware implementation, and improves the decoding speed; in addition, it ensures that all third nodes participate in the calculation of confidence information to ensure decoding performance.

[0167] As a more specific implementation, the i-th confidence information in the iterative operation sequence is operated with the N-1 confidence information before the i-th confidence information, including:

[0168] Based on the Jacobi function, construct an operational relational expression for N pieces of confidence information for operation;

[0169] Here, taking the aggregation level 3 as an example, assuming that the three nodes where the operation occurs are U, V, and W respectively; then the operation relation of this step can be expressed as:

[0170]

[0171] The Taylor series is used to perform linear fitting on the operational relationship. In this step, by performing linear fitting on the above operational relationship, the complexity of module calculation can be increased only slightly, so as to obtain a shorter iteration time and thus improve the decoding speed.

[0172] Specifically, the Taylor series is used to perform linear fitting on the operational relationship, including:

[0173] Sorting the N pieces of confidence information to obtain a first value region that meets a preset convergence condition;

[0174] Here, it should be noted that, taking the above three nodes U, V, and W for example, before sorting, the first term in the above formula can be converted into a univariate correction term function, which can be calculated using the existing linear approximation method. The second term is the amount of information itself, and the third term can be used to extract and construct a binary correction function f c (x,y)=log(1+e x +e y ), and perform a linear approximation on it.

[0175] After transforming the above formula, we can sort L(U), L(V) and L(W) to ensure that f c (x,y) takes values ​​in the region of y≤x≤0 with good convergence. At the same time, f c (-5,-5)=0.0134 is close to 0. For the convenience of calculation, the value of the area x<-5 and y<-5 is set to zero.

[0176] Selecting an expansion point for fitting in the first value region;

[0177] Here, f c (x, y) uses a two-variable Taylor series expansion, which can be intuitively understood as using one or more planes at the tangent points to approximate the surface. Ignoring the high-order terms in the expansion, f c (x,y) can be expressed as a linear approximation near the expansion point (x0,y0)

[0178] f c (x,y)=log(1+e x +e y )

[0179] ≈f c (x0,y0)+f x ′(x0,y0)*(x-x0)+f y ′(x0,y0)*(y-y0)

[0180] Among them, the binary correction function f c The first-order partial derivative of (x,y) with respect to the variable x at the point (x0,y0) is The first-order partial derivative of the variable y at the point (x0, y0) is Since we sort L(U), L(V), and L(W), we can approximate f c When (x, y) is used, we only need to consider the range of -5≤y≤x≤0. For hardware implementation and performance improvement, we consider single and multiple expansion point linear approximation.

[0181] When several expansion points are selected for linear approximation, the binary correction function f c (x, y) has the following linear approximation relationship:

[0182] f c (x,y)≈max(0,k1*x+l1*y+C1,...,k i *x+l i *y+C i )

[0183] where k i , l i , m iand C i All are real parameters.

[0184] When selecting an expansion point, we choose (0, 0) as the expansion point. When selecting multiple expansion points, the expansion and approximate calculation of multivariate functions are more complex. For the convenience of calculation, we expand the point selection scheme, perform iterative operations in the two directions of x=0 and y=x with a step size of 1, and take the error deviation value δ as 0.5. Three expansion points are calculated, namely (0, 0), (0, -2), and (-2, -2). The expansion point list shown in Table 1 is obtained.

[0185] Table 1 Relationship between expansion points and corresponding approximate terms

[0186]

[0187]

[0188] The Taylor series expansion is performed at the expansion point to linearly fit the operational relationship.

[0189] In the above embodiment, the number of iterations of the Jacobi algorithm can be reduced by synchronous iterative operations, and the decoding speed is improved. At the same time, due to the introduction of Taylor series linear approximation, the module calculation complexity increases slightly, and the decoding accuracy is improved. It is worth mentioning that the binary correction term function used in this algorithm can be further expanded to a multivariate correction term function, and then linear approximation or other approximations are performed on the whole to obtain a shorter iteration time. At the same time, this type of algorithm is theoretically superior to MS, NMS, OMS and other algorithms because it fully utilizes the information of all nodes.

[0190] like Figure 3 As shown, the embodiment of the present application further provides a confidence information transmission circuit, which is applicable to the confidence information calculation process in the channel decoding method as described above, and the circuit includes:

[0191] An information calculator, used for calculating the received N pieces of confidence information; Figure 3 In the example of synchronously calculating the confidence information of the three nodes U, V, and W, the information calculator is specifically used to accumulate the confidence information of the three nodes U, V, and W; subtract the confidence information of the two nodes V and W from the confidence information of the U node respectively;

[0192] The first selector is connected to the information calculator and is used to select the calculation results of the information calculator in segments; the information calculator will transmit the three results of the above calculations to the first selector at one time, and the first selector will segment the received results, that is, segment the received results to obtain the results of each calculation.

[0193] The post-calculator is connected to the first selector and is used to calculate the multiple results obtained by the segmented selection, and calculate the calculation results with the Nth confidence information to update the Nth confidence information.

[0194] In the confidence information transmission circuit of the embodiment of the present application, first, the information calculator calculates the N received confidence information; then, the first selector selects the calculation results of the information calculator in segments; finally, the post-calculator calculates the multiple results obtained by the segment selection, and calculates the calculation results with the Nth confidence information to update the Nth confidence information. In this way, the confidence information of multiple nodes before the Nth node is calculated at the same time to update the confidence information of the Nth node. Compared with the one-by-one iteration method, the calculation process of the confidence information of this circuit can reduce the number of iterations and improve the calculation speed.

[0195] As a specific implementation, the post-calculator includes:

[0196] A processor, connected to the first selector, for respectively operating on the results of the selection of each segment; that is, the processor is used to process again the results of the addition and subtraction of the calculations of the multiple nodes;

[0197] The first adder is connected to the processor and is used to accumulate various operation results output by the processor and the Nth confidence information. That is, the first adder is used to process the operation results of the Nth node and other N-1 nodes to update the Nth node.

[0198] As a more specific implementation, the processor includes:

[0199] A positive selector, connected to the first selector, for performing a positive operation on the results of each segment selection;

[0200] A memory, used for storing a parameter lookup table;

[0201] a multiplier connected to the positive detector and used for performing a multiplication operation on an output result of the positive detector and a first parameter k found in the parameter lookup table;

[0202] The second adder is connected to the multiplier and is used to perform an addition operation on the output result of the multiplier and the second parameter c found in the parameter lookup table.

[0203] Furthermore, as an optional implementation, the confidence information transmission circuit further includes:

[0204] The second selector is connected to the first adder, and is used for inputting the Nth confidence information into the second adder.

[0205] That is to say, the working process of the confidence information transmission circuit of the embodiment of the present application is as follows (taking the confidence information of the three nodes U, V, and W for calculation as an example):

[0206] First, add L(U), L(V) and L(W), and simultaneously subtract L(U) from L(V) and L(W). The calculated value will be used to read the corresponding parameters in the LUT and perform segment selection, multiplication and addition operations. Among them, the first selector will control |L(U)+L(V)+L(W)|, |L(V)-L(U)| and |L(W)-L(U)| to enter the post-calculation unit (composed of a memory, a multiplier and a second adder) independently. Specifically, in the post-calculation unit, its core operation is to complete the piecewise linear multiplication and addition operation of the input data according to the input variable x. After the calculation is completed, the calculation results of the three segments are added to complete the calculation of the update information of a single node.

[0207] Here, it should be noted that in the entire process of updating node information, such calculation operations need to be repeated and iterated, and finally all node transmission information is fed back to a specific node to complete all information aggregation work. Among them, the use of this trust information transmission circuit for trust information transmission is that as the number of expanded nodes increases, the complexity of the calculation unit will not change. The only difference is the parameters stored in the LUT. In this way, the complexity of the hardware is simplified.

[0208] like Figure 4 As shown, the embodiment of the present application also provides a reconfigurable chip architecture, which is applicable to the channel decoding method as described above, including:

[0209] A control unit, configured to determine an aggregation level according to computing power information and / or an amount of information related to the bit sequence to be decoded when receiving the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration;

[0210] Specifically, one situation is: when the current computing power overhead of the decoding chip is large, that is, the power consumption is high, in order to reduce the chip power consumption overhead, a large-span aggregation level is used, that is, more computing units are skipped to achieve more confidence information transmission. On the contrary, when the current computing power overhead of the chip is small and the power consumption is low, a small-span aggregation level can be used to improve the decoding accuracy; another situation is: the decoding confidence information is analyzed, and for the case where the confidence information is distributed relatively evenly, that is, the overall value fluctuation or the variance and standard deviation are lower than a certain threshold, it means that the current amount of information is small and the values ​​of each information are similar. At this time, a large-span aggregation level is used, that is, more computing units are skipped to achieve more confidence information transmission. On the contrary, when the confidence information distribution is relatively dispersed, it means that the current confidence information contains a large amount of information. At this time, a small-span aggregation level is used to achieve more accurate decoding operations. In this way, the number of computing units skipped at one time can be flexibly adjusted based on the computing power information and / or the amount of information.

[0211] The decoding intermediate variable unit is used to iteratively calculate the confidence information alternately transmitted between each check node and each variable node according to the aggregation level; here, it should be noted that the decoding intermediate variable unit can be executed according to the calculation method in the aforementioned channel decoding method when transmitting the confidence information, which will not be repeated here.

[0212] The node updating unit is used to decode the to-be-decoded bit sequence according to the confidence information of each of the variable nodes to obtain target information.

[0213] In the reconfigurable chip architecture of the embodiment of the present application, when a bit sequence to be decoded is received, the control unit determines the number of nodes used to indicate synchronous iteration according to the computing power information and / or the amount of information related to the bit sequence to be decoded; in this way, the speed of synchronous transmission of confidence information can be flexibly adjusted according to the amount of calculation; then, the decoding intermediate variable unit iteratively calculates the confidence information alternately transmitted between each check node and each variable node according to the aggregation level; in this way, compared with the one-by-one iteration method, the number of iterations is reduced and the decoding speed can be improved; finally, the node update unit decodes the bit sequence to be decoded according to the confidence information of each variable node to obtain the target information; in this way, when updating the node, the confidence information of all relevant nodes is comprehensively considered, thereby improving the decoding performance.

[0214] As a specific implementation, the decoding intermediate variable unit includes an aggregation unit and a sliding control unit that cooperate with each other;

[0215] Among them, the aggregation level unit is used to: control the number of units that transmit confidence information at a single time according to the aggregation level, and perform multiple confidence information operations according to the number of units that transmit confidence information at a single time; here, the number of units that transmit confidence information at a single time corresponds to the aggregation level. For example, if the aggregation level is 3, the number of units that transmit confidence information at a single time is 3, that is, 3 confidence information are operated on each time.

[0216] The sliding control unit is used to set a calculation unit that needs to be skipped according to the information sent by the aggregation level unit.

[0217] In this optional implementation, through the cooperation between the aggregation level unit and the sliding control unit, multiple calculation units are calculated at one time, and the calculation window is set to the calculation unit of the next calculation according to the aggregation level. In this way, synchronous iterative calculation is achieved and the number of iterations is reduced. In the specific implementation, the aggregation level unit and the sliding control unit can be controlled by the control unit according to the aggregation level.

[0218] As a specific implementation, the node updating unit includes:

[0219] A check node updating unit, used to update the check node according to the confidence information output by the decoding intermediate variable unit; specifically, updating the check node according to the result of the decoding intermediate variable unit calculating the confidence information received by the check node;

[0220] The variable node updating unit is used to update the variable node according to the confidence information output by the decoding intermediate variable unit, specifically, to update the variable node according to the result of the decoding intermediate variable unit operating on the confidence information received by the variable node; and, to decode the to-be-decoded bit sequence according to the confidence information of each of the variable nodes to obtain the target information. Here, the process of decoding the to-be-decoded bit sequence according to the confidence information of each of the variable nodes can be performed in an existing manner.

[0221] Furthermore, the reconfigurable chip architecture also includes:

[0222] A memory is used to store the log-likelihood ratio LLR of the bit sequence to be decoded, the target information and the check matrix. Specifically, Figure 4 As shown, the memory may include ROM_H for storing a check matrix, RAM_OUT for storing target information, and RAM_IN for storing LLR.

[0223] In simple terms, the entire reconfigurable chip architecture mainly includes a control unit (Decoder_Controller), a check node update unit (CNU_UNIT), a variable node update unit (VNU_UNIT), a decoding intermediate variable unit (M_UNIT), and a (RAM_IN) for storing decoding input information, a (RAM_OUT) for storing decoding output information, and a (ROM_H) for storing a check matrix. The implementation of the multivariate algorithm (synchronous iterative operation) proposed in this application is mainly completed in the decoding intermediate variable unit (M_UNIT). Figure 4 In the schematic diagram shown, a feasible aggregation level configuration method is that the aggregation level unit (Joint Unit) controls the number of units that transmit the confidence information at one time, and implements the corresponding multivariate Taylor series. For example, the number of units is two ( Figure 4 When the number of units that the aggregation level unit (Joint Unit) controls to transmit the confidence information at one time is three ( Figure 4 When the sliding control unit (Slide Unit) cooperates with the aggregation level unit (Joint Unit) to set the calculation unit (Calculator) that needs to skip three processes at a time. Among them, the configuration of the aggregation level unit (Joint Unit) and the sliding control unit (Slide Unit) is controlled by the controller (Decoder_controller).

[0224] The channel decoding method, the confidence information transmission circuit and the reconfigurable chip architecture of the embodiment of the present application innovatively propose the concept of the aggregation level to refer to the number of units that continue to transmit multiple confidence information at one time, and at the same time propose an architecture design scheme that can flexibly reconfigure and adaptively adjust the aggregation level during the decoding process to achieve a more intelligent decoding scheme. Specifically, the embodiment of the present application replaces the iteration of node information one by one with the synchronous iteration of multiple node information, and uses the multivariate Taylor series approximation method to fit it. The advantage of this algorithm is that it reduces the number of iterations of the Jacobi algorithm and improves the decoding speed. At the same time, due to the introduction of Taylor series linear approximation, the module calculation complexity increases slightly. It is worth mentioning that, as mentioned above, when performing Taylor series linear approximation, the binary correction term function used in this example can be further expanded to a multivariate correction term function, and linear approximation or other approximation is performed on the whole to obtain a shorter iteration time. At the same time, this type of algorithm fully utilizes the information of all nodes, so it is theoretically superior to MS, NMS, OMS and other algorithms to achieve fast, high-precision, and easy-to-hardware channel decoding. In addition, the embodiment of the present application also designs a corresponding hardware implementation circuit, and the circuit implements nonlinear functions through segmented linear multiplication and addition calculations, and its complexity is low, and its complexity does not change with the increase of expansion points.

[0225] In the embodiment of the present application, module can be implemented with software so that it can be executed by various types of processors. For example, an executable code module of an identification can include one or more physical or logical blocks of computer instructions, for example, it can be constructed as an object, process or function. Nevertheless, the executable code of the identified module does not need to be physically located together, but can include different instructions stored in different positions, and when these instructions are logically combined together, it constitutes a module and realizes the specified purpose of the module.

[0226] In fact, executable code module can be a single instruction or many instructions, and can even be distributed on a plurality of different code segments, distributed among different programs, and distributed across a plurality of memory devices. Similarly, operating data can be identified in the module, and can be implemented and organized in the data structure of any appropriate type according to any appropriate form. The operating data can be collected as a single data set, or can be distributed in different locations (including on different storage devices), and can only be present on a system or network as an electronic signal at least in part.

[0227] When a module can be implemented by software, considering the level of existing hardware technology, a person skilled in the art can build a corresponding hardware circuit to implement the corresponding function of the module that can be implemented by software without considering the cost. The hardware circuit includes a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors such as logic chips, transistors, or other discrete components. The module can also be implemented by a programmable hardware device, such as a field programmable gate array, a programmable array logic, a programmable logic device, etc.

[0228] The above exemplary embodiments are described with reference to the accompanying drawings, and many different forms and embodiments are feasible without departing from the spirit and teachings of the present application. Therefore, the present application should not be constructed as a limitation of the exemplary embodiments proposed herein. More specifically, these exemplary embodiments are provided so that the present application will be perfect and complete, and the scope of the present application will be conveyed to those who are familiar with the technology. In these figures, the component sizes and relative sizes may be exaggerated for clarity. The terms used here are only based on the purpose of describing specific exemplary embodiments and are not intended to be limiting. As used herein, unless the text clearly indicates otherwise, the singular forms "one", "an" and "the" are intended to include these multiple forms. It will be further understood that the terms "comprising" and / or "including" when used in this specification indicate the presence of the features, integers, steps, operations, components and / or components, but do not exclude the presence or increase of one or more other features, integers, steps, operations, components, components and / or their groups. Unless otherwise indicated, when stated, a range of values ​​includes the upper and lower limits of that range and any subranges therebetween.

[0229] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A channel decoding method, characterized in that: include: When receiving a bit sequence to be decoded, determining an aggregation level according to computing power information and / or an amount of information related to the bit sequence to be decoded; The aggregation level is used to indicate the number of nodes for synchronous iteration; Iteratively calculating the confidence information alternately transmitted between each check node and each variable node according to the aggregation level; The to-be-decoded bit sequence is decoded according to the confidence information of each of the variable nodes to obtain target information.

2. The method according to claim 1, characterized in that According to the aggregation level, iteratively calculating the confidence information alternately transmitted between each check node and each variable node, including: When calculating the confidence information transmitted from the first node to the second node, determining, according to the check matrix, a plurality of third nodes that transmit the confidence information to the second node, wherein the first node and the second node are of different types, and the first node and the third nodes are of the same type; According to the aggregation level, the confidence information received by the plurality of third nodes and the confidence information received by the first node are synchronously iterated to obtain the confidence information transmitted by the first node to the second node.

3. The method according to claim 2, characterized in that According to the aggregation level, synchronously iterating the confidence information received by the plurality of third nodes and the confidence information received by the first node to obtain the confidence information transmitted by the first node to the second node includes: Generate an iterative operation sequence according to the confidence information received by the plurality of third nodes and the confidence information received by the first node, wherein the confidence information received by the first node is the last information of the iterative operation sequence; According to the aggregation level, synchronous iterative operation is performed on the information in the iterative operation sequence to obtain confidence information transmitted by the first node to the second node.

4. The method according to claim 3, characterized in that: Generating an iterative operation sequence according to the confidence information received by the plurality of third nodes and the confidence information received by the first node, comprising: When the number of the plurality of third nodes is an integer multiple of the difference between the aggregation level and 1, sorting the confidence information received by the third nodes and the confidence information received by the first node to obtain the iterative operation sequence; When the number of the plurality of third nodes is not an integer multiple of the difference between the aggregation level and 1, preset confidence information is constructed, and the confidence information received by the plurality of third nodes, the preset confidence information and the confidence information received by the first node are sorted to obtain an iterative operation sequence; wherein the preset confidence information is located after the confidence information received by the plurality of third nodes.

5. The method according to claim 3 or 4, characterized in that: According to the aggregation level, performing synchronous iterative operation on the information in the iterative operation sequence to obtain the confidence information transmitted by the first node to the second node includes: The i-th confidence information in the iterative operation sequence is operated in sequence with the N-1 confidence information before the i-th confidence information to obtain a first operation result, and the i-th confidence information is updated to the first operation result; wherein, i=k*(N-1)+1, k is a positive integer, and N is the aggregation level.

6. The method according to claim 5, characterized in that The i-th confidence information in the iterative operation sequence is operated with N-1 confidence information before the i-th confidence information, comprising: Based on the Jacobi function, construct an operational relational expression for N pieces of confidence information for operation; The Taylor series is used to perform linear fitting on the operational relationship.

7. The method according to claim 6, characterized in that The linear fitting of the operational relational expression is performed using Taylor series, including: Sorting the N pieces of confidence information to obtain a first value region that meets a preset convergence condition; Selecting an expansion point for fitting in the first value range; The operation relation is linearly fitted by performing Taylor series expansion at the expansion point.

8. A confidence information transmission circuit, applicable to the confidence information calculation process in the channel decoding method according to any one of claims 1 to 7, characterized in that: include: An information calculator, used for calculating the received N pieces of confidence information; a first selector, connected to the information calculator, for performing segmented selection on the calculation result of the information calculator; A post-calculator, connected to the first selector, is used to operate on multiple results obtained by segmented selection, and calculate the operation results with the Nth confidence information to update the Nth confidence information.

9. The trust information transmission circuit according to claim 8, characterized in that: The post-calculator comprises: A processor, connected to the first selector, and configured to respectively calculate the results of the selection of each segment; A first adder is connected to the processor and is used to accumulate each operation result output by the processor and the Nth confidence information.

10. The trust information transmission circuit according to claim 9, characterized in that: The processor comprises: A positive detector, connected to the first selector, for performing a positive operation on the results of each segment selection respectively; A memory, used for storing a parameter lookup table; a multiplier connected to the positive detector and configured to perform a multiplication operation on an output result of the positive detector and a first parameter found in the parameter lookup table; The second adder is connected to the multiplier and is used to perform an addition operation on an output result of the multiplier and a second parameter found in the parameter lookup table.

11. The trust information transmission circuit according to claim 10, characterized in that: The confidence information transmission circuit also includes: A second selector is connected to the first adder, and is used for inputting the Nth confidence information into the second adder.

12. A reconfigurable chip architecture, applicable to the channel decoding method according to any one of claims 1 to 7, characterized in that: include: A control unit, configured to determine an aggregation level according to computing power information and / or an amount of information related to the bit sequence to be decoded when receiving the bit sequence to be decoded; the aggregation level is used to indicate the number of nodes for synchronous iteration; A decoding intermediate variable unit, used for iteratively calculating the confidence information alternately transmitted between each check node and each variable node according to the aggregation level; The node updating unit is used to decode the to-be-decoded bit sequence according to the confidence information of each of the variable nodes to obtain target information.

13. The reconfigurable chip architecture according to claim 12, characterized in that: The decoding intermediate variable unit includes an aggregation unit and a sliding control unit that cooperate with each other; The aggregation level unit is used to: control the number of units that transmit the confidence information at a time according to the aggregation level, and perform confidence information calculation according to the number of units that transmit the confidence information at a time; The sliding control unit is used to set a calculation unit that needs to be skipped according to the information sent by the aggregation level unit.

14. The reconfigurable chip architecture according to claim 12, characterized in that: The node updating unit comprises: A check node updating unit, used to update the check node according to the confidence information output by the decoding intermediate variable unit; The variable node updating unit is used to update the variable nodes according to the confidence information output by the decoding intermediate variable unit, and decode the to-be-decoded bit sequence according to the confidence information of each of the variable nodes to obtain target information.

15. The reconfigurable chip architecture according to claim 12, characterized in that: Also includes: A memory is connected to the control unit, the decoding intermediate variable unit and the node updating unit respectively, and is used to store the log-likelihood ratio of the to-be-decoded bit sequence, the target information and the check matrix.

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