Method for etching metal structure and semiconductor structure with metal structure

Abstract

The invention provides a method for etching a metal structure and a semiconductor structure with the metal structure, and the method comprises the steps: providing a substrate of which the surface comprises a device layer and a covering layer on the surface of the device layer, and the device layer comprises a first connection structure; forming an etching barrier layer on the surface of the covering layer; a graphical photoresist layer is formed on the surface of the etching barrier layer, the graphical photoresist layer exposes an opening of a region corresponding to the first connection structure in the device layer, and the side wall of the opening is perpendicular to the surface of the etching barrier layer; forming a graphical etching barrier layer to partially expose the covering layer; forming a second connection structure on the surface of the covering layer exposed by the graphical etching barrier layer; and the second connecting structure is used as a mask to pattern the covering layer, so that the key size of the generated metal structure meets the process requirement, the method can be used for preparing a semiconductor metal structure with small-size metal intervals, and the capability of a process platform is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for etching a metal structure and a semiconductor structure having the metal structure. Background Art

[0002] In the metal etching process of the prior art, silicon oxynitride (SiON) is deposited on the metal layer, and photolithography and etching are performed on this basis. During the photolithography process, the area where the photoresist is retained in the patterned photoresist layer corresponds to the functional area in the circuit pattern. Figure 1 Schematic diagram of the structure of a device for forming a patterned photoresist layer in the prior art. Figure 1 As shown, the area 02 where the photoresist is retained corresponds to the metal wire in the circuit pattern and corresponds to the first connection structure 01. Due to the process limit when using the photoresist layer for photolithography, when the spacing between the metal wires in the circuit pattern is very small (for example, the spacing between the metal wires is less than 180 nanometers), the photolithography conditions will be unstable or the surface of the photoresist after photolithography will be uneven during the process, and then the side wall of the photoresist will not be perpendicular to the metal layer, resulting in the key dimension of the top of the metal wire being inconsistent with the key dimension measured by the inspection after development in the subsequent etching process, and the stability of the line cannot be monitored.

[0003] How to provide a method for etching metal structures that can be used to etch scenarios where the spacing between metal lines is very small so that the key dimensions of the formed metal lines meet the requirements is of great value in improving the capabilities of the process platform and providing production efficiency. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for etching a metal structure and a semiconductor structure having a metal structure, which can be used in a scenario where the spacing between etching metal lines is very small, so that the key dimensions of the formed metal lines meet the requirements.

[0005] In order to solve the above problems, the present invention provides a method for etching a metal structure, comprising: providing a substrate, wherein the surface of the substrate comprises a device layer, and a covering layer on the surface of the device layer, wherein the device layer comprises a first connection structure; forming an etch barrier layer on the surface of the covering layer; forming a patterned photoresist layer on the surface of the etch barrier layer, wherein the patterned photoresist layer has an opening for exposing an area corresponding to the first connection structure in the device layer, and the sidewall of the opening is perpendicular to the surface of the etch barrier layer; patterning the etch barrier layer using the patterned photoresist layer as a mask to form a patterned etch barrier layer to partially expose the covering layer, and removing the patterned photoresist layer; forming a second connection structure on the surface of the covering layer exposed by the patterned etch barrier layer; and patterning the covering layer using the second connection structure as a mask to partially expose the device layer.

[0006] In some embodiments, the covering layer is a composite layer consisting of a titanium nitride layer, an aluminum layer, and a titanium nitride layer.

[0007] In some embodiments, the second connection structure and the first connection structure are made of tungsten.

[0008] In some embodiments, the material of the etch stop layer is silicon oxynitride.

[0009] In some embodiments, the step of forming a patterned photoresist layer on the surface of the etch stop layer further includes: forming a photoresist material layer on the surface of the etch stop layer; patterning the photoresist material layer to form the patterned photoresist layer having an opening exposing an area corresponding to the first connection structure in the device layer; and treating the opening with a burning process so that the sidewalls of the opening are perpendicular to the surface of the etch stop layer.

[0010] In some embodiments, the burning process uses plasma to bombard the photoresist on the sidewall of the opening to increase the temperature so as to achieve the purpose of burning.

[0011] In some embodiments, the plasma is formed using an oxygen source.

[0012] In some embodiments, the step of forming a patterned photoresist layer on the surface of the etch stop layer further includes: measuring the size of the opening and comparing it with a target size.

[0013] In some embodiments, the step of forming a second connection structure in the area exposed by the patterned etch barrier layer further includes: forming a continuously distributed second connection material layer on the surface of the patterned etch barrier layer; thinning the second connection material layer using a chemical mechanical polishing process until the patterned etch barrier layer is exposed, and forming a separated second connection structure with the remaining second connection material layer in the gap of the patterned etch barrier layer.

[0014] In some embodiments, the minimum width between two adjacent second connection structures is less than 180 nanometers.

[0015] In some embodiments, the thickness of the patterned photoresist layer is less than 150 nanometers.

[0016] In some embodiments, in the step of patterning the cover layer using the second connection structure as a mask, a metal etch-back process is used to pattern the cover layer.

[0017] In order to solve the above problem, the present invention further provides a semiconductor structure having a metal structure, wherein the semiconductor structure is prepared by the method for etching the metal structure.

[0018] The above technical scheme provides a substrate, wherein the surface of the substrate includes a device layer and a covering layer on the surface of the device layer, wherein the device layer includes a first connection structure; an etching stop layer is formed on the surface of the covering layer; a patterned photoresist layer is formed on the surface of the etching stop layer, wherein the patterned photoresist layer exposes an opening in an area corresponding to the first connection structure in the device layer, and the sidewall of the opening is perpendicular to the surface of the etching stop layer; a patterned etching stop layer is formed using the patterned photoresist layer as a mask to partially expose the covering layer, and the patterned photoresist layer is removed; a second connection structure is formed on the surface of the covering layer exposed by the patterned etching stop layer; the covering layer is patterned using the second connection structure as a mask so that the critical dimensions of the generated metal structure meet the process requirements. The above method for etching a metal structure can be used to prepare a semiconductor metal structure with a small-size metal line spacing, thereby improving the capability of the process platform.

[0019] It should be understood that the above general description and the detailed description below are exemplary and explanatory only and cannot limit the present invention. The techniques, methods and devices known to ordinary technicians in the relevant field may not be discussed in detail, but where appropriate, the techniques, methods and devices should be considered as part of the authorization specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 It is a schematic diagram of the structure of a device for forming a patterned photoresist layer in the prior art;

[0022] Figure 2 is a flow chart of a method for etching a metal structure provided by an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of a device structure including a substrate, a device layer and a cover layer provided by an embodiment of the present invention;

[0024] Figure 4 is a schematic diagram of a device structure formed by the step of forming an etching stop layer provided in one embodiment of the present invention;

[0025] Figure 5A to Figure 5B It is a schematic diagram of a device structure formed by the step of forming a patterned photoresist layer provided by an embodiment of the present invention;

[0026] Figure 6It is a schematic diagram of a device structure formed by the steps of patterning the etching stop layer and removing the patterned photoresist layer provided in one embodiment of the present invention;

[0027] Figure 7A to Figure 7B is a schematic diagram of a device structure formed by the step of forming a second connection structure provided in one embodiment of the present invention;

[0028] Figure 8 It is a schematic diagram of a device structure formed by the step of graphing the covering layer provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0029] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Please refer to Figure 2 to Figure 8 , Figure 2 is a flow chart of a method for etching a metal structure provided by an embodiment of the present invention; Figure 3 is a schematic diagram of a device structure including a substrate, a device layer and a cover layer provided by an embodiment of the present invention; Figure 4 is a schematic diagram of a device structure formed by the step of forming an etching stop layer provided in one embodiment of the present invention; Figure 5A to Figure 5B It is a schematic diagram of a device structure formed by the step of forming a patterned photoresist layer provided by an embodiment of the present invention; Figure 6 It is a schematic diagram of a device structure formed by the steps of patterning the etching stop layer and removing the patterned photoresist layer provided in one embodiment of the present invention; Figure 7A to Figure 7B is a schematic diagram of a device structure formed by the step of forming a second connection structure provided in one embodiment of the present invention; Figure 8 It is a schematic diagram of a device structure formed by the step of graphing the covering layer provided in one embodiment of the present invention.

[0031] like Figure 2As shown, the method for etching a metal structure includes: step S11, providing a substrate, the surface of the substrate includes a device layer, and a covering layer on the surface of the device layer, and the device layer includes a first connection structure; step S12, forming an etch barrier layer on the surface of the covering layer; step S13, forming a patterned photoresist layer on the surface of the etch barrier layer, the patterned photoresist layer has an opening that exposes an area corresponding to the first connection structure in the device layer, and the sidewall of the opening is perpendicular to the surface of the etch barrier layer; step S14, patterning the etch barrier layer using the patterned photoresist layer as a mask to partially expose the covering layer, and removing the patterned photoresist layer; step S15, forming a second connection structure on the surface of the covering layer exposed by the patterned etch barrier layer; step S16, patterning the covering layer using the second connection structure as a mask to partially expose the device layer.

[0032] Refer to step S11 and Figure 3 A substrate 10 is provided, wherein the surface of the substrate 10 includes a device layer 11, and a cover layer 12 on the surface of the device layer 11, wherein the device layer 11 includes a first connection structure 111. The cover layer 12 is a composite layer composed of a titanium nitride layer, an aluminum layer, and a titanium nitride layer. Specifically, the cover layer 12 is composed of a first titanium nitride layer 121, an aluminum layer 122, and a second titanium nitride layer 123. Figure 3 As shown, the material of the device layer 11 is silicon oxide, a first connection structure 111 is formed in the device layer 11, the material of the first connection structure 111 is tungsten, and the device layer 11 further includes a gate structure 112 including a spacer.

[0033] Refer to step S12 and Figure 4 , an etching stop layer 13 is formed on the surface of the cover layer 12. The material of the etching stop layer 13 is silicon oxynitride. Silicon oxynitride can obtain the required refractive index through process adjustment, and has the advantages of good chemical stability, low film stress, strong fracture resistance, etc., and can avoid deformation of the pattern in lithography. In some embodiments, the material of the etching stop layer 13 is silicon nitride.

[0034] Refer to step S13 and Figure 5B A patterned photoresist layer 14 is formed on the surface of the etching stop layer 13, and the patterned photoresist layer 14 has an opening that exposes the area corresponding to the first connection structure 111 in the device layer 11, and the sidewall of the opening is perpendicular to the surface of the etching stop layer 13. The width of the opening is d1. In this embodiment, the minimum width of the interval between the metal lines on the circuit pattern is less than 180 nanometers, and accordingly, the minimum value of the opening size d1 corresponding to the first connection structure 111 is less than 180 nanometers.

[0035] This step further includes: step S131, forming a photoresist material layer on the surface of the etch stop layer; step S132, patterning the photoresist material layer to form the patterned photoresist layer having an opening exposing the area corresponding to the first connection structure in the device layer; step S133, treating the opening with a burning process so that the side wall of the opening is perpendicular to the surface of the etch stop layer.

[0036] Referring to step S131, a photoresist material layer is formed on the surface of the etch stop layer 13. The photoresist material layer can completely cover the etch stop layer 13 (not shown).

[0037] Refer to step S132 and Figure 5A , patterning the photoresist material layer to form the patterned photoresist layer 14 having an opening exposing the area corresponding to the first connection structure 111 in the device layer 11.

[0038] In this embodiment, the photoresist is a positive photoresist, that is, after development, the unexposed part of the photoresist is retained; and the photoresist mask is a negative mask, that is, the circuit pattern on the photoresist mask is transparent and can transmit light. By selecting the polarity of the photoresist and the photoresist mask, the area where the photoresist is retained in the patterned photoresist layer 14 formed after photolithography corresponds to the line gap of the metal line of the circuit pattern, and the area where the photoresist is removed in the patterned photoresist layer 14 corresponds to the metal line in the circuit pattern. Figure 1 It is a schematic diagram of the structure of a device for forming a patterned photoresist layer in the prior art. Figure 5A and Figure 1 It can be seen that, contrary to the prior art, the area where the photoresist is removed in the patterned photoresist layer 14 in this step corresponds to the functional area in the circuit pattern and corresponds to the first connection structure 111 in the device layer 11 .

[0039] In some embodiments, the photoresist is a negative photoresist, that is, the portion of the photoresist that is exposed and developed is retained; and the photoresist mask is a positive mask, that is, the circuit pattern on the photoresist mask is opaque. It is also possible to make the area where the photoresist is removed in the patterned photoresist layer 14 correspond to the functional area in the circuit pattern and to correspond to the first connection structure 111 in the device layer 11.

[0040] In this step, the thickness of the patterned photoresist layer 14 is less than 150 nanometers. Accordingly, the thickness of the photoresist material layer used to form the patterned photoresist layer 14 is less than 150 nanometers, for example, the thickness of the photoresist material layer is 140 nanometers, 120 nanometers, 100 nanometers. Compared with the metal etching process of the prior art, the thickness of the photoresist layer applied to form the patterned photoresist layer is reduced to a quarter or less of the thickness of the photoresist layer applied by photolithography in the prior art. After the photoresist layer is thinned, the limit size that can be completed by the corresponding photolithography process becomes smaller, so that the photolithography process can meet the circuit pattern with a smaller size.

[0041] Refer to step S133 and Figure 5B , the opening is processed by a burning process so that the sidewall of the opening is perpendicular to the surface of the etching stop layer 13. Figure 5A After the patterned photoresist layer 14 is formed by a photolithography process, the sidewalls of the openings of the patterned photoresist layer 14 may have beveled edges, and the edges of the photoresist sidewalls are not flat and uniform. In this step, a burning process is used to make the sidewalls of the openings of the patterned photoresist layer 14 perpendicular to the surface of the cover layer 13.

[0042] In this embodiment, the burning process is a photolithography descum process (also known as Descum), which uses chemical and physical reactions of plasma to remove substances on the surface of the semiconductor. Specifically, plasma is used to bombard the photoresist on the side wall of the opening to increase its temperature to achieve the purpose of burning, thereby flattening and unifying the side wall of the opening. The plasma is formed by an oxygen source, and the highly reactive monatomic oxygen in the oxygen plasma is used to easily react with the hydrocarbon oxygen polymer compound in the photoresist to generate a volatile reactant, thereby removing the excess photoresist on the side wall of the photoresist.

[0043] After executing step S131 to step S133, the process further includes: measuring the size of the opening and comparing it with the target size. That is, measuring the width of the opening in the patterned photoresist layer 14 after the sidewalls are verticalized and comparing it with the target size. The target size is the required size of the functional area in the circuit pattern. Figure 5B , the distance indicated by the double arrow is the opening size d1, and the opening size d1 corresponds to the size of the functional area in the circuit pattern and corresponds to the first connection structure 111 in the device layer 11. The opening size d1 is measured, and if the size error between the measurement result and the process requirement exceeds the range, the patterned photoresist layer 14 is removed, and after cleaning, steps S131 to S133 are re-executed until the formed opening size d1 meets the target size requirement.

[0044] Referring to step S14, the etch stop layer 13 is patterned using the patterned photoresist layer 14 as a mask to form a patterned etch stop layer 131, so as to partially expose the cover layer 12, and then remove the patterned photoresist layer 14. Figure 5B .

[0045] The schematic diagram of the device structure after executing step S14 is as follows: Figure 6 As shown, the patterned etch stop layer 131 is formed on the surface of the cover layer 12, and the spacing dimension d2 in the patterned etch stop layer 131 corresponds to the first connection structure 111 in the device layer 11. In this embodiment, the spacing dimension d2 in the patterned etch stop layer 131 is measured, and the spacing dimension d2 in the patterned etch stop layer 131 corresponds to the first connection structure 111 in the device layer 11. Figure 5B If the spacing dimension d2 is different from the opening dimension d1, the patterned etching stop layer 131 is removed and cleaned, and then steps S12 to S14 are performed again.

[0046] Refer to step S15 and Figure 7B A second connection structure 141 is formed on the surface of the cover layer 12 exposed by the patterned etching stop layer 131. Figure 7B As shown, the gaps in the patterned etch stop layer 131 are filled with the second connection structures 141 , and the critical dimension d3 of the second connection structures 141 is the same as the spacing dimension d2 in the patterned etch stop layer 131 .

[0047] This step further includes: step S151, forming a continuously distributed second connecting material layer on the surface of the patterned etch barrier layer; step S152, thinning the second connecting material layer using a chemical mechanical polishing process until the patterned etch barrier layer is exposed, and the remaining second connecting material layer in the gap of the patterned etch barrier layer forms a separated second connecting structure.

[0048] Refer to step S151 and Fig. 7A A continuously distributed second connection material layer 14 is formed on the surface of the patterned etching stop layer 131. The material of the second connection material layer 14 is tungsten. The metal material tungsten has good electrical conductivity and can be used as a hard mask material.

[0049] Refer to step S152 and Figure 7BThe second connection material layer 14 is thinned by a chemical mechanical polishing process until the patterned etch stop layer 131 is exposed, and the remaining second connection material layer 14 at the gap of the patterned etch stop layer 131 forms a separated second connection structure 141. The second connection structure 141 corresponds to the first connection structure 111. The material of the second connection structure 141 is tungsten.

[0050] After forming the second connection structure 141, measure the critical dimension d3 of the second connection structure 141, that is, measure the width of the second connection structure 141. If the critical dimension d3 of the second connection structure 141 does not match the target dimension required in the circuit pattern, remove the second connection structure 141 and the patterned etching stop layer 131 and clean them, and re-execute steps S12 to S15.

[0051] In this embodiment, the minimum width between two adjacent second connection structures 141 is less than 180 nanometers, thereby achieving the process requirement that the minimum width of the interval between metal lines on the circuit pattern is less than 180 nanometers.

[0052] Refer to step S16 and Figure 8 The second connection structure 141 is used as a mask to pattern the cover layer 12 to partially expose the device layer 11. In this step, the cover layer 12 is patterned by a metal etching back process. Figure 8 As shown, the cover layer 12 after patterning consists of a first titanium nitride layer 121, an aluminum layer 122, and a second titanium nitride layer 123. The critical dimension d4 of the cover layer 12 after patterning is measured and is consistent with the target dimension required by the process in the circuit pattern.

[0053] Based on the same inventive concept, the present invention further provides a semiconductor structure with a metal structure, and the semiconductor structure with a metal structure is prepared by the above-mentioned method for etching a metal structure.

[0054] The device structure schematic diagram of the prepared semiconductor structure is shown in FIG. Figure 8 For details, please refer to Figure 3 to Figure 8The metal structure is prepared by the following steps: step S11, providing a substrate 10, wherein the surface of the substrate includes a device layer 11, and a covering layer 12 on the surface of the device layer 11, wherein the device layer 11 includes a first connection structure 111; step S12, forming an etching stop layer 13 on the surface of the covering layer 12; step S13, forming a patterned photoresist layer 14 on the surface of the etching stop layer 13, wherein the patterned photoresist layer 14 has an opening exposing an area corresponding to the first connection structure 111 in the device layer 11, and the The side wall of the opening is perpendicular to the surface of the etch stop layer 13; step S14, patterning the etch stop layer 13 with the patterned photoresist layer 14 as a mask to form a patterned etch stop layer 131 to partially expose the cover layer 12, and removing the patterned photoresist layer 14; step S15, forming a second connection structure 141 on the surface of the cover layer 12 exposed by the patterned etch stop layer 131; step S16, patterning the cover layer 12 with the second connection structure 141 as a mask to partially expose the device layer 11.

[0055] Among them, step S13 further includes: step S131, forming a photoresist material layer on the surface of the etching stop layer 13; step S132, patterning the photoresist material layer to form the patterned photoresist layer 14 having an opening exposing the area corresponding to the first connection structure 111 in the device layer 11; step S133, using a burning process to process the opening so that the side wall of the opening is perpendicular to the surface of the etching stop layer 13.

[0056] Step S15 further includes: step S151, forming a continuously distributed second connecting material layer 14 on the surface of the patterned etch barrier layer 131; step S152, thinning the second connecting material layer 14 using a chemical mechanical polishing process until the patterned etch barrier layer 131 is exposed, and the remaining second connecting material layer 14 in the gap of the patterned etch barrier layer 131 forms a separated second connecting structure 141.

[0057] The above technical scheme provides a substrate, wherein the surface of the substrate includes a device layer and a covering layer on the surface of the device layer, wherein the device layer includes a first connection structure; an etching stop layer is formed on the surface of the covering layer; a patterned photoresist layer is formed on the surface of the etching stop layer, wherein the patterned photoresist layer exposes an opening in an area corresponding to the first connection structure in the device layer, and the sidewall of the opening is perpendicular to the surface of the etching stop layer; a patterned etching stop layer is formed using the patterned photoresist layer as a mask to partially expose the covering layer, and the patterned photoresist layer is removed; a second connection structure is formed on the surface of the covering layer exposed by the patterned etching stop layer; the covering layer is patterned using the second connection structure as a mask so that the critical dimensions of the generated metal structure meet the process requirements. The above method for etching a metal structure can be used to prepare a semiconductor metal structure with a small-size metal line spacing, thereby improving the capability of the process platform.

[0058] It should be noted that, in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion. The various embodiments in this specification are described in a related manner, and the same and similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0059] The above is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for etching a metal structure, characterized in that: include: Providing a substrate, wherein the surface of the substrate comprises a device layer and a covering layer covering the surface of the device layer, and the device layer comprises a first connection structure; forming an etching stop layer on the surface of the covering layer; Forming a patterned photoresist layer on the surface of the etch stop layer, wherein the patterned photoresist layer has an opening exposing a region corresponding to the first connection structure in the device layer, and a sidewall of the opening is perpendicular to the surface of the etch stop layer; Using the patterned photoresist layer as a mask to pattern the etch stop layer to form a patterned etch stop layer, so as to partially expose the cover layer, and then removing the patterned photoresist layer; forming a second connection structure on the surface of the cover layer exposed by the patterned etch stop layer; The cover layer is patterned using the second connection structure as a mask to partially expose the device layer.

2. The method according to claim 1, characterized in that The covering layer is a composite layer consisting of a titanium nitride layer, an aluminum layer and a titanium nitride layer.

3. The method according to claim 1, characterized in that The second connection structure and the first connection structure are made of tungsten.

4. The method according to claim 1, characterized in that: The material of the etching stop layer is silicon oxynitride.

5. The method according to claim 1, characterized in that The step of forming a patterned photoresist layer on the surface of the etch stop layer further comprises: forming a photoresist material layer on the surface of the etch stop layer; Patterning the photoresist material layer to form the patterned photoresist layer having an opening exposing a region corresponding to the first connection structure in the device layer; The opening is processed by a burning process so that the side wall of the opening is perpendicular to the surface of the etching stop layer.

6. The method according to claim 5, characterized in that The burning process uses plasma to bombard the photoresist on the side wall of the opening to increase the temperature so as to achieve the purpose of burning.

7. The method according to claim 6, characterized in that The plasma is formed using an oxygen source.

8. The method according to claim 1, characterized in that The step of forming a patterned photoresist layer on the surface of the etch stop layer further comprises: The size of the opening is measured and compared to a target size.

9. The method according to claim 1, characterized in that: The step of forming a second connection structure on the surface of the cover layer exposed by the patterned etch stop layer further comprises: forming a continuously distributed second connection material layer on the surface of the patterned etching stop layer; The second connection material layer is thinned by a chemical mechanical polishing process until the patterned etch stop layer is exposed, and the second connection material layer remaining in the gap of the patterned etch stop layer forms a separated second connection structure.

10. The method according to claim 1, characterized in that The minimum width between two adjacent second connection structures is less than 180 nanometers.

11. The method according to claim 1, characterized in that: The thickness of the patterned photoresist layer is less than 150 nanometers.

12. The method according to claim 1, characterized in that In the step of patterning the cover layer using the second connection structure as a mask, the cover layer is patterned using a metal etching back process.

13. A semiconductor structure having a metal structure, characterized in that: The metal structure is prepared by the method for etching a metal structure as described in any one of claims 1 to 12.

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