Staggered PFC circuit control method, control device and switching power supply

Abstract

The invention discloses a staggered PFC circuit control method, a control device and a switching power supply. The control method comprises the following steps: acquiring a first voltage sampling signal representing the magnitude of current flowing through a first power loop and a second voltage sampling signal representing the magnitude of current flowing through a second power loop; the operational transconductance amplifier generates an error current according to a difference value between the first voltage sampling signal and the second voltage sampling signal, and then the filter circuit filters the error current to obtain a current-sharing compensation voltage signal; generating a first power loop driving pulse width modulation signal; and generating a second power loop driving pulse width modulation signal under the regulation of the current-sharing compensation voltage signal, increasing the duty ratio of the second power loop driving pulse width modulation signal when the current-sharing compensation voltage signal is greater than the set threshold voltage, and otherwise, reducing the duty ratio of the second power loop driving pulse width modulation signal. On the basis of reducing the number of the peripheral pins of the IC, the problem of non-uniform current in staggered application can be effectively solved.

Description

Technical Field

[0001] The present invention relates to the technical field of converters, and in particular to a control method, a control device and a switching power supply of an interleaved PFC circuit. Background Art

[0002] Traditional single-phase bridge CRM mode PFC is often used in situations within 300W. In order to further increase the power, single-phase bridge CCM mode PFC is selected in 300W ~ 1000W. If the power level needs to be further increased (for example, 3000W power level), the staggered CCM mode control strategy is often used to implement the PFC function.

[0003] However, in actual applications, the use of interleaved parallel PFC control requires not only that the total input current and input voltage be in phase and have low distortion, but also that the inductor current in each branch be evenly distributed.

[0004] However, in the actual production process, the parameters of the components between the two power branches (such as impedance, inductance, etc.) have certain differences and discreteness. These factors will cause unequal inductance currents in different branches, which will lead to unbalanced distribution of power transmission between the two branches, and even the total PFC circuit energy is only powered by a single branch. This not only increases the power margin left in each branch, but also causes overcurrent faults or overtemperature faults, greatly reducing the reliability of the switching power supply system.

[0005] At the same time, the interleaved parallel PFC system generally samples the current signal of each circuit to limit the peak current to avoid system damage. However, due to the interleaved control, there is a phase shift in the switch drive of the first power circuit and the second power circuit. Therefore, the traditional interleaved current sharing technology generally needs to filter or sample and hold the collected current signals of each circuit to eliminate the influence of the phase, and then perform current sharing feedback control. If this process is applied to an analog IC, it often requires more pins for external capacitors or more complex internal control methods, which is not conducive to simplifying the IC periphery and enhancing reliability. Summary of the invention

[0006] In view of this, the technical problem to be solved by the present invention is to provide a staggered PFC circuit control method, a control device and a switching power supply, which at least solve one of the technical problems existing in the prior art to a certain extent.

[0007] As a first aspect of the present invention, an embodiment and technical solution of an interleaved PFC circuit control method is provided as follows:

[0008] A method for controlling an interleaved PFC circuit, wherein the interleaved PFC circuit comprises a first power circuit and a second power circuit, wherein the method for controlling the interleaved PFC circuit comprises:

[0009] a current sampling step, obtaining a first voltage sampling signal representing the magnitude of the current flowing through the first power circuit, and a second voltage sampling signal representing the magnitude of the current flowing through the second power circuit;

[0010] a compensation signal generating step, wherein a transconductance operational amplifier generates an error current according to a difference between the first voltage sampling signal and the second voltage sampling signal, and then a filter circuit filters the error current to obtain a current-sharing compensation voltage signal;

[0011] A first power loop driving pulse width modulation step, generating a first power loop driving pulse width modulation signal;

[0012] The second power circuit driving pulse width modulation step generates a second power circuit driving pulse width modulation signal under the regulation of the current sharing compensation voltage signal, maintains the duty cycle of the second power circuit driving pulse width modulation signal unchanged when the current sharing compensation voltage signal is equal to the set threshold voltage, increases the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is greater than the set threshold voltage, and reduces the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is less than the set threshold voltage.

[0013] Preferably, the current sampling step obtains the first voltage sampling signal by sampling an instantaneous current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling an average current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling a peak current signal of the current flowing through the first power circuit switch tube, or obtains the first voltage sampling signal by sampling an average current signal of the current flowing through the first power circuit switch tube;

[0014] And or the current sampling step obtains the second voltage sampling signal by sampling the instantaneous current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the average current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the peak current signal of the current flowing through the second power circuit switch tube, or obtains the second voltage sampling signal by sampling the average current signal of the current flowing through the second power circuit switch tube.

[0015] As a second aspect of the present invention, the technical solution of the embodiment of the interleaved PFC circuit control device provided is as follows:

[0016] A staggered PFC circuit control device, the staggered PFC circuit comprising a first power circuit and a second power circuit, wherein the staggered PFC circuit control device comprises:

[0017] A current sampling module, used to obtain a first voltage sampling signal representing the magnitude of the current flowing through the first power circuit, and a second voltage sampling signal representing the magnitude of the current flowing through the second power circuit;

[0018] A compensation signal generating module, comprising a transconductance operational amplifier and a filter circuit, wherein the transconductance operational amplifier is used to generate an error current according to the difference between the first voltage sampling signal and the second voltage sampling signal, and the filter circuit is used to obtain a current-sharing compensation voltage signal after filtering the error current;

[0019] A first power loop driving pulse width modulation module, used for generating a first power loop driving pulse width modulation signal;

[0020] The second power circuit driving pulse width modulation module is used to generate a second power circuit driving pulse width modulation signal under the regulation of the current sharing compensation voltage signal, keep the duty cycle of the second power circuit driving pulse width modulation signal unchanged when the current sharing compensation voltage signal is equal to the set threshold voltage, increase the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is greater than the set threshold voltage, and reduce the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is less than the set threshold voltage.

[0021] Preferably, the current sampling module obtains the first voltage sampling signal by sampling the instantaneous current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the average current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the peak current signal of the current flowing through the first power circuit switch tube, or obtains the first voltage sampling signal by sampling the average current signal of the current flowing through the first power circuit switch tube;

[0022] And or the current sampling module obtains the second voltage sampling signal by sampling the instantaneous current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the average current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the peak current signal of the current flowing through the second power circuit switch tube, or obtains the second voltage sampling signal by sampling the average current signal of the current flowing through the second power circuit switch tube.

[0023] Preferably, the first power circuit pulse width modulation module includes a first comparator and a first trigger module, the same-direction input terminal of the first comparator is used to input the signal obtained by superimposing the first modulation signal and the first bias voltage, the reverse input terminal is used to input the first reference signal, and the output terminal is connected to the S terminal of the first trigger module, the R terminal of the first trigger module is used to input the first clock signal, and the Q terminal outputs the first power circuit driving pulse width modulation signal.

[0024] Preferably, the second power circuit pulse width modulation module includes a second comparator and a second trigger module, the same-direction input terminal of the second comparator is used to input the second modulation signal, the first bias voltage and the signal after the current equalization compensation voltage signal is superimposed, the reverse input terminal inputs the second reference signal, and the output terminal is connected to the S terminal of the second trigger module, the R terminal of the second trigger module is used to input the second clock signal, and the Q terminal outputs the second power circuit drive pulse width modulation signal.

[0025] Preferably, the first power circuit pulse width modulation module includes a first comparator and a first trigger module, the same-direction input terminal of the first comparator is used to input the signal after the first modulation signal and the first bias voltage are superimposed, the reverse input terminal is used to input the first reference signal, and the output terminal is connected to the S terminal of the first trigger module, the R terminal of the first trigger module is used to input the first clock signal, and the Q terminal is used to output the first power circuit driving pulse width modulation signal; the second power circuit pulse width modulation module includes a second comparator and a second trigger module, the same-direction input terminal of the second comparator is used to input the signal after the second modulation signal, the first bias voltage and the current sharing compensation voltage signal are superimposed, the reverse input terminal is used to input the second reference signal, and the output terminal is connected to the S terminal of the second trigger module, the R terminal of the second trigger module is used to input the second clock signal, and the Q terminal is used to output the second power circuit driving pulse width modulation signal.

[0026] Furthermore, the second modulation signal is obtained by shifting the first modulation signal by a first phase shift angle, and the second clock signal is obtained by shifting the first clock signal by a second phase shift angle, and the first phase shift angle is equal to the second phase shift angle.

[0027] Furthermore, the second reference signal is the sum of the first reference signal and the threshold voltage.

[0028] As a third aspect of the present invention, the technical solution of the embodiment of the switching power supply provided is as follows:

[0029] A switching power supply comprises an interleaved PFC circuit, wherein the interleaved PFC circuit comprises a first power loop and a second power loop, wherein: the switching power supply further comprises the interleaved PFC circuit control device as described in any one of the second aspects above.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] (1) In the embodiment of the present invention, a transconductance amplifier generates an error current according to the difference between the first voltage sampling signal and the second voltage sampling signal, and a current sharing compensation voltage signal is obtained after filtering by the filter circuit. The second power circuit driving pulse width modulation signal is adjusted by the current sharing compensation voltage signal, so as to achieve current sharing between each circuit in the interleaved circuit. The current sharing of the traditional interleaved PFC needs to limit the peak current of each power circuit to achieve. Obviously, the current sharing control strategy of the embodiment of the present invention does not need to deal with the problem of phase shift of the sampling signal in the interleaved circuit, and the control is simpler;

[0032] (2) The embodiment of the present invention is simple to control and can greatly reduce the peripheral circuit area when applied in an IC. In theory, only one additional pin is needed, and the additional pin is used to generate a current sharing compensation signal. The current sharing scheme of the traditional interleaved PFC requires additional pins including a first loop current sampling signal filter pin, a second loop current sampling signal filter pin, and a current sharing compensation signal pin. Therefore, the embodiment of the present invention can greatly reduce the number of IC pins, thereby improving the integration of the IC. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 A control block diagram of an existing interleaved PFC;

[0034] Figure 2 for Figure 1 Working waveforms of different branches when there is tolerance in inductance of interleaved PFC control;

[0035] Figure 3 for Figure 1 Working waveforms of different branches when there is a tolerance in the turn-on time of the interleaved PFC control MOS tube;

[0036] Figure 4 for Figure 2 , Figure 3 The resulting inductor current waveforms of different branches under interleaved PFC control;

[0037] Figure 5 A flow chart of an interleaved PFC control method provided by a first embodiment of the present invention;

[0038] Figure 6 A functional block diagram of an interleaved PFC control device provided by a second embodiment of the present invention;

[0039] Figure 7 A principle block diagram of a first preferred interleaved PFC control device provided for the second embodiment of the present invention;

[0040] Figure 8 This is an example of a preferred current sharing signal generating circuit of the present invention;

[0041] Fig. 9 for Figure 7 The working waveform diagram of the switching power supply with interleaved PFC control implemented with tolerance. DETAILED DESCRIPTION

[0042] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application may be combined with each other.

[0043] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0044] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application are described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, the process, method, system, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0045] It should be understood that, in the specification, claims and drawings, when a step is described as being connected to another step, the step may be directly connected to the other step, or be connected to the other step through a third step; when an element / unit is described as being "connected" to another element / unit, the element / unit may be "directly connected" to the other element / unit, or be "connected" to the other element / unit through a third element / unit.

[0046] In addition, the drawings of the present disclosure are only schematic diagrams of the present disclosure and are not necessarily drawn to scale. The same symbols in the drawings represent the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented using software, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontrollers.

[0047] like Figure 1 The figure shows an existing bridge interleaved CCM PFC based on single cycle control, wherein the circuit including the inductor L1, the switch tube S1 and the diode D1 is the main phase power circuit, and the circuit including the inductor L2, the switch tube S2 and the diode D2 is the slave phase power circuit, wherein the working principle of the control device for controlling the switch tube S1 and the switch tube S2 is as follows:

[0048] The sum of the inductor currents of the main phase power loop and the slave phase power loop is detected by the resistor R1 as a current sampling signal. After the current sampling signal passes through the low-pass filter module 11, an input average current sampling signal can be obtained. The signal is connected to the reverse input terminal of the comparator COP1 and COP2;

[0049] The output voltage loop module 41 generates a voltage loop output feedback signal Vfb, and the sawtooth wave generating module 21 and the sawtooth wave generating module 22 generate corresponding currents according to the feedback signal Vfb to charge the capacitor to generate corresponding sawtooth waveforms, wherein the charging reset signal of the sawtooth wave generating module 21 is OSC, and the charging reset signal of the sawtooth wave generating module 22 is a phase shifted charging reset signal of the module 21. For two-phase interleaving applications, a phase shift of 180° is optimal. At the same time, the sawtooth wave signals generated by the sawtooth wave generating module 21 and the sawtooth wave generating module 22 are respectively connected to the positive input terminals of the comparators COP1 and COP2;

[0050] When the sawtooth wave signal voltage generated by the sawtooth wave generating module 21 is greater than the input average current sampling signal output by the low-pass filtering module 11, the comparator COP1 generates a rising edge, and the rising edge signal is input to the S terminal of the trigger module 31. At this time, the output of the trigger module 31 is set to a high level. When the rising edge of the charging reset signal OSC arrives, the output of the drive signal generating module 31 is set to a low level. The output of the drive signal generating module 31 is used to control the conduction and shutdown of the switch tube S1 in the main phase power circuit;

[0051] Similarly, when the sawtooth wave signal voltage generated by the sawtooth wave generating module 22 is greater than the input average current sampling signal output by the low-pass filtering module 11, the comparator COP2 generates a rising edge, and the rising edge signal is input to the S end of the trigger module 32. At this time, the output of the trigger module 32 is set to a high level, and the charging reset signal OSC is phase-shifted. When the rising edge of the signal after the phase shift arrives, the output of the drive signal generating module 32 is set to a low level. The output of the drive signal generating module 32 is used to control the conduction and shutdown of the switch tube S2 in the slave phase power circuit. At the same time, for two-phase interleaving applications, a phase shift of 180° is optimal.

[0052] Figure 1The problem with the circuit is that in the actual production process, the parameters of the components between the two power branches (such as impedance, inductance, etc.) have certain differences and discreteness. If there is no additional current sharing control, these factors will cause unequal inductance currents in different branches, which will lead to unbalanced power distribution during power transmission between the two branches.

[0053] Figure 2 The figure shows a situation where the main phase power circuit and the slave phase power circuit are not balanced. In the actual production process of the product, the inductance of the main phase power circuit and the inductance of the slave phase power circuit cannot be exactly the same, and there may be a deviation of ±10%. Assuming that the inductance of the slave phase power circuit is small and the inductance of the main phase power circuit is large, as shown in 201 and 202, the inductance of the slave phase power circuit is small, so the excitation slope is larger, and when Vfb is consistent, the conduction time of S1 is the same as the conduction time of S2, so it will cause the current flowing through the slave phase power circuit to be larger, and the slave phase power circuit and the main phase power circuit are not balanced.

[0054] Figure 3 The figure shows another situation where the main phase power circuit and the slave phase power circuit are not current-balanced. In the actual production process of the product, the power switch parameters of the main phase power circuit and the slave phase power circuit cannot be exactly the same, such as the turn-on delay time and the turn-off delay time. Here, the turn-off delay time is taken as an example. It is assumed that the inductance of the main phase power circuit and the slave phase power circuit are equal, where 301 is the turn-off delay time of the slave phase power circuit S2, 302 is the turn-off time of S1 of the main phase power circuit, and 303 is the additional turn-on time of the slave phase power circuit S2. Therefore Figure 2 ,as well as Figure 3 The situation will cause the power transmitted by the slave phase power circuit to be greater than the power transmitted by the main phase power circuit. The schematic waveform is as follows Figure 4 As shown, 401 is the inductor current waveform of the slave phase power loop, and 402 is the inductor current waveform of the master phase power loop.

[0055] In view of the deficiencies in the prior art, the present invention provides a control scheme for realizing energy transmission of each branch of an interleaved PFC circuit simply and effectively even when the parameters of the original devices of each branch in the interleaved PFC circuit are greatly different, and current sharing control can be realized without additionally processing the phase problem of the sampling signals when there is a phase shift between the first voltage sampling signal and the second voltage sampling signal.

[0056] First embodiment

[0057] This embodiment provides a method for controlling an interleaved PFC circuit. The interleaved PFC circuit includes a first power circuit and a second power circuit. Figure 5A flow chart of an interleaved PFC control method provided in a first embodiment of the present invention, wherein the interleaved PFC circuit control method comprises:

[0058] A current sampling step S100 is to obtain a first voltage sampling signal representing the magnitude of the current flowing through the first power circuit, and a second voltage sampling signal representing the magnitude of the current flowing through the second power circuit;

[0059] In the compensation signal generating step S200, a transconductance operational amplifier generates an error current according to the difference between the first voltage sampling signal and the second voltage sampling signal, and then a filter circuit filters the error current to obtain a current-sharing compensation voltage signal;

[0060] A first power circuit driving pulse width modulation step S300, generating a first power circuit driving pulse width modulation signal;

[0061] The second power circuit driving pulse width modulation step S400 generates a second power circuit driving pulse width modulation signal under the regulation of the current sharing compensation voltage signal, keeps the duty cycle of the second power circuit driving pulse width modulation signal unchanged when the current sharing compensation voltage signal is equal to the set threshold voltage, increases the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is greater than the set threshold voltage, and reduces the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is less than the set threshold voltage.

[0062] In the interleaved PFC circuit control method of the present embodiment, a transconductance amplifier generates an error current according to the difference between the first voltage sampling signal and the second voltage sampling signal, and a current sharing compensation voltage signal is obtained after filtering by the filtering circuit. The second power circuit driving pulse width modulation signal is adjusted by the current sharing compensation voltage signal, so as to achieve current sharing between each circuit in the interleaved circuit, while the current sharing of the traditional interleaved PFC needs to limit the peak current of each power circuit to achieve. Obviously, the current sharing control strategy of the embodiment of the present invention does not need to deal with the problem of phase shift of the sampling signal in the interleaved circuit, and the control is simpler. In addition, due to the simple control of the embodiment of the present invention, the application of the peripheral circuit area in the IC can be greatly reduced, and theoretically only one pin is required, and the added pin is used to generate the current sharing compensation signal, while the current sharing scheme of the traditional interleaved PFC needs to add pins including the first circuit current sampling signal filter pin, the second circuit current sampling signal filter pin, and the current sharing compensation signal pin. Therefore, the embodiment of the present invention can greatly reduce the number of IC pins, thereby improving the integration of the IC.

[0063] As a specific embodiment, the current sampling step obtains a first voltage sampling signal by sampling the instantaneous current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the average current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the peak current signal of the current flowing through the first power circuit switch tube, or obtains the first voltage sampling signal by sampling the average current signal of the current flowing through the first power circuit switch tube; and or the current sampling step obtains a second voltage sampling signal by sampling the instantaneous current signal of the inductor of the second power circuit, or obtains the second voltage sampling signal by sampling the average current signal of the inductor of the second power circuit, or obtains the second voltage sampling signal by sampling the peak current signal of the current flowing through the second power circuit switch tube, or obtains the second voltage sampling signal by sampling the average current signal of the current flowing through the second power circuit switch tube.

[0064] Second embodiment

[0065] This embodiment provides a staggered PFC circuit control device, the staggered PFC circuit includes a first power circuit and a second power circuit. Figure 6 This is a functional block diagram of an interleaved PFC control device provided in a second embodiment of the present invention, wherein the interleaved PFC circuit control device comprises:

[0066] The current sampling module 100 is used to obtain a first voltage sampling signal representing the magnitude of the current flowing through the first power circuit, and a second voltage sampling signal representing the magnitude of the current flowing through the second power circuit;

[0067] The compensation signal generating module 200 includes a transconductance operational amplifier and a filter circuit, wherein the transconductance operational amplifier is used to generate an error current according to the difference between the first voltage sampling signal and the second voltage sampling signal, and the filter circuit is used to obtain a current-sharing compensation voltage signal after filtering the error current;

[0068] A first power loop driving pulse width modulation module 300, used to generate a first power loop driving pulse width modulation signal;

[0069] The second power circuit driving pulse width modulation module 400 is used to generate a second power circuit driving pulse width modulation signal under the regulation of the current sharing compensation voltage signal, keep the duty cycle of the second power circuit driving pulse width modulation signal unchanged when the current sharing compensation voltage signal is equal to the set threshold voltage, increase the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is greater than the set threshold voltage, and reduce the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is less than the set threshold voltage.

[0070] The technical means adopted by the control device of this embodiment correspond to and are consistent with the control method of the first embodiment, and the beneficial effects are the same, so they are not described in detail.

[0071] Figure 7 The first preferred flow control device principle block diagram provided for the second embodiment of the present invention is as follows: Figure 7 501 is a current sampling module, which can sample the current signal flowing through the main phase power circuit and the slave phase power circuit, which can be the inductor current waveform, or the current flowing through the main phase power circuit switch tube S1 and the slave phase power circuit switch tube S2. After the main phase power circuit current signal and the slave phase power circuit current signal collected by the current sampling module are processed by the leading edge blanking module, the current signal of the slave phase power circuit is subtracted from the current signal of the main phase power circuit, and the error current is given to the transconductance module 502. The transconductance module 502 will output an error current according to the error current, and the error current is connected to the first-order or second-order filtering network to obtain the current sharing compensation signal V2 shown in 504.

[0072] Please continue to see Figure 7 , wherein the first modulation signal is a sawtooth wave signal, OSC is a first clock signal, the first modulation signal has the same frequency as the first clock signal, the first modulation signal is added to the first bias voltage 505 and input to the positive terminal of the first comparator, and the first reference signal is Figure 1 The input average current sampling signal output by the low-pass filter module 11, when the sum of the first modulation signal and the first bias voltage is greater than the first reference signal, the first comparator generates a rising edge signal, the signal is input to the S end of the first trigger to make the main phase power circuit drive signal become a high level, when the rising edge of the first clock signal is input to the R end of the first trigger, the main phase power circuit drive signal becomes a low level.

[0073] Furthermore, the first modulation signal is phase-shifted to obtain the second modulation signal. Generally, the phase shift is 180° when the two phases are staggered. The second modulation signal is added with the first bias voltage and the current sharing compensation signal V2 and input into the positive end of the comparator. The first reference voltage and the threshold voltage 506 are added and input into the reverse end of the comparator. When the sum of the second modulation signal, the first bias voltage and the current sharing compensation signal V2 is greater than the sum of the first reference signal and the threshold voltage, the comparator generates a rising edge signal, which is input into the S end of the second trigger to make the slave phase power circuit drive signal become a high level. At the same time, the first clock signal is phase-shifted to obtain the second clock signal. The phase shift angle is consistent with the phase shift angle of the first modulation signal to obtain the second modulation signal. Generally, the phase shift is 180° when the two phases are staggered. When the rising edge of the second clock signal is input into the R end of the trigger, the slave phase power circuit drive signal becomes a low level.

[0074] The principle of the current sharing regulation is shown in 507. When the current of the main phase power circuit is large, the current sharing compensation signal V2 will be greater than the threshold voltage. Since the first reference signal is an industrial frequency cycle, it can be regarded as approximately unchanged during the switching cycle. Therefore, when the current sharing compensation signal V2 is greater than the threshold voltage, the slave phase power circuit drive signal will increase, thereby realizing current sharing transmission of the two-phase circuits, and vice versa.

[0075] Figure 8 It is a current sharing compensation signal generating circuit, wherein CSB is the current sampling signal of the slave phase power loop (i.e., the second voltage sampling signal), CSA is the current sampling signal of the master phase power loop (i.e., the first voltage sampling signal), the peak current limiting module is mainly used to realize the cycle-by-cycle peak current limiting in the PFC system, GM is a transconductance amplifier, CSB is connected to the positive end of the transconductance amplifier, and CSA is connected to the negative end of the transconductance amplifier.

[0076] When the slave phase power loop current is greater than the master phase power loop current, CSB is greater than CSA, and the transconductance amplifier generates a negative current. At this time, the compensation voltage signal V2 is pulled low. Figure 7 According to the principle, at this time, the pulse width of the driving signal of the slave phase power circuit is reduced, and the current of the slave phase power circuit is reduced, thereby realizing current equalization transmission of the two-phase circuits, and vice versa.

[0077] After simulation verification, the control device of this embodiment can achieve a master-slave transmission power error within 3%, which greatly increases the reliability of the switching power supply. Fig. 9 In the case where the inductance of the two-phase power circuit differs by 40%, Figure 7 The effect diagram of control realization, where 701 is the inductance current of the slave phase power loop, 702 is the inductance current of the master phase power loop, and 703 is the current sharing compensation signal V2. From the actual effect, the master-slave two-phase current sharing effect is good.

[0078] Third embodiment

[0079] The present embodiment provides a switching power supply, including an interleaved PFC circuit, the interleaved PFC circuit including a first power circuit and a second power circuit, wherein: the switching power supply further includes any interleaved PFC circuit control device of the second embodiment.

[0080] Since the switching power supply of this embodiment uses any of the interleaved PFC circuit control devices of the second embodiment, it can effectively solve the problem of poor consistency of current distribution in power transmission of each circuit when using interleaved CCM control when there is tolerance in the switching power supply device, thereby ensuring the safety and reliability of the entire system.

[0081] Although the present invention has been described with reference to several typical embodiments, it should be understood that the terms used are illustrative and exemplary, rather than restrictive. Since the present invention can be embodied in a variety of forms without departing from the spirit or nature of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims, so all changes and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A method for controlling an interleaved PFC circuit, wherein the interleaved PFC circuit comprises a first power circuit and a second power circuit, wherein: The interleaved PFC circuit control method comprises: a current sampling step, obtaining a first voltage sampling signal representing the magnitude of the current flowing through the first power circuit, and a second voltage sampling signal representing the magnitude of the current flowing through the second power circuit; a compensation signal generating step, wherein a transconductance operational amplifier generates an error current according to a difference between the first voltage sampling signal and the second voltage sampling signal, and then a filter circuit filters the error current to obtain a current-sharing compensation voltage signal; A first power loop driving pulse width modulation step, generating a first power loop driving pulse width modulation signal; The second power circuit driving pulse width modulation step generates a second power circuit driving pulse width modulation signal under the regulation of the current sharing compensation voltage signal, maintains the duty cycle of the second power circuit driving pulse width modulation signal unchanged when the current sharing compensation voltage signal is equal to the set threshold voltage, increases the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is greater than the set threshold voltage, and reduces the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is less than the set threshold voltage.

2. The interleaved PFC circuit control method according to claim 1, characterized in that: The current sampling step obtains the first voltage sampling signal by sampling the instantaneous current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the average current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the peak current signal of the current flowing through the first power circuit switch tube, or obtains the first voltage sampling signal by sampling the average current signal of the current flowing through the first power circuit switch tube; And or the current sampling step obtains the second voltage sampling signal by sampling the instantaneous current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the average current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the peak current signal of the current flowing through the second power circuit switch tube, or obtains the second voltage sampling signal by sampling the average current signal of the current flowing through the second power circuit switch tube.

3. A staggered PFC circuit control device, the staggered PFC circuit comprising a first power circuit and a second power circuit, characterized in that: The interleaved PFC circuit control device comprises: A current sampling module, used to obtain a first voltage sampling signal representing the magnitude of the current flowing through the first power circuit, and a second voltage sampling signal representing the magnitude of the current flowing through the second power circuit; A compensation signal generating module, comprising a transconductance operational amplifier and a filter circuit, wherein the transconductance operational amplifier is used to generate an error current according to the difference between the first voltage sampling signal and the second voltage sampling signal, and the filter circuit is used to obtain a current-sharing compensation voltage signal after filtering the error current; A first power loop driving pulse width modulation module, used for generating a first power loop driving pulse width modulation signal; The second power circuit driving pulse width modulation module is used to generate a second power circuit driving pulse width modulation signal under the regulation of the current sharing compensation voltage signal, keep the duty cycle of the second power circuit driving pulse width modulation signal unchanged when the current sharing compensation voltage signal is equal to the set threshold voltage, increase the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is greater than the set threshold voltage, and reduce the duty cycle of the second power circuit driving pulse width modulation signal when the current sharing compensation voltage signal is less than the set threshold voltage.

4. The interleaved PFC circuit control device according to claim 3, characterized in that: The current sampling module obtains the first voltage sampling signal by sampling the instantaneous current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the average current signal of the inductor of the first power circuit, or obtains the first voltage sampling signal by sampling the peak current signal of the current flowing through the first power circuit switch tube, or obtains the first voltage sampling signal by sampling the average current signal of the current flowing through the first power circuit switch tube; And or the current sampling module obtains the second voltage sampling signal by sampling the instantaneous current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the average current signal of the inductance of the second power circuit, or obtains the second voltage sampling signal by sampling the peak current signal of the current flowing through the second power circuit switch tube, or obtains the second voltage sampling signal by sampling the average current signal of the current flowing through the second power circuit switch tube.

5. The interleaved PFC circuit control device according to claim 3, characterized in that: The first power circuit pulse width modulation module includes a first comparator and a first trigger module, the first comparator's non-inverting input terminal is used to input a signal obtained by superimposing a first modulation signal and a first bias voltage, the reverse input terminal is used to input a first reference signal, and the output terminal is connected to the S terminal of the first trigger module, the R terminal of the first trigger module is used to input a first clock signal, and the Q terminal outputs the first power circuit driving pulse width modulation signal.

6. The interleaved PFC circuit control device according to claim 3, characterized in that: The second power circuit pulse width modulation module includes a second comparator and a second trigger module, the same-direction input terminal of the second comparator is used to input the second modulation signal, the first bias voltage and the signal after the current sharing compensation voltage signal is superimposed, the reverse input terminal inputs the second reference signal, and the output terminal is connected to the S terminal of the second trigger module, the R terminal of the second trigger module is used to input the second clock signal, and the Q terminal outputs the second power circuit drive pulse width modulation signal.

7. The interleaved PFC circuit control device according to claim 3, characterized in that: The first power circuit pulse width modulation module includes a first comparator and a first trigger module, wherein the first comparator has a non-inverting input terminal for inputting a signal obtained by superimposing a first modulation signal and a first bias voltage, a reverse input terminal for inputting a first reference signal, and an output terminal connected to an S terminal of the first trigger module, an R terminal of the first trigger module for inputting a first clock signal, and a Q terminal for outputting a first power circuit driving pulse width modulation signal; The second power circuit pulse width modulation module includes a second comparator and a second trigger module, the same-direction input terminal of the second comparator is used to input the second modulation signal, the first bias voltage and the signal after the current sharing compensation voltage signal is superimposed, the reverse input terminal inputs the second reference signal, and the output terminal is connected to the S terminal of the second trigger module, the R terminal of the second trigger module is used to input the second clock signal, and the Q terminal outputs the second power circuit drive pulse width modulation signal.

8. The interleaved PFC circuit control device according to claim 7, characterized in that: The second modulation signal is obtained by shifting the first modulation signal by a first phase shift angle, and the second clock signal is obtained by shifting the first clock signal by a second phase shift angle, wherein the first phase shift angle is equal to the second phase shift angle.

9. The interleaved PFC circuit control device according to claim 7, characterized in that: The second reference signal is the sum of the first reference signal and the threshold voltage.

10. A switching power supply, comprising an interleaved PFC circuit, wherein the interleaved PFC circuit comprises a first power loop and a second power loop, wherein: The switching power supply further comprises the interleaved PFC circuit control device as claimed in any one of claims 3 to 9.

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