Coding method and device for data communication

Abstract

The invention discloses a coding method for data communication, which can be applied to multiple scenes such as metropolitan area, backbone network, data center interconnection and the like, the method comprises the following steps: forming a first code word, the first code word comprises n mirror image bits and n bits to be transmitted, and the n mirror image bits are selected from the bits to be transmitted of m source code words, the source code word is a code word formed before the first code word, n and m are positive integers, and n is greater than m; and sending out the n bits to be transmitted of the first code word. Wherein the bits in the first code word are protected by the code words generated at different moments, and the coding gain effect is better; and moreover, the bits in the code words are protected by different numbers of code words, and the bits protected by more code words have higher convergence speed, so that the decoding speed of the decoder can be improved, and the time delay is reduced.

Description

[0001] This application is a divisional application. The application number of the original application is 202010881014.4, and the original application date is August 27, 2020. The original application claimed priority of a new application with an application date of March 31, 2020 and an application number of 202010245565.1. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0002] The present application relates to a coding technology, and more particularly to a coding technology and device for data communication with low latency. Background Art

[0003] Communication systems usually send data at the transmitting end and transmit it to the receiving end through a communication channel, thereby realizing a large amount of information transmission. For example, communication channels include optical fiber transmission, wireless, cable, etc. However, when the transmitted signal passes through the communication channel, the noise in the channel or the noise of the transceiver device will be superimposed, causing errors in the received signal at the receiving end. In order to be able to recover the original signal sent by the transmitting end from the erroneously received signal, it is a common practice to use Forward Error Correction (FEC).

[0004] FEC uses the information bits to be transmitted to generate check bits of a certain length based on a certain coding relationship, and then combines the check bits and information bits for transmission. At the receiving end, the check bits and the known coding relationship are used to correct the bit errors caused by the transmission process. At present, due to the emergence of new technologies such as artificial intelligence (AI), the demand for ultra-low latency and high reliability interconnection is becoming increasingly prominent, and improving coding gain and reducing latency are becoming more and more important. Summary of the invention

[0005] The present application provides a coding method and device for data communication, which solves the problem in the prior art that high coding gain and low delay cannot be guaranteed at the same time.

[0006] In a first aspect, a coding method for data communication is provided, the method comprising: forming a first codeword, the first codeword comprising 2n bits, formed by k coding bits, and the n bits of the first codeword coming from m codewords formed before the first codeword, the other n bits in the first codeword comprising kn information bits and 2n-k check bits, wherein n, m, and k are all positive integers, and 2n>k>n>m; and sending the other n bits in the first codeword.

[0007] In the embodiment of the present application, the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can improve the decoding speed of the decoder and play a role in reducing latency.

[0008] In combination with the first aspect, in a first possible implementation manner of the first aspect, the method further includes: storing the additional n bits for use in encoding codewords subsequent to the first codeword.

[0009] In combination with the first aspect or the first possible implementation of the first aspect, in a second possible implementation of the first aspect, the first codeword comes from the m codewords formed before the first codeword, and each codeword has the same number of bits, where n is an integer multiple of m. In this implementation, the first codeword shares the same number of bits from each of the m previously formed codewords, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, the number of codewords that need to be shared is reduced, and the data collection and decoding process can be quickly completed at the receiving end, thereby reducing latency.

[0010] In combination with the first aspect or the first possible implementation manner of the first aspect, in a third possible implementation manner of the first aspect, the number of bits of the first codeword from the second codeword is a, and among the m codewords formed before the first codeword, at least one codeword provides the first codeword with a number of bits that is different from a, wherein a is a positive integer, and the second codeword is any one of the m codewords formed before the first codeword.

[0011] In this embodiment, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords. The bits protected by a larger number of codewords converge faster, and then drive the bits protected by fewer codewords to converge, thereby improving the decoding speed of the decoder and reducing the delay.

[0012] In combination with the first aspect or any one of the above possible implementations, in a fourth possible implementation of the first aspect, forming the first codeword specifically includes: encoding n bits from m codewords formed before the first codeword and kn information bits to be transmitted to obtain 2n-k check bits to form the first codeword.

[0013] In combination with the first aspect or any of the above possible implementations, in a fifth possible implementation of the first aspect, the n bits sent out in the first codeword are shared with some codewords formed after the first codeword. Further, the n bits sent out in the first codeword are shared with m codewords formed after the first codeword. Half of the bits in each codeword are shared with the previously formed codeword, and the other half of the bits are shared with the subsequently formed codeword, ensuring that each bit is protected by a different codeword, and better coding gain can be obtained.

[0014] In combination with the first aspect or any one of the above possible implementation manners, in a sixth possible implementation manner of the first aspect, each bit in the first codeword is adopted by at least two codewords.

[0015] In combination with the first aspect or any one of the above possible implementations, in a seventh possible implementation of the first aspect, among the bits in the first codeword from m previously formed codewords, at least some bits are check bits in the previous codeword.

[0016] In combination with the first aspect or any of the above possible implementations, in an eighth possible implementation of the first aspect, n is 360 and k is 700. It should be understood that this is a specific codeword given in the present application, and the first codeword may also be other bit numbers, which is not limited in the present application.

[0017] In combination with the first aspect or any one of the above possible implementations, in a ninth possible implementation of the first aspect, the m codewords formed before the first codeword are divided into b groups, and the n bits in the first codeword shared with the previous codeword are divided into b groups, and each group in the first codeword corresponds to a group of the m codewords formed before the first codeword, wherein b is a positive integer, and n and m are both integer multiples of b.

[0018] In combination with the ninth possible implementation manner of the first aspect, in a tenth possible implementation manner of the first aspect, n is 360, and m is 256; the 256 codewords formed before the first codeword are divided into 4 groups, each with 64 codewords; the 360 ​​bits in the first codeword shared with the previous codeword are divided into 4 groups, each with 90 bits, wherein each group of 90 bits comes from a corresponding group of 64 codewords.

[0019] In a second aspect, a coding device for data communication is provided, the coding device comprising a coding unit and a sending unit, the coding unit being used to form a first codeword, the first codeword comprising 2n bits, formed by k coding bits, and the n bits of the first codeword coming from m codewords formed before the first codeword, the other n bits in the first codeword comprising kn information bits and 2n-k check bits, the other n bits being sent to the sending unit, wherein n, m, and k are all positive integers, and 2n>k>n>m; the sending unit being further used to send out the other n bits in the first codeword.

[0020] In the encoding device provided in the embodiment of the present application, the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can improve the decoding speed of the decoder and play a role in reducing latency.

[0021] In combination with the second aspect, in a first possible implementation manner of the second aspect, the encoding device also includes a storage unit, which is used to store the additional n bits in the first codeword for use by the encoding unit when encoding a codeword after the first codeword.

[0022] In combination with the second aspect or the first possible implementation of the second aspect, in a second possible implementation of the second aspect, the first codeword comes from the m codewords formed before the first codeword, and each codeword has the same number of bits, where n is an integer multiple of m. In this implementation, the first codeword shares the same number of bits from each of the m previously formed codewords, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, the number of codewords that need to be shared is reduced, and the data collection and decoding process can be quickly completed at the receiving end, thereby reducing latency.

[0023] In combination with the second aspect or the first possible implementation of the second aspect, in a third possible implementation of the second aspect, the number of bits of the first codeword from the second codeword is a, and among the m codewords formed before the first codeword, at least one codeword provides the first codeword with a number of bits different from a, wherein a is a positive integer, and the second codeword is any one of the m codewords formed before the first codeword. In this embodiment, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords converge faster, and then drive the bits protected by fewer codewords to converge, thereby improving the decoding speed of the decoder and reducing the delay.

[0024] In combination with the second aspect or any one of the above possible implementations, in a fourth possible implementation of the second aspect, the encoding device is specifically used to: encode n bits from m code words formed before the first code word and kn information bits to be transmitted to obtain 2n-k check bits to form the first code word.

[0025] In combination with the second aspect or any of the above possible implementations, in a fifth possible implementation of the second aspect, the n bits sent out in the first codeword are shared with some codewords formed after the first codeword. Further, the n bits sent out in the first codeword are shared with m codewords formed after the first codeword. Half of the bits in each codeword are shared with the previously formed codeword, and the other half of the bits are shared with the subsequently formed codeword, ensuring that each bit is protected by a different codeword, and better coding gain can be obtained.

[0026] In combination with the second aspect or any of the above possible implementations, in a sixth possible implementation of the second aspect, each bit in the first codeword is adopted by at least two codewords.

[0027] In combination with the first aspect or any one of the above possible implementations, in a seventh possible implementation of the first aspect, among the bits in the first codeword from m previously formed codewords, at least some bits are check bits in the previous codeword.

[0028] In combination with the second aspect or any of the above possible implementations, in an eighth possible implementation of the second aspect, n is 360 and k is 700. It should be understood that this is a specific codeword given in the present application, and the first codeword may also be other bit numbers, which is not limited in the present application.

[0029] In combination with the second aspect or any of the above possible implementations, in a ninth possible implementation of the second aspect, the m codewords formed before the first codeword are divided into b groups, and the n bits in the first codeword shared with the previous codeword are divided into b groups, and each group in the first codeword corresponds to a group of the m codewords formed before the first codeword, wherein b is a positive integer, and n and m are both integer multiples of b.

[0030] In combination with the ninth possible implementation manner of the second aspect, in a tenth possible implementation manner of the second aspect, n is 360, and m is 256; the 256 codewords formed before the first codeword are divided into 4 groups, each with 64 codewords; the 360 ​​bits in the first codeword shared with the previous codeword are divided into 4 groups, each with 90 bits, wherein each group of 90 bits comes from a corresponding group of 64 codewords.

[0031] In a third aspect, a decoding method for data communication is provided, the method comprising: recovering a first codeword, wherein the first codeword comprises 2n bits, is formed by k coded bits, and the n bits of the first codeword come from m codewords decoded before the first codeword, and the other n bits in the first codeword comprise kn information bits and 2n-k check bits, wherein n, m, and k are all positive integers, 2n>k>n>m; decoding the first codeword to obtain decoded bits.

[0032] It should be understood that in this embodiment, before the first codeword is recovered, at least m codewords have been decoded; half of the bits in the first codeword come from the m codewords decoded previously, and the other n bits are the bit stream received at the current moment. In addition, in this embodiment, the number of bits shared between different codewords is different, and there are multiple codewords that share more than one bit. The more bits are shared, the fewer codewords need to be associated, and decoding can be done without waiting too long, thereby reducing system latency.

[0033] In combination with the third aspect, in a first possible implementation of the third aspect, the first codeword comes from the m codewords decoded before the first codeword, and each codeword has the same number of bits, where n is an integer multiple of m. In this implementation, the first codeword shares the same number of bits from each of the m previously decoded codewords, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, the number of codewords that need to be shared is reduced, and the data collection and decoding process can be completed quickly, thereby reducing latency.

[0034] In combination with the third aspect, in a second possible implementation of the third aspect, the number of bits of the first codeword from the second codeword is a, and among the m codewords decoded before the first codeword, at least one codeword provides the first codeword with a number of bits different from a, wherein a is a positive integer, and the second codeword is any one of the m codewords decoded before the first codeword. In this embodiment, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords converge faster, and then drive the bits protected by fewer codewords to converge, thereby improving the decoding speed of the decoder and reducing the delay.

[0035] In combination with the third aspect or any of the above possible implementations, in a third possible implementation of the third aspect, n is 360 and k is 700. It should be understood that this is a specific codeword given in the present application, and the first codeword may also be other bit numbers, which is not limited in the present application.

[0036] In a fourth aspect, a decoding device for data communication is provided, comprising a decoding unit and a storage unit, wherein the decoding unit is used to receive a transmitted codeword, recover a first codeword, and decode the first codeword, wherein the first codeword comprises 2n bits, and the n bits of the first codeword come from m codewords decoded before the first codeword, n and m are both positive integers, and n>m; the storage unit is used to store the codewords from the transmission, and receive decoding information from the decoding unit, update the stored codewords, and send the updated codewords back to the decoding unit in the subsequent decoding process. In the decoding process of this embodiment, the information bits obtained by the previous decoding will be used, and the information bits are protected by different codewords, and the decoding performance is stronger. And the number of bits shared between the two codewords is more, the number of codewords that need to be associated will be reduced, and decoding can be performed without waiting for too long, thereby reducing system latency.

[0037] In conjunction with the fourth aspect, in a first possible implementation of the fourth aspect, the first codeword comes from the m codewords decoded before the first codeword, and each codeword has the same number of bits, where n is an integer multiple of m. In this implementation, the first codeword shares the same number of bits from each of the m previously decoded codewords, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, the number of codewords that need to be shared is reduced, and the data collection and decoding process can be completed quickly, thereby reducing latency.

[0038] In combination with the fourth aspect, in a second possible implementation of the fourth aspect, the number of bits of the first codeword from the second codeword is a, and among the m codewords decoded before the first codeword, at least one codeword provides the first codeword with a number of bits different from a, wherein a is a positive integer, and the second codeword is any one of the m codewords decoded before the first codeword. In this embodiment, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords converge faster, and then drive the bits protected by fewer codewords to converge, thereby improving the decoding speed of the decoder and reducing the delay.

[0039] In combination with the fourth aspect or any of the above possible implementations, in a third possible implementation of the fourth aspect, n is 360 and k is 700. It should be understood that this is a specific codeword given in the present application, and the first codeword may also be other bit numbers, which is not limited in the present application.

[0040] In a fifth aspect, a cascade coding method based on data communication is provided, the method comprising: receiving data bits, performing KP4 coding on the data bits to obtain a KP4 codeword; interleaving the KP4 codeword to obtain an interleaved codeword; encoding the interleaved codeword according to the coding method described in the first aspect or any possible implementation of the first aspect, wherein the interleaved codeword is not decoded before being encoded as described in the first aspect or any possible implementation of the first aspect. In this embodiment, the interleaved KP4 codeword does not need to be decoded, and the next step of cascade coding is directly performed, which can reduce power consumption.

[0041] In a sixth aspect, a cascade coding device based on data communication is provided, the cascade coding device comprising: a first coding unit, an interleaving unit, and a second coding unit; the first coding unit is used to receive data bits, perform KP4 encoding on the data bits, and send the obtained KP4 codeword to the interleaving unit; the interleaving unit is used to interleave the KP4 codeword and send the interleaved codeword to the second coding unit; the second coding unit is used to encode the interleaved codeword according to the encoding method described in the first aspect or any possible implementation of the first aspect, wherein the second coding unit does not decode the interleaved codeword. In this embodiment, the interleaved KP4 codeword does not need to be decoded, and the next step of cascade coding is directly performed, which can reduce power consumption.

[0042] In a seventh aspect, a coding method for data communication is provided, the method comprising: forming a first codeword, the first codeword comprising n mirror bits and n bits to be transmitted, and the n mirror bits are selected from the bits to be transmitted of m source codewords, wherein the source codeword is a codeword formed before the first codeword, n and m are both positive integers, n>m; and sending the n bits to be transmitted of the first codeword.

[0043] In the embodiment of the present application, the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can improve the decoding speed of the decoder and play a role in reducing latency.

[0044] In combination with the seventh aspect, in a first possible implementation of the seventh aspect, the n bits to be transmitted include p check bits and np information bits, wherein the p check bits are encoded by the n mirror bits and the np information bits, and p is a positive integer less than n.

[0045] In combination with the first possible implementation manner of the seventh aspect, in a second possible implementation manner of the seventh aspect, the n mirror bits include mirror check bits and mirror information bits, wherein the mirror check bits are selected from the check bits of the m source codewords, and the mirror information bits are selected from the information bits of the m source codewords.

[0046] In combination with the second possible implementation manner of the seventh aspect, in a third possible implementation manner of the seventh aspect, the number of the mirror check bits and the number of the check bits are the same.

[0047] In combination with the seventh aspect or the above-mentioned possible implementation methods of the seventh aspect, in a fourth possible implementation method of the seventh aspect, among the m source code words, the maximum value of the difference in the number of bits provided to the first code word by different source code words is greater than one bit. At this time, the error correction performance can be further improved while maintaining low latency.

[0048] In combination with the seventh aspect or the foregoing possible implementation manner of the seventh aspect, in a fifth possible implementation manner of the seventh aspect, the code length of the first codeword is not greater than 2048, and the number of error correction bits is not greater than 5. In this embodiment, the first codeword can still have good performance while ensuring low latency.

[0049] In combination with the seventh aspect or the above possible implementation of the seventh aspect, in a sixth possible implementation of the seventh aspect, among the m source codewords, the number of bits provided by at least one source codeword to the first codeword is different from the number of bits provided by other source codewords to the first codeword; or each source codeword provides q bits to the first codeword, where q is an integer greater than 1 and n is an integer multiple of m. In this embodiment, each bit is protected by a different codeword, and the number of bits provided by a codeword to the first codeword can be more than one, so that the decoding speed is faster while ensuring the coding gain.

[0050] In combination with the seventh aspect or the above-mentioned possible implementation manner of the seventh aspect, in a seventh possible implementation manner of the seventh aspect, p_word of the first codewords constitute a first frame, and the mirror bits of the codewords in the first frame come from the bits to be transmitted of the codewords in h second frames generated before the first frame, wherein h and p_word are both positive integers greater than 1.

[0051] In combination with the seventh possible implementation manner of the seventh aspect, in an eighth possible implementation manner of the seventh aspect, the frame coordinates, row coordinates, and column coordinates of the bits in the h second frames are calculated by three functions of Φf(), Φr(), and Φc():

[0052] Φf([Frame,Row_str,Col_str]) = Frame - 1 - frm_map(floor((Col_str + Δ) / ceiling(n / h)));

[0053]

[0054] Φc([Frame,Row_str,Col_str]) = n + h*((Col_str + Δ) % ceiling(n / h)) + (h - 1 - floor((Col_str + Δ) / ceiling(n / h))).

[0055] Among them, the frame coordinate Frame, row coordinate Row_str, and column coordinate Col_str of the mirror bit of the codeword in the first frame are all integers, and Frame ∈ (-∞, +∞), Row_str ∈ [0, p_word - 1], Col_str ∈ [0, 2n - 1]; frm_map(i) = h - 1 - i, i ∈ [0, h - 1];

[0056] If n / h is an integer, Δ = 0; otherwise, if Col_str / floor(n / h) < ceiling(n / h)*h - n, Δ = floor(Col_str / floor(n / h)); if Col_str / floor(n / h) >= ceiling(n / h)*h - n, Δ = ceiling(n / h)*h - n.

[0057] Combined with the eighth possible implementation manner of the seventh aspect, in the ninth possible implementation manner of the seventh aspect, the set of column coordinates Col_str of the mirror check bits of the codewords in the first frame is shown as follows:

[0058] Col_str_vec(i, :) = [i_base(i) - Range(i) + 1:i_base(i)], 0 <= i <= h - 1;

[0059] Among them, if i < ceiling(n / h)*h - n, i_base(i) = (i + 1)*ceiling(n / h) - i - 2; if i >= ceiling(n / h)*h - n, i_base(i) = (i + 1)*ceiling(n / h) - ceiling(n / h)*h - n - 1; Range(i) = ceiling((p - i) / h) ROR (ceiling(n / h)*h - n), where ROR is the circular right shift of the array.

[0060] In combination with the eighth or ninth possible implementation of the seventh aspect, in a tenth possible implementation of the seventh aspect, the first codeword is a BCH (720, 700) code, h=5, p_word=64, then the three function expressions of Φf(), Φr() and Φc() are as follows:

[0061] Φf([Frame,Row_str,Col_str])=Frame-1-frm_map(floor((Col_str) / 72)),

[0062]

[0063] Φc([Frame,Row_str,Col_str])=360+5*((Col_str)%72)+(4−floor((Col_str) / 72)), where frm_map(i)=4−i, i∈[0,4], and i is an integer.

[0064] In combination with the tenth possible implementation manner of the seventh aspect, in an eleventh possible implementation manner of the seventh aspect, a set of column coordinates Col_str of the mirror check bits of the codeword in the first frame is as follows:

[0065] Col_str_vec(i,:)={[68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359]}.

[0066] In combination with the seventh possible implementation manner of the seventh aspect, in a twelfth possible implementation manner of the seventh aspect, the frame coordinate Frame', the row coordinate Row_str' and the column coordinate Col_str' of the bits in the h second frames are obtained by the following formula:

[0067] Frame'=Frame+1+frm_map(Col_str%h);

[0068] Col_str'=(h–1–Col_str%h)*ceiling(n / h)+floor(Col_str / h)–Δ;

[0069]

[0070] Among them, the frame coordinate Frame, row coordinate Row_str, and column coordinate Col_str of the mirror bits of the codeword in the first frame are all integers, and Frame ∈ (-∞, +∞), Row_str ∈ [0, p_word - 1], Col_str ∈ [0, 2n - 1]; frm_map(i) = i, i ∈ [0, h - 1], and i is an integer;

[0071] If n / h is an integer, Δ = 0; otherwise, if Col_str / floor(n / h) < ceiling(n / h)*h - n, Δ = floor(Col_str / floor(n / h)); if Col_str / floor(n / h) >= ceiling(n / h)*h - n, Δ = ceiling(n / h)*h - n.

[0072] Combined with the twelfth possible implementation manner of the seventh aspect, in the thirteenth possible implementation manner of the seventh aspect, the first codeword is a BCH(720, 700) code, h = 5, p_word = 64, then: Frame’ = Frame + 1 + frm_map(Col_str % 5);

[0073] Col_str’ = (4 – Col_str % 5)*72 + floor(Col_str / 5);

[0074] Among them, frm_map(i) = i, i ∈ [0, 4].

[0075] Combined with any possible implementation manner of the seventh aspect, in the fourteenth possible implementation manner of the seventh aspect, the method further includes: storing the n bits to be transmitted for use when encoding the codewords after the first codeword.

[0076] Combined with any possible implementation manner of the seventh aspect, in the fifteenth possible implementation manner of the seventh aspect, the n bits sent out in the first codeword are shared with some codewords formed after the first codeword.

[0077] Combined with any possible implementation manner of the seventh aspect, in the sixteenth possible implementation manner of the seventh aspect, each bit in the first codeword is adopted by at least two codewords.

[0078] Combined with any possible implementation manner of the seventh aspect, in the seventeenth possible implementation manner of the seventh aspect, the first codeword is a BCH(720, 700) code.

[0079] In an eighth aspect, a coding device is provided, comprising a coding unit and a sending unit, the coding unit being used to form a first codeword, the first codeword comprising n mirror bits and n bits to be transmitted, and the n mirror bits are selected from the bits to be transmitted of m source codewords, wherein the source codeword is a codeword formed before the first codeword, n and m are both positive integers, and n>m; the sending unit is used to send out the n bits to be transmitted in the first codeword.

[0080] In the embodiment of the present application, the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can improve the decoding speed of the decoder and play a role in reducing latency.

[0081] In combination with the eighth aspect, in a first possible implementation of the eighth aspect, the n bits to be transmitted include p check bits and np information bits, wherein the p check bits are encoded by the n mirror bits and the np information bits, and p is a positive integer less than n.

[0082] In combination with the first possible implementation manner of the eighth aspect, in a second possible implementation manner of the eighth aspect, the n mirror bits include mirror check bits and mirror information bits, wherein the mirror check bits are selected from the check bits of the m source codewords, and the mirror information bits are selected from the information bits of the m source codewords.

[0083] In combination with the second possible implementation manner of the eighth aspect, in a third possible implementation manner of the eighth aspect, the number of the mirror check bits and the number of the check bits are the same.

[0084] In combination with any possible implementation of the eighth aspect, in a fourth possible implementation of the eighth aspect, among the m source code words, the maximum value of the difference in the number of bits provided to the first code word by different source code words is greater than one bit.

[0085] In combination with any possible implementation of the eighth aspect, in a fifth possible implementation of the eighth aspect, the code length of the first codeword is not greater than 2048, and the number of error correction bits is not greater than 5.

[0086] In combination with any possible implementation manner of the eighth aspect, in a sixth possible implementation manner of the eighth aspect, among the m source codewords, the number of bits provided by at least one source codeword to the first codeword is different from the number of bits provided by other source codewords to the first codeword; or

[0087] Each source code word provides q bits to the first code word, where q is an integer greater than 1, and n is an integer multiple of m.

[0088] Combined with any possible implementation manner of the eighth aspect, in the seventh possible implementation manner of the eighth aspect, p_word of the first code words form a first frame, and the mirror bits of the code words in the first frame come from the bits to be transmitted of the code words in h second frames generated before the first frame, where both h and p_word are positive integers greater than 1.

[0089] Combined with the seventh possible implementation manner of the eighth aspect, in the eighth possible implementation manner of the eighth aspect, the frame coordinates, row coordinates, and column coordinates of the bits in the h second frames are calculated through three functions Φf(), Φr(), and Φc():

[0090] Φf([Frame,Row_str,Col_str]) = Frame - 1 - frm_map(floor((Col_str + Δ) / ceiling(n / h)));

[0091]

[0092] Φc([Frame,Row_str,Col_str]) = n + h*((Col_str + Δ) % ceiling(n / h)) + (h - 1 - floor((Col_str + Δ) / ceiling(n / h))).

[0093] Among them, the frame coordinate Frame, row coordinate Row_str, and column coordinate Col_str of the mirror bits of the code words in the first frame are all integers, and Frame ∈ (-∞, +∞), Row_str ∈ [0, p_word - 1], Col_str ∈ [0, 2n - 1]; frm_map(i) = h - 1 - i, i ∈ [0, h - 1]; if n / h is an integer, Δ = 0; otherwise, if Col_str / floor(n / h) < ceiling(n / h)*h - n, Δ = floor(Col_str / floor(n / h)); if Col_str / floor(n / h) >= ceiling(n / h)*h - n, Δ = ceiling(n / h)*h - n.

[0094] Combined with the eighth possible implementation manner of the eighth aspect, in the ninth possible implementation manner of the eighth aspect, the set of column coordinates Col_str of the mirror check bits of the code words in the first frame is as follows:

[0095] Col_str_vec(i, :) = [i_base(i) - Range(i) + 1:i_base(i)], 0 <= i <= h - 1;

[0096] where, if i < ceiling(n / h) * h - n, i_base(i) = (i + 1) * ceiling(n / h) - i - 2; if i >= ceiling(n / h) * h - n, i_base(i) = (i + 1) * ceiling(n / h) - ceiling(n / h) * h - n - 1; Range(i) = ceiling((p - i) / h) ROR (ceiling(n / h) * h - n), ROR is the right circular shift of the array.

[0097] Combined with the eighth or ninth possible implementation manner of the eighth aspect, in the tenth possible implementation manner of the eighth aspect, the first codeword is a BCH(720, 700) code, h = 5, p_word = 64, then the three function expressions of Φf(), Φr() and Φc() are as follows:

[0098] Φf([Frame, Row_str, Col_str]) = Frame - 1 - frm_map(floor((Col_str) / 72)),

[0099]

[0100] Φc([Frame, Row_str, Col_str]) = 360 + 5 * ((Col_str) % 72) + (4 – floor((Col_str) / 72)), where, frm_map(i) = 4 - i, i ∈ [0, 4], and i is an integer.

[0101] Combined with the tenth possible implementation manner of the eighth aspect, in the eleventh possible implementation manner of the eighth aspect, the set of column coordinates Col_str of the mirror parity bits of the codewords in the first frame is as follows:

[0102] Col_str_vec(i, :) = {[68, 69, 70, 71], [140, 141, 142, 143], [212, 213, 214, 215], [284, 285, 286, 287], [356, 357, 358, 359]}.

[0103] Combined with the seventh possible implementation manner of the eighth aspect, in the twelfth possible implementation manner of the eighth aspect, the frame coordinates Frame’, row coordinates Row_str’ and column coordinates Col_str’ of the bits in the h second frames are obtained by the following formula:

[0104] Frame’ = Frame + 1 + frm_map(Col_str % h);

[0105] Col_str’ = (h - 1 - Col_str % h) * ceiling(n / h) + floor(Col_str / h) - Δ;

[0106]

[0107] Among them, the frame coordinate Frame, row coordinate Row_str, and column coordinate Col_str of the mirror bits of the codewords in the first frame are all integers, and Frame ∈ (-∞, +∞), Row_str ∈ [0, p_word - 1], Col_str ∈ [0, 2n - 1]; frm_map(i) = i, i ∈ [0, h - 1], and i is an integer;

[0108] If n / h is an integer, Δ = 0; otherwise, if Col_str / floor(n / h) < ceiling(n / h) * h - n, Δ = floor(Col_str / floor(n / h)); if Col_str / floor(n / h) >= ceiling(n / h) * h - n, Δ = ceiling(n / h) * h - n.

[0109] Combined with the twelfth possible implementation manner of the eighth aspect, in the thirteenth possible implementation manner of the eighth aspect, the first codeword is a BCH(720, 700) code, h = 5, p_word = 64, then: Frame’ = Frame + 1 + frm_map(Col_str % 5);

[0110] Col_str’ = (4 - Col_str % 5) * 72 + floor(Col_str / 5);

[0111] Among them, frm_map(i) = i, i ∈ [0, 4].

[0112] Combined with any possible implementation manner of the eighth aspect, in the fourteenth possible implementation manner of the eighth aspect, the method further includes: storing the n bits to be transmitted for use when encoding the codewords after the first codeword.

[0113] Combined with any possible implementation manner of the eighth aspect, in the fifteenth possible implementation manner of the eighth aspect, the n bits sent out in the first codeword are shared with some codewords formed after the first codeword.

[0114] In combination with any possible implementation manner of the eighth aspect, in a sixteenth possible implementation manner of the eighth aspect, each bit in the first codeword is adopted by at least two codewords.

[0115] In combination with any possible implementation manner of the eighth aspect, in a seventeenth possible implementation manner of the eighth aspect, the first codeword is a BCH (720, 700) code.

[0116] In the ninth aspect, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores instructions, and when the instructions are executed on a terminal device, the terminal device executes the method as described in the first aspect or any possible implementation of the first aspect; or the terminal device executes the method as described in the third aspect or any possible implementation of the third aspect; or the terminal device executes the method as described in the seventh aspect or any possible implementation of the seventh aspect.

[0117] In a tenth aspect, a computer program product including instructions is provided, which, when executed on a terminal device, enables the terminal device to execute the method described in the first aspect or any possible implementation of the first aspect; or enables the terminal device to execute the method described in the third aspect or any possible implementation of the third aspect; or enables the terminal device to execute the method described in the seventh aspect or any possible implementation of the seventh aspect. It should be understood that the terminal device may be a chip, a processor, etc., and this application does not limit this.

[0118] In an eleventh aspect, a cascade coding method based on data communication is provided, the method comprising: receiving data bits, performing KP4 coding on the data bits to obtain a KP4 codeword; interleaving the KP4 codeword to obtain an interleaved codeword; encoding the interleaved codeword according to the coding method described in the seventh aspect or any possible implementation of the seventh aspect, wherein the interleaved codeword is not decoded before being encoded as described in the seventh aspect or any possible implementation of the seventh aspect. In this embodiment, the interleaved KP4 codeword does not need to be decoded, and the next step of cascade coding is directly performed, which can reduce power consumption.

[0119] In a twelfth aspect, a cascade coding device based on data communication is provided, the cascade coding device comprising: a first coding unit, an interleaving unit and a second coding unit; the first coding unit is used to receive data bits, perform KP4 encoding on the data bits, and send the obtained KP4 codeword to the interleaving unit; the interleaving unit is used to interleave the KP4 codeword and send the interleaved codeword to the second coding unit; the second coding unit is used to encode the interleaved codeword according to the encoding method described in the seventh aspect or any possible implementation of the seventh aspect, wherein the second coding unit does not decode the interleaved codeword. In this embodiment, the interleaved KP4 codeword does not need to be decoded, and the next step of cascade coding is directly performed, which can reduce power consumption.

[0120] In the above embodiment of the present application, the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can improve the decoding speed of the decoder and play a role in reducing the delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0121] Figure 1 It is the structural block diagram of the communication system;

[0122] Figure 2 Flowchart of the encoding method provided for this application;

[0123] Figure 3 A schematic diagram of a codeword sharing rule provided in an embodiment of the present application;

[0124] Figure 4 A schematic diagram of a codeword sharing rule provided in another embodiment of the present application;

[0125] Figure 5 A schematic diagram of a codeword sharing rule provided in another embodiment of the present application;

[0126] Figure 6 A schematic diagram of a storage method of an FEC frame provided in another embodiment of the present application;

[0127] Figure 7 A diagram showing a composition method of bits to be supplemented in an FEC frame provided in another embodiment of the present application;

[0128] Figure 8 A sharing rule diagram of a column of bits to be supplemented in an FEC frame provided by another embodiment of the present application;

[0129] Fig. 9 A flowchart of a decoding method provided by another embodiment of the present application;

[0130] Fig.10 A diagram of an encoding device provided by another embodiment of the present application;

[0131] Fig.11 A diagram of a decoding device provided by another embodiment of the present application;

[0132] Fig.12 A diagram of an encoding device provided by another embodiment of the present application;

[0133] Fig.13 A diagram of a decoding device provided by another embodiment of the present application;

[0134] Fig.14 A structural diagram of a high-speed transmission system provided by another embodiment of the present application;

[0135] Fig.15 A structural diagram of an 800G transmission system provided in another embodiment of the present application;

[0136] Fig.16 A simulation result diagram of the coding scheme provided in this application applied to an 800G transmission system;

[0137] FIG. 17( a ) is a schematic diagram of a codeword structure provided in another embodiment of the present application;

[0138] FIG. 17( b ) is a schematic diagram of an FEC frame structure provided in another embodiment of the present application;

[0139] Fig.18 A schematic diagram of a codeword sharing rule is provided for another embodiment of the present application;

[0140] Fig.19 A schematic diagram of an interleaving scheme provided for another embodiment of the present application;

[0141] Fig. 20 A schematic diagram of a specific FEC frame interleaving scheme provided in another embodiment of the present application;

[0142] Fig.21 A schematic diagram of a specific FEC frame interleaving scheme provided in another embodiment of the present application;

[0143] Fig. 22 A schematic diagram of a specific FEC frame interleaving scheme provided in another embodiment of the present application;

[0144] Fig.23 A coding architecture diagram of an FEC frame provided in another embodiment of the present application;

[0145] Fig.24 To utilize Fig.23 The schematic diagram of the coding architecture shown generates the mirror bits of the current frame;

[0146] Fig.25 A schematic diagram of a specific FEC frame interleaving scheme provided in another embodiment of the present application;

[0147] Fig.26 A schematic diagram of a specific FEC frame interleaving scheme provided in another embodiment of the present application;

[0148] Fig. 27 A schematic diagram of a specific FEC frame interleaving scheme provided for another embodiment of the present application. DETAILED DESCRIPTION

[0149] Before explaining the embodiments of the present application in detail, the application scenarios of the embodiments of the present application are first described. Figure 1 The structure block diagram of the communication system is shown. At the transmitting end, the source provides a data stream to be sent; the encoder receives the data stream and encodes it, and the codeword information obtained by encoding the check bits and information bits is sent, which is transmitted through the channel to the receiving end; after the receiving end receives the erroneous codeword information caused by noise or other damage in the channel, it is decoded by the decoder to restore the original data and send it to the destination. Among them, the encoding method provided by the present application is applied to Figure 1 The encoder shown is a very important part of the communication system.

[0150] The data sent from the source will continuously form multiple codewords consisting of data bits and check bits after passing through the encoder using this coding scheme, forming a codeword stream, wherein the generated codewords will share bits with the codewords generated before or after, so that the bits in the codewords are protected by codewords generated at multiple different times, and better coding gain can be obtained.

[0151] The present application provides a coding method for data communication, such as Figure 2 As shown, including:

[0152] 201. Form a first codeword, the first codeword including 2n bits, formed by k coding bits, and the n bits of the first codeword come from m codewords formed before the first codeword, and the other n bits in the first codeword include kn information bits and 2n-k check bits, wherein n, m, and k are all positive integers, and 2n>k>n>m;

[0153] 202. Send the other n bits in the first codeword.

[0154] It should be understood that in this embodiment, before the first codeword is formed, at least m codewords have been generated; half of the bits in the first codeword come from the previously formed m codewords, that is, this half of the bits are composed of several bits from each of the m codewords, and are shared with the previous m codewords; and the remaining kn bits are information bits at the current moment, and according to the n bits shared from the previously formed m codewords and the kn information bits at the current moment, 2n-k check bits are obtained after encoding, thereby forming the first codeword. Since n bits in the first codeword have been sent in the previously formed codeword and do not need to be sent again, the other n bits in the first codeword are sent out, that is, the remaining kn information bits and the newly generated 2n-k check bits constitute the codeword to be transmitted, and the codeword to be transmitted is sent out.

[0155] Generally speaking, the first codeword shares bits with a previously formed codeword and a subsequently formed codeword; in the first codeword, each bit is located in at least one previously formed or subsequently formed codeword. In addition, in some embodiments, at least some of the k coded bits of the first codeword are data bits of other codewords, and at least some of the k coded bits are check bits of other codewords. In an embodiment of the present application, the bits involved in the codeword encoding are coded bits, the bits to be transmitted received at the current moment are information bits, and among the k coded bits, there are n bits that are shared with the previous codeword, and the remaining kn bits are information bits to be transmitted at the current moment.

[0156] Normally, in the generated codeword stream, the initial part of the codewords needs to include padding bits, such as padding with a full 0 bit sequence, until a sufficient number of codewords are formed, which can provide sufficient shared bits for subsequent codewords. For example, as described in the embodiment of the present application, the codeword includes 2n bits, half of which are shared with the bits of the m codewords formed previously, that is, the bits in the previous codeword will be used as the coding bits of the current codeword; at this time, in the initial m codewords, since there are no m previous codewords, it is impossible to obtain enough coding bits from the previous codewords, therefore, it is necessary to add some padding bits to the codewords to complete the number of coding bits in order to generate check bits and form the first codeword. It should be understood that in the initial m codewords, except for the first codeword, other codewords can share a part of the bits from the previous codeword and then fill the remaining bits; or they may not be shared with the previous codeword, and the missing coding bits are all replaced by padding bits, which is not limited in the present application.

[0157] Furthermore, the other n bits need to be stored for use in encoding code words subsequent to the first code word.

[0158] In the embodiment of the present application, the n bits of the first codeword are shared with m codewords formed before the first codeword, and since n is greater than m, there will always be a codeword among the m codewords that shares multiple bits with the first codeword. There are multiple specific sharing rules, which are described as follows:

[0159] (1) n is an integer multiple of m, and each of the m codewords shares the same number of bits with the first codeword. Figure 3 is a schematic diagram of a specific codeword sharing rule provided according to this solution. Figure 3 In the example, each codeword is 16 bits long, including 14 coded bits (D in the figure) and 2 check bits (P in the figure). Of the 14 coded bits, 8 bits (half of the codeword length) come from the 4 previously formed codewords, each of which takes 2 bits. Figure 3 The codeword surrounded by the solid line in is the codeword X, of which 2 bits come from the codeword X-1, 2 bits come from the codeword X-2, and 2 bits come from X-3. These 6 bits are all information bits in the previous codeword, and 2 bits come from X-4. These 2 bits are check bits in the previous codeword. The remaining 6 information bits in the codeword X are the information bits to be transmitted at the current moment. The 8 bits from the previous codeword and the 6 bits at the current moment are encoded to obtain 2 check bits, thereby forming a codeword X with a length of 16 bits.

[0160] Similarly, the next codeword X+1 of codeword X is Figure 3 In the part surrounded by the dotted line, the code word X+1 includes 16 bits, of which 2 bits come from the code word X, 2 bits come from the code word X-1, and 2 bits come from X-2. These 6 bits are also the information bits of the previous code word. The remaining 2 bits come from X-3, which are the check bits of the previous code word. The remaining 6 bits are the information bits to be transmitted at the current moment. The 8 bits from the previous code word and the 6 bits at the current moment are encoded to obtain 2 check bits, forming a code word X+1 with a length of 16 bits.

[0161] In the codeword stream disclosed in this embodiment, except for the initial 4 bits and the last 4 bits (m=4), in all the intermediate codewords, each codeword has half of its bits shared with the previous codeword and half of its bits shared with the subsequent codeword, so that the bits in the codeword are protected by codewords generated at multiple different times, and better coding gain can be obtained; and the number of bits shared by each codeword with other codewords is 2. As the number of bits shared between two codewords increases, the number of codewords that need to be shared decreases, and the data collection and decoding process can be quickly completed at the receiving end, thereby reducing latency. Of course, the number of shared bits can be further increased, and this application does not limit it.

[0162] (2) Among the m previously formed codewords, there is at least one codeword that shares a different number of bits with the first codeword than the number of bits shared with the first codeword by the other codewords. For example, assuming n = 9 and m = 4, there is one codeword that shares 3 bits with the first codeword, and the remaining three codewords all share 2 bits with the first codeword; or, one codeword shares 1 bit with the first codeword, another codeword shares 2 bits with the first codeword, and the remaining two codewords all share 3 bits with the first codeword.

[0163] Figure 4 A schematic diagram of a specific codeword sharing rule provided according to this solution is shown in FIG. Figure 4 In the example, each codeword is also 16 bits long, including 14 coded bits (D in the figure) and 2 check bits (P in the figure). Of the 14 coded bits, 8 bits (half of the codeword length) come from the 6 codewords formed previously. The number of bits obtained from each codeword is as follows: Figure 4 As shown, for example Figure 4 The code word X surrounded by solid lines in the figure has 2 bits from code word X-1, 1 bit from code word X-2, 1 bit from code word X-3, and 2 bits from code word X-4. These 6 bits are all information bits in the previous code word. The remaining 2 bits are check bits in the previous code word, one bit from code word X-5, and the other bit from code word X-6. The remaining 6 bits in code word X are the information bits to be transmitted at the current moment. The 8 bits from the previous code word and the 6 bits at the current moment are encoded to obtain 2 check bits, thus forming a code word X with a length of 16 bits. Similarly, the subsequent code word X+1 of code word X, such as Figure 4 The portion surrounded by the dotted line is similar to the codeword X and will not be described in detail in this application.

[0164] In addition, when n is an integer multiple of m, there may also be a situation where the number of bits shared by at least one codeword with the first codeword is different from the number of bits shared by other codewords with the first codeword; for example, n=8, m=4, one codeword shares 5 bits with the first codeword, and the remaining codewords each share 1 bit, or two codewords share 3 bits with the first codeword, and the other two codewords share 1 bit with the first codeword.

[0165] Figure 5 Another specific codeword sharing rule diagram provided according to this solution is shown in FIG. Figure 5 In the example, each codeword is also 16 bits long, including 14 coded bits (D in the figure) and 2 check bits (P in the figure). Of the 14 coded bits, 8 bits (half of the codeword length) come from the 4 codewords formed previously. The number of bits obtained from each codeword is as follows: Figure 5 As shown, for example Figure 4The code word X surrounded by solid lines in the figure has 3 bits from code word X-1, 1 bit from code word X-2, 3 bits from code word X-3, and 1 bit from code word X-4. These 8 bits include 6 information bits from the previous code words and 2 check bits from the previous code words. The remaining 6 bits in code word X are the information bits to be transmitted at the current moment. The 8 bits from the previous code words and the 6 bits at the current moment are encoded to obtain 2 check bits, thus forming a code word X with a length of 16 bits. Similarly, the subsequent code word X+1, such as Figure 4 The portion surrounded by the dotted line is similar to the codeword X and will not be described in detail in this application.

[0166] In the codeword stream disclosed in this embodiment, the initial m bits and the final m bits ( Figure 4 m=6, Figure 5 m=4), among all the codewords in the middle, half of the bits of each codeword are shared with the previous codeword, and half of the bits are shared with the subsequent codeword, so that the bits in the codeword are protected by multiple codewords generated at different times, and better coding gain can be obtained. In addition, the number of bits shared between codewords at different times is different, so that the bits in the codeword are protected by different numbers of codewords. The bits protected by more codewords converge faster, and then drive the bits protected by fewer codewords to converge, thereby improving the convergence speed of the decoder and playing a role in reducing latency. It should be understood that Figure 4 and Figure 5 Only two different bit sharing methods are provided. There are other sharing methods, which are not limited in this application.

[0167] Optionally, among the m previously formed codewords, a maximum value of a difference in the number of bits provided by different codewords to the first codeword is greater than one bit, which can further improve error correction performance while maintaining low latency.

[0168] It can be seen from the above two different embodiments that, except for the initial and ending codewords, half of the bits of all the intermediate codewords come from the previously formed codewords, and the role of this half bit is to participate in the generation of the check bit together with the information bit at the current moment, and this half bit itself does not participate in the transmission of the current codeword. The information bit at the current moment and the check bit generated by the encoding constitute the other half of the codeword, which is the bit to be transmitted and is shared with the subsequently formed codeword.

[0169] Take the first codeword as Bose-Chaudhuri-Hocquenghem (BCH) code, whose bit number is 720 as an example, 360 bits come from the previously formed codeword, 340 bits are information bits in the current codeword, and a total of 700 coded bits are encoded according to the generating polynomial corresponding to BCH (720, 700), and 20 check bits can be obtained; wherein, the 360 ​​bits from the previously formed codeword do not participate in data transmission, and the 340 current information bits and 20 check bits together constitute a 360-bit BCH codeword to be transmitted. It should be understood that BCH (720, 700) is obtained by shortening BCH (1023, 1003) by 303 bits. The specific shortening method can be to remove the 303 high bits, or to remove the 303 low bits, or other methods, which are not limited in this application.

[0170] Another embodiment of the present application further provides a method for encoding an FEC frame, wherein the FEC frame includes Num codewords to be transmitted as described in the previous embodiment, which can be referred to as Figure 6 The code is stored in the memory in the manner shown, each column is a code word to be transmitted, and Num is a positive integer greater than 1.

[0171] When encoding and generating an FEC frame at a certain moment, according to the previous embodiment, each codeword to be transmitted (the codeword to be transmitted includes n bits) needs to be supplemented with n bits. The n bits come from some codewords formed previously. In this embodiment, the supplemented bits are recorded as Info_Pad. Therefore, it is necessary to supplement n rows and Num columns of Info_Pad to generate an FEC frame. Assuming that Info_Pad comes from T FEC frames formed previously, the bits of Info_Pad can be represented by (Row_Inf, Col_Inf), where Row_Inf is the row number of Info_Pad, which is any value from 0, 1, 2... n-1; Col_Inf is the column number of Info_Pad, which is any value from 0, 1, 2... Num-1. The bits of the T FEC frames formed previously are represented by (Frame, Row_str, Col_str), where Frame is the number of the FEC frame, which is 0, 1, 2... Any value in T-1, frame 0 is the FEC frame generated at the previous moment, frame 1 is the FEC frame generated at the previous moment, and so on; Row_str is the row number of the FEC frame, which is 0, 1, 2... Any value in n-1; Col_str is the column number of the FEC frame, which is 0, 1, 2... Any value in Num-1. At this time, the correspondence between each bit in Info_Pad and the bit of the previously formed FEC frame can be calculated according to the following formula:

[0172] Frame = floor ((Intial_Row+Row_skip*Row_Inf) / n) (1)

[0173] Row_str = (Intial_Row+Row_skip*Row_Inf + floor(Row_skip*Row_Inf / n))% n (2)

[0174] Col_str = (Col_Inf+Row_Inf) % Num (3)

[0175] Among them, Intial_Row represents the row number of the first row of bits shared with Info_Pad in T FEC frames, and Row_skip represents the number of rows in T FEC frames in which a row of bits is selected to be shared with Info_Pad. It should be noted that Intial_Row is an integer not less than 0, Row_skip is a positive integer, and Intial_Row+Row_skip*(n-1) cannot exceed the value of n*(T-1).

[0176] The T FEC frames formed before the current moment mentioned here can be T FEC frames at any previous moment. For example, FEC frames at T consecutive moments before the current moment, or T consecutive FEC frames after a fixed time interval from the current moment, or FEC frames at any T discontinuous moments before the current moment, which is not limited in this application.

[0177] Specifically, the following describes a specific way of constructing Info_Pad, taking the codeword to be transmitted as BCH (360, 340) and the FEC frame including 64 codewords to be transmitted as an example, wherein generating the FEC frame requires additional Info_Pad of 360 rows and 64 columns. Assuming that the Info_Pad comes from the 4 FEC frames formed previously, with a total of 256 codewords, the way of constructing Info_Pad is as follows: Figure 7 As shown, at this time, the row number Row_Inf of Info_Pad is any value among 0, 1, 2...359, and the column number Col_Inf of Info_Pad is any value among 0, 1, 2...63; the number Frame of the FEC frame is any value among 0, 1, 2, 3, the row number Row_str of the FEC frame is any value among 0, 1, 2...359, and the column number Col_str of the FEC frame is any value among 0, 1, 2...63.

[0178] exist Figure 7In the configuration shown, the initial row number is 0, and one row of bits is selected every 4 rows to share with Info_Pad, that is, Initial_Row = 0, Row_skip = 4, then the formula for the corresponding relationship between each bit in Info_Pad and the bit of the previously formed FEC frame can be simplified as follows:

[0179] Frame = floor (Row_Inf / 90) (4)

[0180] Row_str = (4*Row_Inf + floor (Row_Inf / 90) % 360 (5)

[0181] Col_str = (Col_Inf+Row_Inf) % 64 (6)

[0182] Combining the above formulas (4) and (5), and Figure 7 It can be seen that when Row_Inf=0, Frame=0, Row_str=0, that is, row 0 of Info_Pad corresponds to row 0 of frame 0 of the 4 FEC frames formed previously; when Row_Inf=89, Frame=0, Row_str=356, that is, row 89 of Info_Pad corresponds to row 356 of frame 0 of the 4 FEC frames formed previously; when Row_Inf=90, Frame=1, Row_str=1, that is, row 90 of Info_Pad corresponds to row 1 of frame 1 of the 4 FEC frames formed previously.

[0183] After determining which row in which frame each row in Info_Pad corresponds to according to formulas (4) and (5), it is possible to determine which bit in the corresponding row of the corresponding FEC frame any bit in a row of Info_Pad shares with according to formula (6). For example, when Row_Inf=0, Col_str=Col_Inf, that is, in the 0th row of Info_Pad, the 0th bit is shared with the 0th bit of the corresponding row, the 1st bit is shared with the 1st bit of the corresponding row, and so on; when Row_Inf=1, Col_str=Col_Inf+1, that is, in the 1st row of Info_Pad, the 0th bit is shared with the 1st bit of the corresponding row, the 1st bit is shared with the 2nd bit of the corresponding row, and so on; when Row_Inf=64, Col_str=Col_Inf, that is, in the 64th row of Info_Pad, the 0th bit is shared with the 0th bit of the corresponding row, and the 1st bit is shared with the 1st bit of the corresponding row, wherein the sharing relationship of the 64th row of Info_Pad is consistent with the sharing relationship of the 0th row of Info_Pad.

[0184] In summary, formula (6) gives the interleaving relationship between each row of Info_Pad and the corresponding row in the previous FEC frame, and the period of row interleaving is 64, and the interleaving relationship will be repeated every 64 rows. For example, in rows 0-63 of Info_Pad, the interleaving relationship between each row and the corresponding row of the previous FEC frame is different, but starting from row 64, the interleaving relationship begins to repeat, for example, the interleaving relationship between row 0 and row 64 of Info_Pad is the same, and the interleaving relationship between row 1 and row 65 is the same, and so on. It should be understood that other row interleaving relationships can also be used, for example, interleaving calculations are performed according to Galois Field (GF).

[0185] In this embodiment, every 5760 bits (90 rows×64 columns) of Info_Pad are from a previously formed FEC frame, and the period of row interleaving is 64. Therefore, among the 90 rows of bits, 26 rows of bits can only reuse the interleaving relationship used by other rows. Figure 8 The sharing relationship between the 90 bits included in the first column of Info_Pad and the bits in the corresponding FEC frame is given. Figure 8 The solid blocks in the FEC frame represent the bit positions shared with the first column of Info_Pad in the FEC frame. The sharing relationship satisfies the conditions of formulas (5) and (6). For example, Info_Pad (0, 0) and Figure 8 The bits at the solid block (0,0) are shared, and Info_Pad (1,0) is shared with Figure 8The bits at the solid block (4, 1) are shared, and the Info_Pad (2, 0) is shared with Figure 8 The bits at the solid block (8, 2) are shared, and Info_Pad (64, 0) is shared with Figure 8 The bits at the solid block (256, 0) are shared, and Info_Pad (89, 0) is shared with Figure 8 The bits at position (356, 25) in the solid block are shared, where (a, b) represents the ath row and the bth column.

[0186] from Figure 8 It can be seen that in the FEC frame, columns 0-25 share two bits with column 0 of Info_Pad, and columns 26-63 share one bit with column 0 of Info_Pad. Similarly, it can be deduced that the 90 bits included in each column of Info_Pad share two bits with each of the 26 previously formed codewords to be transmitted, and share one bit with each of the other 38 previously formed codewords to be transmitted. Since each column of Info_Pad includes 360 bits, and every 90 rows corresponds to a previously formed FEC frame, each column of Info_Pad shares two bits with each of the 104 (26×4=104) previously formed codewords to be transmitted, and shares one bit with each of the other 152 (38×4=152) previously formed codewords to be transmitted.

[0187] To summarize, in the process of encoding and generating the FEC frame to be transmitted, taking the generation of the first column of bits in the FEC frame to be transmitted (the first column of bits is recorded as the first codeword to be transmitted) as an example, the generation of the first codeword to be transmitted is related to the first column of bits of Info_Pad and the 340 current information bits received, that is, according to the generating polynomial corresponding to BCH (720, 700), the 360 ​​bits included in the first column of Info_Pad are encoded together with the 340 current information bits received to generate 20 check bits, wherein the 340 current information bits and the generated 20 check bits constitute the first codeword to be transmitted; and so on, 64 codewords to be transmitted can be encoded, which together constitute the currently encoded FEC frame.

[0188] In short, the encoding process of FEC frame is as follows:

[0189] First, receiving information bits to be transmitted. In this embodiment, the number of information bits to be transmitted is 340;

[0190] Secondly, through the method provided in this embodiment, 360 bits are obtained from the 256 code words formed previously;

[0191] Again, the 360 ​​bits are encoded together with the received 340 bits to generate 20 check bits, and the received 340 bits and the generated 20 bits are sent out, wherein the received 340 bits and the generated 20 check bits constitute the first codeword to be transmitted, and the 64 first codewords to be transmitted constitute the FEC frame;

[0192] In the actual encoding process, encoding can be performed by one encoder or by multiple encoders in parallel. For example, 8 encoders encode in parallel to obtain 8 codewords to be transmitted, which are then converted into a bit stream and sent out.

[0193] It should be understood that the codeword to be transmitted is BCH (360, 340) is only a possible embodiment, and it can also be other lengths, for example, BCH (510, 490), BCH (256, 238), etc., and different encoding rules such as Hamming code, Reed-Solomon (RS) code, etc. can also be used. This application does not limit this.

[0194] By adopting the coding method disclosed in this embodiment, the bits in the codewords to be transmitted included in each FEC frame will be protected by the codewords to be transmitted included in multiple FEC frames generated at different times, and better coding gain can be obtained. Moreover, the number of bits shared between different codewords is different, and the codewords that share more bits have a faster convergence speed, which can then drive the convergence of the remaining codewords, thereby improving the convergence speed of the decoder and reducing the delay.

[0195] The present application provides a decoding method for data communication, such as Fig. 9 As shown, including:

[0196] 901. Recover a first codeword; wherein the first codeword includes 2n bits, which are formed by k coded bits, and the n bits of the first codeword come from m codewords decoded before the first codeword, and the other n bits in the first codeword include kn information bits and 2n-k check bits, wherein n, m, and k are all positive integers, and 2n>k>n>m;

[0197] 902. Decode the first codeword to obtain decoded bits.

[0198] It should be understood that in this embodiment, before the first codeword is recovered, at least m codewords have been decoded; half of the bits in the first codeword come from the m previously decoded codewords, and the other n bits are the bit stream received at the current moment. Generally speaking, the first codeword shares bits with previously decoded codewords and subsequently decoded codewords; in the first codeword, each bit is located in at least one previously decoded or subsequently decoded codeword. In addition, in some embodiments, at least some of the k coded bits of the first codeword are data bits of other codewords, and at least some of the k coded bits are check bits of other codewords.

[0199] Normally, in the received codeword stream, the initial part of the codewords needs to include padding bits, such as padding with a full 0 bit sequence, until a sufficient number of codewords are decoded. For example, as described in the embodiment of the present application, when the initial m codewords are received, since there are no m previously decoded codewords, it is impossible to obtain enough coding bits from the previously decoded codewords. Therefore, it is necessary to add some padding bits to the codewords to complete the number of coding bits for decoding. It should be understood that, in the initial m codewords received, except for the first codeword, other codewords can share a part of the bits from the previously decoded codewords and then fill the remaining bits; or they may not be shared with the previously decoded codewords, and the missing coding bits are all replaced by padding bits, which is not limited in the present application. In addition, regarding whether the padding bits use a full 0 bit sequence or other forms of bit sequences, the decoding end should be consistent with the encoding end to facilitate correct decoding.

[0200] In the embodiment of the present application, some of the error bits in the previously decoded codeword have been corrected. After forming a codeword with the bits received at the current moment, it is equivalent to reducing the number of error bits in the composed codeword, which can increase the probability of correct decoding. Furthermore, after this decoding, in addition to correcting the newly received bit errors at the current moment, the remaining errors in the previous codeword can also be corrected to improve the error correction capability. In addition, the number of bits shared between different codewords is different. There are multiple codewords that share more than one bit. The more bits are shared, the fewer codewords need to be associated, and decoding can be done without waiting too long, thereby reducing system latency.

[0201] Another embodiment of the present application provides a coding device for data communication, such as Fig.10As shown, it includes a coding unit 1001 and a sending unit 1002, wherein the coding unit 1001 receives information bits to be transmitted, encodes them to form codewords to be transmitted, and sends the formed codewords to the sending unit 1002; the sending unit 1002 is used to send the received codewords. Further, the coding device also includes a storage unit 1003, which is used to store the codewords to be transmitted and send them back to the coding unit 1001. During the coding process, the coding unit 1001 will use the bits in the previously formed codewords to encode and generate new codewords to be transmitted.

[0202] During the encoding process, a first codeword is formed, which includes 2n bits, formed by k coding bits, and the n bits of the first codeword come from m codewords formed before the first codeword, and the other n bits in the first codeword include kn information bits and 2n-k check bits, where n, m, and k are all positive integers, and 2n>k>n>m; when sending, the bits from the previous m codewords do not participate in data transmission, and the other n bits in the first codeword (i.e., the codeword to be transmitted) will be sent out. The specific encoding process is as described in the previous embodiment, and this embodiment will not be repeated.

[0203] Another embodiment of the present application provides a decoding device for data communication, such as Fig.11 As shown, it includes a decoding unit 1101 and a storage unit 1102, wherein the decoding unit 1101 is used to receive the transmitted codeword, recover the first codeword, and decode the first codeword; the storage unit 1102 is used to store the codeword from the transmission, and receive decoding information from the decoding unit 1101, update the stored codeword, and send the updated codeword back to the decoding unit 1101 in the subsequent decoding process. The decoding unit 1101 will use the information bits obtained by decoding before in the decoding process, and the information bits are protected by different codewords, so the decoding performance is stronger.

[0204] During the decoding process, a first codeword is formed, which includes 2n bits, and the n bits of the first codeword come from m codewords decoded before the first codeword, where n and m are both positive integers, and n>m. At this time, these n bits have been decoded in the previous decoding process, so the number of error bits will be reduced, thereby improving the decoding success rate of the first codeword. For example, codeword x-1 contains y errors before decoding. After decoding, some of the error bits in codeword x-1 are corrected; since some errors are corrected in codeword x-1, other previously uncorrectable codewords that share bits with codeword x-1 can now have a sufficient number of correct bits, making the previously uncorrectable codewords correctable. By analogy, codewords can be decoded repeatedly.

[0205] Another embodiment of the present application provides a coding device for data communication, such as Fig.12 As shown, it includes: an input interface 1201, an encoder 1202, a memory 1203 and an output interface 1204; the encoder 1202 is used to receive information data through the input interface 1201 and send the generated codeword through the output interface 1204; the memory 1203 is used to store the codeword sent by the encoder 1202 and send it back to the encoder 1202 in the subsequent encoding process; the encoder 1202 will use the bits in the previously formed codeword to encode and generate a new codeword during the encoding process. The specific encoding process is as described in the previous embodiment and will not be repeated here.

[0206] Further, Fig.12 The memory shown in is a device independent of the encoder. In actual situations, the storage function can also be implemented in the encoder, that is, there is no need for a separate memory. In addition, the memory 1203 can also receive information data from the input interface 1201 and receive verification data from the encoder 1202, which is not limited in this application.

[0207] In addition, another embodiment of the present application also provides a decoding device for data communication, such as Fig.13 As shown, it includes an input interface 1301, a decoder 1302, a memory 1303 and an output interface 1304; the decoder 1302 is used to receive the codeword sent through the input interface 1301 and decode it; the memory 1303 is used to store the codeword from the input interface 1301, and receive decoding information from the decoder 1302, update the stored codeword, and send the updated codeword back to the decoder 1302 in the subsequent decoding process; the memory 1303 can also send the updated codeword through the output interface 1304. The decoder 1302 will use the information bits obtained by decoding before in the decoding process to improve the decoding ability. Similarly, in the decoding device, the storage function can also be implemented in the decoder, that is, a separate memory may not exist.

[0208] The present application provides an embodiment of a computer-readable storage medium or a computer program product for storing a computer program, which is used to execute the encoding or decoding method involved in the method embodiment of the present application.

[0209] Understandably, Fig.12 Only a simplified design of the encoding device is shown. In practical applications, the encoding device may include any number of interfaces and encoders, and all terminals that can implement the embodiments of the present application are within the protection scope of the embodiments of the present application. Similarly, the decoding device may also include any number of interfaces and decoders to achieve parallel decoding and improve decoding efficiency.

[0210] It is further understood that the encoder or decoder involved in the embodiments of the present application may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0211] The coding scheme disclosed in this application can be used in high-speed transmission systems, for example, 800G transmission systems, and its structure is as follows: Fig.14 As shown, the transmitting end includes a first encoding unit 1401, an interleaving unit 1402 and a second encoding unit 1403; wherein the first encoding unit 1401 is used to receive a data bit stream, perform KP4 encoding on the received data bit stream, and send the encoded bit stream to the interleaving unit 1402; the interleaving unit 1402 is used to interleave the received bit stream, and send the interleaved bit stream to the second encoding unit 1403; the second encoding unit 1403 is used to execute the encoding method disclosed in the previous embodiment on the interleaved bit stream, and send the generated codeword. The specific encoding method will not be repeated here.

[0212] It should be noted that the KP4 codeword is RS (544, 514, 15, 10), that is, the KP4 codeword includes 544 symbols, of which 514 symbols are information symbols. One decoding can correct errors of up to 15 symbols, and each symbol includes 10 bits; the interleaving unit can process the received bit stream in a row-column interleaving manner, that is, the bits are written in the form of rows and read out in the form of columns to perform the interleaving function. This is an interleaving method that is easier to implement. Of course, other interleaving methods can also be used, and this application is not limited.

[0213] Furthermore, the receiving end of the high-speed transmission system includes a first decoding unit 1404, a deinterleaving unit 1405 and a second decoding unit 1406; the first decoding unit 1404 is used for the codeword sent by the transmitting end, and performs the decoding method disclosed in the previous embodiment on the received codeword, and sends the decoded bit stream to the deinterleaving unit 1405; the deinterleaving unit 1405 is used to deinterleave the received bit stream, and send the deinterleaved bit stream to the second decoding unit 1406; the second decoding unit 1406 is used to perform KP4 decoding on the deinterleaved bit stream to obtain the original data bits. The high-speed transmission system provided in this embodiment uses KP4 coding and the coding method provided in the previous embodiment for cascade coding, which can enhance the coding performance and meet the increasingly improved coding performance requirements as the optical transmission rate increases.

[0214] In addition, in an actual high-speed transmission system, KP4 encoding and the encoding method disclosed in this application are implemented in different chips. Taking the 800G transmission system as an example, its basic structure is as follows: Fig.15 As shown, KP4 encoding is implemented in the first chip 1501, the encoding method of the present application is implemented in the second chip 1502, the decoding method disclosed in the present application is implemented in the third chip 1503, and KP4 decoding is implemented in the fourth chip 1504; the two first chips jointly output 8 100G signals to realize the transmission function of 800G signals. It should be understood that the 800G transmission system can also include only one first chip to implement KP4 encoding, and send 800G signals to the second chip through one first chip, which is not limited in the present application.

[0215] Specifically, the second chip 1502 receives the KP4 codeword transmitted from the first chip 1501, does not perform KP4 decoding, and directly encodes the KP4 code with the check bit according to the encoding method provided in the previous embodiment. Since there is circuit noise in the interconnection between the first chip 1501 and the second chip 1502, correlation bit errors will be caused. Therefore, the transceiver needs to perform interleaving and deinterleaving to break up the correlation, that is, at the transmitting end, the KP4 codeword is interleaved and sent to the second chip 1502. Similarly, at the receiving end, the codeword after decoding by the third chip 1503 is deinterleaved and then sent to the fourth chip 1504. It should be noted that the first chip and the fourth chip can be integrated together, and the second chip and the third chip can be integrated together to realize the transceiver function. In addition, the interleaving function can be implemented in the first chip 1501 or the second chip 1502, and the deinterleaving function can be implemented in the third chip 1503 or the fourth chip 1504, which is not limited in this application.

[0216] In order to further reduce latency and power consumption, the data allocation and interleaving functions of the first chip output port can be integrated, that is, when distributing KP4 data, the data sending order is disrupted to realize the interleaving function; similarly, the decoding end can also perform similar processing.

[0217] Further, taking the KP4 cascade as the FEC frame disclosed in the previous embodiment of this application as an example, and when the decoding delay (the encoding delay is small and is ignored here) is only 170ns, the simulation results of the encoding performance are as follows: Fig.16 As shown, when the bit error rate (BER) of the input signal is 2.5E-3 or below, the BER of the decoded signal can be guaranteed to be below 1E-15; that is, the coding performance can also be guaranteed under low latency conditions.

[0218] In the embodiment of the present application, the encoding performance is improved by cascading two different codewords. Moreover, there is no need to decode KP4 at the transmitting end, and the KP4 codeword is directly encoded to achieve transparent transmission of the KP4 codeword, thereby further reducing system power consumption.

[0219] In an embodiment of the present application, another codeword structure of a code is also given, and the specific structure is shown in Figure 17 (a), wherein the code length of each codeword is 2n, the coding bit length of each codeword is k, and the check bit length is p = 2n-k. The interleaving depth of the code is defined as m, and the first n bits in each codeword are derived from the data of the previous m moments, which are called mirror bits; among the last n bits, kn bits are information bits at the current moment, and the remaining p = 2n-k bits are called check bits, wherein n, m, and k are all positive integers, 2n>k>n>m. For the mirror bit, if it comes from the information bit of the previous moment, it is called a mirror information bit; if it comes from the check bit of the previous moment, it is called a mirror check bit. The entire codeword can be called a component code. This embodiment uses a BCH code or a shortened BCH code as a component code, and the number of error correction bits is t.

[0220] Multiple component codes can constitute an FEC frame, and the structure of the FEC frame is shown in Figure 17 (b). Each frame contains p_word component code words, where p_word is an integer greater than 1. It should be understood that p_word in this embodiment has the same meaning as NUM in the previous embodiment. These component codes are encoded at the same time, and then the information bits and check bits of all component codes are combined and sent, for a total of n*p_word bits. The n*p_word mirror bits will not be transmitted on the channel. In addition, the FEC frame can be a spatially coupled code.

[0221] like Fig.18 As shown, the FEC frame described in this scheme can be described by a matrix with n columns and infinite rows. In this matrix, each row represents a component codeword, and the continuous p_word rows represent a frame as shown in Figure 17(b); the bits corresponding to each column have the same bit sequence number. Assuming that the frame at the current moment is frame 0, according to the frame structure given in Figure 17(b), its information bits and check bits are generated at the current moment, and the mirror bits of the current frame (bits marked with slashes) are obtained by interleaving and mapping the information bits and check bits (bits marked with squares) of the previous h frames (frame-h to frame-1). We call the mirror bits of the current frame the interleaving target, and the information bits and check bits of the previous h frames are called the interleaving source. It should be understood that h in this embodiment has the same meaning as T in the previous embodiment.

[0222] We label the coordinates of a specific bit as (Frame, Row_str, Col_str), where the frame identifier Frame∈(-∞,+∞), the row identifier Row_str∈[0, p_word-1], and the column identifier Col_str∈[0, 2n-1]. We use the function Φ([Frame, Row_str, Col_str]) to represent the interleaving mapping relationship from the interleaving target to the interleaving source. Therefore, the input and output of the Φ() function are both a coordinate in the matrix. Φ-1() is the inverse function of Φ(), which represents the mapping relationship from the interleaving source to the interleaving target.

[0223] Specifically, Fig.19 is a schematic diagram of an interleaving scheme, which describes the correspondence between an interleaving source and an interleaving target. For the convenience of representation, we express the p_word bits with the same column coordinates in the interleaving target as {[0,:,Col_str]}={[0,0,Col_str],[0,1,Col_str],…,[0,p_word-1,Col_str]}. They correspond to the p_word bits in the interleaving source, and their corresponding coordinates are Fig.19 It is represented as Φ({[0,:,Col_str]}).

[0224] The specific interleaving scheme is described as follows:

[0225] The specific expression of the Φ() function: Φ([Frame,Row_str,Col_str])=[Φf([Frame,Row_str,Col_str]),Φr([Frame,Row_str,Col_str]),Φc([Frame,Row_str,Col_str])].

[0226] For the convenience of representation, we use three sub-functions Φf(), Φr() and Φc() to respectively represent the calculation of the frame coordinates, row coordinates and column coordinates of the bits in the interleaved source from the coordinates of the bits in the interleaved target. Their specific expressions are as follows:

[0227] Φf([Frame,Row_str,Col_str])=Frame-1-frm_map(floor((Col_str+Δ) / ceiling(b_frm)));

[0228]

[0229] Φc([Frame, Row_str, Col_str])=n+h*((Col_str+Δ)%ceiling(b_frm))+(h-1-floor((Col_str+Δ) / ceiling(b_frm))).

[0230] in:

[0231] The ceiling() and floor() functions round the input up and down, respectively. represents bitwise XOR, and % represents modulo;

[0232] frm_map represents a bijective function whose input domain and output domain are both {0,1,…,h-1}. Fig.19 In the interleaving scheme, the corresponding frm_map(i)=h-1-i,i∈[0,h-1];

[0233] b_frm=n / h represents the average number of bits each codeword in the interleaving target obtains from each frame of the interleaving source;

[0234] Δ is an adjustment item. If b_frm is an integer, Δ=0; if b_frm is not an integer, Δ takes the following values:

[0235] If Col_str / floor(b_frm) <N_ext,Δ=floor(Col_str / floor(b_frm));

[0236] If Col_str / floor(b_frm)>=N_ext, Δ=N_ext, where N_ext=ceiling(b_frm)*hn.

[0237] Since the bits in the interleaving source and the interleaving target are one-to-one corresponding, the interleaving mapping function Φ() is bijective. For a certain number of interleaving associated frames h, the number of codewords per frame p_word, the code length 2n, and the frm_map function, the interleaving mapping function Φ() exists and is uniquely determined. h, p_word, and 2n are independent of each other and do not constrain each other. Therefore, even if p_word and 2n have been determined, h can still be adjusted to balance decoding performance and decoding delay.

[0238] Furthermore, for the codewords in this application, the code length 2n<=2048, the number of BCH component code error correction bits t<=5, and the number of frames included in the interleaving source h>1, then the constructed codeword can still have good performance under the premise of ensuring low latency. It should be understood that the h FEC frames formed before the current moment mentioned here can be h FEC frames at any previous moment. For example, the FEC frames of h consecutive moments before the current moment can also be the FEC frames taken continuously after a fixed interval from the current moment, or the FEC frames of any h discontinuous moments before the current moment, and this application does not limit this.

[0239] According to the above interleaving scheme, if b_frm is an integer, each frame in the interleaving source provides b_frm bits for each codeword of the interleaving target; otherwise, each frame of (ceiling(b_frm)-b_frm)*h frames in the interleaving source provides floor(b_frm) bits for each codeword of the interleaving target, and each frame of the remaining (b_frm-floor(b_frm))*h frames provides ceiling(b_frm) bits for each codeword of the interleaving target. In addition, the definition of b_word=n / (h*p_word) represents the average number of bits that each codeword in the interleaving target obtains from each codeword of the interleaving source. If b_word is an integer, each codeword in the interleaving source provides b_word bits for each codeword of the interleaving target; otherwise, each of the (ceiling(b_word)-b_word)*(h*p_word) codewords included in the interleaving source provides floor(b_word) bits for each codeword of the interleaving target, and each of the remaining (b_word-floor(b_word))*(h*p_word) codewords provides ceiling(b_word) bits for each codeword of the interleaving target. It can be seen that the number of bits obtained from each codeword in the interleaving target is basically the same, and the codewords obtained from each frame are also basically the same, indicating that the interleaving method proposed in this scheme will fully break up the interleaving source, thereby effectively improving the decoding performance. Fig.19 In the example shown, b_frm is an integer, and it can be seen that each frame in the interleaved source provides p_word*b_frm bits to the interleaved target.

[0240] Furthermore, the embodiment of the present application also describes the position of the mirror check bit. Fig.19The FEC frame determined by a set of parameters h, p_word, and code length 2n shown has the positions of a total of p*p_word mirror parity bits also determined. For the mirror parity bits, Frame = 0, Row_str ∈ [0, p_word - 1]. The coordinates of all p Col_str are divided into h groups. The following mainly defines the p Col_str corresponding to the mirror parity bits.

[0241] First, define the following set of h i_base coordinates. Each i_base coordinate represents the maximum value of the column coordinate Col_str of the mirror parity bits from a frame in the mirror bits. If i < N_ext, i_base(i) = (i + 1)*ceiling(b_frm) - i - 2; if i >= N_ext, i_base(i) = (i + 1)*ceiling(b_frm) - N_ext - 1, where 0 <= i <= h - 1.

[0242] Second, define the following array, representing the number of coordinates corresponding to each i_base. Range(i) = ceiling((p - i) / h), Range = Range ROR N_ext, where ROR is a circular right shift of the array. Then, the set containing all Col_str coordinates is Col_str_vec(i,:) = [i_base(i) - Range(i) + 1:i_base(i)].

[0243] It should be noted that to distinguish different types of interleaving schemes, we give the following definitions: If b_word is an integer, the association relationship is a regular pattern, and the interleaving scheme is defined as a fully regular interleaving scheme; if b_word is not an integer but b_frm is an integer, the interleaving scheme is defined as a partially regular interleaving scheme; if neither b_word nor b_frm is an integer, the interleaving scheme is defined as an irregular interleaving scheme. Specific examples of different types of interleaving schemes are given below.

[0244] Combined with Fig. 20 , this application gives a specific FEC frame interleaving scheme. Among them, the number of frames h included in the interleaving source is 5, the number of codewords p_word included in each frame is 64, and the code included in the FEC frame is BCH(720, 700) code. Among them, the BCH(720, 700) code is a shortened BCH code obtained by shortening the BCH(1023, 1003) code on the Galois field GF(2^10) by 303 bits, and its error correction bit number t = 2.

[0245] The corresponding interleaving mapping function Φ() can be expressed as:

[0246] Φf([Frame,Row_str,Col_str])=Frame-1-frm_map(floor((Col_str) / 72)),

[0247]

[0248] Φc([Frame,Row_str,Col_str])=360+5*((Col_str)%72)+(4-floor((Col_str) / 72)), where frm_map(i)=4-i,i∈[0,4].

[0249] In this interleaving scheme, the 360 ​​mirror bits of each codeword come from a total of 5*64 codewords in the previous 5 frames. Specifically, b_frm=360 / 5=72, that is, each frame in the interleaving source provides 72 bits for each codeword of the interleaving target; b_word=360 / (5*64)=1.125, that is, (ceiling(1.125)-1.125)*(5*64)=280 codewords in the interleaving source each provide floor(1.125)=1 bit for each codeword of the interleaving target, and the remaining (1.125-floor(1.125))*(5*64)=40 codewords each provide ceiling(1.125)=2 bits for each codeword of the interleaving target. Therefore, the interleaving scheme in this embodiment is a partially regular interleaving scheme. In this interleaving scheme, the number of bits obtained by the interleaving target from each codeword is very small, which means that the interleaving method proposed in this scheme fully breaks up the interleaving source, thereby effectively improving the decoding performance.

[0250] Further, in the FEC frame provided in the embodiment of the present application, each component code (i.e., the codeword in the interleaving target) includes 20 mirror check bits, wherein the 20 mirror check bits are divided into 5 groups. Since N_ext=ceiling(b_frm)*hn=ceiling(360 / 5)*5-360=0, i>=N_ext, according to the formula i_base(i)=(i+1)*ceiling(b_frm)-N_ext-1, the corresponding Col_str value is calculated as follows:

[0251] i_base([0,1,2,3,4])=[71,143,215,287,359];

[0252] Further, since Range(i)=ceiling((pi) / h), 0<=i<=h-1, and Range=RangeROR N_ext, Range([0,1,2,3,4])=[4,4,4,4,4]. Therefore, the column coordinate set of 20 mirror check bits included in each codeword of the interleaved target is Col_str_vec={[68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359]}. It should be noted that in an embodiment of the present application, the column coordinate set of the mirror check bits of each codeword in the interleaved target is the same. Another embodiment of the present application provides another interleaving scheme for an FEC frame, and the schematic diagram of the interleaving scheme is shown in FIG. Fig.21 As shown, the number of frames included in the interleaving source is h=7, the number of codewords included in each frame is p_word=64, and the code included in the FEC frame is the BCH(720,700) code, which is a shortened BCH code obtained by shortening the BCH(1023,1003) code on the Galois field GF(2^10) by 303 bits, and its error correction bit number is t=2.

[0253] The corresponding interleaving mapping function Φ() can be expressed as:

[0254] Φf([Frame,Row_str,Col_str])=Frame–1–frm_map(floor((Col_str+Δ) / 52)),

[0255]

[0256] Φc([Frame,Row_str,Col_str])=360+7*((Col_str+Δ)%52)+(6–floor((Col_str+Δ) / 52)), where frm_map(i)=i,i∈[0,6]. When Col_str / 51<4, Δ=floor(Col_str / 51); when Col_str / 51>=4, Δ=4.

[0257] In this interleaving scheme, the 360 ​​mirror bits of each codeword come from a total of 7*64 codewords in the previous 7 frames. Specifically, b_frm=360 / 7=51.42. At this time, there are 3 frames in the interleaving source, each frame provides 52 bits for each codeword of the interleaving target, and the remaining 4 frames each provide 51 bits for each codeword of the interleaving target. b_word=360 / (7*64)=0.803, then there are 88 codewords in the interleaving source that do not provide bits for the codewords in the interleaving target, and each of the remaining 360 codewords provides 1 bit for each codeword of the interleaving target. Therefore, the interleaving scheme in this embodiment is an irregular interleaving scheme. In this interleaving scheme, the number of bits obtained by the interleaving target from each of the 360 ​​codewords is the same, and the number of bits obtained from each frame is also very small, indicating that the interleaving method proposed in this scheme fully breaks up the interleaving source, thereby effectively improving the decoding performance.

[0258] In this interleaving scheme, the 20 mirror check bits included in each codeword of the interleaving target are divided into 7 groups. Since N_ext=ceiling(b_frm)*hn=ceiling(360 / 7)*7-360=4, and 0<=i<=6, it can be concluded that when 0<=i<4, i_base(i)=(i+1)*ceiling(b_frm)-i+2; when 4<=i<=6, i_base(i)=(i+1)*ceiling(b_frm)-N_ext-1. Therefore, the corresponding Col_str value is calculated as follows:

[0259] i_base([0,1,2,3,4,5,6])=[50,101,152,203,255,307,359];

[0260] Further, since Range(i)=ceiling((pi) / h), 0<=i<=h-1, and Range=RangeROR N_ext, Range([0,1,2,3,4,5,6])=[3,3,3,2,3,3,3]. Therefore, the column coordinate set of 20 mirror check bits included in each codeword of the interleaved target is Col_str_vec={[48,49,50],[99,100,101],[150,151,152],[202,203],[253,254,255],[305,306,307],[357,358,359]}. It should be noted that in the embodiment of the present application, the column coordinate set of the mirror check bits of each codeword in the interleaved target is the same.

[0261] Another embodiment of the present application also provides an interleaving scheme for FEC frames, and a schematic diagram of the interleaving scheme is shown in FIG. Fig. 22As shown, the number of frames included in the interleaving source is h=8, the number of codewords included in each frame is p_word=16, and the code included in the FEC frame is the extended BCH (256, 239) code. The corresponding interleaving mapping function Φ() can be expressed as:

[0262] Φf([Frame,Row_str,Col_str])=Frame-1-frm_map(floor((Col_str) / 16)),

[0263]

[0264] Φc([Frame,Row_str,Col_str])=128+8*((Col_str)%16)+(7-floor((Col_str) / 16)), where frm_map(i)=7-i,i∈[0,7].

[0265] In this interleaving scheme, the 128 mirror bits of each codeword come from a total of 8*16 codewords in the previous 8 frames. b_frm=128 / 8=16, that is, each frame in the interleaving source provides 16 bits for each codeword of the interleaving target; b_word=128 / (8*16)=1, that is, each codeword in the interleaving source provides 1 bit for each codeword of the interleaving target. Therefore, the interleaving scheme in this embodiment is a completely regular interleaving scheme. In this interleaving scheme, the number of bits obtained by the interleaving target from each codeword in the interleaving source is the same, and the number of bits obtained from each frame is also the same, which means that the interleaving method proposed in this scheme fully breaks up the interleaving source, thereby effectively improving the decoding performance.

[0266] In this interleaving scheme, the 17 mirror check bits included in each codeword of the interleaving target are divided into 8 groups. Since N_ext = ceiling (b_frm) * hn = ceiling (128 / 8) * 8-128 = 0, and 0 < = i < = 7, it can be concluded that i_base (i) = (i + 1) * ceiling (b_frm) - N_ext - 1. Therefore, the corresponding Col_str value is calculated as follows:

[0267] i_base([0,1,2,3,4,5,6,7])=[15,31,47,63,79,95,111,127],

[0268] Further, since Range(i)=ceiling((pi) / h) and Range=Range ROR N_ext, Range([0,1,2,3,4,5,6,7])=[3,2,2,2,2,2,2,2]. Therefore, the column coordinate set of 17 mirror check bits included in each codeword of the interleaved target is Col_str_vec={[13,14,15],[30,31],[46,47],[62,63],[78,79],[94,95],[110,111],[126,127]}. It should be noted that in the embodiment of the present application, the column coordinate set of the mirror check bits of each codeword in the interleaved target is the same.

[0269] Furthermore, the FEC frame described in the above embodiment may be a spatial coupling code, and its coding architecture is as follows: Fig.23 As shown, in this block diagram, there are p_word component code encoders and a convolution interleaver. The convolution interleaver stores the information and check bits of h frames before the current moment, and stores a total of h*n*p_word bits for generating n*p_word mirror bits at the current moment.

[0270] The input of the encoder is (kn)*p_word information bits, which will be distributed to p_word component code encoders. The input of each component code encoder is (kn) information bits and n mirror bits, and the output is (kn) information bits and p check bits. The output of the entire encoder is a total of (k-n+p)*p_word=n*p_word information and check bits from p_word component code encoders. The mirror bits from the convolution interleaver only participate in component code encoding and will not be transmitted. It should be understood that the meanings of h, n, and p_word are the same as in the previous embodiment and will not be repeated in this embodiment.

[0271] Fig.24 Given the use of Fig.23 The coding architecture shown generates the mirror bits of the current frame. Fig.24 The upper part is a matrix of h*p_word rows and n columns. In this matrix, consecutive p_word rows represent a frame as shown in Figure 17(b), so at the current moment, a total of h frames (frame-h to frame-1) are stored in the convolution interleaver. The mirror bits of the current frame (frame 0) are interleaved from the bits in the interleaver. For the convenience of representation, we mark the coordinates of a specific bit as [Frame,Row_str,Col_str]. Among them, the frame coordinate Frame∈(-∞,+∞), the row coordinate Row_str∈[0,p_word-1], and the column coordinate Col_str∈[0,n-1].

[0272] The interleaving relationship in the convolutional interleaver is divided into two layers, namely, inter-frame interleaving and inter-code interleaving. Assuming that the coordinates of the mirrored bits after interleaving are [Frame’, Row_str’, Col_str’], the convolutional interleaver describes the interleaving mapping relationship from [Frame, Row_str, Col_str] to [Frame’, Row_str’, Col_str’]. The following introduces the specific schemes for each layer of interleaving.

[0273] Inter-frame interleaving: For the convenience of description, we call p_word bits in the interleaver that have the same frame coordinates and column coordinates a symbol, and express it as {[Frame, :, Col_str]} = {[Frame, 0, Col_str], [Frame, 1, Col_str], …, [Frame, p_word - 1, Col_str]}. As Fig.24 shown, the symbol corresponding to the mirrored bits of the current frame (frame 0) corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:

[0274] Frame’ = Frame + 1 + frm_map(Col_str % h),

[0275] Col_str’ = (h – 1 – Col_str % h) * ceiling(b_frm) + floor(Col_str / h) – Δ.

[0276] Where:

[0277] The ceiling() and floor() functions round the input up and down respectively, and % represents taking the modulus;

[0278] frm_map represents a bijective function with both the input domain and the output domain being {0, 1, …, h - 1}. In the Fig.24 shown interleaving scheme, the corresponding frm_map(i) = i, i ∈ [0, h - 1];

[0279] b_frm = n / h represents the number of bits that each codeword in the current frame obtains from each frame of the interleaver on average;

[0280] Δ is an adjustment term. If b_frm is an integer, Δ = 0; if b_frm is not an integer, when Col_str / floor(b_frm) < N_ext, Δ = floor(Col_str / floor(b_frm)); when Col_str / floor(b_frm) >= N_ext, Δ = N_ext, where N_ext = ceiling(b_frm) * h - n.

[0281] As can be seen from the formula, inter-frame interleaving does not involve the transformation of row coordinates, so the order of bits in each symbol is the same as the order of bits in the interleaver.

[0282] For each symbol that has been inter-frame interleaved, it is further inter-coded so that the bits of the same codeword after interleaving come from different frames as much as possible. The specific inter-code mapping relationship is shown in the following row coordinate transformation formula:

[0283]

[0284] in, It indicates bitwise XOR. It can be seen that there are p_word different schemes for inter-code interleaving according to the difference of Col_str.

[0285] The input bits and output bits of the interleaver correspond one to one. For a certain number of interleaving-related frames h, the number of codewords per frame p_word, the code length 2n, and the frm_map function, the interleaving method exists and is uniquely determined. h, p_word, and 2n are independent of each other and do not constrain each other. Therefore, even if p_word and 2n are determined, h can still be adjusted to balance decoding performance and decoding latency.

[0286] According to the above interleaving scheme, if b_frm is an integer, each frame in the interleaver provides b_frm bits for each codeword of the current frame; otherwise, each frame of (ceiling(b_frm)-b_frm)*h frames in the interleaver provides floor(b_frm) bits for each codeword of the current frame, and each frame of the remaining (b_frm-floor(b_frm))*h frames provides ceiling(b_frm) bits for each codeword of the current frame. In addition, the definition of b_word=n / (h*p_word) represents the average number of bits obtained by each codeword in the current frame from each codeword of the interleaver. If b_word is an integer, each codeword in the interleaver provides b_word bits for each codeword of the current frame; otherwise, each of the (ceiling(b_word)-b_word)*(h*p_word) codewords included in the interleaver provides floor(b_word) bits for each codeword of the current frame, and each of the remaining (b_word-floor(b_word))*(h*p_word) codewords provides ceiling(b_word) bits for each codeword of the current frame. It can be seen that the number of bits obtained from each codeword in the current frame is basically the same, and the codewords obtained from each frame are also basically the same, indicating that the interleaving method proposed in this scheme can also fully scatter the bits in the interleaver, thereby effectively improving the decoding performance.

[0287] Furthermore, the embodiments of the present application also describe the positions of the mirror check bits. For the FEC frame determined by a set of parameters h, p_word, and code length 2n as shown in Fig.24 , the positions of its total p*p_word mirror check bits are also determined. The Frame of the mirror check bit is 0, and Row_str ∈ [0, p_word - 1]. The coordinates of all p Col_str are divided into h groups. The following mainly defines the Col_str corresponding to p mirror check bits.

[0288] First, define the following set of h i_base coordinates. Each i_base coordinate represents the maximum Col_str value of the mirror check bits from a frame in the mirror bits. If i < N_ext, i_base(i) = (i + 1)*ceiling(b_frm) - i - 2; if i >= N_ext, i_base(i) = (i + 1)*ceiling(b_frm) - N_ext - 1, where 0 <= i <= h - 1.

[0289] Second, define the following array, which represents the number of coordinates corresponding to each i_base. Range(i) = ceiling((p - i) / h), Range = Range ROR N_ext, where ROR is the circular right shift of the array. Then, the set containing all Col_str coordinates is Col_str_vec(i, :) = [i_base(i) - Range(i) + 1:i_base(i)].

[0290] It should be noted that in order to distinguish different types of interleaving scheme types, we give the following definitions: If b_word is an integer, the association relationship is a regular pattern, and the interleaving scheme is defined as a fully regular interleaving scheme; if b_word is not an integer, but b_frm is an integer, the interleaving scheme is defined as a partially regular interleaving scheme; if neither b_word nor b_frm is an integer, the interleaving scheme is defined as an irregular interleaving scheme. The following is based on Fig.23 shown coding architecture to specifically describe different types of interleaving schemes.

[0291] This example describes a spatially coupled code with h = 5, p_word = 64, and the component code being BCH(720, 700). The BCH(720, 700) component code is a shortened BCH code obtained by shortening the BCH(1023, 1003) code over the Galois field GF(2^10) by 303 bits, and its error correction bit number t = 2.

[0292] In the coding architecture of the spatial coupling code of this example, there are 64 component code encoders and one convolutional interleaver, wherein the convolutional interleaver stores the information and check bits of the five frames before the current moment, which stores a total of 115,200 bits for generating 23,040 mirror bits at the current moment.

[0293] The input of the encoder is 21760 information bits, which will be distributed to 64 component code encoders. The input of each component code encoder is 340 information bits and 360 mirror bits, and the output is 340 information bits and 20 check bits. The overall output of the encoder is a total of 23040 information and check bits from 64 component code encoders. The mirror bits from the convolution interleaver only participate in the component code encoding and will not be transmitted.

[0294] like Fig.25 As shown, the symbol corresponding to the mirror bit of the current frame corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:

[0295] Frame'=Frame+1+frm_map(Col_str%5),

[0296] Col_str'=(4-Col_str%5)*72+floor(Col_str / 5).

[0297] frm_map(i)=i,i∈[0,4], where b_frm=72, Δ=0.

[0298] According to the above formula, we can know which symbol of the previous frame the symbol corresponding to the mirror bit of the current frame comes from, that is, inter-frame interleaving is performed. Next, inter-code interleaving is performed according to the following corresponding relationship. The specific inter-code mapping relationship is shown in the following row coordinate transformation formula:

[0299]

[0300] It should be noted that in this interleaving scheme, the 360 ​​mirror bits of each codeword come from a total of 5*64 codewords in the previous 5 frames. The specific number of bits obtained from each frame and each codeword is the same as Fig. 20 The embodiment shown is the same; moreover, the column coordinate set of the 20 mirror check bits included in each component code is also the same as Fig. 20 The embodiments shown are the same, and the embodiments of the present application will not be described in detail.

[0301] This example describes h=7, p_word=64, and the component code is a spatial coupling code of BCH(720,700). The BCH(720,700) component code is a shortened BCH code obtained by shortening the BCH(1023,1003) code on the Galois field GF(2^10) by 303 bits, and its error correction bit number t=2.

[0302] In the coding architecture of the spatial coupling code of this example, there are 64 component code encoders and one convolutional interleaver, wherein the convolutional interleaver stores the information and check bits of the 7 frames before the current moment, which stores a total of 161280 bits for generating 23040 mirror bits at the current moment.

[0303] The input of the encoder is 21760 information bits, which will be distributed to 64 component code encoders. The input of each component code encoder is 340 information bits and 360 mirror bits, and the output is 340 information bits and 20 check bits. The overall output of the encoder is a total of 23040 information and check bits from 64 component code encoders. The mirror bits from the convolution interleaver only participate in the component code encoding and will not be transmitted.

[0304] like Fig.26 As shown, the symbol corresponding to the mirror bit of the current frame corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:

[0305] Frame'=Frame+1+frm_map(Col_str%7),

[0306] Col_str'=(6-Col_str%7)*52+floor(Col_str / 7)-Δ.

[0307] frm_map(i)=6-i,i∈[0,6], where, when Col_str / 51<4, Δ=ceiling(Col_str / 51); when Col_str / 51>=4, Δ=4; b_frm=51.42.

[0308] According to the above formula, we can know which symbol of the previous frame the symbol corresponding to the mirror bit of the current frame comes from, that is, inter-frame interleaving is performed. Next, inter-code interleaving is performed according to the following corresponding relationship. The specific inter-code mapping relationship is shown in the following row coordinate transformation formula:

[0309]

[0310] It should be noted that in this interleaving scheme, the 360 ​​mirror bits of each codeword come from a total of 7*64 codewords in the previous 7 frames. The specific number of bits obtained from each frame and each codeword is the same as Fig.21 The embodiment shown is the same; moreover, the column coordinate set of the 20 mirror check bits included in each component code is also the same as Fig.21 The embodiments shown are the same, and the embodiments of the present application will not be described in detail.

[0311] This example describes a spatial coupling code with h=8, p_word=16, and a component code of extended BCH (256, 239). In the coding architecture of the spatial coupling code of this example, there are 16 component code encoders and one convolution interleaver, wherein the convolution interleaver stores information and check bits of 8 frames before the current moment, which stores a total of 16384 bits for generating 2048 mirror bits at the current moment.

[0312] The input of the encoder is 1776 information bits, which will be distributed to 16 component code encoders. The input of each component code encoder is 111 information bits and 128 mirror bits, and the output is 111 information bits and 17 check bits. The overall output of the encoder is a total of 2048 information and check bits from 16 component code encoders. The mirror bits from the convolution interleaver only participate in the component code encoding and will not be transmitted.

[0313] like Fig. 27 As shown, the symbol corresponding to the mirror bit of the current frame corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:

[0314] Frame'=Frame+1+frm_map(Col_str%8),

[0315] Col_str'=(7-Col_str%8)*16+floor(Col_str / 8).

[0316] frm_map(i)=i,i∈[0,7], where b_frm=16, Δ=0.

[0317] According to the above formula, we can know which symbol of the previous frame the symbol corresponding to the mirror bit of the current frame comes from, that is, inter-frame interleaving is performed. Next, inter-code interleaving is performed according to the following corresponding relationship. The specific inter-code mapping relationship is shown in the following row coordinate transformation formula:

[0318]

[0319] It should be noted that in this interleaving scheme, the 360 ​​mirror bits of each codeword come from a total of 5*64 codewords in the previous 5 frames. The specific number of bits obtained from each frame and each codeword is the same as Fig. 22 The embodiment shown is the same; moreover, the column coordinate set of the 20 mirror check bits included in each component code is also the same as Fig. 22 The embodiments shown are the same, and the embodiments of the present application will not be described in detail.

[0320] Furthermore, for the codewords in this application, the code length 2n<=2048, the number of BCH component code error correction bits t<=5, and the number of frames included in the interleaving source h>1, then the constructed codeword can still have good performance under the premise of ensuring low latency. It should be understood that the h FEC frames formed before the current moment mentioned here can be h FEC frames at any previous moment. For example, the FEC frames of h consecutive moments before the current moment can also be the FEC frames taken continuously after a fixed interval from the current moment, or the FEC frames of any h discontinuous moments before the current moment, and this application does not limit this.

[0321] In addition to the above-mentioned embodiments, the present application may also include the following cases:

[0322] Code length 2n = 720, number of error correction bits t = 2, number of interleaving associated frames h = 4;

[0323] Code length 2n = 720, number of error correction bits t = 2, number of interleaving associated frames h = 5;

[0324] Code length 2n = 804, number of error correction bits t = 2, number of interleaving associated frames h = 4;

[0325] Code length 2n = 1206, number of error correction bits t = 3, number of interleaving associated frames h = 4;

[0326] Code length 2n = 868, number of error correction bits t = 2, number of interleaving associated frames h = 4;

[0327] The code length is 2n=1302, the number of error correction bits is t=3, and the number of interleaving associated frames is h=4.

[0328] The codewords constructed above can still have good performance under the premise of ensuring low latency. In addition, a variety of different interleaving schemes are given in the above embodiments, and any encoding method that satisfies the above interleaving scheme, or is the same as the formula provided by the above interleaving scheme, or is just equivalent or simply modified on the basis of the formula provided by the above interleaving scheme, is within the protection scope of this application.

[0329] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present invention. Therefore, "in one embodiment" or "in an embodiment" appearing in various places throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. In various embodiments of the present invention, the serial numbers of the above-mentioned processes do not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0330] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, or it can be an electrical or other form of connection.

[0331] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0332] In short, the above is only a preferred embodiment of the technical solution of the present invention, and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A data transmission method, characterized in that: The method comprises: Receive a first data stream, wherein the first data stream is a data stream obtained by using Reed-Solomon RS (544, 514, 15, 10) encoding; Interleaving the first data stream to obtain an interleaved data stream; The interleaved data stream is encoded for a second time to obtain a data stream that has been encoded twice, wherein the second encoding includes Hamming encoding, and the interleaved data stream is not decoded before the second encoding.

2. The method according to claim 1, characterized in that The RS (544, 514, 15, 10) encoding is implemented in the first chip, and the Hamming encoding is implemented in the second chip.

3. The method according to claim 2, characterized in that The second chip receives the eight first data streams output from the first chip.

4. The method according to claim 3, characterized in that The rate of the first data stream is 100 Gbps.

5. A data transmission method, characterized in that: Receive a second data stream, wherein the second data stream is a data stream obtained by using Reed-Solomon RS (544, 514, 15, 10) encoding and a second encoding, wherein the second encoding includes Hamming encoding; Deinterleaving the second data stream to obtain a deinterleaved data stream; The deinterleaved data stream is decoded for the first time to obtain a first data stream, wherein the first data stream is a data stream obtained by using RS (544, 514, 15, 10) encoding.

6. The method according to claim 5, characterized in that The first decoding is implemented on a first chip, and the method further includes: The first data stream is sent to a second chip, wherein the first data stream is used to be decoded by the second chip according to RS (544, 514, 15, 10).

7. The method according to claim 6, characterized in that The RS (544, 514, 15, 10) encoding and RS (544, 514, 15, 10) decoding are completed on the same chip, and the second encoding and the first decoding are completed on the same chip.

8. The method according to claim 6 or 7, characterized in that: The second chip receives the eight first data streams output from the first chip.

9. The method according to claim 8, characterized in that The rate of the first data stream is 100 Gbps.

10. A data transmission device, characterized in that: The device comprises: a receiver, an interleaver and an encoder; The receiver is configured to receive a first data stream and send the first data stream to the interleaving unit, wherein the first data stream is a data stream obtained by Reed-Solomon RS (544, 514, 15, 10) encoding; The interleaver is used to interleave the first data stream and send the interleaved data stream to the encoder; The encoder is used to perform a second encoding on the interleaved data stream to obtain a data stream that has been encoded twice, wherein the second encoding includes Hamming coding, and the interleaved data stream is not decoded before the second encoding.

11. The device according to claim 10, characterized in that The RS (544, 514, 15, 10) encoding is implemented in the first chip, and the Hamming encoding is implemented in the second chip.

12. The device according to claim 11, characterized in that The second chip receives the eight first data streams output from the first chip.

13. The device according to claim 12, characterized in that The rate of the first data stream is 100 Gbps.

14. A data transmission device, characterized in that: The device includes a receiver, a deinterleaver and a decoder; The receiver is used to receive a second data stream and send the second data stream to the deinterleaver, wherein the second data stream is a data stream obtained by Reed-Solomon RS (544, 514, 15, 10) encoding and a second encoding, and the second encoding includes Hamming coding; The deinterleaver is used to deinterleave the second data stream to obtain a deinterleaved data stream, and send the deinterleaved data stream to the decoder; The decoder is used to perform a first decoding on the deinterleaved data stream to obtain a first data stream, wherein the first data stream is a data stream obtained by using RS (544, 514, 15, 10) encoding.

15. The device according to claim 14, characterized in that The first decoding is implemented on the first chip, and the decoder is further used to send the first data stream to the second chip, wherein the first data stream is used to be decoded by the second chip according to RS (544, 514, 15, 10).

16. The device according to claim 15, characterized in that The RS (544, 514, 15, 10) encoding and RS (544, 514, 15, 10) decoding are completed on the same chip, and the second encoding and the first decoding are completed on the same chip.

17. The device according to claim 15 or 16, characterized in that The second chip receives the eight first data streams output from the first chip.

18. The device according to claim 17, characterized in that The rate of the first data stream is 100 Gbps.

19. A communication system, characterized in that: It comprises a first data transmission device as claimed in any one of claims 10-13 and a second data transmission device as claimed in any one of claims 14-18, wherein the first data transmission device is connected to the second data transmission device.

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