Vertical NAND flash memory device and electronic device including same

Abstract

A vertical NAND flash memory device and an electronic device including the same are provided. The vertical NAND flash memory device includes a plurality of cell arrays. The plurality of cell arrays each include a channel layer, a charge trapping layer disposed on the channel layer, and a plurality of gate electrodes disposed on the charge trapping layer. The charge trapping layer includes a matrix and nanocrystals dispersed in the matrix and including a nitride having semiconductor properties, the matrix including an amorphous metal oxynitride.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0085990 filed on July 3, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to vertical NAND flash memory devices and electronic devices including the same. Background Art

[0004] As the hard disk of the related art has been replaced by a solid-state drive (SSD), a NAND flash memory device as a non-volatile memory device has been widely commercialized. Recently, a vertical NAND flash memory device in which a plurality of memory cells are stacked in a direction perpendicular to a substrate has been developed based on miniaturization and high integration.

[0005] In vertical NAND flash memory devices, lateral charge spreading between memory cells may occur due to an increase in the number of stacked stages and a decrease in the height of memory cells. Such lateral charge spreading may degrade the charge retention of the memory cells. Summary of the invention

[0006] A vertical NAND flash memory device and an electronic device including the same are provided.

[0007] Additional aspects may be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0008] According to one aspect of the present disclosure, a vertical NAND flash memory device is provided, comprising: a plurality of cell arrays, each of the plurality of cell arrays comprising: a channel layer; a charge trapping layer disposed on the channel layer; and a plurality of gate electrodes disposed on the charge trapping layer, the charge trapping layer comprising: a substrate comprising an amorphous metal oxynitride; and a plurality of nanocrystals disposed in the substrate, the plurality of nanocrystals comprising a nitride.

[0009] The plurality of nanocrystals may be spatially separated from one another in the matrix.

[0010] The matrix may include a metal oxynitride having a dielectric constant (permittivity) greater than that of silicon nitride.

[0011] The matrix may include at least one of AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON.

[0012] The plurality of nanocrystals each include a semiconductor nitride, which may have a band gap greater than 1 eV and smaller than a band gap of a material of the matrix.

[0013] Each of the plurality of nanocrystals may be at least one of: AlN, GaN, GeN, SiN, CN, InN, YN, ScN, or ZrN.

[0014] Each of the plurality of nanocrystals may have a size of about 0.5 nm to about 5 nm.

[0015] Each of the plurality of nanocrystals may have a size of about 1 nm to about 3 nm.

[0016] The plurality of nanocrystals may be formed by heat-treating the amorphous metal oxynitride of the substrate at a heat-treating temperature.

[0017] The heat treatment temperature of the amorphous metal oxynitride may be about 800°C to about 1300°C, for example, about 900°C to about 1300°C.

[0018] The plurality of nanocrystals may be embedded in the matrix.

[0019] One or more of the plurality of nanocrystals may be disposed in a boundary between the substrate and a layer adjacent to the substrate.

[0020] Each of the plurality of unit arrays may be vertically disposed to extend on the substrate.

[0021] The channel hole may extend in a direction perpendicular to the substrate.

[0022] The interior of the channel hole may be filled with an insulating layer.

[0023] The channel layer and the charge trapping layer may each be formed in a cylindrical (cylindrical) shape surrounding the channel hole.

[0024] The plurality of gate electrodes may be spaced apart from one another in a direction perpendicular to the substrate, and each of the plurality of gate electrodes may surround the charge trapping layer.

[0025] A tunneling dielectric layer (dielectric layer) may be provided between the channel layer and the charge trapping layer.

[0026] A blocking dielectric layer may be provided between the charge trapping layer and each of the plurality of gate electrodes.

[0027] According to another aspect of the present disclosure, an electronic device is provided, comprising: a plurality of cell arrays, each of the plurality of cell arrays comprising: a channel layer; a charge trapping layer disposed on the channel layer; and a plurality of gate electrodes disposed on the charge trapping layer, the charge trapping layer comprising: a substrate comprising an amorphous metal oxynitride; and a plurality of nanocrystals disposed in the substrate, the plurality of nanocrystals comprising a nitride. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and other aspects, features and advantages of some embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a perspective view schematically showing a vertical NAND flash memory device according to an embodiment;

[0030] Figure 2 yes Figure 1 A cross-sectional view of the cell array shown in ;

[0031] Figure 3 yes Figure 2 An enlarged view of a portion A of a memory cell shown in FIG.

[0032] Figure 4A shows a transmission electron microscopy (TEM) image of an amorphous AlON film deposited on a substrate;

[0033] Figure 4B Shown by heat treatment Figure 4A TEM image of amorphous AlON film obtained from the amorphous AlON film shown in;

[0034] Figure 5A is a cross-sectional view showing a memory cell of a vertical NAND flash memory device according to a comparative example;

[0035] Figure 5B Schematically showing the Figure 5A The electronic energy band (electronic band) structure taken by line I-I';

[0036] Fig. 6A is a cross-sectional view showing a memory cell of a vertical NAND flash memory device according to an embodiment;

[0037] Figure 6B Schematically showing the Fig. 6A The electronic band structure taken by line II-II' in;

[0038] Figure 6C Schematically showing the Fig. 6A The electronic band structure taken by line III-III' in;

[0039] Figure 7 An example of trapping energy (trap energy) of a charge trapping layer in a vertical NAND flash memory device according to a comparative example is shown;

[0040] Fig. 8A An example of trapping energy of a charge trapping layer in a vertical NAND flash memory device according to an embodiment is shown;

[0041] Figure 8B An example of a trapping density (trap density) of a charge trapping layer in a vertical NAND flash memory device according to an embodiment is shown;

[0042] Fig.9A Another example of trapping energy of a charge trapping layer in a vertical NAND flash memory device according to an embodiment is shown;

[0043] Fig. 9B Another example of a trapping density of a charge trapping layer in a vertical NAND flash memory device according to an embodiment is shown;

[0044] Fig.10 is a cross-sectional view of a vertical NAND flash memory device according to another embodiment; and

[0045] Fig.11 is a conceptual diagram schematically illustrating a device architecture applicable to an electronic device according to an embodiment. DETAILED DESCRIPTION

[0046] Embodiments will now be described in detail, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this regard, the present embodiment may have different forms and should not be construed as being limited to the description set forth herein. Therefore, the following embodiments are described only by reference to the accompanying drawings to illustrate various aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the related enumerated items. Expressions such as "at least one (individual)" when preceding a list of elements modify the entire list of elements and do not modify the individual elements in the list.

[0047] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent the same elements, and the sizes of the elements in the accompanying drawings may be exaggerated for clarity and ease of description. Meanwhile, the embodiments described below are only examples, and various modifications may be made from these embodiments.

[0048] Hereinafter, what is described as "above" or "on" may include those directly above, below, to the left, and to the right of ... in contact, as well as those above, below, to the left, and to the right of ... without contact. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form. In addition, when a part "includes" any element, it means that the part may further include other elements, rather than excluding other elements, unless otherwise specified.

[0049] The term "said" and similar indicative terms can be used in both the singular and the plural. When there is no explicit description of the order of steps constituting a method or there is no description contrary thereto, these steps can be performed in an appropriate order and are not limited to the order described.

[0050] Furthermore, the terms “unit”, “module” and the like described herein mean a unit that processes at least one function or operation and may be implemented as hardware or software, or may be implemented as a combination of software and hardware.

[0051] The connections or connecting means of lines between elements shown in the drawings illustrate functional connections and / or physical or circuit connections and may be replaced in actual devices or may be represented as additional respective functional connections, physical connections or circuit connections.

[0052] All examples or exemplary terms are used only to describe the technical concept in detail, and the scope thereof is not limited by these examples or exemplary terms unless limited by the claims.

[0053] In vertical NAND flash memory devices, data retention is one of the key reliability factors, that is, the property of storing charges for a long time in the charge trapping layer. When the distance between memory cells is reduced to increase the storage density in vertical NAND flash memory devices, the trapped charges may move between memory cells, and therefore, the charge retention property may deteriorate.

[0054] In vertical NAND flash memory devices, charges can move from the charge trapping layer to the tunneling dielectric layer through trapping-assisted tunneling or thermal emission in a direction perpendicular to the charge trapping layer. The extent of such charge movement can be determined by the conduction band offset (CBO) at the interface between the charge trapping layer and the tunneling dielectric layer.

[0055] Charge movement may occur in a direction parallel to the charge trapping layer by lateral migration according to the gradient of charge concentration. Charge movement in a direction parallel to the charge trapping layer may be governed by Poole-Frenkel tunneling.

[0056] The current density due to Poole-Frenkel tunneling can be expressed as the following Poole-Frenkel conduction equation (Equation 1).

[0057]

[0058] Here, J is the current density, q is the electron charge, μ is the carrier mobility, and N c is the density of states in the conduction band, E is the electric field, and E T is the capture energy (trap energy), ε is the dielectric constant, κ is the Boltzmann constant, and T is the temperature.

[0059] The charge movement in the direction parallel to the charge trapping layer by Poole-Frenkel tunneling can be determined by the trapping energy E in the charge trapping layer. T and the capture density (trap density) N T The trapping energy refers to the voltage barrier that electrons in a material need to cross to move from one atom to another. In other words, the trapping energy refers to the depth of the trapped state relative to the conduction band minimum (CBM) of the material. The trapping density refers to the number of trapped charges per unit volume. The trapping density can be calculated by using a charge pump method. The charge retention characteristics in the direction parallel to the charge trapping layer can be improved by high trapping energy and high trapping density.

[0060] Figure 1 is a perspective view schematically showing a vertical NAND flash memory device 100 according to an embodiment.

[0061] refer to Figure 1 , the vertical NAND flash memory device 100 includes a plurality of cell arrays 110 disposed on a substrate 101. Each cell array 110 may be disposed to extend in a direction perpendicular to the substrate 101. For example, each cell array 110 may be disposed in a direction perpendicular to the substrate 101. Figure 1 The plurality of unit arrays 110 may be arranged on the substrate 101 in various forms.

[0062] Figure 2 yes Figure 1 1 is a cross-sectional view of each unit array 110 shown in FIG. Figure 3 yes Figure 2 An enlarged view of a portion A of a memory cell MC shown in FIG.

[0063] Reference Figure 1 , 23, the cell array 110 includes a plurality of memory cells MC stacked in a direction (z-axis direction) perpendicular to the substrate 101. The cell array 110 includes a plurality of gate electrodes 121 spaced apart from each other and stacked in a direction perpendicular to the substrate 101. In addition, the cell array 110 includes a blocking dielectric layer 123, a charge trapping layer 125, a tunneling dielectric layer 127, and a channel layer 129 disposed within the gate electrode 121. According to an embodiment, the blocking dielectric layer 123, the charge trapping layer 125, the tunneling dielectric layer 127, and the channel layer 129 may be disposed in this order within the gate electrode parallel to the substrate 101. The blocking dielectric layer 123, the charge trapping layer 125, the tunneling dielectric layer 127, and the channel layer 129 may each be disposed to extend vertically on the substrate 101 and be shared by a plurality of memory cells MC.

[0064] Each memory cell MC may include a gate electrode 121, a blocking dielectric layer 123, a charge trapping layer 125, a tunneling dielectric layer 127, and a channel layer 129 disposed at a position corresponding to the gate electrode 121. A source (source) and a drain (drain) may be disposed in the channel layer 129 located below and above each memory cell MC, and a channel corresponding to the gate 121 may be formed in the channel layer 129 between the source and the drain. In an example case where a certain voltage is applied to the gate electrode 121 in each memory cell MC, charges flowing between the source and the drain in the channel layer 129 corresponding to the gate electrode 121 may pass through the tunneling dielectric layer 127 and be trapped in the charge trapping layer 125, so that information may be stored.

[0065] According to an embodiment, the interlayer insulating layer 115 and the gate electrode 121 may be alternately stacked on the substrate 101 in a direction perpendicular to the substrate 101. Each interlayer insulating layer 115 and each gate electrode 121 may be arranged in parallel on the substrate 101. The substrate 101 may include a variety of materials. For example, the substrate 110 may include a single crystal silicon substrate, a compound semiconductor substrate, or a silicon on insulator (SOI) substrate. However, the present disclosure is not limited thereto, and thus, according to another embodiment, the substrate 110 may include different types of substrates. In addition, the substrate 101 may further include, for example, an impurity region doped, an electronic device such as a transistor, or a peripheral circuit for selecting and controlling a memory cell for storing data.

[0066] According to an embodiment, the gate electrode 121 may control a channel layer 129 corresponding to the gate electrode 121. According to an embodiment, the vertical NAND flash memory device 100 may include a word line electrically connected to the gate electrode 121. The gate electrode 121 may include, for example, a metal material having excellent conductivity such as gold (Au), a metal nitride, impurity-doped silicon, or a two-dimensional (2D) conductive material. However, this is only an example, and thus, according to another embodiment, the gate electrode 121 may include a variety of other materials. The interlayer insulating layer 115 may be a spacer for insulation between the gate electrodes 121. The interlayer insulating layer 115 may include, for example, silicon oxide or silicon nitride, but is not limited thereto.

[0067] According to an embodiment, a channel hole is formed to pass through the interlayer insulating layer 115 and the gate electrode 121 in a direction (z-axis direction) perpendicular to the substrate 101. Such a channel hole may be formed to have, for example, a circular cross-section.

[0068] The blocking dielectric layer 123, the charge trapping layer 125, the tunneling dielectric layer 127, and the channel layer 129 are sequentially disposed on the inner wall of the channel hole. The blocking dielectric layer 123, the charge trapping layer 125, the tunneling dielectric layer 127, and the channel layer 129 may each be formed to have a cylindrical shape extending in a direction perpendicular to the substrate 101. A filling insulating layer 130 may be disposed in the channel layer 129 to fill the channel hole. The filling insulating layer 130 may include, for example, silicon oxide or air, but the present disclosure is not limited thereto.

[0069] The channel layer 129 may include a semiconductor material. For example, the channel layer 129 may include, for example, Si, Ge, SiGe, a III-V semiconductor, etc. In addition, the channel layer 129 may include, for example, an oxide semiconductor, a nitride semiconductor, an oxynitride semiconductor, a 2D semiconductor material, a quantum dot (QD), or an organic semiconductor. The oxide semiconductor may include, for example, InGaZnO, etc., the 2D semiconductor material may include, for example, a transition metal dichalcogenide (TMD) or graphene, and the QD may include a colloidal QD, a nanocrystalline structure, etc. However, this is only an example, and the present embodiment is not limited thereto.

[0070] The channel layer 129 may further include a dopant. The dopant may include a p-type dopant or an n-type dopant. The p-type dopant may include, for example, a group III element such as B, Al, Ga, and In, and the n-type dopant may include a group V element such as P, As, and Sb.

[0071] The blocking dielectric layer 123, the charge trapping layer 125, and the tunneling dielectric layer 127 are disposed between the gate electrode 121 and the channel layer 129. The blocking dielectric layer 123 is disposed on the inner wall of the channel hole to contact the interlayer insulating layer 115 and the gate electrode 121. The blocking dielectric layer 123 may include, for example, silicon oxide or metal oxide, but is not limited thereto. The tunneling dielectric layer 127 is a layer through which charges tunnel, and may include, for example, silicon oxide or metal oxide, but is not limited thereto.

[0072] The charge trapping layer 125 is disposed between the blocking dielectric layer 123 and the channel dielectric layer 127. The charge trapping layer 125 includes a matrix 125a and nanocrystals 125b disposed within the matrix 125a.

[0073] The substrate 125a may include an amorphous metal oxynitride. The substrate 125a may include a metal oxynitride having a dielectric constant greater than that of silicon nitride. For example, the substrate 125a may include at least one of AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON, but the present disclosure is not limited thereto.

[0074] The nanocrystals 125b may be randomly distributed in the matrix 125a. The nanocrystals 125b may be embedded in the matrix 125a. The nanocrystals 125b may be spatially separated from each other in the matrix 12.

[0075] Each of the nanocrystals 125b may have a spherical or elliptical shape. However, the present disclosure is not limited thereto, and in this way, the nanocrystals 125b may have another shape. For example, each of the nanocrystals 125b may have a size of about 0.5nm to about 5nm. For example, each of the nanocrystals 125b may have a size of about 1nm to about 3nm.

[0076] Each of the nanocrystals 125b may include a semiconductor nitride having a band gap smaller than the band gap of the material of the matrix 125a. For example, each of the nanocrystals 125b may include a semiconductor nitride having a band gap greater than 1eV and smaller than the band gap of the material of the matrix 125a. For example, each of the nanocrystals 125b may include at least one of the following: AlN, GaN, GeN, SiN, CN, InN, YN, ScN or ZrN. However, the present disclosure is not limited thereto, and in this way, the nanocrystals 125a may include other materials. Each of the nanocrystals 125b may have, for example, a hexagonal structure (hexagonal crystal system structure) or a wurtzite structure. However, the present disclosure is not limited thereto, and in this way, the nanocrystals 125b may have another structure.

[0077] The nanocrystals 125b may be formed by heat treating the amorphous metal oxynitride of the substrate 125a at a certain temperature, such as about 800°C to about 1300°C, for example, about 900°C to 1300°C. Figure 4A and 4B A transmission electron microscopy (TEM) image showing AlN nanocrystals formed in an amorphous AlN thin film by heat treating the amorphous AlON thin film. Figure 4A TEM image of an amorphous AlON film formed by cross-deposition of AlO and AlN on a substrate. Figure 4B The results show that the amorphous AlON film was obtained by heat treating it at 1100°C. Figure 4A TEM image of amorphous AlON film shown in . Figure 4B , it can be seen that AlN nanocrystals, each having a size of about 5 nm and having a wurtzite structure, are spatially separated from each other within the amorphous AlON film.

[0078] According to an embodiment, the charge trapping layer 125 includes an amorphous metal oxynitride in which nanocrystals 125b having semiconductor characteristics are dispersed, thereby increasing the trapping energy and the trapping density as described below, and improving the charge retention characteristics by suppressing the movement of trapped charges between memory cells MC. Therefore, the memory operation characteristics can be improved by reducing the threshold voltage.

[0079] Figure 5A is a cross-sectional view showing a memory cell of a vertical NAND flash memory device 10 according to a comparative example. Figure 5A , a blocking dielectric layer 23, a charge trapping layer 25, a tunneling dielectric layer 27, and a channel layer 29 are sequentially disposed within the gate electrode 21. The charge trapping layer 25 includes SiN, the gate electrode 21 includes W (tungsten), the blocking dielectric layer 23 includes an AlO layer and a SiO layer, the tunneling dielectric layer 27 includes SiON, and the channel layer 29 includes polycrystalline Si.

[0080] Figure 5B Schematically showing the Figure 5A The electronic band structure taken along line I-I'. Figure 5B , the capture energy E of SiN of the charge trapping layer 25 T is smaller than the trapping energy E of the AlON of the base of the charge trapping layer 125 according to the embodiment described below. T .

[0081] Fig. 6A is a cross-sectional view showing a memory cell of a vertical NAND flash memory device 100 according to an embodiment. Fig. 6A, a blocking dielectric layer 123, a charge trapping layer 125, a tunneling dielectric layer 127, and a channel layer 129 are sequentially disposed within the gate electrode 121. The charge trapping layer 125 includes amorphous AlON including AlN nanocrystals, the gate electrode 121 includes W (tungsten), the blocking dielectric layer 123 includes AlO / SiO, the tunneling dielectric layer 127 includes SiON, and the channel layer 129 includes polycrystalline Si.

[0082] Figure 6B Schematically showing the Fig. 6A The electronic band structure taken by line II-II' in Figure 6B It can be seen that the capture energy E of the amorphous AlON of the substrate of the charge trapping layer 125 T Higher than Figure 5B The capture energy E of SiN is shown in T .

[0083] Figure 6C Schematically showing the Fig. 6A The electronic band structure taken by line III-III' in Figure 6C In the charge trapping layer 125, AlN nanocrystals each having a band gap smaller than that of amorphous AlON are spatially separated from each other within the amorphous AlN. Therefore, the trapping density N can be increased by forming an additional barrier (blocking) corresponding to the charges trapped in the AlN nanocrystals through an I-type band alignment (alignment) structure at the interface between the amorphous AlON and the AlN nanocrystals. T .

[0084] Hereinafter, regarding the charge trapping layer of the vertical NAND flash memory device according to the comparative example and the charge trapping layer of the vertical NAND flash memory device according to the embodiment, the trapping energy E is evaluated by using the Poole-Frenkel conduction equation (Equation 1) described above and the charge pump method. T and the capture density N T .

[0085] Figure 7 An example of the trapping energy of the charge trapping layer 25 in the vertical NAND flash memory device 10 according to the comparative example is shown. Figure 7 The results of using a SiN film as the charge trapping layer 25 are shown. Figure 7 , the left two figures show the results of SiN thin films formed by plasma enhanced atomic layer deposition (PEALD), and the right three figures show the results of SiN thin films formed by sputtering.

[0086] exist Figure 7 , 8AIn 9A, “C1” and “C2” represent CBM and valence band maximum (VBM), respectively, and “C3” represents the capture energy E T . The same applies below.

[0087] Fig. 8A and 8B One example of the trapping energy and the trapping density of the charge trapping layer 125 in the vertical NAND flash memory device 100 according to the embodiment is respectively shown. Fig. 8A and 8B Results are shown for the case where AlN nanocrystals are formed in an amorphous AlN thin film by heat treating the amorphous AlON thin film at 800°C. Fig. 8A and 8B Here, the oxygen content indicates the atomic fraction of oxygen among oxygen and nitrogen in the amorphous metal oxynitride of the base.

[0088] Reference Fig. 8A It can be seen that the amorphous AlON film including AlN nanocrystals has better Figure 7 The SiN film has high trapping energy as shown in . Figure 8B , it can be seen that the amorphous AlON film including AlN nanocrystals has a high trapping density.

[0089] Fig.9A and 9B Other examples of the trapping energy and the trapping density of the charge trapping layer 125 in the vertical NAND flash memory device according to embodiments are shown. Fig.9A and 9B Results are shown for the case where AlN nanocrystals are formed in an amorphous AlN thin film by heat-treating the amorphous AlON thin film at 1100°C.

[0090] Reference Fig.9A and 9B It can be seen that the amorphous AlON film including AlN nanocrystals has a Figure 7 The SiN film shown in FIG. 4 has a high trapping energy, and it can be seen that the amorphous AlON film including Al nanocrystals has a high trapping density.

[0091] According to the above embodiment, the charge trapping layer 125 includes a matrix 125a and nanocrystals 125b dispersed in the matrix 125a. The driving voltage can be reduced by forming the matrix 125a of an amorphous metal oxynitride having a dielectric constant greater than that of silicon nitride. Amorphous metal oxynitride has a lower CBO and a higher trapping energy E than silicon nitride. TTherefore, the charge movement in the direction perpendicular to the charge trapping layer 125 can be suppressed by the increase of the potential barrier at the interface between the charge trapping layer 125 and the tunnel dielectric layer 127 due to the decrease of CBO, and the trapping energy E T The increase in can suppress the movement of charges in the direction parallel to the charge trapping layer 125.

[0092] The nanocrystal 125b includes a semiconductor material having a band gap smaller than that of the material of the matrix 125a, thereby effectively confining charges within the nanocrystal 125b and, therefore, increasing the trapping density N T As described above, the charge trapping layer 125 includes an amorphous metal oxynitride in which nanocrystals 125b having semiconductor characteristics are dispersed, thereby increasing the trapping energy E T and the capture density N T , and improves the charge retention characteristics by suppressing the movement of trapped charges between memory cells MC. Therefore, the memory operation characteristics can be improved by lowering the threshold voltage.

[0093] In the above Figures 1 to 3 In the vertical NAND flash memory device 100 shown in FIG. 1 , nanocrystals 125b included in the charge trapping layer 125 are disposed to be buried in the matrix 125a, but are not limited thereto, and as will be described below, some of the nanocrystals 125a may be exposed to the outside of the matrix 125a.

[0094] Fig.10 is a cross-sectional view of a vertical NAND flash memory device 200 according to another embodiment. For convenience, Fig.10 A cross section of a memory cell MC of a vertical NAND flash memory device 200 is shown. Hereinafter, differences from the above-described embodiment are mainly described.

[0095] refer to Fig.10 , the blocking dielectric layer 123, the charge trapping layer 225, the tunneling dielectric layer 127, and the channel layer 129 are disposed in the gate electrode 121. According to an embodiment, the blocking dielectric layer 123, the charge trapping layer 225, the tunneling dielectric layer 127, and the channel layer 129 may be disposed in the gate electrode in this order. The gate electrode 121, the blocking dielectric layer 123, the tunneling dielectric layer 127, and the channel layer 129 have been described above, and thus their description is omitted.

[0096] The charge trapping layer 225 is disposed between the blocking dielectric layer 123 and the tunneling dielectric layer 127. The charge trapping layer 225 includes a matrix 225a and nanocrystals 225b disposed in the matrix 225a.

[0097] The substrate 225a may include an amorphous metal oxynitride, for example, a metal oxynitride having a dielectric constant greater than that of silicon nitride. For example, the substrate 125a may include at least one of AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON, but the present disclosure is not limited thereto.

[0098] Nanocrystals 225b may be separated from each other in space. According to an embodiment, some of nanocrystals 225b may be exposed to the outside of substrate 225a, and others may be embedded in substrate 225a. For example, nanocrystals 225b may include a first group of nanocrystals 225a disposed in substrate 225a and a second group of nanocrystals 225b disposed at a boundary between substrate 225 and a layer adjacent to substrate 225a. For example, nanocrystals 225b of the second group may be disposed in substrate 225a so that a first portion of nanocrystals 225b is disposed in substrate 225a and a second portion of nanocrystals 225b is disposed in a layer adjacent to substrate 225a. Nanocrystals 225b exposed to the outside of substrate 225a may be formed at an interface between charge trapping layer 225 and tunneling dielectric layer 127 and at an interface between charge trapping layer 255 and blocking dielectric layer 123.

[0099] For example, each of the nanocrystals 225b may have a spherical or ellipsoidal shape, but this is only an example. For example, each of the nanocrystals 225b may have a size of about 0.5nm to about 5nm (e.g., about 1nm to about 3nm). Each of the nanocrystals 225b may include a semiconductor nitride having a band gap smaller than the band gap of the material of the substrate 225a. Each of the nanocrystals 225b may include a semiconductor nitride having a band gap greater than 1eV and smaller than the band gap of the material of the substrate 225a. For example, each of the nanocrystals 125b may include at least one of the following: AlN, GaN, GeN, SiN, CN, InN, YN, ScN or ZrN, but is not limited thereto.

[0100] In the above, the case where the nanocrystals 225b are disposed at the interface between the charge trapping layer 225 and the tunneling dielectric layer 127 and at the interface between the charge trapping layer 255 and the blocking dielectric layer 123 has been described, but this is only an example. The nanocrystals 225b may be disposed only at one of the following: the interface between the charge trapping layer 225 and the tunneling dielectric layer 127 and the interface between the charge trapping layer 255 and the blocking dielectric layer 123.

[0101] The vertical NAND flash memory devices 100 and 200 described above may be used for data storage in various electronic devices. Fig.11is a conceptual diagram schematically illustrating a device architecture applicable to an electronic device according to an embodiment.

[0102] refer to Fig.11 , the electronic device may include a cache memory 1510, an ALU 1520, and a controller 1530 constituting a central processing unit (CPU) 1500, and the cache memory 1510 may include a static random access memory (SRAM). In addition, the electronic device includes a main memory 1600, an auxiliary memory 1700, and an input / output (IO) device 2500. The main memory 1600 may include a DRAM device, and the auxiliary memory 1700 may include the vertical NAND flash memory device 100 or 200 described above according to one or more embodiments. According to an embodiment, the electronic device architecture may be implemented in a form in which a computing unit device and a memory unit device are adjacent to each other in one chip without distinguishing subunits.

[0103] According to one or more of the above embodiments, in a vertical NAND flash memory device, a charge trapping layer includes a substrate and nanocrystals dispersed in the substrate. By forming a substrate of an amorphous metal oxynitride having a dielectric constant greater than that of silicon nitride, the driving voltage can be reduced, and the movement of charges in directions perpendicular to and parallel to the charge trapping layer can be suppressed by the amorphous metal oxynitride having a higher capture energy than that of silicon nitride. In addition, each of the nanocrystals may include a semiconductor nitride having a band gap smaller than that of the material of the substrate, thereby confining the charge within the nanocrystals, and thus, increasing the capture density. As described above, the charge trapping layer includes an amorphous metal oxynitride in which nanocrystals having semiconductor properties are dispersed, thereby increasing the capture energy and the capture density, and improving the charge retention characteristics by suppressing the movement of the captured charges between the memory cells. Therefore, the memory operation characteristics can be improved by reducing the threshold voltage. Although the embodiments have been described above, this is only an example, and various modifications thereof are possible for those skilled in the art.

[0104] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. A vertical NAND flash memory device, comprising: A plurality of cell arrays, each of the plurality of cell arrays comprising: Channel layer; a charge trapping layer disposed on the channel layer; and A plurality of gate electrodes are disposed on the charge trapping layer, The charge trapping layer comprises: a substrate comprising an amorphous metal oxynitride; and A plurality of nanocrystals are disposed in the matrix, the plurality of nanocrystals comprising nitride.

2. The vertical NAND flash memory device of claim 1, wherein the plurality of nanocrystals are spatially separated from each other in the matrix. 3 . The vertical NAND flash memory device of claim 1 , wherein the base comprises a metal oxynitride having a dielectric constant greater than that of silicon nitride.

4. The vertical NAND flash memory device of claim 3, wherein the substrate comprises at least one of: AlON, ZrON, LaON, AlSiON, HfAlON, LaSiON, AlZrON, LaAlON, HfAlON, or ZrSiON. 5 . The vertical NAND flash memory device of claim 1 , wherein each of the plurality of nanocrystals comprises a semiconductor nitride having a band gap greater than 1 eV and smaller than a band gap of a material of the base.

6. The vertical NAND flash memory device of claim 5, wherein the plurality of nanocrystals each comprise at least one of: AlN, GaN, GeN, SiN, CN, InN, YN, ScN, or ZrN.

7. The vertical NAND flash memory device of claim 1, wherein each of the plurality of nanocrystals has a size of about 0.5 nm to about 5 nm.

8. The vertical NAND flash memory device of claim 7, wherein each of the plurality of nanocrystals has a size of about 1 nm to about 3 nm.

9. The vertical NAND flash memory device of claim 1, wherein the plurality of nanocrystals are formed by heat-treating the amorphous metal oxynitride of the substrate at a heat-treating temperature.

10. The vertical NAND flash memory device of claim 9, wherein a thermal treatment temperature of the amorphous metal oxynitride is about 800°C to about 1300°C.

11. The vertical NAND flash memory device of claim 1, wherein the plurality of nanocrystals are embedded in the matrix.

12. The vertical NAND flash memory device of claim 1, wherein one or more of the plurality of nanocrystals are disposed in a boundary between the base and a layer adjacent to the base.

13. The vertical NAND flash memory device of claim 1, wherein the plurality of cell arrays are each disposed to extend vertically on a substrate.

14. The vertical NAND flash memory device of claim 13, further comprising a channel hole extending in a direction perpendicular to the substrate. 15 . The vertical NAND flash memory device of claim 14 , wherein the interior of the channel hole is filled with an insulating layer. 16 . The vertical NAND flash memory device of claim 14 , wherein the channel layer and the charge trapping layer are each formed in a cylindrical shape surrounding the channel hole.

17. The vertical NAND flash memory device of claim 16, wherein the plurality of gate electrodes are spaced apart from each other in a direction perpendicular to the substrate, and The plurality of gate electrodes each surround the charge trapping layer.

18. The vertical NAND flash memory device of claim 1, further comprising a tunneling dielectric layer disposed between the channel layer and the charge trapping layer.

19. The vertical NAND flash memory device of claim 1, further comprising a blocking dielectric layer disposed between the charge trapping layer and each of the plurality of gate electrodes.

20. An electronic device comprising the vertical NAND flash memory device according to any one of claims 1 to 19.

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