Data processing method and system and readable medium

Abstract

The invention provides a data processing method, which is applied to a first cache unit in a data processing system, and comprises the following steps: predicting a second cache unit as a target cache unit, and sending a first data reading request message to the second cache unit, the first data reading request message being used for reading first target data from the target cache unit; receiving first target data, and updating the state of the first target data according to the type of the first data reading request message; sending a first data reading response message to the node sending the first target data; by predicting the target cache unit, sending the data reading request to the predicted target cache unit, and directly returning the data response if the target cache unit is hit, the data reading time can be shortened, the data reading efficiency can be improved, and the system performance can be improved. The invention further provides a cache unit, a data processing device, a data processing system and a readable medium.

Description

Technical Field

[0001] The present disclosure relates to the field of computer processing technology, and in particular to a data processing method, system and readable medium. Background Art

[0002] SMP (Symmetric multiprocessing) system refers to a system in which multiple CPUs in a server work symmetrically, and there is no master-slave relationship between the CPUs. Each CPU shares the same physical memory, and the time required for each CPU to access any address in the memory is the same, so SMP is also called Uniform Memory Access (UMA).

[0003] For data access based on the SMP system, the cache unit usually directly initiates a data read request to the HN (Home Node), and the HN initiates data monitoring to other cache units storing the corresponding data, so as to read the data from other cache units and then send the data to the cache unit requesting to read the data. The above data access process has a large bus bandwidth overhead, high chip power consumption, and low data reading efficiency, which affects the processing performance of the processing core. Summary of the invention

[0004] The present disclosure provides a data processing method, system and readable medium.

[0005] In a first aspect, an embodiment of the present disclosure provides a data processing method, the method being applied to a first cache unit in a data processing system, comprising:

[0006] Predicting that the second cache unit is a target cache unit, and sending a first data read request message to the second cache unit; wherein the first data read request message is used to read first target data from the target cache unit;

[0007] receiving the first target data, and updating the state of the first target data according to the type of the first data read request message;

[0008] A first data read response message is sent to the node that sent the first target data.

[0009] In another aspect, an embodiment of the present disclosure further provides a data processing method, which is applied to a second cache unit in a data processing system, and includes:

[0010] receiving a first data read request message sent by a first cache unit, where the first data read request message is used to read first target data from the second cache unit;

[0011] In the case where it is determined that the first target data is stored in the second cache unit, the state of the first target data is updated according to the type of the first data read request message, and the first target data is sent to the first cache unit.

[0012] In another aspect, the present disclosure also provides a data processing method, which is applied to a data processing device in a data processing system, and the method includes:

[0013] Receive a status update message sent by the second cache unit, and obtain information, address information, and status information of the first cache unit carried in the status update message;

[0014] updating the state of the corresponding first target data to the state information according to the address information, and updating the cache unit to which the first target data belongs to the first cache unit;

[0015] Sending a status update response message to the second cache unit; or,

[0016] receiving a first data read request message sent by the second cache unit, and acquiring information, address information, and status information of the first cache unit carried in the first data read request message;

[0017] Reading first target data from the memory according to the address information, updating the state of the first target data to the state information, and updating the cache unit to which the first target data belongs to to the first cache unit;

[0018] The first target data is sent to the first cache unit, and a first data read response message sent by the first cache unit is received.

[0019] In another aspect, an embodiment of the present disclosure further provides a data processing method, which is applied to a data processing system including a first cache unit, a second cache unit, and a data processing device, the method comprising:

[0020] The first cache unit predicts that the second cache unit is a target cache unit, and sends a first data read request message to the second cache unit;

[0021] The second cache unit, when determining that the first target data requested by the first data read request message is stored in the second cache unit, updates the state of the first target data according to the type of the first data read request message, and sends the first target data to the first cache unit; when the type of the first data read request message is to read shared state data or to read exclusive state data, sends a state update message to the data processing device;

[0022] The data processing device obtains the information, address information and status information of the first cache unit carried in the status update message; updates the status of the corresponding first target data to the status information according to the address information, and updates the cache unit to which the first target data belongs to the first cache unit; or

[0023] The second cache unit sends a first data read request message to the data processing device when determining that the first target data requested by the first data read request message is not stored in the second cache unit;

[0024] The data processing device obtains the information, address information and status information of the first cache unit carried in the first data read request message; reads the first target data from the memory according to the address information, updates the status of the first target data to the status information, and updates the cache unit to which the first target data belongs to the first cache unit; and sends the first target data to the first cache unit.

[0025] In another aspect, an embodiment of the present disclosure further provides a data processing system, comprising at least one processing chip, wherein the processing chip comprises:

[0026] A first cache unit, configured to predict that a second cache unit is a target cache unit, and send a first data read request message to the second cache unit; and receive the first target data, and update a state of the first target data according to a type of the first data read request message;

[0027] a second cache unit, configured to receive a first data read request message sent by the first cache unit, and, if it is determined that the first target data requested by the first data read request message is stored in the second cache unit, update a state of the first target data according to a type of the first data read request message, and send the first target data to the first cache unit;

[0028] A data processing device, used to receive a status update message sent by the second cache unit, obtain the information, address information and status information of the first cache unit carried in the status update message; update the status of the corresponding first target data to the status information according to the address information, and update the cache unit to which the first target data belongs to the first cache unit; or, receive a first data read request message sent by the second cache unit, obtain the information, address information and status information of the first cache unit carried in the first data read request message; read the first target data from the memory according to the address information, update the status of the first target data to the status information, and update the cache unit to which the first target data belongs to the first cache unit; and send the first target data to the first cache unit.

[0029] On the other hand, an embodiment of the present disclosure further provides a computer-readable medium having a computer program stored thereon, wherein the program implements the data processing method as described above when executed.

[0030] The data processing method provided by the embodiment of the present disclosure is applied to the first cache unit in the data processing system, and the method includes: predicting that the second cache unit is the target cache unit, sending a first data read request message to the second cache unit, wherein the first data read request message is used to read the first target data from the target cache unit; receiving the first target data, and updating the state of the first target data according to the type of the first data read request message; sending a first data read response message to the node that sent the first target data; the embodiment of the present disclosure predicts the target cache unit, sends the data read request to the predicted target cache unit, and if the target cache unit is hit, the data response can be directly returned without first sending the data read request to the data processing device and then the data processing device monitors and returns the data response, which can reduce the data reading time, improve the data reading efficiency, and enhance the system performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 Schematic diagram of the process of requesting to read data for the relevant technology RDE;

[0032] Figure 2 A schematic diagram of a data processing flow with the first cache unit as the execution subject provided in an embodiment of the present disclosure Figure 1 ;

[0033] Figure 3 A schematic diagram of a data processing flow with the first cache unit as the execution subject provided in an embodiment of the present disclosure Figure 2 ;

[0034] Figure 4A schematic diagram of a process of a first cache unit providing an embodiment of the present disclosure as an execution subject requesting to read third target data;

[0035] Figure 5a Schematic diagram of predicting failure for cache unit;

[0036] Figure 5b A schematic diagram of a cache unit prediction failure according to an embodiment of the present disclosure;

[0037] Figure 6 A schematic diagram of a data processing flow using the second cache unit as the execution subject provided in an embodiment of the present disclosure Figure 1 ;

[0038] Figure 7 A schematic diagram of a data processing flow using the second cache unit as the execution subject provided in an embodiment of the present disclosure Figure 2 ;

[0039] Figure 8 The data processing flow diagram of the embodiment of the present disclosure with the data processing device as the execution body is shown in FIG. Figure 1 ;

[0040] Fig. 9 The data processing flow diagram of the embodiment of the present disclosure with the data processing device as the execution body is shown in FIG. Figure 2 ;

[0041] Fig.10 A schematic diagram of the RDE process when the target cache unit prediction is successful provided in an embodiment of the present disclosure;

[0042] Fig.11 A schematic diagram of an RDE process when a target cache unit prediction fails provided by an embodiment of the present disclosure;

[0043] Fig.12 A schematic diagram of the RDS process when the target cache unit prediction is successful provided in an embodiment of the present disclosure;

[0044] Fig.13 A schematic diagram of the RDI process when the target cache unit prediction is successful provided in an embodiment of the present disclosure;

[0045] Fig.14 A schematic diagram of the structure of a data processing system (SMP) provided in an embodiment of the present disclosure Figure 1 ;

[0046] Fig.15 A schematic diagram of the structure of the data processing system provided in the embodiment of the present disclosure Figure 2 ;

[0047] Fig.16 A schematic diagram of the structure of a data processing system (CC-NUMA) provided in an embodiment of the present disclosure Figure 3 . DETAILED DESCRIPTION

[0048] Example embodiments will be described more fully below with reference to the accompanying drawings, but the example embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete and to enable those skilled in the art to fully understand the scope of the present disclosure.

[0049] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0050] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will also be understood that when the terms "comprising" and / or "made of" are used in this specification, the presence of the features, wholes, steps, operations, elements and / or components is specified, but the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof is not excluded.

[0051] The embodiments described herein may be described with reference to plan views and / or cross-sectional views by means of idealized schematic diagrams of the present disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances. Therefore, the embodiments are not limited to the embodiments shown in the accompanying drawings, but include modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the accompanying drawings have schematic properties, and the shapes of the regions shown in the figures illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0052] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined as such herein.

[0053] The data processing method and system of the embodiments of the present disclosure are applicable to any data processing system involving atomic operations, such as an SMP system, a cache-coherent non-uniform memory access system (CC-NUMA), etc. In the following example, the SMP system is used as an example for description, but the embodiments of the present disclosure are not limited thereto.

[0054] Fig.14 A schematic diagram of an SMP system architecture is shown in FIG. Figure 6As shown in FIG. 1 , the SMP system includes: a processing core (Core), a secondary cache (L2), a network-on-chip (NOC), a host node (HN), and a memory (Memory). Both L2 and HN are connected to NOC, and HN is connected to the memory. L2 may include one or more cache units, each of which may be connected to one or more processing cores. Figure 6 In the SMP system shown, L2 includes three cache units L2-0, L2-1 and L2-2, where L2-0 is connected to the processing core Core0, L2-1 is connected to the processing core Core1, and L2-2 is connected to the processing core Core2. In the SMP system, HN interacts with each cache unit of L2 to achieve cache consistency. HN manages the entire memory space in units of cache lines and tracks the memory access of each L2 cache unit.

[0055] MESI represents four states of cache line data. By switching these four states, the purpose of managing cache data is achieved. The states of MESI and their descriptions are shown in Table 1:

[0056] Table 1

[0057]

[0058] HN can track the access of all cache line data by maintaining a directory table (dir table). The data structure of the directory table (dir table) is shown in Table 2:

[0059] Table 2

[0060] State Bit width (VEC) state[1:0] vec[n-1:0]

[0061] In Table 2, each entry corresponds to a cache line data, and the location of the cache line data can be determined based on the address information. An entry includes a state field (State) and a bit width field (VEC). The state field records the state of the data read by the cache unit, and the bit width field corresponds to the number n of cache units in L2. Each bit corresponds to a cache unit in L2, indicating which cache unit in L2 stores the data.

[0062] The state field in Table 2 will only record the three states of ESI, because after the L2 cache unit gets the data in the E state, the action of modifying the data will not notify HN, so HN does not know whether the state of the data stored in the L2 cache unit is the E state or the M state. For example, dir.state = E, VEC = 'b001, indicating that the data of this cache line in L2-0 may be in the M state, E state, S state (downgraded from the E state to the S state without notifying HN), I state (data is replaced from the cache unit without notifying HN); dir.state = S, VEC = 'b011, indicating that the data of this cache line in L2-0 and L2-1 may be in the S state or I state (data is replaced from the cache unit without notifying HN); dir.state = I, indicating that no L2 cache unit stores the cache line data.

[0063] Figure 1 FIG. 1 is a flow chart of RDE requesting to read data in the related art. Figure 1 As shown, the process includes the following steps:

[0064] Step 1, L2-0 sends an RDE (Read Date E, exclusive state data read request) message to HN to request to read data.

[0065] Step 2: After receiving the RDE message, HN queries Table 2 according to the address information carried in the RDE message and finds that the data corresponding to the address information is in the E state in L2-1. Then, it sends a SNPtoI (Snoop to Invalid) message to L2-1 to snoop L2-1.

[0066] Step 3, after receiving the SNPToI message, L2-1 changes the data from the E / M state to the I state, and returns SNPRSPI_DATA (invalid state snoop response data, that is, the data requested to be read by L2-0) to HN.

[0067] Step 4: After receiving SNPRSPI_DATA, HN modifies the data to point to L2-0 and returns a DATE (DateE, exclusive status data response) message to L2-0, which carries the data requested to be read by L2-0.

[0068] Step 5: L2-0 caches the data and changes the state of the data to E state.

[0069] Step 6: L2-0 returns a CmpAck (data read response) message to HN, notifying HN that the RDE request processing is completed.

[0070] The defect of the related technical solution is that the data read request of L2-0 must be sent to HN for query, and then HN initiates monitoring to other cache units and reads data from other cache units. The data reading time is long, the reading efficiency is low, and the processing performance of the processing core is low.

[0071] In order to solve the above technical problems, the embodiment of the present disclosure provides a data processing method, which is applied to a data processing system, in which the lock performance is particularly important. The data processing system can be an SMP system or a CC-NUMA system. In the embodiment of the present disclosure, Fig.14 The data processing system (SMP) shown in the figure is used as an example for explanation, wherein L2-0 is the first cache unit, L2-1 is the second cache unit, and the data processing device interacting with L2-1 and L2-0 is HN.

[0072] Figure 2 A schematic diagram of a data processing flow with the first cache unit as the execution subject provided in an embodiment of the present disclosure Figure 1 ,like Figure 2 As shown, the data processing method is applied to a first cache unit in a data processing system, and comprises the following steps:

[0073] Step 11, predicting that the second cache unit is the target cache unit, and sending a first data read request message to the second cache unit; wherein the first data read request message is used to read the first target data from the target cache unit.

[0074] The target cache unit is a cache unit suspected of storing the first target data. The target cache unit and the first cache unit can be cache units of the same level or cache units of different levels. In the embodiment of the present disclosure, the target cache unit and the first cache unit are cache units of the same level as an example for explanation.

[0075] In this step, L2-0 predicts that the requested data (i.e., the first target data) is stored in L2-1, that is, L2-0 predicts that the target cache unit is L2-1, and then sends a first data read request message to L2-1, so that L2-1 returns the first target data. The first data request message can be one of the following: RDE message, RDS (Read Date S, shared state data read request) message, RDI (Read Date I, invalid state data read request) message, wherein the RDE message indicates a request to read data and record it as E state, RDS indicates a request to read data and record it as S state, and RDI indicates a request to read data and record it as I state.

[0076] Step S12: receiving the first target data, and updating the state of the first target data according to the type of the first data read request message.

[0077] Types of the first data read request message include RDE message, RDS message, and RDI message.

[0078] In this step, after receiving the first target data, L2 - 0 updates the state of the first target data to a corresponding state according to whether the type of the first data read request message is an RDE message, an RDS message, or an RDI message.

[0079] In some embodiments, the node sending the first target data may be a second cache unit or a data processing device. If the target cache unit prediction is successful in step S11, it means that the predicted target cache unit L2-1 stores the first target data, and the first target data is sent from L2-1 to L2-0; if the target cache unit prediction fails in step S11, it means that the predicted target cache unit L2-1 does not store the first target data, and the first target data is sent from HN to L2-0.

[0080] In some embodiments, updating the state of the first target data according to the type of the first data read request message includes: when the type of the first data read request message is to read shared state data, that is, the first data read request message is an RDS message, updating the state of the first data to a shared state (S state); when the type of the first data read request message is to read exclusive state data, that is, the first data read request message is an RDE message, updating the state of the first data to an exclusive state (E state); when the type of the first data read request message is to read invalid state data, that is, the first data read request message is an RDI message, keeping the state of the first data in an invalid state (I state).

[0081] Step S13: Send a first data read response message to the node that sends the first target data.

[0082] In this step, L2-0 sends a CmpAck message to the corresponding node sending the first target data.

[0083] The data processing method provided by the embodiment of the present disclosure is applied to the first cache unit in the data processing system, and the method includes: predicting the second cache unit as the target cache unit, sending a first data read request message to the second cache unit, wherein the first data read request message is used to read the first target data from the target cache unit; receiving the first target data, and updating the state of the first target data according to the type of the first data read request message; sending a first data read response message to the node that sent the first target data; the embodiment of the present disclosure predicts the target cache unit, sends the data read request to the predicted target cache unit, and if the target cache unit hits, the data response can be directly returned without first sending the data read request to the data processing device and then the data processing device monitors and returns the data response, which can reduce the data reading time, improve the data reading efficiency, and enhance the system performance. It should be noted that the prediction of the target cache unit can be performed based on multiple previous data reading processes, and the embodiment of the present disclosure is described by taking the prediction of the target cache unit based on the previous data reading process as an example.

[0084] In some embodiments, after receiving the first target data (i.e., step S12), the data processing method further includes the following steps: when the type of the first data read request message is to read shared state data or read exclusive state data, cache the first target data. That is, if it is an RDS message or an RDE message, L2-0 caches the first target data locally after receiving the first target data. If it is an RDI message, there is no need to cache the first target data, but directly send it to the processing core requesting the first target data.

[0085] In the case where the target cache unit prediction fails, the node sending the first target data is a data processing device. In some embodiments, Figure 3 As shown, after sending the first data read response message to the data processing device (i.e., step S13), the data processing method may further include the following steps:

[0086] Step S21: Send a second data read request message to the data processing device, where the second data read request message is used to read second target data from the data processing device.

[0087] In this step, if L2-0 fails to predict the target cache unit, a second data read request message is sent to HN to request HN to read the second target data. The second data read request message may be one of the following: RDE message, RDS message, RDI message.

[0088] Step S22: receiving the second target data sent by the data processing device, and sending a second data read response message to the data processing device.

[0089] In this step, after receiving the second target data sent by HN, L2-0 returns a CmpAck message to HN.

[0090] It can be seen from the above steps S21-S22 that if the previous target cache unit prediction fails and the first target data requested to be read is provided by HN, when it is necessary to request to read the second target data again, L2-0 directly requests HN to read the data, and HN reads the second target data from the memory and directly returns it to L2-0.

[0091] In some embodiments, before predicting that the second cache unit is the target cache unit (ie, step S11), the data processing method further includes the step of requesting to read data n times, where n is an integer greater than or equal to 1.

[0092] Accordingly, the prediction of the second cache unit as the target cache unit (i.e., step S11) includes the following steps: determining the cache unit to which the data requested to be read each time belongs, and determining the second cache unit as the target cache unit based on each cache unit. In other words, the target cache unit is predicted based on the source of the data requested to be read once or multiple times previously.

[0093] Figure 4 The first cache unit provided in the embodiment of the present disclosure is a flowchart of executing a request of a subject to read the third target data, such as Figure 4 As shown, the step of requesting to read data once in n times includes the following steps:

[0094] Step S31: Send a third data read request message to the data processing device.

[0095] In this step, L2-0 sends a third data read request message to HN, and the third data read request message may be one of the following: RDE message, RDS message, RDI message. It should be noted that the type of the third data read request message may be the same as or different from the type of the first data read request message.

[0096] Step S32: receiving the third target data and the cache unit information storing the third target data sent by the data processing device, and updating the state of the third target data according to the type of the third data read request message.

[0097] If HN finds that the third data is stored in L2-1, it sends a SNPtoI message to L2-1 to monitor L2-1. After receiving the SNPToI message, L2-1 updates the status of the data and returns the third data to HN. HN updates the cache unit to which the third data belongs by updating the bit width field in Table 2, and returns the third data and the source of the third data (that is, from which cache unit the third data is read) to L2-0.

[0098] In this step, after L2-0 receives the third target data and the cache unit information storing the third target data sent by HN, it updates the state of the third target data according to the type of the third data read request message, that is, updates the state of the third data from I state to E state, S state or keeps I state unchanged.

[0099] Step S33: Send a third data read response message to the data processing device.

[0100] In this step, after completing the third data status update, L2-0 returns a CmpAck message to HN to notify HN that the third data reading process is completed.

[0101] By initiating a third target data read request to the HN, the source of the third target data is determined so as to serve as a target cache unit predicted in subsequent data read requests.

[0102] In the case of a target cache unit prediction failure, the data read request will be sent to the predicted target cache unit first, and then to the HN. In the actual topology, routing detours may occur, resulting in additional delays. Figure 5a As shown, L2-0 is the cache unit that initiates the data read request, and L2-1 is the predicted target cache unit. When the prediction of the target cache unit fails, the actual message transmission path is shown by the arrow, that is, first from L2-0 through the routing module xp to L2-1, and then through the routing module from L2-1 to HN. It can be seen that there is a detour in the routing path.

[0103] In order to solve the above problems, the disclosed embodiments further define the strategy of predicting the target cache unit. In some embodiments, the second cache unit is determined according to each cache unit, including the following steps: in each cache unit, a cache unit located on the route from the first cache unit to the data processing device is determined as the second cache unit. In other words, a cache unit on the route from L2-0 (i.e., the cache unit that initiates the data read request) to HN is selected as the target cache unit.

[0104] like Figure 5b As shown, selecting L2-2 on the routing path from L2-0 to HN as the target cache unit can avoid detours in the routing path, reduce data reading latency, and further improve data reading efficiency.

[0105] Figure 6 A schematic diagram of a data processing flow using the second cache unit as the execution subject provided in an embodiment of the present disclosure Figure 1 ,like Figure 6As shown, the data processing method is applied to the second cache unit in the data processing system, and includes the following steps:

[0106] Step S41: receiving a first data read request message sent by a first cache unit, where the first data read request message is used to read first target data from a second cache unit.

[0107] In this step, L2-1 receives the first data read request message sent by L2-0, and obtains the address information carried in the first data read request message.

[0108] Step S42: when it is determined that the first target data is stored in the second cache unit, the state of the first target data is updated according to the type of the first data read request message, and the first target data is sent to the first cache unit.

[0109] In this step, L2-1 queries locally according to the address information. If the corresponding first target data is found, that is, the data hits, the state of the first target data is updated according to the type of the first data read request message, and the first target data is returned to L2-0.

[0110] In some embodiments, updating the status of the first target data according to the type of the first data read request message includes: when the type of the first data read request message is to read shared status data, that is, the first data read request message is an RDS message, updating the status of the first data to a shared status; when the type of the first data read request message is to read exclusive status data, that is, the first data read request message is an RDE message, updating the status of the first data to an invalid status; when the type of the first data read request message is to read invalid status data, that is, the first data read request message is an RDI message, keeping the status of the first data unchanged.

[0111] It can be seen from steps S41-S42 that when the target cache unit is predicted successfully, the predicted second cache unit L2-1 can directly return the first target data to L2-0 without the need for interaction between the first cache unit and HN, thereby saving bandwidth and power consumption, reducing data reading time, improving data reading efficiency, and enhancing system performance.

[0112] In some embodiments, after sending the first target data to the first cache unit, the data processing method further includes the following steps: receiving a first data read response message sent by the first cache unit. That is, after receiving the first target data sent by L2-1, L2-0 returns a CmpAck message to L2-1.

[0113] like Figure 7As shown, after updating the state of the first target data according to the type of the first data read request message (ie, step S42), the data processing method may further include the following steps:

[0114] Step S51, when the type of the first data read request message is to read shared state data or to read exclusive state data, a state update message is sent to the data processing device, where the state update message carries information, address information and state information of the first cache unit.

[0115] The status update message is used to instruct the data processing device to update the status of the first target data according to the status information and the address information, and to update the cache unit to which the first target data belongs according to the information of the first cache unit.

[0116] In this step, if L2-1 receives an RDE message or an RDS message sent by L2-0, a status update message (UpDir) is sent to HN. The status update message carries information of the first cache unit, address information and status information, wherein the address information is the address of the first target data, and HN can determine the cache unit to which the first target data in Table 2 belongs according to the address information. The status information is the status of the first target data that needs to be recorded in Table 2. The status update message is used to instruct HN to modify the status of the first target data to the status information in the status field of Table 2, and update the cache unit to which the first target data belongs in the bit width field of Table 2. In the embodiment of the present disclosure, the cache unit to which the first target data belongs is the first cache unit.

[0117] Step S52: receiving a status update response message sent by the data processing device.

[0118] In this step, L2-1 receives the status update response message (UpCmp) sent by HN. The UpCmp message is sent by HN to L2-1 after the status update of the first target data and the update of the corresponding cache unit are completed. After L2-1 receives the CmpAck message sent by L2-0 and the UpCmp message sent by HN, it indicates that the first data read request process is completed.

[0119] In some embodiments, after receiving the first data read request message sent by the first cache unit (i.e., step S41), the data processing method may further include the following steps: when it is determined that the first target data is not stored in the second cache unit, sending the first data read request message to the data processing device, so that the data processing device reads the first target data from the memory and sends the first target data to the first cache unit, and updates the state of the first target data and the cache unit to which the first target data belongs. That is, in the case of a target cache unit prediction failure, L2-1 receives the first target data read request message sent by L2-0, and does not query the first target data locally, then forwards the first target data read request message to HN, and HN reads the first target data from the memory and directly returns it to L2-0. In addition, HN also updates the state of the first target data and the cache unit to which the first target data belongs in Table 2. Among them, if the first data read request message is an RDS message, the HN updates the state of the first target data to the S state and records the L2-0 to which it belongs; if the first data read request message is an RDE message, the HN updates the state of the first target data to the E state and records the L2-0 to which it belongs; if the first data read request message is an RDI message, the HN does not update the state of the first target data.

[0120] Figure 8 The data processing flow diagram of the embodiment of the present disclosure with the data processing device as the execution body is shown in FIG. Figure 1 ,like Figure 8 As shown, the data processing method is applied to a data processing device in a data processing system, comprising the following steps:

[0121] Step S61: receiving a status update message sent by the second cache unit, and obtaining information, address information, and status information of the first cache unit carried in the status update message.

[0122] In this step, HN receives the status update message (UpDir) sent by L2-1, and obtains the information of L2-0, the address information of the first target data and the status information of the first target data carried therein, where the status information of the first target data is the modified status information of the first target data.

[0123] Step S62: updating the state of the corresponding first target data to the state information according to the address information, and updating the cache unit to which the first target data belongs to the first cache unit.

[0124] In this step, HN determines the entry corresponding to the address information in Table 2, which is the entry corresponding to the first target data, updates the status field in the entry to the status information, and updates the bit width field in the entry to the information of the first cache unit.

[0125] Step S63: Send a status update response message to the second cache unit.

[0126] In this step, HN sends a status update response message (UpCmp) to L2-1.

[0127] Step S61-step S63 is the process of successful prediction of the target cache unit. When the target cache unit is predicted successfully, HN only needs to modify the state of the first target data requested to be read by the first cache unit and the cache unit to which it belongs in Table 2 without reading data from the memory.

[0128] Fig. 9 The data processing flow diagram provided by the embodiment of the present disclosure with the data processing device as the execution subject Figure 2 ,like Fig. 9 As shown, the data processing method is applied to a data processing device in a data processing system, comprising the following steps:

[0129] Step S71: receiving a first data read request message sent by a second cache unit, and obtaining information, address information, and status information of the first cache unit carried in the first data read request message.

[0130] In this step, HN receives the first data read request message sent by L2-1, and obtains the information of L2-0, the address information of the first target data and the state information of the first target data carried therein, where the state information of the first target data is the modified state information of the first target data.

[0131] The first data request message may be one of the following: an RDE message, an RDS message, or an RDI message.

[0132] Step S72, reading the first target data from the memory according to the address information, updating the state of the first target data to the state information, and updating the cache unit to which the first target data belongs to to the first cache unit.

[0133] In this step, HN obtains the first target data by querying the memory according to the address information, determines the entry corresponding to the address information in Table 2, which is the entry corresponding to the first target data, updates the status field in the entry to the status information, and updates the bit width field in the entry to the information of the first cache unit.

[0134] Step S73: Send the first target data to the first cache unit, and receive a first data read response message sent by the first cache unit.

[0135] In this step, HN sends the first target data read from the memory to L2 - 0 , and receives a first data read response message (CmpAck) sent by L2 - 0 .

[0136] Step S71-Step S73 is the process of target cache unit prediction failure. In the case of target cache unit prediction failure, HN not only needs to modify the state of the first target data requested to be read by the first cache unit and the cache unit to which it belongs in Table 2, but also needs to read the first target data from the memory and directly return the first target data to the first cache unit.

[0137] The present disclosure also provides a data processing method, which is applied to a data processing system including a first cache unit, a second cache unit, and a data processing device, and the method includes the following steps:

[0138] Step S81: The first cache unit predicts that the second cache unit is a target cache unit, and sends a first data read request message to the second cache unit.

[0139] Step S82, when the second cache unit determines that the first target data requested by the first data read request message is stored in the second cache unit, it updates the status of the first target data according to the type of the first data read request message and sends the first target data to the first cache unit; when the type of the first data read request message is to read shared status data or read exclusive status data, it sends a status update message to the data processing device.

[0140] Step S83, the data processing device obtains the information, address information and status information of the first cache unit carried in the status update message; updates the status of the corresponding first target data to the status information according to the address information, and updates the cache unit to which the first target data belongs to the first cache unit.

[0141] After the first cache unit predicts that the second cache unit is the target cache unit and sends the first data read request message to the second cache unit (ie, step S81), the method further includes the following steps:

[0142] Step S82': when the second cache unit determines that the first target data requested by the first data read request message is not stored in the second cache unit, the second cache unit sends the first data read request message to the data processing device.

[0143] Step S83', the data processing device obtains the information, address information and status information of the first cache unit carried in the first data read request message; reads the first target data from the memory according to the address information, updates the status of the first target data to the status information, and updates the cache unit to which the first target data belongs to the first cache unit; sends the first target data to the first cache unit.

[0144] In order to clearly illustrate the technical solution of the embodiment of the present disclosure, the following Fig.10, the RDE process when the target cache unit prediction is successful is described. Fig.10 As shown, the RDE processing flow includes the following steps:

[0145] Step 101, L2-0 sends an RDE message to HN to request to read data.

[0146] Step 102, after receiving the RDE message, HN queries Table 2 according to the address information (address A) carried in the RDE message, and finds that the third target data corresponding to the address information is in the E state in L2-1, then sends a SNPtoI message to L2-1 to monitor L2-1.

[0147] Step 103, after receiving the SNPToI message, L2-1 changes the third target data from the E / M state to the I state, and returns SNPRSPI_DATA (ie, the third target data requested to be read by L2-0) to HN.

[0148] Step 104, after receiving SNPRSPI_DATA, HN modifies the data to point to L2-0, and returns SNPRSPI_DATA (ie, the third target data) to L2-0, which carries the source of the third target data, ie, L2-1.

[0149] Step 105: L2-0 caches the data and changes the state of the data to the E state.

[0150] The above steps 101 - 105 are a process of requesting to read address A.

[0151] Step 106: The third target data received by L2-0 in step 104 carries the information of L2-1, so the target cache unit is predicted to be L2-1, and the RDE message carrying address B is directly sent to L2-1.

[0152] Step 107, after L2-1 receives the RDE message carrying address B, it queries the cache and finds that the first target data is hit, and directly returns the DATE message carrying the first target data to L2-0, and updates the state of the first target data from E state to I state, and at the same time sends an UpDir message to HN. The UpDir message carries L2-0 information, address B and state E, which is used to instruct HN to update the state of the second target data corresponding to address B in Table 2 to E state and point the second target data to L2-0.

[0153] Step 108: After receiving the first target data, L2-0 caches the first target data, updates its state to the E state, and returns a CmpAck message to L2-1.

[0154] Step 109: After updating Table 2, HN returns an UpCmp message to L2-1.

[0155] After L2-1 receives the UpCmp message and the CmpAck message, it indicates that the RDE processing flow for address B is completed.

[0156] It can be seen from the above steps 101 to 109 that the embodiment of the present disclosure predicts the target cache unit of this time according to the result of the previous data read request. If the target cache unit prediction is successful, the time for reading data is greatly reduced, and the number of times data flows in the NOC is reduced, thereby improving processing performance and reducing power consumption.

[0157] In order to clearly illustrate the technical solution of the embodiment of the present disclosure, the following Fig.11 , the RDE process when the target cache unit prediction fails is explained. Fig.11 As shown, the RDE processing flow includes the following steps:

[0158] Steps 201 to 205 are the process of RDE requesting to read address A. Fig.10 Steps 101 to 105 are the same and will not be repeated here.

[0159] Step 206: The third target data received by L2-0 in step 204 carries the information of L2-1, so the target cache unit is predicted to be L2-1, and the RDE message carrying address B is directly sent to L2-1.

[0160] Step 207: After L2-1 receives the RDE message carrying address B, it searches the cache and finds a miss, and then sends the RDE message carrying address B to HN.

[0161] Step 208, after receiving the RDE message carrying address B, HN reads the corresponding first target data from the memory according to address B, returns a DATE message to L2-0, and updates the cache unit to which the first target data in Table 2 belongs to L2-0.

[0162] Step 209, after receiving the first target data sent by HN, L2-0 caches the first target data, changes its state from I state to E state, and sends a CmpAck message to HN to notify HN that the RDE data reading process requesting to read address B is completed.

[0163] The above steps 206 to 209 are the RDE process for the target cache prediction failure of address B. It should be noted that since the first target data corresponding to address B comes from HN, the next RDE of address C can be directly initiated to HN without predicting the target cache unit (see Fig.11In step 210-step 212), the RDE process of address C is the same as the RDE process of address B, which will not be repeated here.

[0164] In order to clearly illustrate the technical solution of the embodiment of the present disclosure, the following Fig.12 , the RDS process when the target cache unit prediction is successful is described. Fig.12 As shown, the RDS processing flow includes the following steps:

[0165] Steps 301 to 305 are the process of RDS requesting to read address A. Fig.10 Steps 101 to 105 are the same, except that: in step 303, after L2-1 receives the SNPToI message, it changes the third target data from the E / M state to the S state; in step 304, after HN receives SNPRSPI_DATA, it updates the state of the third target data to the E state, and points the third target data to L2-0 and L2-1; in step 305, after L2-0 receives the third target data, it updates the state of the third target data to the S state.

[0166] Step 306: The third target data received by L2-0 in step 304 carries the information of L2-1, so the target cache unit is predicted to be L2-1, and the RDS message carrying address B is directly sent to L2-1.

[0167] Step 307, after L2-1 receives the RDE message carrying address B, it queries the cache and finds that the first target data is hit, and directly returns a DATS (Date S, shared data read response) message to L2-0, which carries the first target data, updates the state of the first target data from the E / M state to the S state, and sends an UpDir message to HN at the same time. The UpDir message carries L2-0 and L2-1 information, address B and state S, which is used to instruct HN to update the state of the first target data corresponding to address B in Table 2 to the S state and point the first target data to L2-0 and L2-1.

[0168] Step 308: After receiving the first target data, L2-0 caches the first target data, updates its state to the S state, and returns a CmpAck message to L2-1.

[0169] Step 309: After updating Table 2, HN returns an UpCmp message to L2-1.

[0170] After L2-1 receives the UpCmp message and the CmpAck message, it indicates that the RDS processing flow for address B is completed.

[0171] It should be noted that the target cache unit prediction success process of RDS and RDE is the same, the difference lies in the different data update states of HN and L2-1.

[0172] It can be seen from the above steps 301 to 309 that the embodiment of the present disclosure predicts the target cache unit of this time according to the result of the previous data read request. If the target cache unit prediction is successful, the time for reading data is greatly reduced, and the number of times data flows in the NOC is reduced, thereby improving processing performance and reducing power consumption.

[0173] In order to clearly illustrate the technical solution of the embodiment of the present disclosure, the following Fig.13 , the RDI process when the target cache unit prediction is successful is described. Fig.13 As shown, the RDI processing flow includes the following steps:

[0174] Steps 401 to 405 are the process of RDI requesting to read address A. Fig.10 Steps 101 to 105 are the same, except that: in step 403, after L2-1 receives the SNPToI message, it does not update the status of the third target data; in step 404, after HN receives SNPRSPI_DATA, it does not update the status of the third target data; in step 405, after L2-0 receives the third target data, it does not update the status of the third target data.

[0175] Steps 406 to 408 are the process of RDI requesting to read address B, including the following steps:

[0176] Step 406: The third target data received by L2-0 in step 404 carries the information of L2-1, so the target cache unit is predicted to be L2-1, and the RDI message carrying the address B is directly sent to L2-1.

[0177] Step 407, after receiving the RDI message carrying address B, L2-1 queries the cache and finds that the first target data is hit, and directly returns a DATI (Date I, invalid data read response) message to L2-0 without changing the message to carry the first target data.

[0178] Step 408: After receiving the first target data, L2-0 returns a CmpAck message to L2-1.

[0179] It can be seen from the above steps 401 to 409 that the embodiment of the present disclosure predicts the target cache unit of this time according to the result of the previous data read request. If the target cache unit prediction is successful, the time for reading data is greatly reduced, and the number of times data flows in the NOC is reduced, thereby improving processing performance and reducing power consumption.

[0180] The disclosed embodiments improve the transmission process of data read requests in a cache coherence system and can be applied to systems such as SMP and CC-NUMA, where the latency of data access is particularly important for performance. The disclosed embodiments can reduce the latency of data reads in the system, while also reducing bandwidth overhead and chip power consumption.

[0181] In the disclosed embodiment, by predicting the target cache unit, a data read request is sent to the predicted target cache unit. If the requested data is hit in the target cache unit, a data response can be directly returned without first sending the data read request to the HN and then the HN monitoring and returning the data response. In the case that the target cache unit is predicted successfully, the disclosed embodiment can reduce the data read time and reduce the number of data flows in the NOC, thereby improving performance and reducing power consumption.

[0182] The present disclosure also provides a data processing system, the data processing system comprising at least one processing chip, the processing chip comprising:

[0183] The first cache unit is used to predict that the second cache unit is a target cache unit, send a first data read request message to the second cache unit; and receive the first target data, and update the state of the first target data according to the type of the first data read request message;

[0184] a second cache unit, configured to receive a first data read request message sent by the first cache unit, and when determining that the first target data requested by the first data read request message is stored in the second cache unit, update the state of the first target data according to the type of the first data read request message, and send the first target data to the first cache unit;

[0185] A data processing device, used to receive a status update message sent by a second cache unit, obtain information, address information and status information of a first cache unit carried in the status update message; update the status of corresponding first target data to status information according to the address information, and update the cache unit to which the first target data belongs to the first cache unit; or, receive a first data read request message sent by the second cache unit, obtain information, address information and status information of the first cache unit carried in the first data read request message; read the first target data from a memory according to the address information, update the status of the first target data to status information, and update the cache unit to which the first target data belongs to the first cache unit; and send the first target data to the first cache unit.

[0186] In some embodiments, the processing system further includes at least two levels of cache, each level of cache includes a memory and at least one cache unit, and the data processing device may be a master node (HN), or the data processing device may also be one of the cache units at different levels from the first cache unit and the second cache unit. That is, the embodiments of the present disclosure are not limited to the cache unit accessing the memory data by interacting with the HN, and the cache unit may also access the memory data by interacting with cache units at other levels.

[0187] It should be noted that the processing system may further include an on-chip network NOC, and cache units at different levels and the master node may communicate through the NOC.

[0188] like Fig.15 As shown, the processing system includes a second-level cache L2, a third-level cache L3 and a fourth-level cache L4, L2 includes three cache units L2-0, L2-1, and L2-2, L2-0 is connected to the processing core Core0, L2-1 is connected to the processing core Core1, and L2-2 is connected to the processing core Core2. L3 includes two processing units L3-1 and L3-2, and the data processing device can be a cache unit of the master node HN or L4.

[0189] The data processing system may be a symmetric multi-processor system (Symmetric Multi-Processor, SMP) or a cache-coherent non-uniform memory access system (Cache-Coherent Non-Uniform Memory Access, CC-NUMA).

[0190] In some embodiments, there may be at least two processing chips, each processing chip is connected to at least another processing chip, and the processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

[0191] In some embodiments, the processing chip includes but is not limited to: a central processing unit (CPU), a graphics processing unit (GPU), an embedded neural network processor (NPU), and a data processor (DPU).

[0192] In a data processing system including multiple processing chips, such as a CC-NUMA system, a cache unit can access memory data of the same processing chip as well as memory data of other processing chips, that is, cross-CPU access is achieved.

[0193] In a CC-NUMA system, distributed memories are connected to form a single memory. There is no page copying or data copying between memories, and there is no software message transmission. It is relatively fast for a processing chip to access local memory, but it is relatively slow to access remote memory belonging to another processing chip because additional delays are generated through the interconnection network. CC-NUMA has only one memory image, and the memory of each processing chip is physically connected using copper cables and some intelligent hardware. Cache-Coherent means that no software is required to maintain the consistency of multiple copies of data, nor is software required to implement data transmission between the operating system and the application system. The CC-NUMA system is the same as the SMP system. A single operating system and multiple processors are managed completely at the hardware level.

[0194] like Fig.16 The CC-NUMA system shown includes four processing chips, each of which is connected in pairs, and a cache unit in one of the processing chips can implement cross-chip memory data access. It should be noted that the embodiment of the present disclosure does not limit the connection method of each processing chip in the CC-NUMA system. For example, each processing chip can also be connected in series.

[0195] The embodiments of the present disclosure further provide a computer-readable medium on which a computer program is stored, wherein the computer program, when executed, implements the data processing method provided in the aforementioned embodiments.

[0196] It will be appreciated by those skilled in the art that all or some of the steps in the method disclosed above, the functional modules / units in the device may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those of ordinary skill in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0197] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A data processing method, characterized in that: Applied to a first cache unit in a data processing system, the method comprises: Predicting that the second cache unit is a target cache unit, and sending a first data read request message to the second cache unit; wherein the first data read request message is used to read first target data from the target cache unit; receiving the first target data, and updating the state of the first target data according to the type of the first data read request message; A first data read response message is sent to the node that sent the first target data.

2. The method according to claim 1, characterized in that The node sending the first target data includes the second cache unit or a data processing device.

3. The method according to claim 2, characterized in that The node sending the first target data is a data processing device. After sending the first data read response message to the data processing device, the method further includes: Sending a second data read request message to the data processing device, where the second data read request message is used to read second target data from the data processing device; The second target data sent by the data processing device is received, and a second data read response message is sent to the data processing device.

4. The method according to claim 1, characterized in that The updating the state of the first target data according to the type of the first data read request message includes: When the type of the first data read request message is to read shared state data, updating the state of the first data to a shared state; In a case where the type of the first data read request message is to read data in an exclusive state, updating the state of the first data to an exclusive state; In a case where the type of the first data read request message is to read invalid state data, the state of the first data is maintained as an invalid state.

5. The method according to claim 1, characterized in that After receiving the first target data, the method further includes: In a case where the type of the first data read request message is to read shared state data or to read exclusive state data, the first target data is cached.

6. The method according to any one of claims 1 to 5, characterized in that: Before predicting that the second cache unit is the target cache unit, the method further includes the step of requesting to read data n times, where n is an integer greater than or equal to 1; The predicting second cache unit as a target cache unit includes: The cache units to which the data requested to be read each time belongs are determined, and the second cache unit is determined as the target cache unit according to the cache units.

7. The method according to claim 6, characterized in that The steps of requesting to read data once in n times include: Sending a third data read request message to the data processing device; receiving the third target data and the cache unit information storing the third target data sent by the data processing device, and updating the state of the third target data according to the type of the third data read request message; A third data read response message is sent to the data processing device.

8. The method according to claim 6, characterized in that The determining the second cache unit according to each of the cache units includes: Among the cache units, a cache unit located on a route from the first cache unit to the data processing device is determined as a second cache unit.

9. The method according to claim 7, characterized in that The first data read request message, the second data read request message and the third data read request message include one of the following: a shared state data read request message, an exclusive state data read request message, and an invalid state data read request message.

10. The method according to claims 1 to 5, characterized in that: The data processing system includes a processing chip, a memory, and at least two levels of cache. The processing chip includes the data processing device. Each level of the cache includes at least one cache unit. The data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

11. A data processing method, characterized in that: Applied to a second cache unit in a data processing system, the method comprising: receiving a first data read request message sent by a first cache unit, where the first data read request message is used to read first target data from the second cache unit; In the case where it is determined that the first target data is stored in the second cache unit, the state of the first target data is updated according to the type of the first data read request message, and the first target data is sent to the first cache unit.

12. The method according to claim 11, characterized in that After sending the first target data to the first cache unit, the method further includes: receiving a first data read response message sent by the first cache unit; After updating the state of the first target data according to the type of the first data read request message, the method further includes: In the case where the type of the first data read request message is to read shared state data or to read exclusive state data, a state update message is sent to the data processing device, wherein the state update message carries information, address information and state information of the first cache unit; wherein the state update message is used to instruct the data processing device to update the state of the first target data according to the state information and the address information, and to update the cache unit to which the first target data belongs according to the information of the first cache unit; Receive a status update response message sent by the data processing device.

13. The method according to claim 11, characterized in that After receiving the first data read request message sent by the first cache unit, the method further includes: When it is determined that the first target data is not stored in the second cache unit, the first data read request message is sent to the data processing device, so that the data processing device reads the first target data from the memory and sends the first target data to the first cache unit, and updates the status of the first target data and the cache unit to which the first target data belongs.

14. The method according to any one of claims 11 to 13, characterized in that: The updating the state of the first target data according to the type of the first data read request message includes: When the type of the first data read request message is to read shared state data, updating the state of the first data to a shared state; In a case where the type of the first data read request message is to read exclusive state data, updating the state of the first data to an invalid state; When the type of the first data read request message is to read invalid state data, the state of the first data is kept unchanged.

15. A data processing method, characterized in that: A data processing device applied to a data processing system, the method comprising: Receive a status update message sent by the second cache unit, and obtain information, address information, and status information of the first cache unit carried in the status update message; updating the state of the corresponding first target data to the state information according to the address information, and updating the cache unit to which the first target data belongs to the first cache unit; Sending a status update response message to the second cache unit; or, receiving a first data read request message sent by the second cache unit, and acquiring information, address information, and status information of the first cache unit carried in the first data read request message; Reading first target data from the memory according to the address information, updating the state of the first target data to the state information, and updating the cache unit to which the first target data belongs to to the first cache unit; The first target data is sent to the first cache unit, and a first data read response message sent by the first cache unit is received.

16. A data processing method, characterized in that: Applied to a data processing system including a first cache unit, a second cache unit and a data processing device, the method includes: The first cache unit predicts that the second cache unit is a target cache unit, and sends a first data read request message to the second cache unit; The second cache unit, when determining that the first target data requested by the first data read request message is stored in the second cache unit, updates the state of the first target data according to the type of the first data read request message, and sends the first target data to the first cache unit; when the type of the first data read request message is to read shared state data or to read exclusive state data, sends a state update message to the data processing device; The data processing device obtains the information, address information and status information of the first cache unit carried in the status update message; updates the status of the corresponding first target data to the status information according to the address information, and updates the cache unit to which the first target data belongs to the first cache unit; or The second cache unit sends a first data read request message to the data processing device when determining that the first target data requested by the first data read request message is not stored in the second cache unit; The data processing device obtains the information, address information and status information of the first cache unit carried in the first data read request message; reads the first target data from the memory according to the address information, updates the status of the first target data to the status information, and updates the cache unit to which the first target data belongs to the first cache unit; and sends the first target data to the first cache unit.

17. A data processing system, characterized in that: The device comprises at least one processing chip, wherein the processing chip comprises: A first cache unit, configured to predict that a second cache unit is a target cache unit, and send a first data read request message to the second cache unit; and receive the first target data, and update a state of the first target data according to a type of the first data read request message; a second cache unit, configured to receive a first data read request message sent by the first cache unit, and, if it is determined that the first target data requested by the first data read request message is stored in the second cache unit, update a state of the first target data according to a type of the first data read request message, and send the first target data to the first cache unit; A data processing device, used to receive a status update message sent by the second cache unit, obtain the information, address information and status information of the first cache unit carried in the status update message; update the status of the corresponding first target data to the status information according to the address information, and update the cache unit to which the first target data belongs to the first cache unit; or, receive a first data read request message sent by the second cache unit, obtain the information, address information and status information of the first cache unit carried in the first data read request message; read the first target data from the memory according to the address information, update the status of the first target data to the status information, and update the cache unit to which the first target data belongs to the first cache unit; and send the first target data to the first cache unit.

18. The data processing system according to claim 17, characterized in that The processing system includes a memory and at least two levels of cache, each level of the cache includes at least one cache unit, the data processing device is a master node, or the data processing device is one of the cache units at a different level from the first cache unit and the second cache unit.

19. The data processing system according to claim 17, wherein: The data processing system is a symmetric multiprocessor system or a cache consistency non-uniform storage access system.

20. The data processing system according to claim 19, characterized in that There are at least two processing chips, each of which is connected to at least another processing chip. The processing chip to which the data processing device belongs is the same as or different from the processing chip to which the first cache unit and the second cache unit belong.

21. The data processing system according to any one of claims 17 to 20, characterized in that: The processing chip is one of the following: a central processing unit, a graphics processing unit, an embedded neural network processor, and a data processor.

22. A computer readable medium having a computer program stored thereon, wherein: When the program is executed, it implements the data processing method according to any one of claims 1 to 10, or the data processing method according to claims 11 to 14, or the data processing method according to claim 15, or the data processing method according to claim 16.

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