Time synchronization method and device of chip system

Abstract

The invention discloses a time synchronization method and device of a chip system, and belongs to the technical field of chip time synchronization. The time synchronization method of the chip system comprises the following steps: receiving a first trigger input signal sent by a first-stage chip in a current trigger input signal period; in response to the first trigger input signal, obtaining trigger input time under a current trigger input signal period based on initial trigger input time corresponding to the first trigger input signal and the current trigger input signal period corresponding to the first trigger input signal; determining a frequency deviation of a system clock period based on first timing information obtained by performing daily timing accumulation on the trigger input time in the current trigger input signal period and second timing information obtained by performing timing accumulation on the basis of the system clock period; and correcting the system clock period based on frequency deviation, and performing time synchronization on the first-stage chip and each second-stage chip.

Description

Technical Field

[0001] The present application belongs to the field of chip time synchronization technology, and in particular, relates to a time synchronization method and device for a chip system. Background Art

[0002] The network equipment of the time-sensitive network can be implemented by multiple chips. For example, the switching equipment can be composed of multiple switching chips stacked together. The system equipment composed of multiple chips needs to complete the precise time synchronization between multiple chips. In the related technology, the time information is mainly synchronized to other slave chips through a clock synchronization pulse signal and a set of customized interface signals. However, in the above method, the slave chip synchronizes the timing information once a second. When the crystal oscillator or phase-locked loop of the slave chip has a large frequency deviation relative to the master chip, it cannot meet the requirement of nanosecond timing deviation between chips. Summary of the invention

[0003] The present application aims to solve at least one of the technical problems existing in the related art. To this end, the present application proposes a time synchronization method and device for a chip system, which can ensure that the time synchronization between chips reaches the nanosecond level, and only requires a single trigger signal to meet the time accuracy requirements while meeting the time accuracy requirements, and the control logic is simple and easy to implement.

[0004] In a first aspect, the present application provides a time synchronization method for a chip system, the chip system comprising a first-level chip and at least one second-level chip connected to an output end of the first-level chip, the method comprising:

[0005] Receiving a first trigger input signal sent by the first-stage chip in a current trigger input signal cycle;

[0006] In response to the first trigger input signal, based on the initial trigger input time corresponding to the first trigger input signal and the current trigger input signal cycle corresponding to the first trigger input signal, a trigger input time in the current trigger input signal cycle is obtained; the initial trigger input time is the trigger input time corresponding to the first trigger input signal sent within the first trigger input signal cycle;

[0007] Determine the frequency deviation of the system clock cycle based on first timing information obtained by accumulating daily time timing of the trigger input time under the current trigger input signal cycle and second timing information obtained by accumulating timing of the system clock cycle;

[0008] Based on the frequency deviation, the system clock cycle is corrected, and the first-level chip and each of the second-level chips are time synchronized.

[0009] According to the time synchronization method of the chip system of the present application, a trigger signal is set between the first-level chip and the second-level chip, and a trigger signal is sent based on a trigger input signal cycle that can be configured as microseconds, so that the daily time timing is accumulated based on the trigger input time corresponding to the trigger signal, and the first timing information is obtained, and the second timing information is obtained by timing based on the system clock cycle, and the system clock cycle is adjusted through the frequency deviation determined by the first timing information and the second timing information, and the deviation of the system clock timing is continuously reduced, the accuracy of the system clock timing is improved, and real-time time synchronization between chips is realized, ensuring that the time synchronization between each chip reaches the nanosecond level. While meeting the time accuracy requirements, only a single trigger signal is required to meet the time accuracy requirements, and the control logic is simple and easy to implement.

[0010] According to the time synchronization method of the chip system of the present application, the trigger input time under the current trigger input signal cycle is obtained based on the initial trigger input time corresponding to the first trigger input signal and the current trigger input signal cycle corresponding to the first trigger input signal, including:

[0011] determining the initial trigger input time based on a trigger input time reference value corresponding to the trigger input time corresponding to the first trigger input signal and a trigger input delay compensation;

[0012] The initial trigger input time and the period difference between the current trigger input signal period and the first trigger input signal period are accumulated to obtain the trigger input time under the current trigger input signal period.

[0013] According to the time synchronization method of the chip system of the present application, the first timing information obtained by accumulating the daily time timing based on the trigger input time under the current trigger input signal cycle, and the second timing information obtained by accumulating the timing based on the system clock cycle, determine the frequency deviation of the system clock cycle, including:

[0014] Taking the trigger input time in the current trigger input signal cycle as the starting value, and accumulating the daily time based on the trigger input signal cycle, to obtain the first timing information;

[0015] Taking the trigger input time in the current trigger input signal cycle as the starting value, and performing timing accumulation based on the system clock cycle, to obtain the second timing information;

[0016] The frequency deviation is obtained by subtracting the first timing information from the second timing information; the system clock period is smaller than the trigger input signal period.

[0017] According to the time synchronization method of the chip system of the present application, before taking the trigger input time under the current trigger input signal cycle as the starting value and performing daily time timing accumulation based on the trigger input signal cycle to obtain the first timing information, the method further includes:

[0018] Determine a timing frequency deviation between the first-level chip and the second-level chip based on first timing information of a previous trigger input signal cycle corresponding to the current trigger input signal cycle and a trigger input time under the current trigger input signal cycle;

[0019] Based on the timing frequency deviation, the timing frequency deviation generated by the daily time accumulation during the previous trigger input signal cycle is corrected.

[0020] According to the time synchronization method of the chip system of the present application, after correcting the system clock cycle based on the frequency deviation and performing time synchronization on the first-level chip and each of the second-level chips, the method further includes:

[0021] When the first timing information is greater than the trigger output time threshold, the first trigger output signal is output; the first trigger output signal is the first trigger input signal of the next-level chip corresponding to the second-level chip; the first trigger output signal is used for time synchronization of the next-level chip.

[0022] According to the time synchronization method of the chip system of the present application, the first trigger input signal is determined based on the trigger input signal polarity and the trigger input signal pulse width.

[0023] According to the time synchronization method of the chip system of the present application, before receiving the first trigger input signal sent by the first-level chip in the current trigger input signal period, the method further includes:

[0024] configuring the system clock cycle;

[0025] Configure the trigger output signal parameters and trigger input signal parameters corresponding to each level of chips; the trigger output signal parameters include: first trigger output time, trigger output signal period, trigger output signal pulse width and trigger output signal polarity; the trigger output time threshold is determined based on the first trigger output time; the trigger input signal parameters include: first trigger input time, trigger input signal period, trigger input signal polarity, the trigger input signal pulse width and trigger input delay compensation; the trigger input time reference value is determined based on the first trigger input time.

[0026] In a second aspect, the present application provides a time synchronization device for a chip system, the chip system comprising a first-level chip and at least one second-level chip connected to an output end of the first-level chip, the device comprising:

[0027] A first processing module, configured to receive a first trigger input signal sent by the first-stage chip in a current trigger input signal cycle;

[0028] a second processing module, configured to obtain, in response to the first trigger input signal, a trigger input time in the current trigger input signal cycle based on an initial trigger input time corresponding to the first trigger input signal and a current trigger input signal cycle corresponding to the first trigger input signal; the initial trigger input time is a trigger input time corresponding to the first trigger input signal sent within the first trigger input signal cycle;

[0029] A third processing module, configured to determine a frequency deviation of the system clock cycle based on first timing information obtained by accumulating daily time timing based on the trigger input time under the current trigger input signal cycle and second timing information obtained by accumulating timing based on the system clock cycle;

[0030] The fourth processing module is used to correct the system clock cycle based on the frequency deviation and perform time synchronization on the first-level chip and each of the second-level chips.

[0031] According to the time synchronization device of the chip system of the present application, a trigger signal is set between the first-level chip and the second-level chip, and a trigger signal is sent based on a trigger input signal cycle that can be configured as microseconds, so that the daily time timing is accumulated based on the trigger input time corresponding to the trigger signal, and the first timing information is obtained, and the second timing information is obtained by timing based on the system clock cycle, and the system clock cycle is adjusted through the frequency deviation determined by the first timing information and the second timing information, so as to continuously reduce the deviation of the system clock timing and improve the accuracy of the system clock timing, realize real-time time synchronization between chips, ensure that the time synchronization between each chip reaches the nanosecond level, and meet the time accuracy requirements while only a single trigger signal is required, and the control logic is simple and easy to implement.

[0032] In a third aspect, the present application provides a chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run a program or instruction. When the processor executes the program or instruction, the time synchronization method of the chip system described in the first aspect above is implemented.

[0033] In a fourth aspect, the present application provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the time synchronization method for the chip system as described in the first aspect above.

[0034] In a fifth aspect, the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the time synchronization method of the chip system as described in the first aspect above.

[0035] The above one or more technical solutions in the embodiments of the present application have at least one of the following technical effects:

[0036] A trigger signal is set between the first-level chip and the second-level chip, and a trigger signal is sent based on a trigger input signal cycle that can be configured as microseconds, so that the daily time timing is accumulated based on the trigger input time corresponding to the trigger signal, and the first timing information is obtained, and the second timing information is obtained by timing based on the system clock cycle. The system clock cycle is adjusted through the frequency deviation determined by the first timing information and the second timing information, and the deviation of the system clock timing is continuously reduced, the accuracy of the system clock timing is improved, and real-time time synchronization between chips is realized. It is ensured that the time synchronization between each chip reaches the nanosecond level. While meeting the time accuracy requirement, only a single trigger signal is required to meet the time accuracy requirement, and the control logic is simple and easy to implement.

[0037] Furthermore, by snapshotting the first timing information in the current trigger input signal cycle to the module that processes the trigger input signal, the frequency deviation is effectively calculated based on the trigger input time and the first timing information in the current trigger input signal cycle of the snapshot, and then based on the frequency deviation, the frequency deviation is corrected, and the accumulated nanosecond time per system clock cycle is updated to perform timing accumulation, thereby effectively reducing the impact of frequency offset in each chip system on the synchronization time between chips, so that nanosecond synchronization can be achieved between chips, effectively improving the accuracy of time synchronization.

[0038] Furthermore, by comparing the correlation between the first timing information and the trigger output time threshold, the time for sending the first trigger output signal can be effectively determined, so that based on the first trigger output signal, the next level chip can perform time synchronization, thereby achieving time synchronization between multiple levels of chips.

[0039] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0041] Figure 1 This is one of the flow charts of the time synchronization method of the chip system provided in the embodiment of the present application;

[0042] Figure 2 This is the second flow chart of the time synchronization method of the chip system provided in the embodiment of the present application;

[0043] Figure 3 This is the third flow chart of the time synchronization method of the chip system provided in the embodiment of the present application;

[0044] Figure 4 is a schematic diagram of the structure of a time synchronization device for a chip system provided in an embodiment of the present application;

[0045] Figure 5 It is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0047] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0048] In combination with the accompanying drawings, the time synchronization method of the chip system, the time synchronization device of the chip system, the chip and the readable storage medium provided in the embodiments of the present application are described in detail through specific embodiments and their application scenarios.

[0049] The time synchronization method of the chip system may be applied to a terminal, and may be specifically executed by hardware or software in the terminal.

[0050] The terminal includes but is not limited to portable communication devices such as mobile phones or tablet computers. It should also be understood that in some embodiments, the terminal may not be a portable communication device, but a desktop computer.

[0051] In the following various embodiments, a terminal including a display and a touch-sensitive surface is described. However, it should be understood that the terminal may include one or more other physical user interface devices such as a physical keyboard, a mouse and a joystick.

[0052] The time synchronization method for a chip system provided in an embodiment of the present application may be executed by an electronic device or a functional module or functional entity in the electronic device that can implement the time synchronization method for the chip system. The electronic devices mentioned in the embodiment of the present application include but are not limited to mobile phones, tablet computers, computers, cameras, and wearable devices. The time synchronization method for a chip system provided in an embodiment of the present application is described below using an electronic device as an example of an execution subject.

[0053] like Figure 1 As shown, the time synchronization method of the chip system includes: step 110, step 120, step 130 and step 140.

[0054] like Figure 3 As shown, the chip system includes a first-level chip and at least one second-level chip connected to an output terminal of the first-level chip.

[0055] In the case where the first-level chip is a master chip, the second-level chip can be a slave chip of the master chip.

[0056] The second-level chip can be the master chip of the next-level chip relative to its next-level chip, and the next-level chip is the slave chip of the second-level chip, that is, the second-level chip is the new first-level chip, and the next-level chip of the second-level chip is the second-level chip.

[0057] The following description takes the first-level chip as the master chip and the second-level chip as the slave chip as an example.

[0058] The second-level chip receives the first trigger input signal sent by the first-level chip, and the second-level chip can process the first trigger input signal as an execution subject to enable the second-level chip to perform time synchronization.

[0059] The second-level chip can also act as a first-level chip relative to its next-level chip, sending a first trigger input signal, and the next-level chip acts as a new second-level chip, performing time synchronization based on the received first trigger input signal. Step 110, receiving the first trigger input signal sent by the first-level chip in the current trigger input signal cycle;

[0060] In this step, the current trigger input signal period is the time period corresponding to the current acquisition moment.

[0061] The trigger input signal period can be pre-configured.

[0062] The specific value of the trigger input signal period can be determined based on actual conditions and is not limited in this application.

[0063] The first trigger input signal is a trigger output signal sent by the first-level chip to the second-level chip, and a trigger input signal corresponding to the trigger output signal received by the second-level chip.

[0064] The first trigger input signal is used to trigger the second-level chip to perform timing accumulation based on the system clock cycle.

[0065] During the actual execution process, the first-level chip can send a trigger output signal to the second-level chip in each trigger input signal cycle. At this time, the second-level chip can receive the trigger input signal corresponding to the trigger output signal sent by the first-level chip.

[0066] Taking the trigger input signal cycle of 1 microsecond as an example, the second-level chip will receive the first trigger input signal sent by the first-level chip again 1 microsecond after the second-level chip first receives the first trigger input signal sent by the first-level chip.

[0067] In the actual execution process, after the second-level chip receives the trigger input signal sent by the first-level chip, the time corresponding to the trigger input signal can be recorded.

[0068] Step 120, in response to the first trigger input signal, obtaining the trigger input time in the current trigger input signal cycle based on the initial trigger input time corresponding to the first trigger input signal and the trigger input signal cycle corresponding to the first trigger input signal;

[0069] In this step, the initial trigger input time is the trigger input time corresponding to the first trigger input signal sent within the first trigger input signal cycle.

[0070] The trigger input time is the time corresponding to the first trigger input signal received in the current trigger input signal cycle.

[0071] In actual execution, the trigger input time in the current trigger input signal cycle can be calculated based on the trigger input time corresponding to the first trigger input signal sent in the first trigger input signal cycle and the specific value of the current trigger input signal cycle.

[0072] In some embodiments, step 120 may further include:

[0073] determining an initial trigger input time based on a trigger input time reference value corresponding to a trigger input time corresponding to the first trigger input signal and a trigger input delay compensation;

[0074] The initial trigger input time and the period difference between the current trigger input signal period and the first trigger input signal period are accumulated to obtain the trigger input time under the current trigger input signal period.

[0075] In this embodiment, the trigger input time reference value is a preset trigger input time when the trigger input signal is first received.

[0076] The trigger input time reference value can be expressed as (first_trgi_s, first_trgi_ns).

[0077] The trigger input delay compensation is the preset delay compensation value.

[0078] The trigger input delay compensation can be expressed as trgi_dly_comp.

[0079] The trigger input time reference value and trigger input delay compensation can be pre-configured.

[0080] The trigger input time is the starting value for timing accumulation of the system clock cycle.

[0081] The trigger input time can be expressed as (trgi_load_s, trgi_load_ns).

[0082] It is understandable that the trigger input time will be different if the trigger input signal cycle is different.

[0083] During the actual execution process, when the trigger input signal is received for the first time, the initial trigger input time (trgi_load_s, trgi_load_ns) can be updated to the sum of the trigger input time reference value (first_trgi_s, first_trgi_ns) and the trigger input delay compensation trgi_dly_comp to obtain the initial trigger input time. Based on the initial trigger input time, the current trigger input signal cycle is added to the length of 1 trigger input signal cycle to obtain the trigger input time under the current trigger input signal cycle.

[0084] Taking the current trigger input signal cycle as the 4th cycle and the trigger input signal cycle of 1 microsecond as an example, when the initial trigger input time is (trgi_load_s, trgi_load_ns), the trigger input time under the current trigger input signal cycle is (trgi_load_s, trgi_load_ns) + 4 microseconds.

[0085] Step 130, determining a frequency deviation of a system clock cycle based on first timing information obtained by accumulating daily time timing based on the trigger input time under the current trigger input signal cycle and second timing information obtained by accumulating timing based on the system clock cycle;

[0086] In this step, the first timing information is the timing information obtained by taking the trigger input time as the starting value and performing daily time timing accumulation.

[0087] The second timing information is the timing information obtained by performing timing accumulation based on the system clock cycle while taking the trigger input time as the starting value while performing daily time accumulation.

[0088] Frequency deviation is the frequency deviation of the system clock cycle that occurs during the operation of the crystal oscillator or phase-locked loop.

[0089] The system clock cycle may be a cycle that is divisible by 1 second or a cycle that is not divisible by 1 second.

[0090] The system clock period can be pre-configured.

[0091] In the actual execution process, after each second-level chip receives the first trigger input signal, the trigger input time of the first trigger input signal in the current trigger input signal cycle can be used as the starting value to accumulate the daily time timing, thereby obtaining the first timing information.

[0092] While daily time counting is accumulated based on the trigger input time, the trigger input time is also used as a starting value to synchronously count based on the system clock cycle to obtain second timing information.

[0093] It can be understood that, when the timing result accumulated based on the system clock cycle is accurate, the first timing information is the same as the second timing information.

[0094] In the case where the timing result accumulated based on the system clock cycle is inaccurate, there may be a difference between the first timing information and the second timing information.

[0095] In the case where the first timing information is different from the second timing information, the frequency deviation generated by timing of the system clock can be calculated through actual values ​​of the two.

[0096] Step 140: Based on the frequency deviation, correct the system clock cycle and perform time synchronization on the first-level chip and each second-level chip.

[0097] In this step, during the actual execution process, after the frequency deviation is obtained through the first timing information and the second timing information, the system clock cycle can be adjusted based on the frequency deviation so that the timing information of the next trigger input signal cycle based on the system clock cycle is more accurate.

[0098] In the actual execution process, when the first timing information is different from the second timing information, in the next trigger input signal cycle, the first timing information will be assigned to the second timing information to perform a new timing accumulation of the trigger input signal cycle based on the first timing information and the system clock cycle to obtain new second timing information.

[0099] In the new trigger input signal cycle, the daily time timing is accumulated based on the first timing information and the trigger input signal cycle to obtain new first timing information.

[0100] During the actual execution process, the system clock cycle can be corrected based on the frequency deviation obtained in each trigger input signal cycle, and the process is repeated continuously so that the first timing information and the second timing information are continuously approached, thereby making the second timing information equal to the first timing information. Based on the accurate timing information of the system clock cycle, time synchronization between the first-level chip and each second-level chip is achieved.

[0101] During the actual execution process, after receiving the first trigger input signal, the system clock cycle is corrected based on the trigger input time, that is, the trigger input time is sent to the TOD timing module, and the daily time timing is accumulated based on the trigger input time to obtain the first timing information. In addition, the timing is accumulated based on the system clock cycle to obtain the second timing information, and then the frequency deviation of the system clock cycle is determined based on the first timing information and the second timing information, so as to correct the system clock cycle based on the frequency deviation and synchronize the time between the first-level chip and the second-level chip.

[0102] In the actual execution process, the trigger input time can be loaded into the TOD timing module through the loading interface to perform timing accumulation based on the system clock cycle.

[0103] It is understandable that, when a new trigger input signal is subsequently received, the trigger input time (trgi_load_s, trgi_load_ns) may be added to the trigger input signal period to obtain a new trigger input time.

[0104] The trigger input signal period can be expressed as trgi_period, that is, the new trigger input time is (trgi_load_s, trgi_load_ns)+trgi_period.

[0105] like Figure 2As shown, after receiving the first trigger input signal, the trigger input time of the first trigger input signal is loaded into the TOD timing module, and TOD timing accumulation is performed. Based on the first timing information obtained by the TOD timing accumulation, the first timing information is obtained, and then based on the first timing information, the time of the first-level chip and the second-level chip is updated to achieve time synchronization between the first-level chip and the second-level chip.

[0106] The first timing information is a value accumulated by a time of day (TOD) timing module based on the system clock cycle timing.

[0107] The first timing information may be expressed as TOD (s, ns).

[0108] like Figure 2 As shown, TOD (s, ns) can also be output to other modules for time synchronization of other modules.

[0109] According to the time synchronization method of the chip system provided in the embodiment of the present application, a trigger signal is set between the first-level chip and the second-level chip, and a trigger signal is sent based on a trigger input signal cycle that can be configured as microseconds, so that the daily time timing is accumulated based on the trigger input time corresponding to the trigger signal, and the first timing information is obtained, and the second timing information is obtained by timing based on the system clock cycle, and the system clock cycle is adjusted through the frequency deviation determined by the first timing information and the second timing information, and the deviation of the system clock timing is continuously reduced, the accuracy of the system clock timing is improved, and real-time time synchronization between chips is realized, ensuring that the time synchronization between each chip reaches the nanosecond level. While meeting the time accuracy requirements, only a single trigger signal is required to meet the time accuracy requirements, and the control logic is simple and easy to implement.

[0110] In some embodiments, step 130 may further include:

[0111] Taking the trigger input time under the current trigger input signal cycle as the starting value, and accumulating the daily time based on the trigger input signal cycle, to obtain first timing information;

[0112] Taking the trigger input time in the current trigger input signal cycle as the starting value, and performing timing accumulation based on the system clock cycle, to obtain second timing information;

[0113] The first timing information is subtracted from the second timing information to obtain a frequency deviation; the system clock period is less than the trigger input signal period.

[0114] In this embodiment, during the actual execution process, the TOD timing module takes the trigger input time under the current trigger input signal cycle as the starting value, and based on the trigger input signal cycle, performs daily time timing accumulation to obtain the first timing information TOD (s, ns), that is, the first timing information.

[0115] For example, in the actual execution process, taking the trigger input time as A and the trigger input signal period as 1 microsecond, when a first trigger input signal is received within the trigger input signal period, the first timing information will increase by 1 microsecond, that is, at this time, the first timing information is A+1.

[0116] In the actual execution process, in the process of accumulating the daily time based on the trigger input time corresponding to the first trigger input signal, the time accumulation is also synchronously performed based on the system clock cycle.

[0117] The system clock cycle is smaller than the trigger input signal cycle. For example, the trigger input signal cycle is 1 microsecond, the system clock cycle is 1 nanosecond, and the first timing information obtained by timing based on the trigger input signal cycle of 1 microsecond with the initial time of the trigger input as the starting value may be different from the second timing information obtained by timing based on the system clock cycle of 1 nanosecond. That is, there is a frequency deviation in the system clock cycle.

[0118] The frequency deviation can be obtained by subtracting the first timing information from the second timing information.

[0119] For example, when the second timing information is greater than the first timing information, it indicates that the frequency of timing accumulation of the system clock cycle is relatively fast and there is a frequency deviation. At this time, the system clock cycle can be corrected based on the frequency deviation obtained by calculation, so that the first timing information and the second timing information are closer in the next trigger input signal cycle.

[0120] In some embodiments, when the system clock cycle cannot be divided by 1 second, each system clock cycle also needs to accumulate fractional nanosecond values, that is, the day time accumulation (accumulated nanosecond values, accumulated fractional nanosecond values), which can be expressed as TOD (add_ns, add_subns).

[0121] According to the time synchronization method of the chip system provided in the embodiment of the present application, the first timing information is obtained by accumulating the daily time timing of the trigger input time, and the frequency deviation of the system clock cycle is obtained based on the second timing information of the system clock synchronization timing. The system clock cycle is effectively corrected through the external time source corresponding to the trigger signal, and the accuracy of the system clock timing is improved, so that the time synchronization between chips is subsequently performed based on the accurate system clock cycle.

[0122] In some embodiments, before taking the trigger input time under the current trigger input signal cycle as the starting value and performing daily time accumulation based on the trigger input signal cycle to obtain the first timing information, the method may further include:

[0123] Determine the timing frequency deviation between the first-level chip and the second-level chip based on the first timing information of the previous trigger input signal cycle corresponding to the current trigger input signal cycle and the trigger input time under the current trigger input signal cycle;

[0124] Based on the timing frequency deviation, the timing frequency deviation generated by the daily time accumulation during the previous trigger input signal cycle is corrected.

[0125] In this embodiment, the previous trigger input signal cycle is a trigger input signal cycle that is closest to the current trigger input signal cycle.

[0126] The timing frequency deviation is the frequency deviation generated during the daily time accumulation process.

[0127] After obtaining the first timing information of the previous trigger input signal cycle, the trigger input time corresponding to the current trigger input signal cycle will also be updated. At this time, based on the difference between the first timing information of the previous trigger input signal cycle and the trigger input time corresponding to the current trigger input signal cycle, the timing frequency deviation between the first-level chip and each second-level chip is determined, and then based on the timing frequency deviation, the system clock cycle in the current trigger input signal cycle is corrected to improve the timing accuracy in the current trigger input signal cycle.

[0128] like Figure 2 As shown, in the actual execution process, after obtaining the first timing information TOD (s, ns) of the previous trigger input signal cycle, the TOD (s, ns) can be snapshotted to the module that processes the trigger input signal information, that is, the trigger input module. The trigger output module can calculate the difference between the snapshot TOD (s, ns) and the trigger input time of the current trigger input signal cycle, and at the same time, based on the trigger input signal cycle, calculate the timing frequency deviation freq_drift between the first-level chip and the second-level chip.

[0129] In actual implementation, the timing frequency deviation may be read periodically and converted into a timing accumulated calibration fractional nanosecond value and a calibration direction.

[0130] The calibration fractional nanosecond value may be expressed as drift_subns, and the calibration direction may be expressed as drift_direction.

[0131] It can be understood that the calibration direction includes a positive direction and a negative direction.

[0132] During the actual execution process, in the process of timing accumulation based on the system clock cycle, timing accumulation is performed according to add_ns, add_subns, drift_subns and drift_direction, wherein drift_subns and drift_direction are used to adjust the frequency, and add_ns and add_subns are used to adjust the phase. In each system clock cycle, timing accumulation is performed through the configured frequency and phase, so that the first timing information increases or decreases the specified time, thereby obtaining the first timing information.

[0133] According to the time synchronization method of the chip system provided in the embodiment of the present application, by snapshotting the first timing information in the current trigger input signal cycle to the module that processes the trigger input signal, the frequency deviation is effectively calculated based on the trigger input time and the first timing information in the current trigger input signal cycle of the snapshot, and then based on the frequency deviation, the frequency deviation is corrected, and the accumulated nanosecond time per system clock cycle is updated to perform timing accumulation, thereby effectively reducing the impact of frequency offset in each chip system on the synchronization time between chips, so that nanosecond synchronization is achieved between chips, and the time synchronization accuracy is effectively improved.

[0134] In some embodiments, after step 120, the method may further include:

[0135] When the first timing information is greater than the trigger output time threshold, a first trigger output signal is output.

[0136] In this embodiment, the trigger output time threshold is a preset trigger output time for sending a trigger output signal for the first time.

[0137] The first trigger output signal is the first trigger input signal of the next-level chip corresponding to the second-level chip.

[0138] The first trigger output signal is used for time synchronization of the next-level chip.

[0139] During the actual execution process, when the first timing information is greater than the trigger output time threshold, the first trigger output signal may be output.

[0140] like Figure 3 As shown, the master chip sends a trigger signal to the slave chip of the next level, and the slave chip achieves time synchronization with the master chip based on the trigger signal. The slave chip also serves as the master chip of the slave chip of the next level, and sends a trigger signal to the slave chip of the next level. Based on the trigger signal sent by the slave chip, the time of the slave chip and the chip of the next level is synchronized, thereby achieving time synchronization between multiple levels of chips.

[0141] It can be understood that the trigger signal includes a trigger input signal and a trigger output signal.

[0142] The trigger output signal sent by the master chip corresponds to the trigger input signal of the slave chip.

[0143] According to the time synchronization method of the chip system provided in the embodiment of the present application, by comparing the correlation between the first timing information and the trigger output time threshold, the time of sending the first trigger output signal is effectively determined, so that based on the first trigger output signal, the next level chip can perform time synchronization, thereby realizing time synchronization between multi-level chips.

[0144] In some embodiments, the first trigger input signal is determined based on a trigger input signal polarity and a trigger input signal pulse width.

[0145] In this embodiment, the level of the first trigger input signal is controlled to select a high level or a low level according to the polarity of the trigger input signal.

[0146] It can be understood that the first trigger output signal is the first trigger input signal of the next-level chip corresponding to the second-level chip, and thus, the first trigger output signal is also determined based on the polarity of the trigger input signal and the pulse width of the trigger input signal.

[0147] Every time a trigger output signal cycle passes, a pulse signal having a width equal to the trigger output signal pulse width and a polarity equal to the trigger output signal polarity can be output.

[0148] It can be understood that the first trigger input signal and the first trigger output signal are pulse signals having a width equal to the pulse width of the trigger output signal and a polarity equal to the polarity of the trigger output signal.

[0149] According to the time synchronization method of the chip system provided in the embodiment of the present application, the pulse input signal is determined by triggering the input signal polarity and the trigger input signal pulse width, so as to effectively receive the first trigger input signal or send the first trigger output signal, so as to achieve time synchronization between chips based on the first trigger input signal and the first trigger output signal to meet the time accuracy requirements.

[0150] In some embodiments, before step 110, the method may further include:

[0151] Configure the system clock period;

[0152] Configure the trigger output signal parameters and trigger input signal parameters corresponding to each level of chips.

[0153] In this embodiment, the specific value of the system clock period can be determined based on actual conditions and is not limited in this application.

[0154] The system clock period can be a period that is divisible by 1 second or a period that is not divisible by 1 second.

[0155] The trigger output signal parameters are the parameters corresponding to the trigger output signal.

[0156] The trigger output signal parameters include: first trigger output time, trigger output signal period, trigger output signal pulse width and trigger output signal polarity.

[0157] The trigger output time threshold is determined based on the first trigger output time.

[0158] The trigger input signal parameters are the parameters corresponding to the trigger input signal.

[0159] The trigger input signal parameters include: first trigger input time, trigger input signal period, trigger input signal polarity, trigger input signal pulse width and trigger input delay compensation.

[0160] The trigger input time reference value is determined based on the first trigger input time.

[0161] It can be understood that, the smaller the values ​​of the configured trigger output signal period trgo_period and the trigger input signal period trgi_period are, the higher the accuracy of the subsequent time synchronization between the chips based on the trigger input signal and the trigger output signal will be.

[0162] In some embodiments, the trigger output signal parameters and the trigger input signal parameters may further include: restarting the first trigger enable.

[0163] In this embodiment, restarting the first trigger enable is to update the configured trigger output signal parameters and trigger input signal parameters.

[0164] During the actual execution process, the trigger output signal parameters and the trigger input signal parameters may also be reconfigured. After the configuration restart first trigger enable is enabled, the first trigger output signal may be output based on the new configuration data.

[0165] According to the time synchronization method of the chip system provided in the embodiment of the present application, by pre-configuring the system clock cycle, trigger input signal parameters and trigger output signal parameters, when the chips at all levels receive a trigger input signal or need to send a trigger output signal, they can effectively send or receive the trigger signal based on the configured parameters, i.e., the configured period, polarity and width, thereby improving the stability of trigger signal reception and transmission.

[0166] The chip system time synchronization method provided in the embodiment of the present application can be executed by a chip system time synchronization device. In the embodiment of the present application, the chip system time synchronization method is executed by a chip system time synchronization device as an example to illustrate the chip system time synchronization device provided in the embodiment of the present application.

[0167] An embodiment of the present application also provides a time synchronization device for a chip system.

[0168] The chip system includes a first-level chip and at least one second-level chip connected to an output terminal of the first-level chip.

[0169] like Figure 4 As shown, the time synchronization device of the chip system includes: a first processing module 410 , a second processing module 420 , a third processing module 430 and a fourth processing module 440 .

[0170] The first processing module 410 is used to receive a first trigger input signal sent by the first-stage chip in a current trigger input signal cycle;

[0171] The second processing module 420 is used to obtain the trigger input time in the current trigger input signal cycle based on the initial trigger input time corresponding to the first trigger input signal and the current trigger input signal cycle corresponding to the first trigger input signal; the initial trigger input time is the trigger input time corresponding to the first trigger input signal sent in the first trigger input signal cycle;

[0172] The third processing module 430 is used to determine the frequency deviation of the system clock cycle based on the first timing information obtained by accumulating the daily time timing of the trigger input time under the current trigger input signal cycle and the second timing information obtained by accumulating the timing of the system clock cycle;

[0173] The fourth processing module 440 is used to correct the system clock cycle based on the frequency deviation and perform time synchronization on the first-level chip and each second-level chip.

[0174] According to the time synchronization device of the chip system provided in the embodiment of the present application, a trigger signal is set between the first-level chip and the second-level chip, and a trigger signal is sent based on a trigger input signal cycle that can be configured as microseconds, so that the daily time timing is accumulated based on the trigger input time corresponding to the trigger signal, and the first timing information is obtained, and the second timing information is obtained by timing based on the system clock cycle. The system clock cycle is adjusted through the frequency deviation determined by the first timing information and the second timing information, and the deviation of the system clock timing is continuously reduced, the accuracy of the system clock timing is improved, and real-time time synchronization between chips is realized, ensuring that the time synchronization between each chip reaches the nanosecond level. While meeting the time accuracy requirement, only a single trigger signal is required to meet the time accuracy requirement, and the control logic is simple and easy to implement.

[0175] In some embodiments, the second processing module 420 may also be used to:

[0176] determining an initial trigger input time based on a trigger input time reference value corresponding to a trigger input time corresponding to the first trigger input signal and a trigger input delay compensation;

[0177] The initial trigger input time and the period difference between the current trigger input signal period and the first trigger input signal period are accumulated to obtain the trigger input time under the current trigger input signal period.

[0178] In some embodiments, the third processing module 430 may also be used to:

[0179] Taking the trigger input time under the current trigger input signal cycle as the starting value, and accumulating the daily time based on the trigger input signal cycle, to obtain first timing information;

[0180] Taking the trigger input time in the current trigger input signal cycle as the starting value, and performing timing accumulation based on the system clock cycle, to obtain second timing information;

[0181] The first timing information is subtracted from the second timing information to obtain a frequency deviation; the system clock period is less than the trigger input signal period.

[0182] In some embodiments, the apparatus may further include a fourth processing module, configured to:

[0183] Determine the timing frequency deviation between the first-level chip and the second-level chip based on the first timing information of the previous trigger input signal cycle corresponding to the current trigger input signal cycle and the trigger input time under the current trigger input signal cycle;

[0184] Based on the timing frequency deviation, the timing frequency deviation generated by the daily time accumulation during the previous trigger input signal cycle is corrected.

[0185] In some embodiments, the apparatus may further include a fifth processing module, configured to:

[0186] When the first timing information is greater than the trigger output time threshold, the first trigger output signal is output; the first trigger output signal is the first trigger input signal of the next-level chip corresponding to the second-level chip; the first trigger output signal is used for time synchronization of the next-level chip.

[0187] In some embodiments, the apparatus may further include a sixth processing module, configured to:

[0188] Configure the system clock period;

[0189] Configure the trigger output signal parameters and trigger input signal parameters corresponding to each level of chips; the trigger output signal parameters include: first trigger output time, trigger output signal period, trigger output signal pulse width and trigger output signal polarity; the trigger output time threshold is determined based on the first trigger output time; the trigger input signal parameters include: first trigger input time, trigger input signal period, trigger input signal polarity, trigger input signal pulse width and trigger input delay compensation; the trigger input time reference value is determined based on the first trigger input time.

[0190] The chip time synchronization device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or it can be other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0191] The chip time synchronization device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an IOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0192] The chip time synchronization device provided in the embodiment of the present application can achieve Figures 1 to 3 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0193] An embodiment of the present application also provides a time synchronization system for a chip system.

[0194] like Figure 2 As shown, the time synchronization system of the chip system includes: a trigger input module, a daily time timing module, a trigger output module and a configuration and status interface module.

[0195] In this embodiment, the configuration and status interface module is used to configure the system clock period, trigger input signal parameters and trigger output signal parameters.

[0196] The trigger input module is used to receive parameters such as the first trigger input time (first_trgi_s, first_trgi_ns), trigger input signal period (trgi_period), trigger input signal polarity (trgi_pol) and trigger input delay compensation (trgi_dly_comp) configured by the configuration and status interface module.

[0197] The trigger input module is also used to receive a trigger input signal and record a timing value that needs to be loaded into the time-of-day timing module when the trigger input signal is received.

[0198] The time-of-day timing module is used to perform timing accumulation based on the timing value sent by the received trigger input module to obtain first timing information.

[0199] The trigger output module is used to receive the first trigger output time (first_trgo_s, first_trgo_ns), trigger output signal period (trgo_period), trigger output signal pulse width (trgo_width), trigger output signal polarity (trgo_pol) and other parameters configured by the configuration and status interface module.

[0200] The trigger output module is also used to send a trigger output signal.

[0201] During the actual execution process, the configuration and status interface module can configure and update the configuration register of the trigger input module, and configure the trigger input module to restart the first trigger enable. After configuring the restart trigger enable, the trigger input module operates according to the new configuration register to receive the trigger input signal and perform corresponding actions.

[0202] In the actual execution process, accurate time synchronization between the master chip and the slave chip can be achieved by collaboratively configuring the trgo_period of the master chip and the trgi_period of the slave chip, the trigger signal polarity, and the first trigger time (first_trgo_s, first_trgo_ns), (first_trgi_s, first_trgi_ns).

[0203] It can be understood that the smaller the configured values ​​of trgo_period and trgi_period are, the higher the accuracy of time synchronization between chips is.

[0204] According to the time synchronization system of the chip system provided in the embodiment of the present application, a trigger signal is set between the first-level chip and the second-level chip, and a trigger signal is sent based on a trigger input signal cycle that can be configured as microseconds, so that the daily time timing is accumulated based on the trigger input time corresponding to the trigger signal, and the first timing information is obtained, and the second timing information is obtained by timing based on the system clock cycle. The system clock cycle is adjusted through the frequency deviation determined by the first timing information and the second timing information, and the deviation of the system clock timing is continuously reduced, the accuracy of the system clock timing is improved, and real-time time synchronization between chips is realized. It is ensured that the time synchronization between each chip reaches the nanosecond level. While meeting the time accuracy requirements, only a single trigger signal is required to meet the time accuracy requirements, and the control logic is simple and easy to implement.

[0205] In some embodiments, Figure 5 As shown, an embodiment of the present application also provides an electronic device 500, including a processor 501, a memory 502, and a computer program stored in the memory 502 and executable on the processor 501. When the program is executed by the processor 501, each process of the above-mentioned chip time synchronization method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be described here.

[0206] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0207] An embodiment of the present application also provides a non-transitory computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the above-mentioned chip time synchronization method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0208] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0209] An embodiment of the present application also provides a computer program product, including a computer program, which implements the above-mentioned chip time synchronization method when executed by a processor.

[0210] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0211] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned chip time synchronization method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0212] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0213] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0214] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the relevant technology, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0215] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

[0216] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0217] Although the embodiments of the present application have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present application, and that the scope of the present application is defined by the claims and their equivalents.

Claims

1. A time synchronization method for a chip system, characterized in that: The chip system comprises a first-level chip and at least one second-level chip connected to an output terminal of the first-level chip, and the method comprises: Receiving a first trigger input signal sent by the first-stage chip in a current trigger input signal cycle; In response to the first trigger input signal, based on the initial trigger input time corresponding to the first trigger input signal and the current trigger input signal cycle corresponding to the first trigger input signal, a trigger input time in the current trigger input signal cycle is obtained; the initial trigger input time is the trigger input time corresponding to the first trigger input signal sent within the first trigger input signal cycle; Determine the frequency deviation of the system clock cycle based on first timing information obtained by accumulating daily time timing of the trigger input time under the current trigger input signal cycle and second timing information obtained by accumulating timing of the system clock cycle; Based on the frequency deviation, the system clock cycle is corrected, and the first-level chip and each of the second-level chips are time synchronized.

2. The time synchronization method of the chip system according to claim 1, characterized in that: The obtaining, based on the initial trigger input time corresponding to the first trigger input signal and the current trigger input signal period corresponding to the first trigger input signal, the trigger input time in the current trigger input signal period includes: determining the initial trigger input time based on a trigger input time reference value corresponding to the trigger input time corresponding to the first trigger input signal and a trigger input delay compensation; The initial trigger input time and the period difference between the current trigger input signal period and the first trigger input signal period are accumulated to obtain the trigger input time under the current trigger input signal period.

3. The time synchronization method of the chip system according to claim 1, characterized in that: The first timing information obtained by accumulating daily time timing based on the trigger input time under the current trigger input signal cycle and the second timing information obtained by accumulating timing based on the system clock cycle are used to determine the frequency deviation of the system clock cycle, including: Taking the trigger input time in the current trigger input signal cycle as the starting value, and accumulating the daily time based on the trigger input signal cycle, to obtain the first timing information; Taking the trigger input time in the current trigger input signal cycle as the starting value, and performing timing accumulation based on the system clock cycle, to obtain the second timing information; The frequency deviation is obtained by subtracting the first timing information from the second timing information; the system clock period is smaller than the trigger input signal period.

4. The time synchronization method of the chip system according to claim 3, characterized in that: Before taking the trigger input time under the current trigger input signal cycle as the starting value and performing daily time accumulation based on the trigger input signal cycle to obtain the first timing information, the method further includes: Determine a timing frequency deviation between the first-level chip and the second-level chip based on first timing information of a previous trigger input signal cycle corresponding to the current trigger input signal cycle and a trigger input time under the current trigger input signal cycle; Based on the timing frequency deviation, the timing frequency deviation generated by the daily time accumulation during the previous trigger input signal cycle is corrected.

5. The time synchronization method of a chip system according to any one of claims 1 to 4, characterized in that: After the system clock cycle is corrected based on the frequency deviation and the time synchronization is performed on the first-level chip and each of the second-level chips, the method further includes: When the first timing information is greater than the trigger output time threshold, the first trigger output signal is output; the first trigger output signal is the first trigger input signal of the next-level chip corresponding to the second-level chip; the first trigger output signal is used for time synchronization of the next-level chip.

6. The time synchronization method of a chip system according to any one of claims 1 to 4, characterized in that: The first trigger input signal is determined based on a trigger input signal polarity and a trigger input signal pulse width.

7. The time synchronization method of a chip system according to any one of claims 1 to 4, characterized in that: Before receiving the first trigger input signal sent by the first-level chip in the current trigger input signal cycle, the method further includes: configuring the system clock cycle; Configure the trigger output signal parameters and trigger input signal parameters corresponding to each level of chips; the trigger output signal parameters include: first trigger output time, trigger output signal period, trigger output signal pulse width and trigger output signal polarity; the trigger output time threshold is determined based on the first trigger output time; the trigger input signal parameters include: first trigger input time, trigger input signal period, trigger input signal polarity, the trigger input signal pulse width and trigger input delay compensation; the trigger input time reference value is determined based on the first trigger input time.

8. A time synchronization device for a chip system, characterized in that: The chip system includes a first-level chip and at least one second-level chip connected to an output terminal of the first-level chip, including: A first processing module, configured to receive a first trigger input signal sent by the first-stage chip in a current trigger input signal cycle; A second processing module is used to obtain the trigger input time in the current trigger input signal cycle based on the initial trigger input time corresponding to the first trigger input signal and the current trigger input signal cycle corresponding to the first trigger input signal; the initial trigger input time is the trigger input time corresponding to the first trigger input signal sent within the first trigger input signal cycle; A third processing module, configured to determine a frequency deviation of the system clock cycle based on first timing information obtained by accumulating daily time timing based on the trigger input time under the current trigger input signal cycle and second timing information obtained by accumulating timing based on the system clock cycle; The fourth processing module is used to correct the system clock cycle based on the frequency deviation and perform time synchronization on the first-level chip and each of the second-level chips.

9. A chip, comprising a processor and a communication interface, wherein the communication interface is coupled to the processor, characterized in that: The processor is used to run a program or instruction, and when the processor executes the program or instruction, it implements the time synchronization method of the chip system as described in any one of claims 1-8.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the time synchronization method of the chip system as described in any one of claims 1 to 7 is implemented.

11. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the time synchronization method of the chip system as described in any one of claims 1 to 7 is implemented.

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