Camera serial interface controller test system and method based on ZYNQ and HAPS

Abstract

The invention discloses a camera serial interface controller test system based on ZYNQ and HAPS and a method thereof. The system comprises a ZYNQ FPGA device serving as a master device and an HAPS FPGA device serving as a slave device. Wherein the interior of the ZYNQ FPGA device comprises a D-PHY module and a C-IL module, and the interior of the HAPS FPGA device comprises a CS I controller and a DDR memory; the ZYNQ FPGA device is connected with a camera, the camera transmits image data to the ZYNQ FPGA device through an MIPI interface, and the ZYNQ FPGA device converts the image data into a PPI interface signal and transmits the PPI interface signal to a CS I controller in the HAPS FPGA device; and the CS I controller processes the PPI interface signal, extracts image data from the PPI interface signal and stores the image data in the DDR memory. Through combined use of the ZYNQ FPGA device and the HAPS FPGA device, the MIPI analog signal output by the camera can be received, converted and processed, and then the performance and reliability of the CS I controller are verified.

Description

Technical Field

[0001] The present invention relates to a camera serial interface (CSI) controller test system, in particular to a camera serial interface controller test system based on ZYNQ and HAPS, and also to a corresponding test method, belonging to the field of image communication testing. Background Art

[0002] ZYNQ is a fully programmable system-on-chip launched by Xilinx. Its design concept is to integrate the ARM processor and FPGA on a single chip. This design allows developers to use the ARM processor for advanced processing and control, while using FPGA to implement customized hardware to meet the needs of specific applications. The architecture of the ZYNQ system allows the ARM processor and FPGA to maximize their respective performance, while achieving high-speed, low-latency connection between the two through the AXI interface.

[0003] On the other hand, HAPS (High-Performance ASIC Prototyping System) is an FPGA-based hardware prototyping platform. It was developed by Synopsys to provide fast and efficient physical prototyping during the verification phase of ASIC (Application Specific Integrated Circuit) or SoC (System-on-Chip) design. The HAPS system reduces risk and cost by using FPGA (Field Programmable Gate Array) to simulate the behavior of ASIC, allowing designers to test and verify the design before actual silicon production.

[0004] At present, advanced driver assistance systems (ADAS) are increasingly being used in automobiles to improve driving safety and comfort. Among them, the CSI controller plays a vital role. It is responsible for receiving image data captured by the camera sensor and transmitting the data to the vehicle's central processing unit or other processor through high-speed serial communication to process high-resolution video streams. In order to ensure the performance and reliability of the CSI controller, it is particularly important to carry out simulation testing on it. For example, in the Chinese invention patent with patent number ZL 201811518013.2, a camera controller test system and test method are disclosed. The system uses a simulation host to create virtual driving scenes, the video signal processing module obtains the data of these scenes from the simulation host, and then the CSI controller processes these data to generate corresponding control signals. The simulation host then simulates the dynamic response of the vehicle based on these control signals, and finally outputs the test results of the CSI controller.

[0005] However, existing HAPS systems have great limitations when simulating CSI controllers. In particular, HAPS systems cannot directly simulate MIPI DPHY, which is a high-speed serial interface that connects camera sensors to application processors. Since the camera outputs analog signals and the HAPS system cannot directly receive and process these signals, it cannot be used to verify the CSI controller in the prototype chip. This means that the functional verification of the CSI controller often needs to wait until the ASIC chip is manufactured. This not only increases the risk of R&D projects, but may also lead to a longer development cycle. Summary of the invention

[0006] The primary technical problem to be solved by the present invention is to provide a camera serial interface controller test system based on ZYNQ and HAPS.

[0007] Another technical problem to be solved by the present invention is to provide a camera serial interface controller testing method based on ZYNQ and HAPS.

[0008] In order to achieve the above technical objectives, the present invention adopts the following technical solutions:

[0009] According to a first aspect of an embodiment of the present invention, a camera serial interface controller test system based on ZYNQ and HAPS is provided, comprising a ZYNQ FPGA device as a master device and a HAPS FPGA device as a slave device; wherein:

[0010] The ZYNQ FPGA device includes a D-PHY module and a CIL module, and the HAPS FPGA device includes a CSI controller and a DDR memory;

[0011] The ZYNQ FPGA device is connected to a camera, and the camera transmits image data to the ZYNQ FPGA device through a MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to a CSI controller in the HAPS FPGA device;

[0012] The CSI controller processes the PPI interface signal, extracts image data therefrom, and stores the image data in the DDR memory.

[0013] Preferably, the camera outputs a MIPI analog signal through a MIPI data channel, and the D-PHY module receives the MIPI analog signal and converts it into a digital signal, which is then input into the CIL module.

[0014] Preferably, the CIL module outputs the decomposed signal to the CSI controller inside the HAPSFPGA device in the form of a PPI interface signal.

[0015] According to a second aspect of an embodiment of the present invention, a camera serial interface controller testing method based on ZYNQ and HAPS is provided, comprising the following steps:

[0016] Step 1: Burn FPGA logic to the ZYNQ FPGA device so that the ZYNQ FPGA device can be compatible with and process the MIPI analog signal from the camera;

[0017] Step 2: Burn FPGA logic to the HAPS FPGA device to realize the control functions of the CSI controller, CPU and DDR memory;

[0018] Step 3: The camera transmits image data to the ZYNQ FPGA device through the MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to the CSI controller in the HAPS FPGA device. The CSI controller extracts the image data and stores it in the DDR memory in the HAPS FPGA device. By observing the correctness of the image data exported from the DDR memory, it is determined whether the logic of the CSI controller works as expected.

[0019] Preferably, in the step 1, the FPGA logic executed by the ZYNQ FPGA device is burned into the configuration program to initialize the camera.

[0020] Preferably, in step 1, the FPGA logic is designed and developed using the Vivado development environment, and bare metal software development of the ZYNQ FPGA device is performed using development tools in the Vitis development environment.

[0021] Preferably, in step 2, first use HAPS Configuration Tool to download the clock configuration file, and then download the FPGA logic including the CSI controller and the ARM core; after the FPGA logic is downloaded, the HAPSFPGA device is instantiated as a fully functional system-on-chip.

[0022] Preferably, in step 2, the camera outputs a MIPI clock signal through a MIPI interface, the MIPI clock signal is processed by a D-PHY module of a ZYNQ FPGA device and converted into a PPI clock signal, and then transmitted to a HAPS FPGA device. The CSI controller in the HAPS FPGA device uses the PPI clock signal to synchronously acquire image data.

[0023] Preferably, in the step three, a series of configurations are performed during the initialization phase of the CSI controller, including setting the DDR memory address, resolution and image format for storing image data, so that the developer can determine from which position of the DDR memory to start exporting data and the size of the exported data; after the CSI controller starts working, it collects image data transmitted by the camera through the MIPI interface and stores it in the DDR memory.

[0024] Preferably, in step three, the camera is set to a test mode to output a fixed, predictable color bar image; by comparing the exported image file with the expected color bar image, it is checked whether the image data is locally damaged.

[0025] Compared with the prior art, the present invention provides a camera serial interface controller test system and method based on ZYNQ and HAPS, which effectively solves the problem that the existing HAPS system cannot directly simulate MIPI DPH analog signals, and thus cannot be used to verify the limitations of prototype chips with CSI controllers. By combining the use of ZYNQ FPGA devices and HAPS FPGA devices, the present invention can realize the reception, conversion and processing of MIPI analog signals output by the camera, and then verify the performance and reliability of the CSI controller. The ZYNQ FPGA device is responsible for directly docking with the camera interface, collecting MIPI analog signals and converting them into PPI interface signals, while the HAPS FPGA device processes these signals and verifies the CSI controller. This method significantly reduces the risk of problems with the CSI controller, improves the success rate of chip tape-out, and speeds up the verification process, reducing the risk and cost of R&D projects. In addition, the present invention also provides a test method, by setting the camera to output a fixed image in test mode, and comparing the exported image data with the expected image, the correctness of the CSI controller logic and the integrity of the image data are further ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of the framework of a camera serial interface controller test system provided by an embodiment of the present invention;

[0027] Figure 2 The present invention provides a flowchart of a camera serial interface controller testing method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] In the prior art, the HAPS system cannot directly simulate the analog signal of MIPI DDPHY, which limits its application in verifying prototype chips with CSI controllers. In order to solve this problem, the technical concept of the present invention is to use two FPGA devices in combination, one ZYNQ FPGA device as the master device and the other HAPS FPGA device as the slave device. Among them, the ZYNQ FPGA device plays a key role. It is directly connected to the camera interface and is responsible for collecting the MIPI analog signal output by the camera. The logic circuit inside the ZYNQ FPGA device performs necessary processing on these MIPI data and converts them into interface signals of the Parallel Peripheral Interface (PPI). This conversion process is crucial because the CSI controller only supports PPI interface signals and cannot directly process the analog signals of MIPI DPHY. The converted PPI interface signal is then transmitted to the HAPS FPGA device through the logic interface circuit. On the HAPS FPGA device, the logic circuit containing the relevant logic such as the CSI controller, CPU and DDR memory has been pre-burned. These logic circuits are responsible for receiving and processing PPI interface signals from the ZYNQ FPGA device. After receiving the PPI interface signal on the HAPS FPGA device, the CSI controller further processes it and finally transfers the image data to the DDR memory. Through the above test solution combining the ZYNQ FPGA device and the HAPS FPGA device, the CSI controller can be effectively tested during the FPGA prototype verification phase, thus solving the problem that the HAPS system cannot directly process MIPI analog signals, significantly reducing the risk of problems with the CSI controller, and improving the success rate of chip tape-out.

[0030] like Figure 1As shown, in the camera serial interface controller test system provided in an embodiment of the present invention, a ZYNQ FPGA device as a master device and a HAPS FPGA device as a slave device are included. Among them, the ZYNQ FPGA device includes a D-PHY module and a CIL (Control and Interface Logic) module, and the HAPS FPGA device includes a CSI controller and a DDR memory. The ZYNQ FPGA device and the HAPS FPGA device work together to verify the CSI controller. As the master device, the ZYNQ FPGA device is responsible for directly connecting to the camera interface, while the HAPS FPGA device is responsible for processing and verifying the CSI controller as a slave device. The camera outputs MIPI analog signals through the MIPI data channel (lane), and these signals are first sent to the ZYNQ FPGA device. The D-PHY module inside the ZYNQ FPGA device is responsible for receiving the MIPI analog signals of the camera. The D-PHY module converts these signals into digital signals for further processing. The D-PHY module supports two modes: high speed (HS) and low power consumption (LP), and can be dynamically switched as needed to optimize data transmission speed and power consumption. The digital signals processed by the D-PHY module enter the CIL module of the ZYNQ FPGA device. The CIL module is responsible for decomposing these signals into clock signals, data signals, and control signals to prepare for the interface with the HAPS FPGA device. The CIL module outputs the decomposed signals in the form of PHY-ProtocolInterface (PPI) interface signals. The PPI interface signal is a digital interface that transmits the signal to the HAPS FPGA device. The HAPS FPGA device contains a CSI controller, which receives the PPI interface signal from the ZYNQ FPGA device through the PPI interface. The CSI controller is responsible for processing these signals and extracting the image data from the data channel. The processed image data is finally transmitted to the DDR memory in the HAPS FPGA device. The DDR memory is used to store image data for further analysis and verification.

[0031] Next, combine Figure 2 The specific steps shown are used to describe in detail the camera serial interface controller testing method provided by the embodiment of the present invention.

[0032] Step 1: Burn FPGA logic into the ZYNQ FPGA device so that the ZYNQ FPGA device can be compatible with and process the MIPI analog signal from the camera.

[0033] In this step, we are committed to programming a dedicated FPGA logic for the ZYNQ FPGA device. This logic is carefully designed to ensure that it is fully compatible and can handle the MIPI analog signals from the camera. MIPI analog signals are the industry standard for communication between the camera and the processor in mobile devices.

[0034] The FPGA logic burned into the ZYNQ FPGA device is not only capable of processing MIPI analog signals, but also has the ability to initialize the camera. The initialization process includes powering on the camera, which is a necessary step to start the camera and prepare it for image capture. Once the camera is powered on, the FPGA logic will execute the configuration program to initialize the camera. This includes adjusting the camera's parameters such as resolution, frame rate, and exposure settings to ensure that it can work properly according to the predetermined performance standards.

[0035] After configuration is completed, the camera will start capturing images and outputting them. These image data will be transmitted through the FPGA logic in the format of MIPI analog signals to provide input for subsequent processing and verification steps.

[0036] In one embodiment of the present invention, Xilinx's ZYNQ UltraScale+MP SoC series platform is used, which integrates the two major functional blocks of PS (Processing System) and PL (Programmable Logic). Among them, the PS part integrates the ARM processor, while the PL part provides flexible FPGA logic. In order to meet the test requirements, a dedicated development board can be built. It is not only equipped with a download interface such as JTAG, but also designed with the necessary interface for docking with HAPS FPGA devices.

[0037] The specific development process is carried out on the Windows operating system. The Vivado development environment of Xilinx is used to design and develop FPGA logic. At the same time, the bare metal software development of ZYNQ FPGA devices is carried out with the development tools in the Vitis development environment. In the Vivado development environment, the MIPI DPHY IP core provided by Xilinx is used, which is designed for receiving and processing camera data. By creating programmable logic (PL), adding IP cores, allocating pins, setting pin constraints, and adding timing constraints, the design of FPGA logic is completed, and the XSA (Xilinx Software Archive) file is generated. In the Vitis development environment, the XSA file is imported as a hardware platform project, and an APP software project is created on this basis. In the APP software project, code is written to initialize the relevant peripherals on the processing system (PS) side. After compilation, the final executable and linkable format (ELF) file is generated.

[0038] In terms of physical connection, the development board is connected to the computer through the JTAG line, and the USB line of the UART is used for communication. After setting the boot mode of the development board to JTAG mode, power it on again, and burn the program into the ZYNQ FPGA device through the Vitis development environment, thus completing the entire development and verification process.

[0039] It should be noted that when processing the MIPI analog signal data output by the camera, the key component is the D-PHY module, which is responsible for receiving and processing the signal in the programmable logic (PL) part of the ZYNQ FPGA device. In Xilinx's Vivado development environment, the IP core of the D-PHY module is used to implement this function, and detailed configuration is required to ensure smooth docking with another FPGA device - the HAPS FPGA device. This includes allocating IO output pins for the PPI (PHY-ProtocolInterface) interface, setting the number of MIPI data channels (lanes), and configuring the data transmission rate (lane rate) of each MIPI data channel.

[0040] The data transmission rate (lane rate) of each MIPI data channel is calculated based on the configuration of the camera. The formula for calculating the data transmission rate involves the camera's resolution, frame rate, number of pixels, and an empirical coefficient of 1.2. Generally, the data transmission rate of each MIPI data channel can be estimated by multiplying the frequency of the MIPI clock signal output by the camera by 2. In practical applications, the data transmission rate setting does not need to completely match the camera's output, because the D-PHY module has good adaptability and can work normally within a certain range.

[0041] For the configuration of the camera, it is necessary to develop the corresponding software program in the Vitis development environment to access and set the camera's registers through the I2C interface. The configuration content includes the camera's output format, resolution, frame rate, and the number of MIPI data channels used. In a preferred embodiment of the present invention, the camera is set to output RAW10 pixel format, with a resolution of VGA (640*480), a frame rate of 10fps, and a single MIPI data channel for data transmission.

[0042] Through the above configuration, it can be ensured that the camera's image data is efficiently transmitted to the ZYNQ FPGA device through the MIPI interface, and then transmitted to the HAPS FPGA device through the PPI interface, ultimately realizing the storage and further processing of the image data.

[0043] Step 2: Burn the FPGA logic into the HAPS FPGA device to implement the control functions of the CSI controller, CPU, and DDR memory.

[0044] In this step, the logic burning of the HAPS FPGA device will be performed. This process involves burning the FPGA logic code containing key functions into the HAPS FPGA device. These key functions include the CSI controller, CPU, and DDR memory control functions, which are key components to achieve the full functionality of the entire test system.

[0045] The CSI controller is the core component responsible for managing and processing image data from the camera. It ensures that image data can be efficiently received and processed for subsequent use. The CPU is responsible for executing the operation and control tasks of the entire test system. The DDR memory is responsible for managing the interface with the DDR memory, ensuring that data can be quickly and stably transmitted between the FPGA device and the memory.

[0046] The FPGA logic code burned into the HAPS FPGA device will implement the initialization and configuration of the above functional components to ensure that they can work together. Among them, the CSI controller will be set to match the output specifications of the camera, including data format, resolution, and frame rate. The CPU will load the necessary operating system and applications to support the execution of image processing and other tasks. The DDR memory will be configured to optimize the data transfer rate and improve memory access efficiency.

[0047] After the burning is completed, the HAPS FPGA device will be ready to receive the image data from the ZYNQ FPGA device and process and verify it through its internal logic. This process ensures that the HAPS FPGA device can process the image data efficiently and prepare it for final storage and analysis.

[0048] In one embodiment of the present invention, the HAPS series verification platform provided by Synopsys is used. This is a high-performance prototype verification hardware platform developed specifically for complex and large-scale FPGA / ASIC designs. The design of this platform is intended to accelerate the design verification process by providing a prototype that is close to the performance of the final product.

[0049] The process of burning FPGA logic to HAPS FPGA devices is completed through the dedicated software HAPS Configuration Tool provided by Synopsys. This tool is designed for the Windows operating system and connects to the HAPS FPGA device through the USB interface. At the beginning of the operation, the clock configuration file is first downloaded using the HAPS Configuration Tool, which is responsible for establishing the clock resources required by the system. These clock resources are crucial for driving each IP core in the system.

[0050] Next, the FPGA logic containing key IP cores such as CSI controller, ARM core, SRAM, DDR, etc. will be downloaded. These IP cores constitute the core functions of the entire test system. After the FPGA logic is downloaded, the HAPS FPGA device is instantiated as a fully functional SoC (system-on-chip). At this point, the HAPS FPGA device has the ability to perform complex tasks, including image processing, data storage, and system control.

[0051] In order to achieve effective connection with external devices, the HAPS FPGA device provides a variety of external interfaces. In a preferred embodiment of the present invention, a functional sub-board can be designed to connect with the HAPS FPGA device. For example, the PPI interface mentioned above can be connected to the ZYNQ FPGA device through these functional sub-boards. Such a design not only ensures that data can be efficiently transmitted between the HAPS FPGA device and the ZYNQ FPGA device, but also facilitates the integration and testing of the entire test system.

[0052] Through this series of configuration and burning steps, the HAPS FPGA device can accurately simulate the behavior of the final product, allowing technicians to fully test and verify the entire design before actual production.

[0053] In order to ensure that only necessary resources are used when implementing the test scheme of the CS I controller, a development board based on the ZYNQ core board is specially designed in the preferred embodiment of the present invention, which is equipped with carefully selected peripheral circuits. Such a design strategy aims to build a system dedicated to verifying the logic of the CS I controller IP part in the HAPS FPGA device.

[0054] On the development board, the configuration of logic cells, memories, and I / O ports depends entirely on the functions required to verify the CS I controller. This means that only those IP cores and resources that are critical to achieving this goal are included in the design. This selective resource configuration approach helps improve development efficiency and ensures that resources are not wasted on unnecessary functions.

[0055] The same principle is followed in I / O allocation and configuration. Only those I / O ports that are critical to the verification process are allocated and configured. Doing so not only simplifies system design, but also helps reduce potential errors and complexities, thereby ensuring a smooth verification process.

[0056] In addition, clock synchronization is a critical link in verifying the correctness of the CS I controller. The starting point of clock synchronization is the crystal oscillator inside the camera, which provides the necessary working clock for the camera. Once the camera is initialized through the program of the ZYNQ device - this process involves configuring the camera through the I 2C interface, including setting the resolution, the number of MIPI data channels, and the output image format - the camera starts to work normally and outputs the MIPI clock signal (c lk) and data signal (data) through the MIPI interface.

[0057] The frequency of the MIPI clock signal output by the camera is determined by the camera's operating clock, and in some configurations, this rate may be half the operating clock frequency. This operating clock then becomes the synchronization reference clock for the entire signal transmission path. The MIPI clock signal (c lk) and data signal (data) enter the D-PHY module of the ZYNQ FPGA device for processing, where they are converted into parallel signals of the PPI interface. The PPI interface includes the PPI clock, 8 data lines, and some status and control signals. The frequency of the PPI clock signal is one-fourth of the operating clock frequency, which is one-eighth of the frequency of the MIPI clock signal.

[0058] On the development board, the PPI interface is connected to the HAPS FPGA device through a predetermined connection method. Inside the HAPS FPGA device, the CSI controller uses the input PPI clock signal as the synchronization signal for collecting data. When the CSI controller receives the PPI interface signal from the ZYNQ FPGA device, it starts to collect image data and stores the data in the DDR memory.

[0059] In summary, the entire clock signal synchronization process can be summarized as follows: the camera outputs the MIPI clock signal through the MIPI interface, the MIPI clock signal is processed by the D-PHY module of the ZYNQ FPGA device and converted into a PPI clock signal, and then passed to the HAPS FPGA device through the ZYNQ development board, and finally the CSI controller in the HAPS FPGA device uses the PPI clock signal to synchronize the acquisition of image data. Such a clock synchronization mechanism ensures that the image data remains consistent and accurate throughout the entire process from the camera to the final storage.

[0060] Step 3: The camera transmits image data to the ZYNQ FPGA device through the MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to the CSI controller in the HAPS FPGA device. The CSI controller extracts the image data and stores it in the DDR memory in the HAPS FPGA device. By observing the correctness of the image data exported from the DDR memory, it is determined whether the logic of the CSI controller works as expected.

[0061] During the testing of the CS I controller, specific program firmware needs to be burned into the HAPS FPGA device. This program firmware is designed to test the functionality of the CS I controller and ensure that it can process image data correctly. The burning process is completed through a dedicated configuration tool, which loads the program firmware into the memory of the HAPS FPGA device.

[0062] Once the program firmware is burned into the HAPS FPGA device, it will automatically run and begin the initialization process. This includes initializing related peripherals such as the CS I controller and DDR memory. The CS I controller is the key component responsible for receiving and processing image data from the camera, while the DDR memory manages the storage of image data. Initialization ensures that these peripherals are configured as expected and are ready to receive and process the upcoming data stream.

[0063] After initialization, the CS I controller starts working and collects the image data transmitted by the camera through the MIPI interface. The collected image data is then stored in the DDR memory. In order to test whether the logic of the CS I controller is correct, it is necessary to inspect the image data stored on the DDR. This is usually done through specialized tools, which will export the image data from the DDR memory for further analysis.

[0064] The ultimate goal of the test process is to confirm whether the CSI controller can accurately process and store image data. By observing the correctness of the image data exported from the DDR memory, it can be determined whether the logic of the CSI controller works as expected. If the image data is correct, this indicates that the logic of the CSI controller is correct, thus testing the functionality of the prototype chip.

[0065] In one embodiment of the present invention, U-Boot can be selected when developing the program of the CSI controller. U-Boot is an open source boot loader (Bootloader) that is widely used in various embedded devices. It was originally designed for the PowerPC architecture, but now supports a variety of different processor architectures, including ARM, MIPS, x86, etc. It is a well-known open source software tool in the industry and will not be described in detail here.

[0066] The main function of the CSI controller program is to initialize peripherals on the HAPS FPGA device, such as the UART serial port. The UART serial port is an important tool for monitoring the running status of the CSI controller program. After the program development is completed on the software environment, the source code is compiled through an open source cross-compiler to generate the final bin file, which is the executable file. A cross-compiler is a special compiler that can generate code that runs on a target platform different from the compiler's operating environment, allowing developers to compile programs on the host system that run on the target hardware.

[0067] After the compilation is complete, use the JTAG emulator to download the executable program's bin file to the RAM of the HAPS FPGA device. The JTAG emulator is a standard test access port that allows developers to program and debug the target hardware. After running the program on the HAPS FPGA device, you can observe the program's operation through the UART serial port connected to the computer. On the computer side, use the serial port debugging assistant software to receive and display the information sent by the HAPS FPGA device through the UART serial port, thereby achieving real-time monitoring of the CSI controller program's running status.

[0068] In a preferred embodiment of the present invention, the image data can be easily exported from the DDR memory using TRACE32 PowerView for ARM software. Specifically, during the initialization phase of the CSI controller, a series of configurations are performed, including setting the DDR memory address, resolution, and image format for storing the image data. These configuration information enables the developer to determine from which position of the DDR memory to start exporting the data, as well as the size of the exported data (determined by the resolution and image format). Subsequently, these data are output in the form of an image file using TRACE32 PowerView for ARM software. In order to ensure the accuracy of the exported image data, the camera is set to a test mode to output a fixed, predictable color bar image. In this mode, the image data generated by the camera can be expected, thereby providing a benchmark to test the exported image file. By comparing the exported image file with the expected color bar image, it is possible to check whether the image data has local damage or other problems. This comparison process is an effective method for determining whether the image captured by the CSI controller is correct.

[0069] Through the above test process, the accuracy and reliability of the CS I controller in receiving and processing image data can be ensured, thus providing a solid foundation for the successful deployment and operation of the entire test system.

[0070] Compared with the prior art, the present invention provides a camera serial interface controller test system and method based on ZYNQ and HAPS, which effectively solves the problem that the existing HAPS system cannot directly simulate MIPI DPH analog signals, and thus cannot be used to verify the limitations of prototype chips with CSI controllers. By combining the ZYNQ FPGA device and the HAPS FPGA device, the present invention can realize the reception, conversion and processing of the MIPI analog signals output by the camera, and then verify the performance and reliability of the CSI controller. The ZYNQ FPGA device is responsible for directly docking with the camera interface, collecting the MIPI analog signals and converting them into PPI interface signals, while the HAPS FPGA device processes these signals and verifies the CSI controller. This method significantly reduces the risk of problems with the CSI controller, improves the success rate of chip tape-out, and speeds up the verification process, reducing the risk and cost of R&D projects. In addition, the present invention also provides a test method, by setting the camera to output a fixed image in test mode, and comparing the exported image data with the expected image, the correctness of the CSI controller logic and the integrity of the image data are further ensured.

[0071] It should be noted that the above embodiments are only examples, and the technical solutions of various embodiments can be combined, all within the protection scope of the present invention.

[0072] The camera serial interface controller test system and method based on ZYNQ and HAPS provided by the present invention are described in detail above. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. A camera serial interface controller test system based on ZYNQ and HAPS, characterized in that It includes a ZYNQ FPGA device as a master device and a HAPS FPGA device as a slave device; wherein, The ZYNQ FPGA device includes a D-PHY module and a CIL module, and the HAPS FPGA device includes a CSI controller and a DDR memory; The ZYNQ FPGA device is connected to a camera, and the camera transmits image data to the ZYNQ FPGA device through a MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to a CSI controller in the HAPS FPGA device. The CSI controller processes the PPI interface signal, extracts image data therefrom, and stores the image data in the DDR memory.

2. The camera serial interface controller test system as claimed in claim 1, characterized in that: The camera outputs a MIPI analog signal through a MIPI data channel, and the D-PHY module receives the MIPI analog signal and converts it into a digital signal, which is then input into the CIL module.

3. The camera serial interface controller test system as claimed in claim 2, characterized in that: The CIL module outputs the decomposed signal to the CSI controller inside the HAPS FPGA device in the form of a PPI interface signal.

4. A camera serial interface controller test method based on ZYNQ and HAPS, implemented based on the camera serial interface controller test system according to any one of claims 1 to 3, characterized in that The steps include: Step 1: Burn FPGA logic to the ZYNQ FPGA device so that the ZYNQ FPGA device can be compatible with and process the MIPI analog signal from the camera; Step 2: Burn FPGA logic to the HAPS FPGA device to realize the control functions of the CS I controller, CPU and DDR memory; Step 3: The camera transmits image data to the ZYNQ FPGA device through the MIPI interface. The ZYNQ FPGA device converts the image data into a PPI interface signal and transmits it to the CSI controller in the HAPS FPGA device. The CSI controller extracts the image data and stores it in the DDR memory in the HAPS FPGA device. By observing the correctness of the image data exported from the DDR memory, it is determined whether the logic of the CSI controller works as expected.

5. The camera serial interface controller testing method as claimed in claim 4, characterized in that: In the step 1, the FPGA logic executed by the ZYNQ FPGA device is burned into a configuration program to initialize the camera.

6. The camera serial interface controller testing method as claimed in claim 4, characterized in that: In step 1, the Vivado development environment is used to design and develop FPGA logic, and the bare metal software development of the ZYNQ FPGA device is carried out with the help of the development tools in the Vitis development environment.

7. The camera serial interface controller testing method as claimed in claim 4, characterized in that: In the step 2, the clock configuration file is first downloaded using the HAPS Configuration Tool, and then the FPGA logic including the CSI controller and the ARM core is downloaded; after the FPGA logic is downloaded, the HAPS FPGA device is instantiated into a fully functional system-level chip.

8. The camera serial interface controller testing method as claimed in claim 7, characterized in that: In the step 2, the camera outputs a MIPI clock signal through the MIPI interface. The MIPI clock signal is converted into a PPI clock signal after being processed by the D-PHY module of the ZYNQ FPGA device, and then transmitted to the HAPS FPGA device. The CSI controller in the HAPS FPGA device uses the PPI clock signal to synchronously collect image data.

9. The camera serial interface controller testing method as claimed in claim 4, characterized in that: In the step three, a series of configurations are performed during the initialization phase of the CSI controller, including setting the DDR memory address, resolution, and image format for storing image data, so that the developer can determine the location of the DDR memory from which to start exporting data and the size of the exported data; after the CSI controller starts working, it collects image data transmitted by the camera through the MIPI interface and stores it in the DDR memory.

10. The camera serial interface controller testing method according to claim 9, wherein: In the step three, the camera is set to a test mode to output a fixed, predictable color bar image; by comparing the exported image file with the expected color bar image, it is checked whether the image data has local damage.

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