Device multiplexing type differential operational amplifier device

Abstract

The invention provides a device multiplexing type differential operational amplifier device, relates to the technical field of differential amplifiers, and is used for solving the technical problems of large area and high power consumption of a common-mode feedback circuit in the prior art. The device comprises a first differential amplifier circuit which comprises an input transistor N1, an input transistor N2, an output transistor N3, an output transistor N4 and a transistor N8; the bias circuit comprises a transistor N7 which is connected with the base electrode of the transistor N8 and is used for providing bias current; the collector of the transistor N7 is configured to be connected with the base of the output transistor N3 and the base of the output transistor N4, so that the transistor N7, the transistor N8, the input transistor N1, the output transistor N3, the output transistor N4 and the input transistor N2 jointly form a first common-mode feedback loop, and the first common-mode feedback loop can be used for generating current through copying the current of the transistor N7 and the transistor N8; the common-mode voltage of the collectors of the output transistor N3 and the output transistor N4 is controlled through negative feedback, and stable operation of the circuit is ensured.

Description

Technical Field

[0001] The present disclosure relates to the technical field of differential amplifiers, and more specifically, to a device multiplexing type differential operational amplifier apparatus. Background Art

[0002] The current two-stage high-gain differential amplifier is generally implemented using the Cascode (common source and common gate) architecture. For this type of differential amplifier, the output is a high-impedance node. When the process and design deviate, the high-impedance output node is a voltage floating node, which may float and cause the upper power supply or the lower power supply to enter the linear region, thereby reducing the gain and deteriorating the circuit performance. Therefore, a common-mode feedback circuit is required to determine the voltage of the output node.

[0003] Currently, the common-mode feedback circuit is mainly implemented through a common-mode feedback amplifier. However, this method requires the design of an additional common-mode feedback amplifier, which requires additional area and power consumption. Summary of the invention

[0004] In view of this, the present disclosure provides a device multiplexing type differential operational amplifier apparatus to solve the technical problems of large common mode feedback circuit area and high power consumption in the prior art.

[0005] One aspect of the present disclosure provides a device multiplexing type differential operational amplifier device, comprising: a first differential amplifier circuit, comprising: an input transistor N1 and an input transistor N2, respectively used to receive an input signal; an output transistor N3 and an output transistor N4, respectively connected to the emitters of the input transistor N1 and the input transistor N2, and used to output the amplified input signal, wherein the collectors of the output transistor N3 and the output transistor N4 are configured to be in a high impedance state; a transistor N8, connected to the collectors of the input transistor N1 and the input transistor N2; a bias circuit, comprising : Transistor N7 is connected to the base of transistor N8 for providing bias current; wherein the collector of transistor N7 is configured to be connected to the bases of output transistor N3 and output transistor N4, so that transistor N7, transistor N8, input transistor N1, output transistor N3, output transistor N4 and input transistor N2 together constitute a first common-mode feedback loop, and the first common-mode feedback loop can control the common-mode voltage of the collectors of output transistor N3 and output transistor N4 by replicating the current of transistor N7 and transistor N8 and using negative feedback to ensure stable operation of the circuit.

[0006] According to an embodiment of the present disclosure, the base and the collector of the transistor N8 are configured to be short-circuited.

[0007] According to an embodiment of the present disclosure, the first differential amplifier circuit is configured as a symmetrical differential input structure, so that the magnitudes of the currents flowing through the input transistor N1 and the input transistor N2 are equal.

[0008] According to an embodiment of the present disclosure, the first differential amplifier circuit further includes: a transistor N5 connected to the collector of the output transistor N3; and a transistor N6 connected to the collector of the output transistor N4.

[0009] According to an embodiment of the present disclosure, the first differential amplifier circuit further includes: a resistor R3 connected to the emitter of the transistor N5; a resistor R4 connected to the emitter of the transistor N6; wherein the resistance value of the resistor R3 is equal to the resistance value of the resistor R4.

[0010] According to an embodiment of the present disclosure, the device further includes: a second differential amplifier circuit, including: a transistor N14 connected to the collector of the output transistor N4; a transistor N12 connected to the collector of the transistor N14; a transistor N15 connected to the collector of the output transistor N3; a transistor N13 connected to the collector of the transistor N15, wherein the base of the transistor N13 is connected to the base of the transistor N12, and is used to output the input signal after secondary amplification; a transistor N17 connected to the emitters of the transistors N14 and N15; Transistor N18 is connected to the collector of transistor N17; wherein the collector of transistor N18 is configured to be connected to the base of output transistor N3 and output transistor N4, so that transistor N15, transistor N14, transistor N17, transistor N18, output transistor N4 and output transistor N3 together constitute a second common-mode feedback loop, and the second common-mode feedback loop can control the common-mode voltage of the collectors of output transistor N3 and output transistor N4 by replicating the current of transistor N14 and transistor N15, thereby ensuring stable operation of the circuit.

[0011] According to an embodiment of the present disclosure, the second differential amplifier circuit also includes: a transistor N19, which is connected to the collector of the output transistor N4 and is used to determine the collector voltage of the output transistor N4 so that the output transistor N4 remains in a high-impedance state; a transistor N20, which is connected to the collector of the output transistor N3 and is used to determine the collector voltage of the output transistor N3 so that the output transistor N3 remains in a high-impedance state.

[0012] According to an embodiment of the present disclosure, the base and collector of the transistor N17 are configured to be short-circuited, and the base and collector of the transistor N18 are configured to be short-circuited.

[0013] According to an embodiment of the present disclosure, the second differential amplifier circuit further includes: a transistor N16 connected to the emitter of the transistor N17, and a base of the transistor N16 connected to the bases of the transistors N5 and N6; and a resistor R5 connected to the emitter of the transistor N16.

[0014] According to an embodiment of the present disclosure, the bias circuit further includes: a transistor N9 connected to the emitter of the transistor N7, wherein the base and the collector of the transistor N9 are configured as a short-circuit connection; a resistor R1 connected to the collector of the transistor N9; a transistor N10 connected to the resistor R1, wherein the base and the collector of the transistor N10 are configured as a short-circuit connection; a transistor N11 connected to the base of the transistor N10, and the collector of the transistor N11 is connected to the collector of the transistor N7; and a resistor R2 connected to the emitter of the transistor N11.

[0015] The device multiplexing differential operational amplifier device provided by the embodiment of the present disclosure has at least the following beneficial effects:

[0016] (1) The device multiplexing differential operational amplifier device provided in the embodiment of the present disclosure uses transistor N7, transistor N8, input transistor N1, output transistor N3, output transistor N4 and input transistor N2 to form a first common-mode feedback loop, and uses negative feedback to control the common-mode voltage of the collectors of output transistors N3 and N4 by replicating the current of transistors N7 and N8. Since the device does not use a bias current to generate a bias voltage to define the base voltage of the output transistors N3 and N4 of the cascade gain stage of the amplifier, but reuses the branch current of current mirror transistors N7 and N8 to construct a common-mode feedback loop to stabilize the DC voltage, thereby saving power consumption and area.

[0017] (2) In the device multiplexing differential operational amplifier device provided in the embodiment of the present disclosure, since the collectors of the output transistors N3 and N4 are configured in a high-impedance state, a common-mode feedback loop is required to stabilize the DC voltage. Therefore, the device uses transistors N19 and N20 to define the collector high-impedance nodes of the output transistors N3 and N4 through the VBE voltage (referring to the voltage between the base and the emitter of the transistor), and at the same time uses the second common-mode feedback loop composed of transistors N15, N14, N17, N18, N3, and N4 to multiplex the currents of the transistors N15, N14, N3, and N4, thereby saving current and area. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1The structure of a device multiplexing differential operational amplifier apparatus according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0020] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0021] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0022] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0023] When using expressions such as "at least one of A, B, and C, etc.", they should generally be interpreted according to the meaning of the expression commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0024] The current two-stage high-gain differential amplifier is generally implemented using the Cascode (common source and common gate) architecture. For this type of differential amplifier, the output is a high-impedance node. When the process and design deviate, the high-impedance output node is a voltage floating node, which may float and cause the upper power supply or the lower power supply to enter the linear region, thereby reducing the gain and deteriorating the circuit performance. Therefore, a common-mode feedback circuit is required to determine the voltage of the output node.

[0025] Currently, the common-mode feedback circuit is mainly implemented through a common-mode feedback amplifier. However, this method requires the design of an additional common-mode feedback amplifier, which requires additional area and power consumption.

[0026] In addition, the architecture provided by the related technology also realizes common-mode feedback of the first-stage circuit by reusing the current of the second stage. However, the architecture uses a special device, the JFET transistor (Junction Field-Effect Transistor), in a special process. For ordinary architectures, there is no JFET transistor, which makes it impossible to be widely used.

[0027] Based on this, an embodiment of the present disclosure provides a device multiplexing type differential operational amplifier apparatus to solve the technical problems of large common-mode feedback circuit area and high power consumption in the prior art.

[0028] Figure 1 The structure of a device multiplexing differential operational amplifier apparatus according to an embodiment of the present disclosure is schematically shown.

[0029] like Figure 1 As shown, the device multiplexing differential operational amplifier apparatus of the embodiment of the present disclosure may include, for example: a first differential amplifier circuit and a bias circuit.

[0030] The first differential amplifier circuit may specifically include: an input transistor N1, an input transistor N2, an output transistor N3, an output transistor N4, and a transistor N8.

[0031] The input transistor N1 and the input transistor N2 are respectively used for receiving input signals.

[0032] The output transistor N3 and the output transistor N4 are connected to the emitters of the input transistor N1 and the input transistor N2 respectively, and are used to output the amplified input signal, wherein the collectors of the output transistor N3 and the output transistor N4 are configured to be in a high impedance state.

[0033] The transistor N8 is connected to the collectors of the input transistor N1 and the input transistor N2.

[0034] In this embodiment, the collectors of the output transistors N3 and N4 are the output terminals of the first differential amplifier circuit. In the first differential amplifier circuit, the collector resistance (or output impedance) should generally be very high to ensure sufficient gain. The high impedance state generally means that the collector terminal presents a very high resistance, hindering the flow of current, so that a small voltage change can cause a large output voltage swing.

[0035] The bias circuit includes: a transistor N7.

[0036] The transistor N7 is connected to the base of the transistor N8 for providing a bias current.

[0037] In this embodiment, the collector of transistor N7 is configured to be connected to the base of output transistor N3 and output transistor N4, so that transistor N7, transistor N8, input transistor N1, output transistor N3, output transistor N4 and input transistor N2 together constitute a first common-mode feedback loop. The first common-mode feedback loop can control the common-mode voltage of the collectors of output transistor N3 and output transistor N4 by replicating the current of transistor N7 and transistor N8 and using negative feedback to ensure stable operation of the circuit.

[0038] In this embodiment, the signal flows from the base of the output transistor N3 to the emitter of the output transistor N3, enters from the emitter of the input transistor N1, flows out from the collector of the input transistor N1, flows into the base of the transistor N8, flows out from the collector of the transistor N7, and flows into the base of the output transistor N3 again. This feedback is negative feedback, which has the effect of stabilizing the collector voltage of the transistor N7.

[0039] The device multiplexing differential operational amplifier device provided in the embodiment of the present disclosure uses transistor N7, transistor N8, input transistor N1, output transistor N3, output transistor N4 and input transistor N2 to form a first common-mode feedback loop, and uses negative feedback to control the common-mode voltage of the collectors of output transistors N3 and N4 by copying the current of transistors N7 and N8. Since the device does not use a bias current to generate a bias voltage to define the base voltage of the cascade gain stage output transistors N3 and N4 of the amplifier, but reuses the branch current of current mirror transistors N7 and N8 to construct a common-mode feedback loop to stabilize the DC voltage, thereby saving power consumption and area.

[0040] According to an embodiment of the present disclosure, the base and the collector of the transistor N8 are configured to be short-circuited.

[0041] In this embodiment, configuring the base and collector of the transistor as a short-circuit connection (i.e., the base and collector are connected) causes the transistor to operate in a diode connection mode. In this case, the transistor loses its amplification characteristics and only exhibits a behavior similar to a PN junction diode. Therefore, it can be used as a voltage regulator or a current conduction control element.

[0042] According to an embodiment of the present disclosure, the first differential amplifier circuit is configured as a symmetrical differential input structure, so that the magnitudes of the currents flowing through the input transistor N1 and the input transistor N2 are equal.

[0043] In this embodiment, the symmetrical differential input structure can effectively suppress the common mode signal (i.e., the noise or interference signal shared by the input terminals), so that the circuit only amplifies the differential signal (the voltage difference between the two input terminals). In practical applications, the input signal is often accompanied by external noise or interference, such as electromagnetic radiation, power supply noise, etc., which generally manifests as a common mode signal. If the circuit is a symmetrical differential structure, then since the common mode signal has an equal effect on the two input terminals, the amplifier can suppress these common mode noises well. In addition, in a symmetrical differential input structure, the two input transistors are completely symmetrical. This design can reduce distortion caused by device parameter mismatch or circuit imbalance.

[0044] According to an embodiment of the present disclosure, the first differential amplifier circuit further includes: a transistor N5, a transistor N6, a resistor R3, and a resistor R4.

[0045] The transistor N5 is connected to the collector of the output transistor N3.

[0046] The transistor N6 is connected to the collector of the output transistor N4.

[0047] The resistor R3 is connected to the emitter of the transistor N5.

[0048] The resistor R4 is connected to the emitter of the transistor N6 ; wherein the resistance value of the resistor R3 is equal to the resistance value of the resistor R4 .

[0049] In this embodiment, transistors N5 and N6 can be used as active loads for output transistors N3 and N4. Compared with simple resistive loads, active loads can provide higher gains. Transistors N5 and N6 can be used to adjust the output current in conjunction with resistors R3 and R4. Resistors R3 and R4 determine the currents flowing through transistors N5 and N6, which in turn affect the currents of output transistors N3 and N4, thereby controlling the operating point of the entire amplifier.

[0050] According to an embodiment of the present disclosure, the device multiplexing differential operational amplifier apparatus further includes: a second differential amplifier circuit.

[0051] The second differential amplifier circuit may specifically include: a transistor N14, a transistor N12, a transistor N15, a transistor N13, a transistor N17 and a transistor N18.

[0052] The transistor N14 is connected to the collector of the output transistor N4.

[0053] The transistor N12 is connected to the collector of the transistor N14.

[0054] The transistor N15 is connected to the collector of the output transistor N3.

[0055] The transistor N13 is connected to the collector of the transistor N15 , wherein the base of the transistor N13 is connected to the base of the transistor N12 , for outputting the input signal after secondary amplification.

[0056] In this embodiment, the second differential amplifier circuit is configured as a dual-end input and single-end output structure, that is, the signal is input from transistors N14 and 15 and output from transistor 13.

[0057] The transistor N17 is connected to the emitters of the transistor N14 and the transistor N15.

[0058] The transistor N18 is connected to the collector of the transistor N17.

[0059] In this embodiment, the collector of transistor N18 is configured to be connected to the base of output transistor N3 and output transistor N4, so that transistor N15, transistor N14, transistor N17, transistor N18, output transistor N4 and output transistor N3 together constitute a second common-mode feedback loop. The second common-mode feedback loop can control the common-mode voltage of the collectors of output transistor N3 and output transistor N4 by replicating the current of transistor N14 and transistor N15, thereby ensuring stable operation of the circuit.

[0060] Since a single-stage differential amplifier usually cannot provide a sufficiently high gain, especially in a design with low power consumption or limited device reuse, a two-stage differential amplifier structure can significantly increase the total gain of the amplifier and meet the demand for signal amplification. Therefore, in this embodiment, a second differential amplifier circuit is also provided.

[0061] The first differential amplifier circuit provides preliminary gain, and the second differential amplifier circuit further amplifies the signal. Through staged amplification, the bandwidth of each stage of the amplifier can be designed to be wider without affecting the overall gain, which can improve the gain-bandwidth product of the circuit and optimize the frequency response.

[0062] In a multi-stage differential amplifier circuit, if there is no effective common-mode feedback, the common-mode level of the output voltage may deviate from expectations, resulting in a drift of the DC operating point. Therefore, in this embodiment, a second common-mode feedback loop composed of transistor N15, transistor N14, transistor N17, transistor N18, output transistor N4 and output transistor N3 is also provided to control the common-mode voltage of the collectors of output transistors N3 and output transistor N4 by copying the current of transistors N14 and N15, thereby ensuring stable operation of the circuit. The two common-mode feedback circuits can control the output common-mode voltage of each stage of the amplifier respectively, ensuring that the output of the circuit remains at a stable operating point, thereby improving the linearity of the output.

[0063] In order to ensure that the second common-mode feedback loop can work better, according to an embodiment of the present disclosure, the second differential amplifier circuit further includes: a transistor N19 and a transistor N20 to define a DC voltage of the high-impedance output node.

[0064] The transistor N19 is connected to the collector of the output transistor N4 and is used to determine the collector voltage of the output transistor N4 so that the output transistor N4 maintains a high-impedance state.

[0065] The transistor N20 is connected to the collector of the output transistor N3 and is used to determine the collector voltage of the output transistor N3 so that the output transistor N3 maintains a high impedance state.

[0066] In this embodiment, the transistor N19 and the transistor N20 define the collector high-impedance node of the output transistors N3 and N4 through the VBE voltage (referring to the voltage between the base and the emitter of the transistor).

[0067] According to an embodiment of the present disclosure, the base and collector of the transistor N17 are configured to be short-circuited, and the base and collector of the transistor N18 are configured to be short-circuited.

[0068] According to an embodiment of the present disclosure, the second differential amplifier circuit further includes: a transistor N16 and a resistor R5.

[0069] The transistor N16 is connected to the emitter of the transistor N17, and the base of the transistor N16 is connected to the bases of the transistor N5 and the transistor N6.

[0070] The resistor R5 is connected to the emitter of the transistor N16.

[0071] In this embodiment, the transistor N16 and the resistor R5 are part of a cascade connection and can provide a current amplification function.

[0072] According to an embodiment of the present disclosure, the bias circuit further includes: a transistor N9, a resistor R1, a transistor N10, a transistor N11 and a resistor R2. These components and the transistor N7 together provide a bias current to ensure the stability of the circuit.

[0073] The transistor N9 is connected to the emitter of the transistor N7 , and the base and the collector of the transistor N9 are configured to be short-circuited.

[0074] The resistor R1 is connected to the collector of the transistor N9.

[0075] The transistor N10 is connected to the resistor R1 , wherein the base and the collector of the transistor N10 are short-circuited.

[0076] The transistor N11 is connected to the base of the transistor N10 , and the collector of the transistor N11 is connected to the collector of the transistor N7 .

[0077] The resistor R2 is connected to the emitter of the transistor N11.

[0078] The device multiplexing differential operational amplifier device provided in the embodiment of the present disclosure requires a common-mode feedback loop to stabilize the DC voltage because the collectors of the output transistors N3 and N4 are configured in a high-impedance state. Therefore, the device uses transistors N19 and N20 to define the collector high-impedance nodes of the output transistors N3 and N4 through the VBE voltage (referring to the voltage between the base and the emitter of the transistor), and at the same time uses the second common-mode feedback loop composed of transistors N15, N14, N17, N18, N3, and N4 to multiplex the currents of the transistors N15, N14, N3, and N4, thereby saving current and area.

[0079] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram may represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of the code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box may also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions. It can be understood by those skilled in the art that the features recorded in the various embodiments of the present disclosure can be combined and / or combined in a variety of ways, even if such a combination or combination is not explicitly recorded in the present disclosure. In particular, without departing from the spirit and teaching of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or combined in a variety of ways. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0080] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A device multiplexing type differential operational amplifier device, characterized in that: The device comprises: A first differential amplifier circuit comprising: The input transistor N1 and the input transistor N2 are respectively used for receiving input signals; An output transistor N3 and an output transistor N4 are connected to the emitters of the input transistor N1 and the input transistor N2, respectively, and are used to output the amplified input signal, wherein the collectors of the output transistor N3 and the output transistor N4 are configured to be in a high impedance state; A transistor N8 connected to the collectors of the input transistor N1 and the input transistor N2; Bias circuit, including: A transistor N7 connected to the base of the transistor N8 and configured to provide a bias current; The collector of the transistor N7 is configured to be connected to the base of the output transistor N3 and the output transistor N4, so that the transistor N7, the transistor N8, the input transistor N1, the output transistor N3, the output transistor N4 and the input transistor N2 together constitute a first common-mode feedback loop. The first common-mode feedback loop can control the common-mode voltage of the collectors of the output transistor N3 and the output transistor N4 by replicating the current of the transistor N7 and the transistor N8 and using negative feedback to ensure stable operation of the circuit.

2. The device multiplexing type differential operational amplifier device according to claim 1, characterized in that: The base and the collector of the transistor N8 are configured to be short-circuited.

3. The device multiplexing type differential operational amplifier device according to claim 1, characterized in that: The first differential amplifier circuit is configured as a symmetrical differential input structure so that the magnitudes of the currents flowing through the input transistor N1 and the input transistor N2 are equal.

4. The device multiplexing type differential operational amplifier device according to claim 1, characterized in that: The first differential amplifier circuit further includes: A transistor N5 connected to the collector of the output transistor N3; The transistor N6 is connected to the collector of the output transistor N4.

5. The device multiplexing type differential operational amplifier device according to claim 4, characterized in that: The first differential amplifier circuit further includes: A resistor R3 connected to the emitter of the transistor N5; A resistor R4 connected to the emitter of the transistor N6; The resistance value of the resistor R3 is equal to the resistance value of the resistor R4.

6. The device multiplexing type differential operational amplifier apparatus according to claim 5, characterized in that: The device also includes: The second differential amplifier circuit comprises: A transistor N14 connected to the collector of the output transistor N4; A transistor N12 connected to the collector of the transistor N14; A transistor N15 connected to the collector of the output transistor N3; A transistor N13 connected to the collector of the transistor N15, wherein the base of the transistor N13 is connected to the base of the transistor N12, and is used to output the input signal after secondary amplification; A transistor N17 connected to the emitters of the transistor N14 and the transistor N15; A transistor N18 connected to the collector of the transistor N17; Among them, the collector of the transistor N18 is configured to be connected to the base of the output transistor N3 and the output transistor N4, so that the transistor N15, the transistor N14, the transistor N17, the transistor N18, the output transistor N4 and the output transistor N3 together constitute a second common-mode feedback loop, and the second common-mode feedback loop can control the common-mode voltage of the collectors of the output transistor N3 and the output transistor N4 by replicating the current of the transistor N14 and the transistor N15, thereby ensuring stable operation of the circuit.

7. The device multiplexing type differential operational amplifier device according to claim 6, characterized in that: The second differential amplifier circuit further includes: A transistor N19 connected to the collector of the output transistor N4 and used to determine the collector voltage of the output transistor N4 so that the output transistor N4 maintains a high impedance state; The transistor N20 is connected to the collector of the output transistor N3 and is used to determine the collector voltage of the output transistor N3 so that the output transistor N3 maintains a high-impedance state.

8. The device multiplexing type differential operational amplifier device according to claim 7, characterized in that: The base and collector of the transistor N17 are configured to be short-circuited, and the base and collector of the transistor N18 are configured to be short-circuited.

9. The device multiplexing type differential operational amplifier apparatus according to claim 7, characterized in that: The second differential amplifier circuit further includes: A transistor N16 connected to the emitter of the transistor N17, and a base of the transistor N16 connected to the bases of the transistor N5 and the transistor N6; The resistor R5 is connected to the emitter of the transistor N16.

10. The device multiplexing type differential operational amplifier device according to any one of claims 1 to 9, characterized in that: The bias circuit further comprises: A transistor N9 connected to the emitter of the transistor N7, wherein the base and the collector of the transistor N9 are configured to be short-circuited; A resistor R1 connected to the collector of the transistor N9; A transistor N10 connected to the resistor R1, wherein a base and a collector of the transistor N10 are configured to be short-circuited; A transistor N11 connected to the base of the transistor N10, and a collector of the transistor N11 connected to the collector of the transistor N7; The resistor R2 is connected to the emitter of the transistor N11.

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