Circuit layout processing method and device, equipment and storage medium

Abstract

This application discloses a method, apparatus, device, and storage medium for processing circuit layouts, relating to the field of electronic technology. The method includes: acquiring a circuit layout, the circuit layout including M pre-deployed circuit modules; for any one of the M circuit modules, determining a first sub-module and a second sub-module from the circuit module; and performing clock tree synthesis on the first sub-module and the second sub-module respectively. During clock tree synthesis, this method decouples the input / output registers and internal registers of the circuit modules, avoiding problems such as excessively long traces and excessive buffer insertions caused by mutual interference during clock tree synthesis due to their coupling under the same clock tree, thereby saving chip power and area.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a method, apparatus, device, and storage medium for processing circuit layouts. Background Technology

[0002] In integrated circuit design, clock tree synthesis is a critical step in ensuring chip timing performance. Its objectives include minimizing clock skew between different devices using the same clock source.

[0003] Typically, a circuit layout designed by an engineer includes a series of circuit modules, each with independent input registers, output registers, and internal logic structures (e.g., internal registers in addition to the input and output registers). In related technologies, clock-number synthesis is performed on the circuit modules to reduce clock skew between these devices.

[0004] However, in practice, after completing the clock tree synthesis, the circuit module often experiences problems such as excessively long windings and too many buffer insertions, leading to an increase in chip power consumption and area. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for processing circuit layouts. The technical solutions provided by this application are as follows: According to one aspect of the embodiments of this application, a method for processing circuit layout is provided, the method comprising: Obtain the circuit layout, which includes M pre-deployed circuit modules, where M is a positive integer; For any one of the M circuit modules, a first submodule and a second submodule are determined from the circuit module, wherein the first submodule includes all or part of the structure of the input register and all or part of the structure of the output register in the circuit module, and the second submodule includes all or part of the structure of the internal register in the circuit module. Clock tree synthesis is performed on the first submodule and the second submodule respectively.

[0006] According to one aspect of the embodiments of this application, a circuit layout processing apparatus is provided, the apparatus comprising: The acquisition module is used to acquire the circuit layout, which includes M pre-deployed circuit modules, where M is a positive integer; The determining module is used to determine a first submodule and a second submodule from any one of the M circuit modules, wherein the first submodule includes all or part of the structure of the input register and all or part of the structure of the output register in the circuit module, and the second submodule includes all or part of the structure of the internal register in the circuit module. The execution module is used to perform clock tree synthesis for the first submodule and the second submodule respectively.

[0007] According to one aspect of the embodiments of this application, a computer device is provided, the computer device including a processor and a memory, the memory storing a computer program, the computer program being loaded and executed by the processor to implement the above-described circuit layout processing method.

[0008] According to one aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored in the computer program, which is loaded and executed by a processor to implement the above-described circuit layout processing method.

[0009] According to one aspect of the embodiments of this application, a computer program product is provided, the computer program product including a computer program executed by a processor to implement the above-described circuit layout processing method.

[0010] The technical solutions provided in this application have at least the following beneficial effects: From the circuit modules already configured in the circuit layout, a first submodule, comprising all or part of the structure of two types of registers (input registers and output registers), and a second submodule, comprising all or part of the structure of internal registers, are identified. Then, clock tree synthesis is performed separately for the first and second submodules. This decouples the input / output registers and internal registers of the circuit module during clock tree synthesis, avoiding problems such as excessively long traces and excessive buffer insertions caused by mutual interference when they are coupled under the same clock tree, thereby saving chip power and area. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a chip design flow provided in one embodiment of this application; Figure 2 This is a flowchart of a circuit layout processing method provided in one embodiment of this application; Figure 3 This is a schematic diagram of a register in a circuit module provided in one embodiment of this application; Figure 4 This is a schematic diagram of a first sub-clock tree and a second sub-clock tree provided in one embodiment of this application; Figure 5 This is a schematic diagram of a first offset group and a second offset group provided in one embodiment of this application; Figure 6 This is a flowchart of a clock tree synthesis process provided in one embodiment of this application; Figure 7 This is a schematic diagram of an adjacent circuit module provided in one embodiment of this application; Figure 8 This is a flowchart of a timing optimization method for a circuit layout provided in one embodiment of this application; Figure 9 This is a block diagram of a circuit layout processing apparatus provided in one embodiment of this application; Figure 10 This is a structural block diagram of a computer device provided in one embodiment of this application. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0013] Before introducing the technical solution of this application, some terms involved in this application will be explained. The following related explanations are optional and can be combined with the technical solutions of the embodiments of this application in any way, all of which fall within the protection scope of this application. The embodiments of this application include at least some of the following contents.

[0014] Electronic Design Automation (EDA) is a design methodology in the electronics field that uses computer software (computer-aided design software) to automate design work. The aforementioned computer software is collectively referred to as EDA tools, which support processes such as functional design, functional verification, and placement and routing of integrated circuit chips.

[0015] Circuit layout: A circuit layout is a design drawing that describes how the components in a circuit are arranged, placed, and connected. It is a planar geometric description of the actual physical state of the circuit. The layout design must comply with constraints such as manufacturing process, timing, area, and power consumption. Circuit layout can include chip layout, and chip layout design files contain information such as the shape, area, and location of each hardware unit on the chip.

[0016] Clock skew: Clock skew refers to the time difference in arrival of the same clock signal at different registers or timing units.

[0017] Clock tree: A tree structure in a chip used to distribute clock signals to leaf nodes (such as registers).

[0018] Clock tree synthesis: a step to reduce clock skew by optimizing the internal buffer and / or line settings of the chip.

[0019] Input register: The first-level register coupled to the input port of the circuit module; that is, no other registers are connected between the input port of the circuit module and the input register.

[0020] Output register: The first-level register coupled to the output port of the circuit module, that is, no other registers are connected between the output port of the circuit module and the output register.

[0021] Setup Time: The shortest duration for which input data must remain stable before the clock signal's valid edge (such as the rising edge) arrives at the flip-flop (register).

[0022] Hold Time: The shortest duration for which input data must remain stable after the valid edge of the clock signal arrives at a flip-flop (register). In integrated circuit design, clock tree synthesis is a critical step in ensuring chip timing performance. Traditional clock tree design methods typically pursue a globally unified clock network, which includes the following two parts: 1. Within the same circuit module, the input / output (I / O) registers and internal registers are included in the same clock tree for balancing (i.e., ensuring that the delay from the clock source to the clock pin of each register is the same) to meet the setup and hold timing requirements between the input / output registers and the internal registers.

[0023] 2. Ensure that the clock tree length is consistent across different circuit modules, so that the clock length from the clock source to all registers (including input / output registers and internal registers) in different circuit modules is the same, in order to meet the timing requirements for cross-module setup and hold times.

[0024] However, the above method has obvious drawbacks: 1. Mutual Interference: I / O registers are typically located at the edges of circuit modules, and their load characteristics and drive units differ significantly from those of internal registers located in the core area of ​​the circuit module. Coupled to the same clock tree for balancing, they severely distort the clock tree structure, resulting in excessively long internal clock network windings, excessive buffer insertions, and increased power consumption, area, and clock skew.

[0025] 2. Timing Convergence Difficulty: Although a physically decoupled design of I / O registers and internal registers is preferable, there is a significant amount of data interaction between them (such as sampling input data from I / O registers to internal logic, or latching internal calculation results to I / O register outputs). If their clock latency differs too much, unacceptable clock skew will occur, directly leading to setup and hold time violations, making timing convergence impossible.

[0026] 3. Timing conflicts between modules: In block-level design, different circuit modules have their own I / O registers. If the clock delay of each circuit module's I / O register is designed independently, the timing of the interfaces between modules will become extremely complex and uncontrollable due to the different clock arrival times during top-level integration.

[0027] Therefore, there is an urgent need for an innovative clock tree design method that can eliminate the negative mutual influence between I / O registers and internal registers during clock tree synthesis, accurately control their timing relationships, and ensure the consistency of timing across module interfaces.

[0028] This application aims to overcome the shortcomings of the above-mentioned solutions and provide a comprehensive design method for clock tree decoupling and delay equalization. The core idea of ​​this method is "physical decoupling, logical association, and unified goal," that is, isolating the clock tree in terms of physical structure, associating it in terms of timing constraints, and achieving global timing control through a unified delay target. The technical solution provided by this application will be described in more detail in the following embodiments.

[0029] Please refer to Figure 1 The diagram illustrates a circuit design flow provided in one embodiment of this application. The design flow includes an EDA stage and a fabrication stage.

[0030] During the EDA phase, technicians can input EDA commands into the EDA tool through computer device 10, enabling the EDA tool to automatically complete the circuit layout design process. This design process can include any necessary steps in integrated circuit design, such as circuit module placement, clock tree synthesis, and timing optimization.

[0031] The aforementioned computer equipment can be any electronic device with computing and storage capabilities, such as a PC (Personal Computer), tablet computer, server, industrial design equipment, etc.

[0032] During the fabrication phase, the circuit layout produced in the EDA phase will be used to guide the fabrication process of chips / electronic products, thereby ensuring that the final product meets the quality standards.

[0033] It should be noted that the above is only a simplified overview of the chip design process. Other steps may be introduced into this process as needed, and this application does not limit this.

[0034] Please refer to Figure 2 This document illustrates a flowchart of a circuit layout design method according to an embodiment of this application. The execution entity for each step of this method is a computer device, such as the computer device 10 described above. The method may include at least one of the following steps 210-230.

[0035] Step 210: Obtain the circuit layout, which includes the M circuit modules that have been deployed.

[0036] M is a positive integer.

[0037] In some embodiments, the M circuit modules can all be regarded as functional modules in the same chip.

[0038] In some embodiments, each of the M circuit modules can be considered as a chip.

[0039] In some embodiments, a circuit layout file is opened using an EDA tool to obtain the circuit layout.

[0040] In some embodiments, the circuit module includes an input register, an output register, and internal registers other than the input register and the output register.

[0041] For example, please refer to Figure 3 For a circuit module 30 in a circuit layout, the circuit module 30 has 8 registers, including 4 input / output registers 31 located near the edge of the circuit module 30 and 4 internal registers 32 located in the central region of the circuit module 30.

[0042] Step 220: For any one of the M circuit modules, determine the first submodule and the second submodule from the circuit module.

[0043] The first submodule includes all or part of the structure of the input registers and all or part of the structure of the output registers in the circuit module, and the second submodule includes all or part of the structure of the internal registers in the circuit module. Internal registers are those registers included in the circuit module other than the input and output registers.

[0044] In some embodiments, the first submodule includes all or part of the structure of each input register and all or part of the structure of each output register in the circuit module, and the second submodule includes all or part of the structure of each internal register in the circuit module.

[0045] In some embodiments, all or part of the structure of the input register includes a clock pin for the input register, all or part of the structure of the output register includes a clock pin for the output register, and all or part of the structure of the internal register includes a clock pin for the internal register.

[0046] In some embodiments, the first submodule includes an input register and an output register in the circuit module, and the second submodule includes an internal register in the circuit module.

[0047] In some embodiments, the first submodule includes clock pins for the input register and clock pins for the output register in the circuit module, and the second submodule includes clock pins for the internal registers in the circuit module.

[0048] In some embodiments, each of the M circuit modules is processed in accordance with steps 220 and 230.

[0049] The clock pin of a register is the pin that the register uses to receive clock signals.

[0050] In some embodiments, step 220 above includes steps 222 and 224 as follows ( Figure 2 (not shown in the image) Steps 222 and 224 can be executed simultaneously or sequentially. This application does not impose any restrictions on the execution order of steps 222 and 224.

[0051] Step 222: From the clock tree structure of the circuit module, determine the first sub-clock tree with the clock source of the circuit module as the root node and the clock pins of each input register and each output register in the circuit module as leaf nodes.

[0052] The first sub-clock tree is the first sub-module mentioned above. A clock source is a device used to generate clock signals, and the clock source of a circuit module is used to provide clock signals to the devices in the circuit module. In some embodiments, the clock sources of the M circuit modules are the same clock source, that is, the clock source mentioned in this application can be the top-level clock source in the circuit layout, and the top-level clock source supports providing clock signals to the devices in the different circuit modules included in the circuit layout.

[0053] Step 224: From the clock tree structure of the circuit module, determine the second sub-clock tree with the clock source as the root node and the clock pins of each internal register in the circuit module as leaf nodes.

[0054] The second sub-clock tree is the second sub-module mentioned above.

[0055] The clock tree structure of the circuit module is a tree structure with the clock source as the root node and the clock pins of each register in the circuit module as leaf nodes. The first sub-clock tree described above can also be understood as a clock tree serving each input register and each output register in the circuit module, providing clock signals to the input / output registers it serves. The second sub-clock tree described above can also be understood as a clock tree serving each internal register in the circuit module, providing clock signals to the internal registers it serves.

[0056] In some embodiments, in response to a first EDA command, steps 222 and 224 described above are executed to divide the clock tree structure of the circuit module into a first sub-clock tree and a second sub-clock tree. The first EDA command is an EDA command used to divide the clock tree; for example, the first EDA command is an EDA command such as create_clock (create clock) or create_generate_clock (create derived clock).

[0057] For example, please refer to Figure 4 The clock tree structure in circuit module 30 is divided into a first sub-clock tree and a second sub-clock tree. The first sub-clock tree connects the clock port of circuit module 30 to the clock pins of the input / output registers within the circuit module. The second sub-clock tree connects the clock port of circuit module 30 to the clock pins of the internal registers within the circuit module. The clock port of circuit module 30 is the port coupled to the top-level clock source in the circuit layout.

[0058] In this embodiment, during the clock tree synthesis stage, the clock network structure of the circuit module is explicitly divided into two physically independent parts. This step eliminates mutual interference caused by load and location mismatch during clock tree synthesis, allowing the tree structure of each part to reach a local optimum.

[0059] In some embodiments, the first submodule includes a first offset group, and the second submodule includes a second offset group. Step 220 includes: assigning each input register and each output register included in the circuit module to the first offset group, and assigning each internal register included in the circuit module to the second offset group. Figure 2 (Not shown in the image).

[0060] An offset group refers to a group of internal devices that have uniform requirements for clock delay. The first offset group and the second offset group are different offset groups. Clock delay refers to the delay in the clock signal traveling from the clock source to the corresponding device.

[0061] In some embodiments, in response to a second EDA command, the input registers and output registers included in the circuit module are assigned to a first offset group, and the internal registers included in the circuit module are assigned to a second offset group. The second EDA command is an EDA command used to assign offset groups, such as create_skew_group or set_skew_group.

[0062] For example, please refer to Figure 5 For the various registers included in circuit module 30, the input / output registers are assigned to the first offset group, and the internal registers are assigned to the second offset group. Therefore, during clock tree synthesis, the input / output registers and internal registers are not balanced with each other by default.

[0063] In this embodiment, the input / output registers and internal registers of circuit module 30 are directly divided into different offset groups. This eliminates the requirement for circuit module 30 to have an established clock tree structure, thus improving the flexibility of applying this solution.

[0064] Step 230: Perform clock tree synthesis for the first submodule and the second submodule respectively.

[0065] Performing clock tree synthesis for a submodule (first submodule / second submodule) is a step of determining or adjusting the device (such as gating unit, clock buffer) insertion strategy and routing resources from the clock source to the clock pin in the submodule. This clock tree synthesis step can be automatically completed by the clock tree synthesis function of an EDA tool, and this application does not impose hard limitations on the specific content such as device configuration and circuit layout involved.

[0066] In some embodiments, clock tree synthesis is performed on the first submodule with the goal of reducing the clock skew of each register within the first submodule. Similarly, clock tree synthesis is performed on the first submodule with the goal of reducing the clock skew of each register within the second submodule.

[0067] The technical solution provided in this application identifies a first submodule, comprising all or part of the structures of two types of registers (input registers and output registers), and a second submodule, comprising all or part of the structures of internal registers, from the circuit modules already configured in the circuit layout. Then, clock tree synthesis is performed on the first and second submodules respectively. This decouples the input / output registers and internal registers of the circuit module during clock tree synthesis, avoiding problems such as excessively long traces and excessive buffer insertions caused by mutual interference during the synthesis process due to their coupling under the same clock tree, thereby saving chip power and area.

[0068] In some embodiments, step 230 includes: performing clock tree synthesis on the first submodule and the second submodule respectively according to the first parameters for clock tree synthesis of the first submodule and the second submodule respectively.

[0069] That is to say, clock tree synthesis is performed on the first submodule according to the first parameter set for the first submodule; and clock tree synthesis is performed on the first submodule according to the first parameter set for the second submodule.

[0070] The first parameter mentioned above is the parameter used to perform clock tree synthesis in the first clock tree synthesis stage. The first clock tree synthesis stage is a stage in which clock tree synthesis is performed separately for different sub-modules (first sub-module and second sub-module) included in the same circuit module.

[0071] The first parameter set for the first submodule is the parameter used by the first submodule to perform clock tree synthesis during the first clock tree synthesis stage; the first parameter set for the second submodule is the parameter used by the second submodule to perform clock tree synthesis during the first clock tree synthesis stage.

[0072] The parameters for performing clock tree synthesis may include various parameters that may be used in the clock tree synthesis process, such as constraint parameters, performance target parameters, and routing rule parameters. These parameters depend on the specific development environment and EDA tools, and this application does not limit them.

[0073] The constraint parameters mentioned above are used to constrain the clock tree synthesis process, such as limiting the maximum load capacitance of devices in the clock tree and the maximum trace length of the clock tree wiring. The performance target parameters mentioned above indicate the performance requirements for the clock tree; for example, performance target parameters include the desired clock skew and the desired clock delay. The routing rule parameters mentioned above are the parameters for the routing rules during the clock tree synthesis process.

[0074] In other words, after decoupling the input / output registers and internal registers into different sub-modules, this application will further decouple the clock tree synthesis process of different sub-modules from the parameter setting process, so that the clock tree synthesis process of the two is physically independent.

[0075] In some embodiments, the first parameter includes a first delay corresponding to the first submodule and a second delay corresponding to the second submodule. Further, the first parameter set for the first submodule includes the first delay, and the first parameter set for the second submodule includes the second delay. For a more detailed explanation of the first and second delays, please refer to the embodiments below.

[0076] In some embodiments, please refer to Figure 6 Step 230 above includes at least one of steps 232 to 234 below.

[0077] Step 232: With the goal of making the clock delay corresponding to each clock pin in the first submodule close to the first delay, perform clock tree synthesis for the first submodule.

[0078] The clock pins in the first submodule include the clock pins of each input register and each output register in the circuit module.

[0079] Step 234: With the goal of making the clock delay corresponding to each clock pin in the second submodule close to the second delay, perform clock tree synthesis on the second submodule.

[0080] The clock pins in the second submodule include the clock pins of the internal registers in the circuit module.

[0081] The clock delay corresponding to the clock pin is the delay from when the clock signal arrives at the clock pin from the clock source of the circuit module. The first delay and the second delay are equal, or the difference between the first delay and the second delay is less than a first threshold.

[0082] The first threshold is set by the technicians as needed; it is a small threshold that allows the first delay and the second delay to be as close as possible.

[0083] The first delay is used to indicate the expected clock delay for the clock pins inside the first submodule during the first clock tree synthesis phase. The second delay is used to indicate the expected clock delay for the clock pins inside the second submodule during the first clock tree synthesis phase.

[0084] The aforementioned first and second delays can be determined by technicians based on factors such as the overall chip frequency, wiring resources, and power consumption budget; this application does not impose any restrictions on this.

[0085] In the above embodiment, when performing clock tree synthesis for the first and second submodules respectively, the optimization objective is not only to minimize the clock skew of the clock pins of their respective included registers, but more importantly, to drive the delay from the clock source to the clock pins of their respective included registers to converge towards a unified delay target. Through this method, even with physically decoupled input / output registers, the clock skew between the input / output registers and internal registers can be actively controlled, ensuring that the clock skew is limited to a pre-calculated range that meets timing convergence requirements, thereby avoiding timing problems caused by decoupling the input / output registers from the internal registers.

[0086] In some embodiments, before step 232, the following step 231 is also included ( Figure 6 (Not shown in the image).

[0087] Step 231: Set a first delay for the first submodule and a second delay for the second submodule.

[0088] In some embodiments, in response to a third EDA command for a first submodule, a first delay is set for the first submodule. In response to a third EDA command for a second submodule, a second delay is set for the second submodule. The third EDA command is an EDA command for setting clock delays, such as `set_target_latency` (set target delay), `cts_skew_group_target_insertion_delay` (clock tree offset group target insertion delay), `set_clock_delay` (set clock delay), etc. In some embodiments, after step 230 above, the method further includes: performing timing optimization on the paths between the registers included in the circuit module, with the goal of satisfying the first hold time requirements and the first setup time requirements of the registers included in the circuit module.

[0089] The aforementioned registers include at least one of the following in the circuit module: each input register, each output register, and each internal register.

[0090] Timing optimization for a path is a step of determining or adjusting the hardware units (such as logic function units, buffers, etc.) and circuit settings in the path. This timing optimization step can be automatically completed by the timing optimization function of EDA tools, and this application does not impose hard limitations on the specific content such as device configuration and circuit layout involved.

[0091] The first setup time requirement is the setup time requirement used in the first timing optimization phase. The first hold time requirement is the hold time requirement used in the first timing optimization phase. The first timing optimization phase is the phase that performs timing optimization on the data transmission paths (paths between registers) within the circuit module.

[0092] The setup time requirement refers to the requirement related to the setup time of a register (the flip-flop in the register). In one example, for the path between two registers, the setup time requirement of the register can be expressed by the following setup time verification formula: T_ck2q + T_dp < T_skew + T_cycle - T_setup. Here, T_ck2q is the clock delay corresponding to the initiating register among the two registers, and T_dp is the delay of data transmission on the path between the two registers. T_skew is the clock skew between the two registers, T_cycle is the length of the clock cycle, and T_setup is the setup time of the capture register. The initiating register is the register that provides data among the two registers, and the capture register is the register that receives data among the two registers. One of the objectives of performing timing optimization for the path between these two registers is to make the path between these two registers meet the above setup time verification formula. It can be seen that if the negative clock skew is too large here, it will be very difficult for the setup time of the capture register to converge.

[0093] The hold time requirement refers to the requirement related to the hold time of a register (the flip-flop in the register). In one example, for the path between two registers, the hold time requirement of the register can be expressed by the following hold time verification formula: T_ck2q + T_dp > T_skew + T_hold. Here, T_hold is the hold time of the capture register. One of the objectives of performing timing optimization for the path between these two registers is to make the path between these two registers meet the above hold time verification formula. It can be seen that if the positive clock skew is too large here, it will be very difficult for the hold time of the capture register to converge.

[0094] It should be noted that the hold time requirement and setup time requirement of any register mentioned in this application can be determined by those skilled in the art according to the design requirements, and this application does not make any limitations in this regard.

[0095] In some embodiments, the paths between the above-mentioned registers include: the path between the input register and the internal register, the path between different internal registers, and the path between the internal register and the output register. Thus, this solution can comprehensively cover the timing optimization of various data interaction paths in the circuit module.

[0096] The path between the input register and the internal register can also be understood as the data transmission path between the first-level register and the second-level register coupled to the input port inside the circuit module. The path between different internal registers can also be understood as the data transmission path between different internal registers. The path between the internal register and the output register can also be understood as the data transmission path between the first-level register and the second-level register coupled to the output port inside the circuit module.

[0097] In summary, the above scheme, by setting a unified target delay for the first and second sub-modules during the clock tree synthesis stage, re-associates the seemingly independent sub-modules in timing, thereby achieving proactive management and precise control of the clock offset between input / output registers and internal registers. Therefore, performing timing optimization after completing the above clock tree synthesis steps ensures the determinism and reliability of timing convergence.

[0098] In some embodiments, the method further includes: generating a timing report of the circuit module, the timing report of the circuit module being used to reflect whether the paths between the various registers included in the circuit module meet timing requirements.

[0099] In some embodiments, a timing report for the circuit module is generated after timing optimization is performed on the paths between the various registers included in the circuit module.

[0100] Timing requirements refer to the requirements for data transmission timing, including the first hold time requirement and the first setup time requirement mentioned above.

[0101] In some embodiments, an EDA tool is used to verify whether the paths between the registers included in the circuit module meet the first hold time requirements and the first setup time requirements of the registers included in the circuit module (i.e., whether timing violations occur) in order to generate a timing report for the circuit module.

[0102] In the above embodiment, after timing optimization is performed on the path between registers in the circuit module, a timing report at the circuit module level is automatically generated. This allows technicians to perform timing verification on circuit modules whose path between registers meets the timing requirements, and to perform error correction and adjustment on circuit modules whose path between registers does not meet the timing requirements.

[0103] For chip designs that include multiple circuit modules, this application extends the unified clock delay to a global constraint, which will be described in the following embodiments.

[0104] In some embodiments, M is an integer greater than 1, and the above circuit layout processing method further includes the following step S11.

[0105] Step S11: Perform clock tree synthesis on each of the M first sub-modules according to the second parameters of the clock tree synthesis set for each of the M first sub-modules. The M first sub-modules are the first sub-modules corresponding to the M circuit modules respectively.

[0106] In other words, for each of the M first submodules, clock tree synthesis is performed on the first submodule according to the second parameter set for that first submodule.

[0107] The first submodule corresponding to the circuit module is the first submodule determined from the circuit module.

[0108] The second parameter mentioned above is the parameter for performing clock tree synthesis in the second clock tree synthesis stage. The second clock tree synthesis stage is a stage in which clock tree synthesis is performed separately for the first sub-modules included in different circuit modules. The first clock tree synthesis stage and the second clock tree synthesis stage are different. In some embodiments, the second clock tree synthesis stage is located after the first clock tree synthesis stage.

[0109] The second parameter set for the first submodule is the parameter used by the first submodule to perform clock tree synthesis during the second clock tree synthesis stage.

[0110] In some embodiments, the first parameter set for the first submodule and the second parameter set for the first submodule may be the same or different.

[0111] In the above embodiment, clock tree synthesis is performed in two stages. The first stage focuses on different sub-modules in the same circuit module, and the second stage focuses on the first sub-module in different circuit modules, thereby effectively improving the overall clock line rationality of the circuit layout.

[0112] In some embodiments, the second parameter includes the third delay corresponding to each of the M first sub-modules, wherein the third delays corresponding to any two of the M first sub-modules are equal, or the difference between the corresponding third delays is less than the second threshold.

[0113] The second threshold is set by the technicians as needed. It is a small threshold that allows the third delays corresponding to the M first sub-modules to be as close as possible.

[0114] The third delay corresponding to the first submodule is the third delay included in the second parameter set for the first submodule. The third delay is used to indicate the expected clock delay reached by the clock pin inside the first submodule during the second clock tree synthesis stage. It can be equal to the first delay mentioned above, for example, the first delay can be directly used as the third delay; or it can be set to deviate from the first delay, which is not limited in this application.

[0115] In some embodiments, step S11 above includes the following steps: for each of the M first sub-modules, clock tree synthesis is performed on the first sub-module with the goal of making the clock delay corresponding to each clock pin in the first sub-module close to the third delay corresponding to the first sub-module.

[0116] The clock delay corresponding to the clock pin is the delay from when the clock signal arrives at the clock pin from the clock source of the circuit module.

[0117] In some embodiments, before step S11, the method further includes setting a third delay for each of the M first sub-modules.

[0118] In some embodiments, for each of the M first submodules, a third delay corresponding to that first submodule is set in response to a third EDA command for that first submodule. In some embodiments, each first submodule sets the third delay via a separate third EDA command.

[0119] In the above embodiment, when performing clock tree synthesis for the first sub-module in different circuit modules, it is clearly stipulated that the first sub-module of all circuit modules should be synthesized towards a unified and specified clock delay target. This unified delay target across modules allows each circuit module to perform clock tree synthesis independently without impairing the timing of the top-level interface. This not only supports parallel clock tree synthesis by multiple modules, but also reduces the number of iterations for timing optimization between subsequent modules, thereby shortening the chip design cycle.

[0120] In some embodiments, after step S11, the circuit layout processing method further includes the following step S12: Step S12, with the goal of satisfying the second hold time requirement and the second setup time requirement of the registers included in the M first sub-modules respectively, timing optimization is performed on the path between the M circuit modules.

[0121] In some embodiments, the registers included in the M first sub-modules mentioned in the above steps refer to the input registers and output registers included in the M first sub-modules respectively.

[0122] The second setup time requirement is the setup time requirement used in the second timing optimization phase. The second hold time requirement is the hold time requirement used in the second timing optimization phase. The second timing optimization phase is the phase that performs timing optimization on the data transmission paths between circuit modules. The first timing optimization phase and the second timing optimization phase are different. In some embodiments, the second timing optimization phase is located after the first timing optimization phase.

[0123] In some embodiments, the first setup time requirement and the second setup time requirement for the same register may be the same or different. The first hold time requirement and the second hold time requirement for the same register may be the same or different.

[0124] In some embodiments, step S12 includes: performing timing optimization on the paths between the M circuit modules, and on the input and output paths of each of the M circuit modules, with the goal of satisfying the second hold time requirements and the second setup time requirements of the registers included in the M first sub-modules respectively. The input path of a circuit module refers to the path between the input port of the circuit module and the input register of the circuit module. The output path of a circuit module refers to the path between the output register of the circuit module and the output port of the circuit module.

[0125] In some embodiments, the path between the M circuit modules includes the path between any two adjacent circuit modules that are connected.

[0126] The following section uses two adjacent circuit modules (the first circuit module and the second circuit module) out of M circuit modules as an example to illustrate the path between the circuit modules.

[0127] Assuming the first circuit module is the data provider and the second circuit module is the data receiver, then the path between the first circuit module and the second circuit module refers to the path between the output port of the first circuit module and the input port of the second circuit module.

[0128] In some embodiments, prior to step S12, the method further includes: setting interface timing constraints for each of the M circuit modules, wherein the interface timing constraints of each circuit module are used to constrain the data transmission delay from outside the circuit module. Step S12 includes: under the interface timing constraints corresponding to the M circuit modules respectively, performing timing optimization on the paths between the M circuit modules with the goal of satisfying the second hold time requirements and the second setup time requirements of the registers included in the M first sub-modules respectively.

[0129] After introducing interface timing constraints, the principle of performing timing optimization on the path between M circuit modules is similar to the principle of performing timing optimization on the path between registers, which will not be elaborated here.

[0130] In some embodiments, for any one of the M circuit modules, in response to a fourth EDA command for that circuit module, interface timing constraints are set for that circuit module. The fourth EDA command is an EDA command used to set interface timing constraints, such as commands like set_input_delay (set input delay) and set_output_delay (set output delay).

[0131] The command to set the input delay is used to configure the input delay of the circuit module. The input delay refers to the time it takes for data to travel from the external register, through the layout traces and external logic, to reach the input port of the circuit module. The command to set the output delay is used to configure the output delay of the circuit module. The output delay refers to the time it takes for data to travel from the output port of the circuit module to be sampled by the external register.

[0132] It can be seen that, as Figure 7 As shown, since the above scheme explicitly specifies that all first sub-modules are synthesized towards the same designated clock delay target, the clock delays for data transmission and reception are known and nearly identical when any two adjacent circuit modules (such as the first and second circuit modules) communicate through their input / output registers. Therefore, when optimizing the timing between circuit modules, it is no longer necessary to specifically consider the clock offsets of the input / output registers of different circuit modules. This greatly simplifies the timing verification steps between circuit modules and also ensures the timing predictability and convergence of the top-level integration.

[0133] In some embodiments, the method further includes: generating an inter-module timing report, which reflects whether the paths between the M circuit modules meet the timing requirements.

[0134] The timing requirements here include the second hold time requirement and the second setup time requirement mentioned above.

[0135] In some embodiments, an EDA tool is used to verify whether the paths between the M circuit modules meet the second hold time requirements and the second setup time requirements of the registers included in the M first sub-modules (i.e., whether timing violations occur) in order to generate an inter-module timing report.

[0136] In the above embodiment, after timing optimization is performed on the paths between circuit modules, an inter-module timing report is generated. This allows technicians to perform timing verification on the inter-module combinational logic that meets the timing requirements and to perform error correction and adjustment on the inter-module combinational logic that does not meet the timing requirements.

[0137] In some embodiments, the method further includes generating a timing report for the circuit layout based on the timing reports of each of the M circuit modules and the timing reports between the modules.

[0138] Among them, the timing report of the circuit module is used to reflect whether the path between the various registers included in the circuit module meets the timing requirements, and the timing report between modules is used to reflect whether the path between M circuit modules meets the timing requirements.

[0139] Timing reports for circuit layouts are used to reflect whether data transmission paths in the circuit layout meet timing requirements.

[0140] In some embodiments, the timing reports of each of the M circuit modules and the timing reports between modules are combined into a timing report for the circuit layout.

[0141] In some embodiments, if no timing violation is reported in the individual timing reports and inter-module timing reports of the M circuit modules, the individual timing reports and inter-module timing reports of the M circuit modules are combined into a timing report of the circuit layout.

[0142] In the above embodiment, the final circuit board is generated based on the timing reports of each of the M circuit modules and the timing reports between the modules. Figure 1 A timing report at the level of [level 1]. This allows technicians to confirm that all paths in the circuit layout meet design constraints and to perform static timing verification for the entire chip.

[0143] It should be noted that the different embodiments mentioned above, such as the different steps in different embodiments, can be arbitrarily combined to form new embodiments. All embodiments formed by combining the content described in the above embodiments should also fall within the protection scope of this application.

[0144] For example, please refer to Figure 8 The diagram illustrates a flowchart of a timing optimization method for a circuit layout according to an embodiment of this application. The method includes at least one of the following steps 810-890.

[0145] Step 810: Obtain the circuit layout, which includes M pre-deployed circuit modules.

[0146] Where M is an integer greater than 1.

[0147] Step 820: For each circuit module, determine the first submodule and the second submodule from that circuit module.

[0148] Step 830: Perform clock tree synthesis on the first submodule and the second submodule respectively according to the unified target clock delay.

[0149] The target clock delay is the clock delay that the register is expected to obtain.

[0150] Step 840: With the goal of satisfying the first hold time requirement and the first setup time requirement of the registers included in the circuit module, timing optimization is performed on the paths between the various registers included in the circuit module.

[0151] Step 850: Verify that the paths between each register meet the timing requirements and generate a timing report for the circuit module.

[0152] Step 860: Perform clock tree synthesis on each of the M first sub-modules according to the unified target clock delay.

[0153] Among them, the M first sub-modules are the first sub-modules included in each of the M circuit modules.

[0154] Step 870: With the goal of satisfying the second hold time requirements and the second setup time requirements of the registers included in the M first sub-modules respectively, timing optimization is performed on the path between the M circuit modules.

[0155] Step 880: Verify whether the paths between the M circuit modules meet the timing requirements, and generate an inter-module timing report.

[0156] Step 890: Generate a timing report for the circuit layout based on the timing reports of each of the M circuit modules and the timing reports between modules.

[0157] It is evident that the above-mentioned timing optimization method has the following beneficial effects: 1. High-quality optimization: The decoupled design allows clock tree synthesis tools to adopt optimal strategies for the different physical characteristics of I / O and internal registers, improving the quality of the local clock network and reducing the overall chip area and power consumption.

[0158] 2. Strong timing controllability: By setting a unified delay target, the seemingly independent clock networks in the unified circuit module are re-associated in timing, realizing active management and precise control of clock offset, and ensuring the determinism and reliability of timing convergence.

[0159] 3. Improved design efficiency: The unified delay target across modules allows different circuit modules to be synthesized independently of clock tree without compromising the timing of the top-level interface, supports parallel design flow, reduces the number of iterations in the timing optimization process, and shortens the design cycle.

[0160] 4. Good compatibility: This method is compatible with existing EDA tools and processes. It can be implemented by dividing the clock tree and modifying or adding clock constraints through EDA commands, without changing the underlying circuit architecture, resulting in low implementation cost.

[0161] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0162] Please refer to Figure 9 This diagram illustrates a block diagram of a circuit layout processing apparatus according to an embodiment of this application. The apparatus has the function of implementing the circuit layout processing method described above; this function can be implemented in hardware or by hardware executing corresponding software. The apparatus 900 can be a computer device or can be installed within a computer device. The apparatus 900 may include an acquisition module 910, a determination module 920, and an execution module 930.

[0163] The acquisition module 910 is used to acquire the circuit layout, which includes M pre-deployed circuit modules, where M is a positive integer.

[0164] The determining module 920 is used to determine a first submodule and a second submodule from any one of the M circuit modules, wherein the first submodule includes all or part of the structure of the input register and all or part of the structure of the output register in the circuit module, and the second submodule includes all or part of the structure of each internal register in the circuit module.

[0165] The execution module 930 is used to perform clock tree synthesis for the first submodule and the second submodule respectively.

[0166] In some embodiments, the execution module 930 is configured to perform clock tree synthesis on the first submodule and the second submodule respectively, based on the first parameters for clock tree synthesis of the first submodule and the second submodule respectively.

[0167] In some embodiments, the first parameter includes a first delay corresponding to the first submodule and a second delay corresponding to the second submodule.

[0168] The execution module 930 is configured to perform clock tree synthesis on the first submodule with the goal that the clock delay corresponding to each clock pin in the first submodule is close to the first delay; and to perform clock tree synthesis on the second submodule with the goal that the clock delay corresponding to each clock pin in the second submodule is close to the second delay; wherein the clock delay corresponding to the clock pin is the delay of the clock signal from the clock source of the circuit module to the clock pin, the first delay and the second delay are equal, or the difference between the first delay and the second delay is less than a first threshold.

[0169] In some embodiments, the execution module 930 is further configured to perform timing optimization on the path between the registers included in the circuit module with the goal of satisfying the first hold time requirement and the first setup time requirement of the registers included in the circuit module; the registers include at least one of the following: each input register, each output register and each internal register.

[0170] In some embodiments, the paths between the registers include at least one of the following: a path between an input register and an internal register, a path between different internal registers, and a path between an internal register and an output register.

[0171] In some embodiments, the above-described apparatus 900 further includes a generation module ( Figure 9 (Not shown in the image).

[0172] A generation module is used to generate a timing report for the circuit module. The timing report of the circuit module is used to reflect whether the paths between the various registers included in the circuit module meet the timing requirements.

[0173] In some embodiments, M is an integer greater than 1. The execution module 930 is further configured to perform clock tree synthesis on the M first sub-modules respectively according to the second parameters for clock tree synthesis of the M first sub-modules, wherein the M first sub-modules are the first sub-modules corresponding to the M circuit modules respectively.

[0174] In some embodiments, the second parameter includes the third delay corresponding to each of the M first sub-modules; the third delays corresponding to any two of the M first sub-modules are equal, or the difference between the corresponding third delays is less than the second threshold.

[0175] The execution module 930 described above is used to perform clock tree synthesis on each of the M first sub-modules, with the goal of making the clock delay corresponding to each clock pin in the first sub-module close to the third delay corresponding to the first sub-module; wherein, the clock delay corresponding to the clock pin is the delay of the clock signal from the clock source of the circuit module to the clock pin.

[0176] In some embodiments, the execution module 930 is further configured to perform timing optimization on the paths between the M circuit modules with the goal of satisfying the second hold time requirement and the second setup time requirement of the registers included in the M first sub-modules respectively.

[0177] In some embodiments, a generation module is used to generate an inter-module timing report, which reflects whether the paths between the M circuit modules meet timing requirements.

[0178] In some embodiments, the generation module is configured to generate a timing report for the circuit layout based on the timing reports of each of the M circuit modules and the timing reports between the modules; wherein the timing reports of the circuit modules are used to reflect whether the paths between the registers included in the circuit modules meet the timing requirements, and the timing reports between the modules are used to reflect whether the paths between the M circuit modules meet the timing requirements.

[0179] In some embodiments, the determining module 920 is configured to determine, from the clock tree structure of the circuit module, a first sub-clock tree with the clock source of the circuit module as the root node and the clock pins of each input register and each output register in the circuit module as leaf nodes, the first sub-clock tree being the first sub-module; and to determine, from the clock tree structure of the circuit module, a second sub-clock tree with the clock source as the root node and the clock pins of each internal register in the circuit module as leaf nodes, the second sub-clock tree being the second sub-module.

[0180] In some embodiments, the first submodule includes a first offset group, and the second submodule includes a second offset group. A determining module 920 is configured to assign each input register and each output register included in the circuit module to the first offset group, and to assign each internal register included in the circuit module to the second offset group.

[0181] It should be noted that the apparatus provided in the above embodiments is only illustrated by the division of the above functional modules when implementing its functions. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the apparatus and method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0182] Please refer to Figure 10 The diagram illustrates a structural block diagram of a computer device provided in one embodiment of this application.

[0183] Typically, computer device 1000 includes a processor 1001 and a memory 1002.

[0184] Processor 1001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 1001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 1001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 1001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content required to be displayed on the screen. In some embodiments, processor 1001 may also include an AI processor, which is used to handle computational operations related to machine learning.

[0185] The memory 1002 may include one or more computer-readable storage media, which may be tangible and non-transitory. The memory 1002 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage media in the memory 1002 stores a computer program that is loaded and executed by the processor 1001 to implement the processing method of the circuit layout described above.

[0186] Those skilled in the art will understand that Figure 10 The structure shown does not constitute a limitation on the computer device 1000, and may include more or fewer components than shown, or combine certain components, or use different component arrangements.

[0187] In some embodiments, a computer-readable storage medium is also provided, wherein a computer program is stored therein, the computer program being loaded and executed by a processor to implement the above-described circuit layout processing method.

[0188] Optionally, the computer-readable storage medium may include: ROM (Read-Only Memory), RAM (Random-Access Memory), SSD (Solid State Drives), or optical disc, etc. The random access memory may include ReRAM (Resistance Random Access Memory) and DRAM (Dynamic Random Access Memory).

[0189] In some embodiments, a computer program product is also provided, the computer program product including a computer program executed by a processor to implement the above-described circuit layout processing method.

[0190] In some embodiments, a computer program product is also provided, the computer program product including a computer program stored in a computer-readable storage medium, and a processor reading from the computer-readable storage medium and executing the computer program to implement the above-described circuit layout processing method.

[0191] It should be understood that "multiple" as used herein refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, the step numbers described herein are merely illustrative of one possible execution order. In some other embodiments, the steps may not be executed in numerical order, such as two steps with different numbers being executed simultaneously, or two steps with different numbers being executed in the reverse order of the illustration. This application does not limit this.

[0192] The above are merely exemplary embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application shall be included within the protection scope of this application.

Claims

1. A method for processing circuit layouts, characterized in that, The method includes: Obtain the circuit layout, which includes M pre-deployed circuit modules, where M is a positive integer; For any one of the M circuit modules, a first submodule and a second submodule are determined from the circuit module, wherein the first submodule includes all or part of the structure of the input register and all or part of the structure of the output register in the circuit module, and the second submodule includes all or part of the structure of the internal register in the circuit module. Clock tree synthesis is performed on the first submodule and the second submodule respectively.

2. The method according to claim 1, characterized in that, The step of performing clock tree synthesis on the first submodule and the second submodule respectively includes: Clock tree synthesis is performed on the first submodule and the second submodule respectively according to the first parameters set for clock tree synthesis.

3. The method according to claim 2, characterized in that, The first parameter includes the first delay corresponding to the first submodule and the second delay corresponding to the second submodule; The step of performing clock tree synthesis on the first submodule and the second submodule respectively according to the parameters set for clock tree synthesis includes: With the goal of ensuring that the clock delays corresponding to each clock pin in the first submodule are close to the first delay, clock tree synthesis is performed on the first submodule; and, With the goal of making the clock delay corresponding to each clock pin in the second submodule close to the second delay, clock tree synthesis is performed on the second submodule. The clock delay corresponding to the clock pin is the delay from the clock signal arriving at the clock pin from the clock source of the circuit module. The first delay and the second delay are equal, or the difference between the first delay and the second delay is less than a first threshold.

4. The method according to claim 1, characterized in that, After performing clock tree synthesis on the first submodule and the second submodule respectively, the process further includes: With the goal of meeting the first hold time requirements and the first setup time requirements of each register included in the circuit module, timing optimization is performed on the paths between the registers included in the circuit module; each register includes at least one of the following: each input register, each output register, and each internal register.

5. The method according to claim 4, characterized in that, The paths between the various registers include at least one of the following: The paths between the input register and the internal register, the paths between different internal registers, and the paths between the internal register and the output register.

6. The method according to claim 4, characterized in that, The method further includes: A timing report is generated for the circuit module, which reflects whether the paths between the various registers included in the circuit module meet the timing requirements.

7. The method according to claim 1, characterized in that, M is an integer greater than 1; the method further includes: Based on the second parameters of the clock tree synthesis for the M first sub-modules respectively set, clock tree synthesis is performed on the M first sub-modules respectively, and the M first sub-modules are the first sub-modules corresponding to the M circuit modules respectively.

8. The method according to claim 7, characterized in that, The second parameter includes the third delay corresponding to each of the M first sub-modules; the third delays corresponding to any two of the M first sub-modules are equal, or the difference between the corresponding third delays is less than the second threshold. The step of performing clock tree synthesis on each of the M first sub-modules according to the second parameters set for clock tree synthesis includes: For each of the M first sub-modules, clock tree synthesis is performed on the first sub-module with the goal of making the clock delay corresponding to each clock pin in the first sub-module close to the third delay corresponding to the first sub-module. The clock delay corresponding to the clock pin is the delay of the clock signal from the clock source of the circuit module to the clock pin.

9. The method according to claim 7, characterized in that, After performing clock tree synthesis on the M first sub-modules respectively, the process further includes: With the goal of satisfying the second hold time requirement and the second setup time requirement of the registers included in the M first sub-modules, timing optimization is performed on the paths between the M circuit modules.

10. The method according to claim 9, characterized in that, The method further includes: Generate an inter-module timing report, which reflects whether the paths between the M circuit modules meet the timing requirements.

11. The method according to claim 1, characterized in that, The method further includes: Based on the timing reports of each of the M circuit modules and the timing reports between modules, a timing report for the circuit layout is generated; The timing report of the circuit module is used to reflect whether the paths between the registers included in the circuit module meet the timing requirements, and the timing report between modules is used to reflect whether the paths between the M circuit modules meet the timing requirements.

12. The method according to any one of claims 1 to 11, characterized in that, The step of determining the first submodule and the second submodule from the circuit module includes: From the clock tree structure of the circuit module, a first sub-clock tree is determined, with the clock source of the circuit module as the root node and the clock pins of each input register and each output register in the circuit module as leaf nodes. This first sub-clock tree is the first sub-module. From the clock tree structure of the circuit module, a second sub-clock tree is determined, with the clock source as the root node and the clock pins of each internal register in the circuit module as leaf nodes. The second sub-clock tree is the second sub-module.

13. The method according to any one of claims 1 to 11, characterized in that, The first submodule includes a first offset group, and the second submodule includes a second offset group; determining the first submodule and the second submodule from the circuit module includes: The input registers and output registers of the circuit module are assigned to the first offset group, and the internal registers of the circuit module are assigned to the second offset group.

14. A circuit layout processing apparatus, characterized in that, The device includes: The acquisition module is used to acquire the circuit layout, which includes M pre-deployed circuit modules, where M is a positive integer; The determining module is used to determine a first submodule and a second submodule from any one of the M circuit modules, wherein the first submodule includes all or part of the structure of the input register and all or part of the structure of the output register in the circuit module, and the second submodule includes all or part of the structure of the internal register in the circuit module. The execution module is used to perform clock tree synthesis for the first submodule and the second submodule respectively.

15. A computer device, characterized in that, The computer device includes a processor and a memory, the memory storing a computer program that is loaded and executed by the processor to implement the method as claimed in any one of claims 1 to 13.

16. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which is loaded and executed by a processor to implement the method as described in any one of claims 1 to 13.

17. A computer program product, characterized in that, The computer program product includes a computer program executed by a processor to implement the method as described in any one of claims 1 to 13.

Images