Low power consumption control method, medium and low power consumption processor of network message pre-classification processor

Abstract

The present application provides a low-power control method, medium and low-power processor for a network message pre-classification processor, supports a scheduling strategy based on an index generated by a microengine cluster, a microengine group and a microengine arrangement order, and supports dynamic modification of the total number of microengines and the microengine scheduling strategy. Users can dynamically switch scheduling strategies according to traffic load. A fully shared storage structure is also adopted, each microengine group includes a microengine group memory, which is only accessible to the microengines within the group, and each microengine cluster is provided with a microengine cluster memory, which can be shared by all microengines in the cluster, saving more area and power consumption. When the number of microengines used is less than the total number of microengines in the microengine pool, the enable mapping table in the packet inlet scheduling module and the packet outlet scheduling module will generate an enable control signal for the microengine and the related memory according to the number of microengines currently actually used and the scheduling rules, shut down the idle microengines and memory, and reduce power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of network message pre-classification processing, and in particular to a low-power consumption control method, medium and low-power consumption processor of a network message pre-classification processor. Background Art

[0002] With the rapid development of network technology, especially the introduction of the "low-carbon economy" development concept, the low power consumption characteristics of high-performance network processors have attracted more and more attention. At present, the industry mainly adopts a multi-core network processor architecture, and the message pre-classification processor is responsible for pre-analyzing incoming messages, classifying traffic based on message characteristics, and even directly forwarding. From the perspective of performance and programmability, it also adopts a multi-core structure. Although multi-core is an effective way to improve processor performance, the core is often also a key factor affecting system power consumption.

[0003] Some traditional multi-core network processors usually use a certain number of cores and supporting storage resources based on the maximum performance indicators, and then evenly dispatch messages to each micro-engine for processing to ensure performance. However, in some low-traffic scenarios, this method will increase the number of redundant online cores, resulting in a waste of power consumption. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a low-power control method, medium and low-power processor of a network message pre-classification processor, so as to solve the technical problem of high power consumption of the message pre-classifier.

[0005] To achieve the above-mentioned purpose and other related purposes, the first aspect of the present application provides a low-power control method for a low-power network message pre-classification processor, comprising: after the message to be processed enters the pre-classification processor, it is parsed by a message feature parsing module to generate a message pre-parsing result; when the packet inlet scheduling module detects the message pre-parsing result output by the message feature parsing module, a micro-engine number of a message to be received is provided; if the corresponding micro-engine in the micro-engine pool is in a state of being ready to receive the message, the message header and the message pre-parsing result are sent to the micro-engine; wherein the sending action triggers the sequencer in the packet inlet scheduling module to shift backward , in order to prepare a new micro-engine number, so as to enter the new micro-engine according to the new micro-engine number when the next message pre-parsing result is output; after the micro-engine completes message processing, the packet output scheduling module authorizes the prepared micro-engine output packet processing result according to the current number of the internal sequencer; if the post-processing device of the network message pre-classification processor is in a state of being ready to receive the packet processing result, the packet processing result is sent to the post-processing device; the sending action triggers the sequencer in the packet output scheduling module to shift backward to prepare the new micro-engine number; wherein, the packet input scheduling module and the packet output scheduling module support a variety of low-power scheduling strategies.

[0006] In some embodiments of the first aspect of the present application, the microengine pool includes a plurality of microengine clusters; each microengine cluster includes a plurality of microengine groups, and each microengine group includes a plurality of microengines; a microengine cluster memory is provided for a preset number of microengine clusters for shared access by all microengines in the cluster to obtain instructions or data; and a microengine group memory is provided for each microengine group for shared access by all microengines in the group to obtain instructions or data.

[0007] In some embodiments of the first aspect of the present application, each of the microengines processes input messages in a 5-stage pipeline manner to perform any one or more of the following operations according to the business microcode: instruction fetch operation, decoding operation, execution operation and table lookup operation.

[0008] In some embodiments of the first aspect of the present application, the scheduling strategies supported by the incoming packet scheduling module and the outgoing packet scheduling module include any one of the following strategies or a combination of multiple strategies:

[0009] Scheduling strategy 1: Process the initial microengine in the initial group and generate a microengine index; after processing other microengines in the initial group in sequence, process other groups with the same cluster number in sequence according to the group number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated;

[0010] Scheduling strategy 2: Process the initial microengine in the initial group and generate a microengine index; after processing other microengines in the initial group in turn, process other groups with the same group number in different clusters in turn according to the cluster number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated;

[0011] Scheduling strategy 3: Process the initial microengine in the initial group and generate a microengine index, and process other microengines with the same group number and group number as the initial microengine in different clusters in sequence according to the cluster number; repeat the above operation to traverse other microengines in the initial group; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated;

[0012] Scheduling strategy 4: Process the initial microengine in the initial group and generate a microengine index, and process other microengines with the same group number and group number as the initial microengine in different clusters in sequence according to the cluster number; flip to the microengine with the same group number as the initial microengine in the next group in the cluster where the initial group is located, and repeat the above operation to traverse the microengines with the same group number in different groups in different clusters; and so on, until all microengines in the microengine pool are traversed and a microengine index is generated;

[0013] Scheduling strategy 5: Process the initial microengine in the initial group and generate a microengine index, and then traverse the other microengines with the same group number as the initial microengine in sequence according to the group number and cluster number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated;

[0014] Scheduling strategy 6: process the initial microengine in the initial group and generate a microengine index, and then process other microengines in different groups in the cluster with the same group sequence number as the initial microengine; repeat the above operation to traverse all microengines in the cluster; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated.

[0015] In some embodiments of the first aspect of the present application, the low-power control method also includes: in response to a user's scheduling strategy selection instruction, dynamically sending a scheduling strategy selection and a signal of the number of micro-engines used to the packet-in scheduling module and the packet-out scheduling module; the packet-in scheduling module and the packet-out scheduling module switch to the selected scheduling strategy after all micro-engines have been selected for one round under the currently executing scheduling strategy.

[0016] In some embodiments of the first aspect of the present application, the packet inbound scheduling module and the packet outbound scheduling module each integrate a micro-engine enable table with consistent mapping rules, which is used to index the micro-engines and their related memories that need to be turned on in the inbound and outbound directions according to the scheduling strategy and number of micro-engines currently in use, respectively, to generate enable control signals for the micro-engines and related memories, and shut down idle micro-engines and memories.

[0017] In some embodiments of the first aspect of the present application, the enable signal of the outgoing packet scheduling module is sent to the incoming packet scheduling module for aggregation to generate a multi-bit enable signal; each bit of the enable signal controls a microengine or a memory; the microengine enable controls whether the microengine is enabled by clock gating, and the memory enable reduces power consumption by lowering the voltage provided to the memory, and is used to prevent the loss of stored data.

[0018] To achieve the above-mentioned purpose and other related purposes, the second aspect of the present application provides a low-power network message pre-classification processor, including:

[0019] A feature analysis module, used for receiving the message to be processed and analyzing it to generate a message pre-analysis result;

[0020] The packet-in scheduling module is used to provide a micro-engine number of a message to be received when the message pre-parsing result output by the message feature parsing module is detected; if the corresponding micro-engine in the micro-engine pool is ready to receive the message, the message header and the message pre-parsing result are sent to the micro-engine; wherein the sending action triggers the sequencer in the packet-in scheduling module to shift backward to prepare a new micro-engine number, so as to enter the new micro-engine according to the new micro-engine number when the next message pre-parsing result is output;

[0021] The packet output scheduling module is used to authorize the prepared packet processing result output by the micro-engine according to the current number of the internal sequencer after the micro-engine completes the message processing; if the post-processing device of the network message pre-classification processor is ready to receive the packet processing result, the packet processing result is sent to the post-processing device; the sending action triggers the sequencer in the packet output scheduling module to shift backward to prepare a new micro-engine number; wherein the packet input scheduling module and the packet output scheduling module support multiple low-power scheduling strategies.

[0022] In some embodiments of the second aspect of the present application, the microengine pool is also included; the microengine pool includes a plurality of microengine clusters; each microengine cluster includes a plurality of microengine groups, and each microengine group includes a plurality of microengines; a microengine cluster memory is set for a preset number of microengine clusters for shared access by all microengines in the cluster to obtain instructions or data; and a microengine group memory is set for each microengine group for shared access by all microengines in the group to obtain instructions or data.

[0023] In some embodiments of the second aspect of the present application, the packet inbound scheduling module and the packet outbound scheduling module each integrate a micro-engine enable table with consistent mapping rules, which is used to index the micro-engines and their related memories that need to be turned on in the inbound and outbound directions according to the scheduling strategy and number of micro-engines currently in use, respectively, to generate enable control signals for the micro-engines and related memories, and shut down idle micro-engines and memories.

[0024] To achieve the above-mentioned purpose and other related purposes, the third aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, a low power consumption control method of the network message pre-classification processor is implemented.

[0025] As described above, the low power consumption control method, medium and low power consumption processor of the network message pre-classification processor of the present application have the following beneficial effects:

[0026] 1) The present invention supports scheduling strategies based on indexes generated by microengine clusters, microengine groups, and microengine arrangement sequences, and supports dynamic modification of the total number of microengines and microengine scheduling strategies. Users can dynamically switch scheduling strategies based on traffic load, which can not only adjust the organizational structure of actual working microengines and optimize processing performance, but also reduce the number of lightly loaded microengines and the memory they occupy, making them in a closable state.

[0027] 2) The present invention adopts a fully shared storage structure, wherein each microengine group includes a microengine group memory, which is only accessible to the microengines in the group, and each microengine cluster is provided with a microengine cluster memory, which can be shared by all microengines in the cluster. No microengine is provided with an exclusive memory, and access to the shared memory saves more area and power consumption while meeting the performance of instruction fetch and table lookup.

[0028] 3) When the number of microengines in use is less than the total number of microengines in the microengine pool, the enable mapping table in the packet inbound scheduling module and the packet outbound scheduling module will generate an enable control signal for the microengine and related memory according to the number of microengines currently in use and the scheduling rules, shut down the idle microengines and memory, and reduce power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Shown is a flow chart of a low power consumption control method of a low power consumption network message pre-classification processor in one embodiment of the present application.

[0030] Figure 2 Shown is a schematic diagram of the micro-engine organizational structure in an embodiment of the present application.

[0031] Figure 3 Shown is a schematic diagram of six scheduling strategies in an embodiment of the present application.

[0032] Figure 4 Shown is a schematic diagram of the scheduling results of scheduling strategy 1 in one embodiment of the present application.

[0033] Figure 5 Shown is a schematic diagram of the scheduling results of scheduling strategy 4 in one embodiment of the present application.

[0034] Figure 6 Shown is a structural schematic diagram of a low-power network message pre-classification processor in one embodiment of the present application. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0036] It should be noted that in the following description, with reference to the accompanying drawings, several embodiments of the present application are described in the accompanying drawings. It should be understood that other embodiments may also be used, and mechanical composition, structure, electrical and operational changes may be made without departing from the spirit and scope of the present application. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present application is limited only by the claims of the published patents. The terms used here are only for describing specific embodiments and are not intended to limit the present application. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0037] In this application, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix", "hold" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0038] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0039] In order to solve the problems in the above-mentioned background technology, the present invention provides a low-power control method, medium and low-power processor of a network message pre-classification processor. The network message pre-classification processor includes a plurality of general programmable microengines, which form a microengine pool. The microengine pool is hierarchically organized in the form of clusters and groups. Each cluster and group has a corresponding memory. The incoming message is pre-parsed by the message feature parsing unit, and then the message and the pre-parsed result are dispatched to the corresponding microengine according to the microengine number output by the incoming packet scheduling module. The microengine executes the microcode instruction to process the message. After the processing is completed, the microengine outputs the message and the final parsing result when obtaining the authorization of the outgoing packet scheduling module. The outgoing and incoming packet scheduling modules support multiple scheduling strategies. By synchronously switching the scheduling rules of the incoming packet scheduling module and the outgoing packet scheduling module, the microengine and memory used by the processor can be adjusted in real time, and then the hardware automatically shuts down the idle microengine and memory to achieve the goal of balancing performance and power consumption.

[0040] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the technical solution in the embodiments of the present invention is further described in detail through the following embodiments and in combination with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the invention.

[0041] The embodiment of the present invention provides a low-power consumption control method of a low-power network message pre-classification processor, a system of the low-power consumption control method of the low-power network message pre-classification processor, and a storage medium storing an executable program for implementing the low-power consumption control method of the low-power network message pre-classification processor. As for the implementation of the low-power consumption control method of the low-power network message pre-classification processor, the embodiment of the present invention will illustrate an exemplary implementation scenario of the low-power consumption control of the low-power network message pre-classification processor.

[0042] like Figure 1 As shown, a flowchart of a low-power consumption control method of a low-power consumption network message pre-classification processor in an embodiment of the present invention is shown. The low-power consumption method in this embodiment mainly includes the following steps:

[0043] Step S11: After the message to be processed enters the pre-classification processor, it is parsed by the message feature parsing module to generate a message pre-parsing result.

[0044] Step S12: When the packet-in scheduling module detects the message pre-parsing result output by the message feature parsing module, it provides a micro-engine number of a message to be received; if the corresponding micro-engine in the micro-engine pool is ready to receive the message, the message header and the message pre-parsing result are sent to the micro-engine; wherein the sending action triggers the sequencer in the packet-in scheduling module to shift backward to prepare a new micro-engine number, so as to enter the new micro-engine according to the new micro-engine number when the next message pre-parsing result is output.

[0045] In this embodiment, the microengine pool includes a plurality of microengine clusters; each microengine cluster includes a plurality of microengine groups, and each microengine group includes a plurality of microengines; a microengine cluster memory is set for a preset number of microengine clusters for shared access by all microengines in the cluster to obtain instructions or data; and a microengine group memory is set for each microengine group for shared access by all microengines in the group to obtain instructions or data.

[0046] For the convenience of understanding by those skilled in the art, Figure 2 The microengine organizational structure shown is used as an example for explanation: the microengine cluster contains a total of 48 microengines, and every 4 microengines (microengine 0 to microengine 3) constitute a microengine group, and a microengine group memory is set for the microengines in the group to share access and obtain instructions or data. Every 3 microengine groups (microengine group MEM1 to microengine group MEM3) constitute a microengine cluster, and every 2 microengine clusters are set with a microengine cluster memory for all microengines in the cluster (microengine 0 to microengine 11) to share and obtain instructions or data.

[0047] In this embodiment, the microengine processes the input message in a 5-stage pipeline manner, and can perform operations such as instruction fetch (IF), decoding (ID), execution (ALU), and table lookup according to the business microcode. Compared with the microengine cluster memory, the distance between the microengine group memory and the microengine in the group is shorter, and the bandwidth supporting a single microengine to access is larger, so the object of instruction fetch and search is mainly the microengine group memory, so as to reduce the delay of the microengine waiting for the result to be returned and improve the performance.

[0048] It should be understood that the "5-stage pipeline" refers to the division of instructions into five stages: fetch (ID), decode (ID), execute (ALU), access memory (MEM), write back (WB). "Microcode" is a CPU instruction set as a sequence of microcode instructions (microinstructions), each of which is electrically composed of many bit fields and the address of the next microinstruction to be executed. Microcode is a translation layer between machine instructions and computer elementary transformations. Microcode is stored in ROM and allows new machine instructions to be added without the need for them to be designed as electronic switches.

[0049] It is worth noting that the present invention adopts a fully shared storage structure, wherein each microengine group includes a microengine group memory, which is only accessible to the microengines in the group, and each microengine cluster is provided with a microengine cluster memory, which can be shared by all microengines in the cluster. No microengine is provided with an exclusive memory, and access to the shared memory saves more area and power consumption while satisfying the performance of instruction fetch and table lookup.

[0050] Step S13: After the micro-engine completes message processing, the packet output scheduling module authorizes the prepared packet processing result output by the micro-engine according to the current number of the internal sequencer; if the post-processing device of the network message pre-classification processor is ready to receive the packet processing result, the packet processing result is sent to the post-processing device; the sending action triggers the sequencer in the packet output scheduling module to shift backward to prepare a new micro-engine number; wherein the packet input scheduling module and the packet output scheduling module support a variety of low-power scheduling strategies.

[0051] In this embodiment, the packet inbound scheduling module and the packet outbound scheduling module can support 6 scheduling strategies. The strategy selection principle in the embodiment of the present invention is to first calculate the required number of engines and memory access bandwidth according to different traffic loads, and then select according to the characteristics of the 6 scheduling strategies. The advantages and characteristics of each scheduling strategy will be described in detail below. Under any scheduling strategy, the first 48 messages are sent to the corresponding micro-engine number as follows Figure 3 As shown, the cycle then begins. The generation principles of these six scheduling strategies are as follows:

[0052] For the convenience of representation, let E i (0≦i≦3) represents microengine i, G j (0≦j≦2) represents micro-engine group j, Ck(0≦k≦3) represents micro-engine cluster k, and the first micro-engine scheduled by all strategies is E0G0C0, which represents micro-engine 0.

[0053] Scheduling strategy 1: Process the initial microengine in the initial group and generate a microengine index; after processing other microengines in the initial group in turn, process other groups with the same cluster number in turn according to the group number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated.

[0054] It is worth mentioning that the advantages and characteristics of scheduling strategy 1 are: if in some business scenarios, only 24 micro-engines are needed to handle the performance requirements, then if scheduling strategy 1 is selected, such as Figure 4 As shown, all microengines in microengine cluster 2 and microengine cluster 3 and their group-shared and cluster-shared memories are turned off, which can greatly save computing resources and reduce energy consumption.

[0055] For example: Scheduling strategy 1 can be expressed as E i G j C k , which means that i is accumulated from 0 to 3 first, and each time it accumulates 1, j and k are both 0, generating microengine indexes E1G0C0, E2G0C0, E3G0C0, which represent microengine 1, microengine 2 and microengine 3 respectively. After i accumulates to 3, it flips. At this time, j accumulates 1, and microengine indexes E0G1C0, E1G1C0, E2G1C0, E3G1C0 represent microengine 4, microengine 5, microengine 6 and microengine 7 respectively..., and when j accumulates to 2 and flips, k accumulates 1, and microengine indexes E0G0C1, E1G0C1, E2G0C1, E3G0C1 represent microengine 12, microengine 13, microengine 14 and microengine 15 respectively... and so on, until the last microengines 44, microengine 45, microengine 46 and microengine 47 are processed.

[0056] Scheduling strategy 2: Process the initial microengine in the initial group and generate a microengine index; after processing other microengines in the initial group in turn, process other groups with the same group number in different clusters in turn according to the cluster number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated.

[0057] It is worth noting that the advantages and characteristics of scheduling strategy 2 are: assuming that the business scenario requires the processing power of 16 microengines, according to strategy 2, the four microengine groups of each microengine group 0 of microengine clusters 0 to 3 can be enabled and share microengine cluster Memory0; if strategy 1 is adopted, due to performance consistency requirements, only microengine cluster 0 and microengine cluster 1 can be enabled at the same time, with a total of 24 microengines, which increases the number of redundant online cores and power consumption. Therefore, scheduling strategy 2 can better reduce the number of cores and reduce power consumption.

[0058] For example: Scheduling strategy 2 can be expressed as E i C k G j , which means that i is accumulated from 0 to 3 first, and each time it accumulates 1, j and k are both 0, generating microengine indexes E1C0G0, E2C0G0 and E3C0G0, which represent microengine 1, microengine 2 and microengine 3 respectively. After i accumulates to 3, it flips. At this time, k accumulates 1, and the microengine indexes E0C1G0, E1C1G0, E2C1G0, E3C1G0 represent microengine 12, microengine 13, microengine 14 and microengine 15 respectively..., and when k accumulates to 3 and flips, j accumulates 1, and the microengine indexes E0C0G1, E1C0G1, E2C0G1, E3C0G1 represent microengine 4, microengine 5, microengine 6 and microengine 7 respectively... and so on, until the last microengines 44, microengine 45, microengine 46 and microengine 47 are processed.

[0059] Scheduling strategy 3: Process the initial microengine in the initial group and generate a microengine index, and process other microengines with the same group number and group number as the initial microengine in different clusters in sequence according to the cluster number; repeat the above operation to traverse other microengines in the initial group; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated.

[0060] It is worth mentioning that the advantages and characteristics of scheduling strategy 3 are: assuming that the business scenario requires the processing power of 8 microengines, according to strategy 3, microengines 0, 12, 24, 36, 1, 13, 25, and 37 are enabled. According to strategy 1, microengines 0, 1, 2, 3, 4, 5, 6, and 7 are enabled. Compared with strategy 1, the access bandwidth of each microengine in strategy 3 to the group shared memory and cluster shared memory is doubled without adding additional hardware resources.

[0061] For example: Scheduling strategy 3 can be expressed as C k E i G j , which means k is accumulated from 0 to 3 first, and each time it accumulates 1, i and j are both 0, generating microengine indexes C1E0G0, C2E0G0, C3E0G0, which represent microengine 12, microengine 24 and microengine 36 respectively. After k accumulates to 3, it flips. At this time, i accumulates 1, and microengine indexes C0E1G0, C1E1G0, C2E1G0, C3E1G0 represent microengine 1, microengine 13, microengine 25 and microengine 37 respectively..., and when i accumulates to 3 and flips, j accumulates 1, and microengine indexes C0E0G1, C1E0G1, C2E0G1, C3E0G1 represent microengine 4, microengine 16, microengine 28 and microengine 40 respectively... and so on, until the last microengine 11, microengine 23, microengine 35, microengine 47 are processed.

[0062] Scheduling strategy 4: Process the initial microengine in the initial group and generate a microengine index, and process other microengines with the same group number and group number as the initial microengine in different clusters in sequence according to the cluster number; flip to the microengine with the same group number as the initial microengine in the next group in the cluster where the initial group is located, and repeat the above operation to traverse all microengines with the same group number in different groups in different clusters; and so on, until all microengines in the microengine pool are traversed and a microengine index is generated.

[0063] It is worth noting that the advantages and characteristics of scheduling strategy 4 are: Assuming that the business scenario requires the processing power of 24 micro-engines, if scheduling strategy 4 is selected, Figure 5 As shown in the figure, the memory of the enabled micro-engine group becomes shared by two micro-engines, and the bandwidth of access by a single micro-engine is doubled.

[0064] Scheduling strategy 4 can be expressed as C k G j E i , which means k is accumulated from 0 to 3 first, and each time it is accumulated by 1, j and i are both 0, and the microengine indexes C1G0E0, C2G0E0, and C3G0E0 represent microengine 12, microengine 24, and microengine 36 respectively. After k is accumulated to 3, it is flipped. At this time, j is accumulated by 1, and the microengine indexes C0G1E0, C1G1E0, C2G1E0, and C3G1E0 represent microengine 4, microengine 16, microengine 28, and microengine 40 respectively..., and when j is accumulated to 2, it is flipped, and i is accumulated by 1. The microengine indexes C0G0E1, C1G0E1, C2G0E1, and C3G0E1 represent microengine 1, microengine 13, microengine 25, and microengine 37 respectively...

[0065] Scheduling strategy 5: Process the initial microengine in the initial group and generate a microengine index, and traverse other microengines with the same group number as the initial microengine in sequence according to the group number and cluster number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated.

[0066] It is worth mentioning that the advantages and characteristics of scheduling strategy 5 are: Figure 2 ,Assume that the business scenario requires the processing power of 12 microengines.,According to strategy 5, microengines 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, and 44 will be enabled.,According to strategy 1, microengines 0 to 11 will be enabled.,Compared to strategy 1, the access bandwidth of each microengine in strategy 5 to the group shared memory,increases three times, and the access bandwidth to the cluster shared memory,doubles without adding additional hardware resources.

[0067] For example: Scheduling strategy 4 can be expressed as C k G j E i , which means k is accumulated from 0 to 3 first, and each time it accumulates 1, j and i are both 0, generating microengine indexes C1G0E0, C2G0E0, C3G0E0, which represent microengine 12, microengine 24 and microengine 36 respectively. After k accumulates to 3, it flips. At this time, j accumulates 1, and microengine indexes C0G1E0, C1G1E0, C2G1E0, C3G1E0 represent microengine 4, microengine 16, microengine 28 and microengine 40 respectively..., and when j accumulates to 2 and flips, i accumulates 1, and microengine indexes C0G0E1, C1G0E1, C2G0E1, C3G0E1 represent microengine 1, microengine 13, microengine 25 and microengine 37 respectively... and so on, until the last microengine 35, microengine 39, microengine 43, microengine 47 are processed.

[0068] Scheduling strategy 6: process the initial microengine in the initial group and generate a microengine index, and then process other microengines in different groups in the cluster with the same group sequence number as the initial microengine; repeat the above operation to traverse all microengines in the cluster; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated.

[0069] It is worth mentioning that the advantages and characteristics of scheduling strategy 6 are: Figure 2 ,Assume that the business scenario requires the processing power of 6 micro-engines. According to strategy 6, micro-engines 0, 4, 8, 1, 5, and 9 are enabled. If strategy 1 is adopted, due to the performance consistency requirement, only 8 micro-engines, 0 to 7, can be enabled at the same time, which increases the number of redundant online cores and power consumption.

[0070] For example: Scheduling strategy 6 can be expressed as G j E i C k , which means that j is accumulated from 0 to 2 first, and each time it accumulates 1, i and k are both 0, generating microengine indexes G1E0C0 and G2E0C0, which represent microengine 4 and microengine 8 respectively. After j accumulates to 2, it flips. At this time, i accumulates 1, and the microengine indexes G0E1C0, G1E1C0, and G2E1C0 represent microengine 1, microengine 5, and microengine 9 respectively..., and when i accumulates to 3 and flips, k accumulates 1, and the microengine indexes G0E0C1, G1E0C1, and G2E0C1 represent microengine 12, microengine 16, and microengine 20 respectively... and so on, until the last microengines 39, 43, and 47 are processed.

[0071] It should be noted that the six scheduling strategies 1 to 6 in the above embodiment are not just permutations and combinations of the number and order of microengine selection. Each scheduling strategy has its own unique advantages and characteristics, and are technical means explored in the actual research and development process.

[0072] In this embodiment, the method also includes: responding to the user's scheduling strategy selection instruction, dynamically sending the scheduling strategy selection and the number of micro-engines used to the packet input scheduling module and the packet output scheduling module; after all micro-engines have been selected for one round under the currently executed scheduling strategy, the packet input scheduling module and the packet output scheduling module switch to the selected scheduling strategy, thereby avoiding destroying the consistency of the order of incoming and outgoing packets.

[0073] In this embodiment, the packet inbound scheduling module and the packet outbound scheduling module are each integrated with a micro-engine enable table with consistent mapping rules, which is used to index the micro-engines and their related memories that need to be turned on in the inbound and outbound directions according to the scheduling strategy and the number of micro-engines actually used, respectively, to generate enable control signals for the micro-engines and related memories, and shut down idle micro-engines and memories.

[0074] It is worth noting that: when the number of microengines in use is less than the total number of microengines in the microengine pool, the enable mapping table in the packet inlet scheduling module and the packet outlet scheduling module will generate an enable control signal for the microengine and related memory according to the number of microengines currently in use and the scheduling rules, shut down the idle microengines and memory, and reduce power consumption.

[0075] Furthermore, the enable signal of the outgoing packet scheduling module is sent to the incoming packet scheduling module for aggregation to generate a multi-bit enable signal; each bit of the enable signal controls one microengine or memory; the microengine enable controls whether the microengine is enabled through clock gating, and the memory enable reduces power consumption by lowering the voltage provided to the memory, while preventing the loss of stored data.

[0076] The following example illustrates the impact of changes in the number of microengines and scheduling strategies on system power consumption and performance:

[0077] Currently, 48 micro-engines are used to process messages. In a certain period of time, the traffic load changes, and only 24 micro-engines are needed to meet the processing performance requirements. At this time, the user sends the switching information. If scheduling strategy 1 is selected, such as Figure 4 As shown, all microengines in microengine cluster 2 and microengine cluster 3 and their group shared and cluster shared memories are all closed; if scheduling strategy 4 is selected, such as Figure 5 As shown in the figure, each micro-engine group can shut down two micro-engines. Therefore, scheduling strategy 1 can shut down more micro-engines and memory than scheduling strategy 4, which can save more power. The advantage of scheduling strategy 4 is that the memory of the enabled micro-engine group becomes shared by two micro-engines, supporting the bandwidth accessed by a single micro-engine to double.

[0078] like Figure 6 , which shows a schematic diagram of the structure of a low-power network message pre-classification processor in an embodiment of the present invention. The network message pre-classification processor in this embodiment includes: a feature analysis module 601, an incoming packet scheduling module 602 and an outgoing packet scheduling module 603.

[0079] The feature analysis module 601 is used to receive the message to be processed and analyze it to generate a message pre-analysis result.

[0080] The packet-in scheduling module 602 is used to provide a micro-engine number of a message to be received when the message pre-parsing result output by the message feature parsing module is detected; if the corresponding micro-engine in the micro-engine pool is ready to receive the message, the message header and the message pre-parsing result are sent to the micro-engine; wherein the sending action triggers the sequencer in the packet-in scheduling module to shift backward to prepare a new micro-engine number, so that when the next message pre-parsing result is output, the new micro-engine is entered according to the new micro-engine number.

[0081] The packet output scheduling module 603 is used to authorize the prepared packet processing result output by the micro-engine according to the current number of the internal sequencer after the micro-engine completes the message processing; if the post-processing device of the network message pre-classification processor is ready to receive the packet processing result, the packet processing result is sent to the post-processing device; the sending action triggers the sequencer in the packet output scheduling module to shift backward to prepare a new micro-engine number; wherein the packet input scheduling module and the packet output scheduling module support a variety of low-power scheduling strategies.

[0082] It should be noted that: the network message pre-classification processor provided in the above embodiment only uses the division of the above program modules as an example when performing network message pre-classification. In actual applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the device is divided into different program modules to complete all or part of the processing described above. In addition, the network message pre-classification processor provided in the above embodiment and the low-power consumption control method embodiment of the network message pre-classification processor belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0083] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to the computer program. The aforementioned computer program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, magnetic disk or optical disk and other media that can store program codes.

[0084] In the embodiments provided in the present application, the computer readable and writable storage medium may include a read-only memory, a random access memory, an EEPROM, a CD-ROM or other optical disk storage device, a disk storage device or other magnetic storage device, a flash memory, a USB flash drive, a mobile hard disk, or any other medium that can be used to store a desired program code in the form of an instruction or data structure and can be accessed by a computer. In addition, any connection can be appropriately a computer readable medium. For example, if the instruction is sent from a website, a server or other remote source using a coaxial cable, an optical fiber cable, a twisted pair, a digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwaves, the coaxial cable, optical fiber cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwaves are included in the definition of the medium. However, it should be understood that computer readable and writable storage media and data storage media do not include connections, carriers, signals, or other temporary media, but are intended to be non-temporary, tangible storage media. Disk and disc, as used in this application, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers.

[0085] In summary, the present application provides a low-power control method, medium and low-power processor for a network message pre-classification processor. The present invention supports a strategy for scheduling based on an index generated by a microengine cluster, a microengine group and a microengine arrangement order, and supports dynamic modification of the total number of microengines and the microengine scheduling strategy. Users can dynamically switch scheduling strategies according to traffic loads, which can not only adjust the organizational structure of the actual working microengines and optimize processing performance, but also reduce the number of light-load microengines and the memory they occupy, making them closable. The present invention adopts a fully shared storage structure, in which each microengine group includes a microengine group memory, which is only accessible to the microengines within the group, and each microengine cluster is provided with a microengine cluster memory, which can be shared by all microengines in the cluster. Any microengine does not set an exclusive memory, and accessing the shared memory saves more area and power consumption under the premise of satisfying the performance of instruction fetching and table lookup. When the number of microengines in use is less than the total number of microengines in the microengine pool, the enable mapping table in the packet inlet scheduling module and the packet outlet scheduling module will generate an enable control signal for the microengine and the related memory according to the number of microengines currently in use and the scheduling rules, shut down the idle microengines and memory, and reduce power consumption. Therefore, the present application effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0086] The above embodiments are merely illustrative of the principles and effects of the present application and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A low power consumption control method for a low power consumption network message pre-classification processor, characterized in that: include: After the message to be processed enters the pre-classification processor, it is parsed by the message feature parsing module to generate a message pre-parsing result; When the packet-in scheduling module detects the message pre-analysis result output by the message feature analysis module, it provides a micro-engine number of a message to be received; If the corresponding micro-engine in the micro-engine pool is in a state of being ready to receive a message, the message header and the message pre-parsing result are sent to the micro-engine; wherein the sending action triggers the sequencer in the packet-in scheduling module to shift backward to prepare a new micro-engine number, so that when the next message pre-parsing result is output, the new micro-engine is entered according to the new micro-engine number; the micro-engine pool includes a plurality of micro-engine clusters; each micro-engine cluster includes a plurality of micro-engine groups, and each micro-engine group includes a plurality of micro-engines; a micro-engine cluster memory is set for a preset number of micro-engine clusters for shared access by all micro-engines in the cluster to obtain instructions or data; and a micro-engine group memory is set for each micro-engine group for shared access by all micro-engines in the group to obtain instructions or data; After the micro-engine completes message processing, the packet output scheduling module authorizes the prepared packet processing result output by the micro-engine according to the current number of the internal sequencer; if the post-processing device of the network message pre-classification processor is in a state of being ready to receive the packet processing result, the packet processing result is sent to the post-processing device; the sending action triggers the sequencer in the packet output scheduling module to shift backward to prepare a new micro-engine number; wherein the packet input scheduling module and the packet output scheduling module support a variety of low-power scheduling strategies; the packet input scheduling module and the packet output scheduling module are each integrated with a micro-engine enable table with consistent mapping rules, which is used to index the scheduling strategy and the number of micro-engines currently actually used to the micro-engines and their related memories that need to be turned on in the inbound and outbound directions, respectively, so as to generate an enable control signal for the micro-engines and related memories, and turn off the idle micro-engines and memories.

2. The low power consumption control method of the network message pre-classification processor according to claim 1, characterized in that: Each of the microengines processes input messages in a five-stage pipeline manner to perform any one or more of the following operations according to the business microcode: instruction fetch operation, decoding operation, execution operation and table lookup operation.

3. The low power consumption control method of the network message pre-classification processor according to claim 1, characterized in that: The scheduling strategies supported by the packet inbound scheduling module and the packet outbound scheduling module include any one of the following strategies or a combination of multiple strategies: Scheduling strategy 1: Process the initial microengine in the initial group and generate a microengine index; after processing other microengines in the initial group in sequence, process other groups with the same cluster number in sequence according to the group number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated; Scheduling strategy 2: Process the initial microengines in the initial group and generate microengine indexes; After processing other micro-engines in the initial group in sequence, other groups with the same group number in different clusters are processed in sequence according to the cluster number; and so on, until all micro-engines in the micro-engine pool are traversed and micro-engine indexes are generated; Scheduling strategy 3: Process the initial microengine in the initial group and generate a microengine index, and process other microengines with the same group number and group number as the initial microengine in different clusters in sequence according to the cluster number; repeat the above operation to traverse other microengines in the initial group; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated; Scheduling strategy 4: Process the initial microengine in the initial group and generate a microengine index, and process other microengines with the same group number and group number as the initial microengine in different clusters in sequence according to the cluster number; flip to the microengine with the same group number as the initial microengine in the next group in the cluster where the initial group is located, and repeat the above operation to traverse the microengines with the same group number in different groups in different clusters; and so on, until all microengines in the microengine pool are traversed and a microengine index is generated; Scheduling strategy 5: Process the initial microengine in the initial group and generate a microengine index, and then traverse the other microengines with the same group number as the initial microengine in sequence according to the group number and cluster number; and so on, until all microengines in the microengine pool are traversed and microengine indexes are generated; Scheduling strategy 6: Processing the initial microengine in the initial group and generating a microengine index, and sequentially processing other microengines in different groups in the cluster with the same group sequence number as the initial microengine; repeating the above operation to traverse all microengines in the cluster; This process is repeated in this way until all micro-engines in the micro-engine pool are traversed and micro-engine indexes are generated.

4. The low power consumption control method of the network message pre-classification processor according to claim 1, characterized in that: The low power consumption control method further includes: in response to a user's scheduling strategy selection instruction, dynamically sending a scheduling strategy selection and a signal of the number of micro-engines used to the packet inbound scheduling module and the packet outbound scheduling module; after all micro-engines have been selected for one round under the currently executed scheduling strategy, the packet inbound scheduling module and the packet outbound scheduling module switch to the selected scheduling strategy.

5. The low power consumption control method of the network message pre-classification processor according to claim 1, characterized in that: The enable signal of the outgoing packet scheduling module is sent to the incoming packet scheduling module for aggregation to generate a multi-bit enable signal; each bit of the enable signal controls a microengine or memory; the microengine enable controls whether the microengine is enabled through clock gating, and the memory enable reduces power consumption by lowering the voltage provided to the memory, and is used to prevent the loss of stored data.

6. A low-power network message pre-classification processor, characterized in that: include: A feature analysis module, used for receiving the message to be processed and analyzing it to generate a message pre-analysis result; The packet-in scheduling module is used to provide a micro-engine number of a message to be received when detecting the message pre-analysis result output by the feature analysis module; If the corresponding micro-engine in the micro-engine pool is ready to receive the message, the message header and the message pre-parse result are sent to the micro-engine; wherein the sending action triggers the sequencer in the packet-in scheduling module to shift backward to prepare a new micro-engine number, so that when the next message pre-parse result is output, the new micro-engine is entered according to the new micro-engine number; the micro-engine pool; the micro-engine pool includes a plurality of micro-engine clusters; each micro-engine cluster includes a plurality of micro-engine groups, and each micro-engine group includes a plurality of micro-engines; a micro-engine cluster memory is set for a preset number of micro-engine clusters for all micro-engines in the cluster to share access to obtain instructions or data; and a micro-engine group memory is set for each micro-engine group for all micro-engines in the group to share access to obtain instructions or data; The outgoing packet scheduling module is used to authorize the prepared micro-engine output packet processing results according to the current number of the internal sequencer after the micro-engine completes the message processing; if the post-processing device of the network message pre-classification processor is in a state of being ready to receive the packet processing results, the packet processing results are sent to the post-processing device; the sending action triggers the sequencer in the outgoing packet scheduling module to shift backward to prepare a new micro-engine number; wherein the incoming packet scheduling module and the outgoing packet scheduling module support a variety of low-power scheduling strategies; the incoming packet scheduling module and the outgoing packet scheduling module are each integrated with a micro-engine enable table with consistent mapping rules, which is used to index the currently actually used scheduling strategy and the number of micro-engines to the micro-engines and their related memories required to be turned on in the inbound and outbound directions, respectively, so as to generate an enable control signal for the micro-engines and related memories, and turn off the idle micro-engines and memories.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the low power consumption control method of the network message pre-classification processor according to any one of claims 1 to 5 is implemented.

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