Graphene field effect transistor based on spin-coated insulating medium and preparation method thereof

Abstract

The invention provides a graphene field effect transistor based on a spin-coated insulating medium and a preparation method thereof, and the transistor comprises a substrate, a gate electrode, a gate medium layer, a first insulating layer, a second insulating layer, a source electrode, a drain electrode, and a graphene channel layer. Gate dielectric layers with the same height as a gate electrode are formed at the two ends of a gate electrode in the buried gate structure through a spin-coating insulating medium technology, so that the smoothness of subsequent processing is ensured, and an insulating dielectric layer with the same height as a source electrode and a drain electrode is formed through the spin-coating insulating medium technology and etching; when the graphene thin film is transferred to the processed substrate, the stress borne by the graphene thin film is greatly reduced, so that the damage to the graphene thin film is reduced, the contact area of the graphene and the substrate is reduced by the nano-sized grooves in the insulating layer, the influence of substrate scattering is reduced, the carrier mobility of the graphene is improved, and the performance of the device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor electronic devices, and in particular to a graphene field effect transistor based on spin-coated insulating medium and a preparation method thereof. Background Art

[0002] Graphene is a zero-bandgap semiconductor, whose conduction band and valence band intersect at the Dirac point, so field-effect devices based on graphene have two characteristics: electron transport and hole transport. The type and concentration of carriers vary under different gate voltages, so graphene has a field regulation effect, and field-effect transistors can be prepared using the field regulation characteristics of graphene. Currently, field-effect transistors based on graphene mainly include top-gate graphene field-effect transistors, back-gate graphene field-effect transistors, and double-gate graphene field-effect transistors.

[0003] Top-gate graphene field-effect transistors can achieve independent control of the graphene channel by the transistor gate electrode. The channel is covered by the gate dielectric layer so that the graphene is less affected by the outside world, but the channel graphene is more susceptible to the gate dielectric layer, thereby reducing the carrier mobility. Back-gate graphene field-effect transistors have two structures: full back-gate and buried gate. Although the full back-gate structure has a simple process and is easy to implement, all field-effect transistors on a sample use a back-gate electrode, which makes it difficult to achieve individual regulation of a single graphene field-effect transistor. Based on this, a buried gate structure is usually used for graphene field-effect transistors that require higher performance and regulation capabilities. The buried gate structure is easy to achieve regulation of a single transistor, and because the gate dielectric is grown first and then the graphene is transferred, the growth process of the gate dielectric has no effect on the graphene. However, the buried-gate graphene field-effect transistor process first forms the back-gate electrode and then grows the dielectric layer. For the commonly used dielectric layer manufacturing methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), etc., it is inevitable that the dielectric layer above the electrode will be inconsistent with the dielectric layer in other areas, and local protrusions may appear in the adjacent parts of the electrode and the dielectric layer, which will undoubtedly affect the performance of the graphene transferred subsequently, such as causing the graphene at the step position to break or break or reduce the graphene carrier mobility. Therefore, a buried-gate field-effect transistor and a preparation method thereof are needed, which can keep the dielectric layer height consistent and prevent local protrusions in the dielectric layer above the gate electrode, so as to improve the device manufacturing yield and carrier mobility and improve the performance of the graphene field-effect transistor. Summary of the invention

[0004] In response to the above problems, the present invention proposes a graphene field effect transistor based on spin-coated insulating dielectric and a preparation method. Because the spin-coated insulating dielectric has excellent filling ability and local flattening effect, it can easily penetrate into tiny gaps, effectively solve the problem of gate oxide layer flatness in the existing buried gate technology, eliminate the height difference of the dielectric layer in the buried gate structure, improve the flatness of the contact area between the electrode and the gate dielectric, reduce the fracture and damage of graphene, and reduce the influence of the substrate on carrier scattering in graphene. In addition, the spin-coated insulating dielectric does not require excessively high temperature, reduces the thermal strain in the processing process, and thus improves the overall performance of the buried gate device.

[0005] The present invention provides a graphene field effect transistor based on spin-coated insulating dielectric, comprising:

[0006] substrate;

[0007] A gate electrode is disposed on the substrate and a portion of the gate electrode is not covered by the second insulating layer;

[0008] A gate dielectric layer, disposed on the gate electrode and the first insulating layer;

[0009] A first insulating layer and a second insulating layer, wherein the first insulating layer is disposed on the substrate and located at both ends of the gate electrode, and the first insulating layer is consistent in height with the gate electrode, and the second insulating layer is located on the gate dielectric layer and has a plurality of nanometer-sized grooves;

[0010] A source electrode and a drain electrode are arranged on the gate dielectric layer and located at two ends of the second insulating layer;

[0011] The graphene channel layer is arranged on a portion of the source and drain regions and the second insulating layer.

[0012] Furthermore, the gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, and Ti / Au.

[0013] Furthermore, the gate dielectric layer is made of dielectric material, including TiO 2、 Al 2 O 3 , HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 、ZrO 2 , LaAlO, the thickness of the gate dielectric layer is 100nm-300nm.

[0014] Furthermore, the second insulating layer is located in a partial area above the gate dielectric layer and is adjacent to the source and drain. The height of the second insulating layer is consistent with that of the source and drain regions.

[0015] Furthermore, the dielectric material of the insulating layer is one or more of SiO2, barium strontium titanate BST, and lead zirconate titanate PZT.

[0016] Furthermore, the graphene channel layer is a large-area graphene film with uniform synthetic properties, which is also covered with a boron nitride protective layer.

[0017] The present invention also proposes a method for preparing the graphene field effect transistor based on the spin coating insulating dielectric technology, the method comprising:

[0018] providing a substrate, and forming a gate electrode on the substrate;

[0019] An insulating layer is formed on the substrate and the gate electrode, and the insulating layer higher than the gate electrode is etched away to form a first insulating layer on both ends of the gate electrode and keep the height consistent with the gate electrode;

[0020] forming a gate dielectric layer on the first insulating layer and the gate electrode;

[0021] forming a source electrode and a drain electrode on the gate dielectric layer;

[0022] A second insulating layer is formed on the gate dielectric layer and between the source, drain and gate electrodes, and after forming, a portion higher than the source and drain electrodes is etched away to make the height of the second insulating layer consistent with the source and drain regions, and a plurality of nanometer-scale grooves are etched on the second insulating layer;

[0023] The graphene film is grown by chemical vapor deposition and then transferred onto the source and drain electrodes and the second insulating layer. Boron nitride is covered on top of the graphene, and the film is patterned by laser direct writing and etching to form a graphene channel layer.

[0024] Furthermore, the gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, and Ti / Au, and the gate electrode metal is realized by electron beam evaporation; the gate dielectric layer is realized by atomic layer deposition ALD or chemical vapor deposition PECVD, and the gate dielectric layer is TiO 2、 Al 2 O 3 , HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 、ZrO 2 , LaAlO, and the thickness of the gate dielectric layer is 100nm-300nm.

[0025] Furthermore, the formation of the source-drain electrode includes: spin coating a high-precision photoresist layer on the gate dielectric layer, then performing precision patterning on the photoresist layer to expose the area where the electrode needs to be evaporated, and performing electron beam evaporation on the area.

[0026] Furthermore, the first insulating layer and the second insulating layer are formed by preparing a precursor solution and then using surface treatment, spin coating, low-temperature baking and high-temperature annealing processes, and nanometer-scale grooves are formed on the second insulating layer by focused ion beam or etching.

[0027] Compared with the prior art, the present invention has the following beneficial technical effects:

[0028] (1) The scheme of the present invention utilizes the fluidity of spin-coated insulating dielectrics, which can achieve the same height between the gate electrode of a buried gate structure transistor and the insulating dielectric layers at both ends during processing, so that there will be no protrusions of the insulating dielectric layer on the gate electrode, thereby ensuring the flatness of subsequent processing. By spin-coating the insulating dielectric technology and etching to form a second insulating layer with the same height as the source and drain electrodes, the second insulating layer is also kept in the same height as the source and drain regions, thereby achieving the flattening of the dielectric layer, and there will be no curling, wrinkles, etc. that may affect graphene. The stress on the graphene film when it is transferred to the processed substrate will be greatly reduced, thereby reducing the damage to the graphene film. At the same time, the provision of nanometer-sized grooves on the insulating layer reduces the contact area between the graphene and the substrate, thereby reducing the influence of substrate scattering, improving the carrier mobility of the graphene, and thus improving the device performance;

[0029] (2) In the preparation method of the graphene field effect transistor based on spin-coated insulating dielectric proposed in the present invention, the insulating dielectric layer is processed by spin coating, low-temperature baking and high-temperature annealing, etc., with a fast generation rate and low preparation temperature, which is very helpful in reducing the thermal stress in the device processing process, and also realizes the flatness of the dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1It is a schematic diagram of the cross-sectional structure of a graphene field effect transistor based on spin-on insulating dielectric (SOD) technology provided by an embodiment of the present invention, wherein: 1-substrate, 2-gate electrode, 31-first insulating layer, 32-second insulating layer, 41-source electrode, 42-drain electrode, 5-gate dielectric layer, 6-groove, 7-graphene channel layer;

[0032] Figure 2 Schematic diagram of the top structure of a graphene field effect transistor based on spin-on insulating dielectric (SOD) technology provided by an embodiment of the present invention, wherein: 2-gate electrode, 32-second insulating layer, 41-source electrode, 42-drain electrode, 7-graphene channel layer;

[0033] Figure 3 It is a flow chart of a method for preparing a graphene field effect transistor based on a spin-on insulating dielectric (SOD) technology according to an embodiment of the present invention, wherein: 1-substrate, 2-gate electrode, 31-first insulating layer, 32-second insulating layer, 41-source, 42-drain, 5-gate dielectric layer, 6-groove, 7-graphene channel layer. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] On the one hand, the present invention provides a graphene field effect transistor based on spin-coated insulating dielectric, the cross-sectional structure schematic diagram of which is as follows Figure 1 As shown, the graphene field effect transistor comprises:

[0036] substrate;

[0037] A gate electrode is disposed on the substrate and a portion of the gate electrode is not covered by the second insulating layer to provide a gate voltage;

[0038] A gate dielectric layer, disposed on the gate electrode and the first insulating layer;

[0039] A first insulating layer and a second insulating layer, wherein the first insulating layer is disposed on the substrate and located at both ends of the gate electrode, and the first insulating layer is consistent in height with the gate electrode, and the second insulating layer is located on the gate dielectric layer and has a plurality of nanometer-sized grooves;

[0040] A source electrode and a drain electrode are arranged on the gate dielectric layer and located at two ends of the second insulating layer;

[0041] The graphene channel layer is arranged on a portion of the source and drain regions and the second insulating layer.

[0042] Furthermore, the gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, and Ti / Au.

[0043] Furthermore, the gate dielectric layer is made of dielectric material, including TiO 2、 Al 2 O 3 , HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 、ZrO 2 , LaAlO, the thickness of the gate dielectric layer is 100nm-300nm.

[0044] Furthermore, the second insulating layer is located in a partial area above the gate dielectric layer and is adjacent to the source and drain. The height of the second insulating layer is consistent with that of the source and drain regions.

[0045] Furthermore, the dielectric material of the insulating layer is one or more of SiO2, barium strontium titanate BST, and lead zirconate titanate PZT.

[0046] Furthermore, the graphene channel layer is a large-area graphene film with uniform synthetic properties, which is also covered with a boron nitride protective layer.

[0047] Figure 2 A schematic diagram of the top structure of a graphene field effect transistor based on spin-coated insulating dielectric is shown. As shown in the figure, the gate electrode has two regions, one part is not covered by the second insulating layer and the gate dielectric layer, and the other part is exposed by etching to provide a gate voltage. The source, drain and second insulating layer have the same height, and the graphene film covers part of the source, drain and second insulating layer.

[0048] On the other hand, the present invention also provides a method for preparing the graphene field effect transistor based on the spin coating insulating dielectric technology, such as Figure 3 As shown, the method includes:

[0049] Providing a substrate, forming a gate electrode on the substrate, and exposing a portion of the gate electrode by etching to provide a gate voltage;

[0050] An insulating layer is formed on the substrate and the gate electrode, and the insulating layer higher than the gate electrode is etched away to form a first insulating layer on both ends of the gate electrode and keep the height consistent with the gate electrode;

[0051] forming a gate dielectric layer on the first insulating layer and the gate electrode;

[0052] forming a source electrode and a drain electrode on the gate dielectric layer;

[0053] A second insulating layer is formed on the gate dielectric layer and between the source, drain and gate electrodes, and after forming, a portion higher than the source and drain electrodes is etched away to make the height of the second insulating layer consistent with the source and drain regions, and a plurality of nanometer-scale grooves are etched on the second insulating layer;

[0054] The graphene film is grown by chemical vapor deposition and then transferred onto the source and drain electrodes and the second insulating layer. Boron nitride is covered on top of the graphene, and the film is patterned by laser direct writing and etching to form a graphene channel layer.

[0055] Furthermore, the area on the substrate where the gate electrode is not required to be formed is covered by ultraviolet lithography, development and other processes. The gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, and Ti / Au, and the gate electrode metal is realized by electron beam evaporation; the gate dielectric layer is realized by atomic layer deposition ALD or chemical vapor deposition PECVD, and the gate dielectric layer is TiO 2、 Al 2 O 3 , HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La 2 O 3 、ZrO 2 , LaAlO, and the thickness of the gate dielectric layer is 100nm-300nm.

[0056] Furthermore, the formation of the source-drain electrode includes: spin coating a high-precision photoresist layer on the gate dielectric layer, then performing precision patterning on the photoresist layer to expose the area where the electrode needs to be evaporated, and performing electron beam evaporation on the area.

[0057] Furthermore, the first insulating layer and the second insulating layer are formed by preparing a precursor solution and then using surface treatment, spin coating, low-temperature baking and high-temperature annealing processes, and nanometer-scale grooves are formed on the second insulating layer by focused ion beam or etching.

[0058] The following is a detailed description of the preparation process of a graphene field effect transistor based on spin coating insulating dielectric technology using a specific embodiment.

[0059] Example 1

[0060] Step 1, forming a gate electrode, covering the area on the substrate where the gate electrode is not required by ultraviolet lithography, and then depositing 10nm of Ti and 40nm of Au in the above area in sequence by electron beam evaporation to form a gate electrode, and then stripping the photoresist and the metal above with acetone;

[0061] Step 2, forming a first insulating dielectric layer of the graphene field effect transistor based on spin-on insulating dielectric (SOD) technology, forming the first insulating layer by processes such as spin coating, low-temperature baking and high-temperature annealing, and etching away the insulating dielectric covering the gate electrode so that the first insulating layer and the gate electrode are kept at the same height, and the material of the first insulating dielectric layer is SiO2;

[0062] Step 3: forming a gate dielectric layer by chemical vapor deposition to form a 100 nm thick gate dielectric layer. The gate dielectric layer is made of TiO 2 ;

[0063] Step 4, generating a source electrode and a drain electrode on the gate dielectric layer, spin-coating a photoresist on the substrate on which the gate dielectric layer has been deposited, exposing the area where the electrode needs to be plated after patterning by ultraviolet photolithography, and then depositing 10 nm of Ti and 40 nm of Au in the area of ​​the source electrode and the drain electrode by electron beam evaporation to form the source electrode and the drain electrode;

[0064] Step 5, forming a second insulating layer, on the substrate on which the source and drain electrodes have been deposited, by spin coating, low temperature baking and high temperature annealing, etc., to solidify the insulating medium to form the second insulating layer, and similarly, by etching away the insulating medium covering the source and drain electrodes, the second insulating layer and the source and drain electrodes are kept at the same height, and the material of the second insulating dielectric layer is SiO2;

[0065] Step 6, forming a plurality of nanometer-scale grooves, forming a plurality of nanometer-scale grooves on the second insulating layer by means of a focused ion beam;

[0066] Step 7, transfer the graphene boron nitride film grown on other substrates by chemical vapor deposition onto the substrate filled with the second insulating layer, pattern the graphene boron nitride film, and then remove the graphene boron nitride outside the channel area and the source and drain electrodes to form a graphene channel layer; optionally, the patterned graphene boron nitride film adopts laser direct writing technology to avoid other substances from contacting the film and thus affecting the properties of the film.

[0067] Example 2

[0068] Step 1, forming a gate electrode, covering the area on the substrate where the gate electrode is not required by ultraviolet lithography, and then depositing 10nm of Ni and 40nm of Au in the above area in sequence by electron beam evaporation to form a gate electrode, and then stripping the photoresist and the metal above with acetone;

[0069] Step 2, forming a first insulating dielectric layer of a graphene field effect transistor based on a spin-on insulating dielectric (SOD) technology, forming the first insulating layer by processes such as spin coating, low-temperature baking and high-temperature annealing, and etching away the insulating dielectric covering the gate electrode so that the first insulating layer and the gate electrode are kept at the same height, and the material of the first insulating dielectric layer is lead zirconate titanate PZT;

[0070] Step 3: forming a gate dielectric layer by chemical vapor deposition to form a 300 nm thick gate dielectric layer. 2 O 3 ;

[0071] Step 4, generating a source electrode and a drain electrode on the gate dielectric layer, spin-coating a photoresist on the substrate on which the gate dielectric layer has been deposited, exposing the area where the electrode needs to be plated after patterning by ultraviolet photolithography, and then depositing 10 nm of Ni and 40 nm of Au in the area of ​​the source electrode and the drain electrode by electron beam evaporation to form the source electrode and the drain electrode;

[0072] Step 5, forming a second insulating layer, on the substrate on which the source and drain electrodes have been deposited, by spin coating, low-temperature baking, high-temperature annealing and other processes to solidify the insulating medium to form the second insulating layer, and similarly by etching away the insulating medium covering the source and drain electrodes so that the second insulating layer and the source and drain electrodes are kept at the same height, and the material of the second insulating dielectric layer is lead zirconate titanate PZT;

[0073] Step 6, forming a plurality of nanometer-scale grooves, forming a plurality of nanometer-scale grooves on the second insulating layer by etching;

[0074] Step 7, transfer the graphene boron nitride film grown on other substrates by chemical vapor deposition onto the substrate filled with the second insulating layer, pattern the graphene boron nitride film, and then remove the graphene boron nitride outside the channel area and the source and drain electrodes to form a graphene channel layer; optionally, the patterned graphene boron nitride film adopts laser direct writing technology to avoid other substances from contacting the film and thus affecting the properties of the film.

[0075] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A graphene field effect transistor based on spin-coated insulating dielectric technology, characterized in that: The graphene field effect transistor comprises: substrate; A gate electrode is disposed on the substrate and a portion of the gate electrode is not covered by the second insulating layer; A gate dielectric layer, disposed on the gate electrode and the first insulating layer; A first insulating layer and a second insulating layer, wherein the first insulating layer is disposed on the substrate and located at both ends of the gate electrode, and the first insulating layer is consistent in height with the gate electrode, and the second insulating layer is located on the gate dielectric layer and has a plurality of nanometer-sized grooves; A source electrode and a drain electrode are arranged on the gate dielectric layer and located at two ends of the second insulating layer; The graphene channel layer is arranged on a portion of the source and drain regions and the second insulating layer.

2. The graphene field effect transistor based on spin-coated insulating dielectric technology according to claim 1, characterized in that: The gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, and Ti / Au.

3. The graphene field effect transistor based on spin-coated insulating dielectric technology according to claim 1, characterized in that: The gate dielectric layer is made of dielectric material, including TiO 2、 Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, LaAlO, the thickness of the gate dielectric layer is 100nm-300nm.

4. The graphene field effect transistor based on spin-coated insulating dielectric technology according to claim 1, characterized in that: The second insulating layer is located in a partial area above the gate dielectric layer and is adjacent to the source and drain. The height of the second insulating layer is consistent with that of the source and drain areas.

5. The graphene field effect transistor based on spin-coated insulating dielectric technology according to claim 1, characterized in that: The dielectric material of the insulating layer is one or more of SiO2, barium strontium titanate BST, and lead zirconate titanate PZT.

6. The graphene field effect transistor based on spin-coated insulating dielectric technology according to claim 1, characterized in that: The graphene channel layer is a graphene film with uniform performance synthesized over a large area, and is also covered with a boron nitride protective layer.

7. A method for preparing a graphene field effect transistor based on spin coating insulating dielectric technology according to any one of claims 1 to 6, characterized in that: The method comprises: providing a substrate, and forming a gate electrode on the substrate; An insulating layer is formed on the substrate and the gate electrode, and the insulating layer higher than the gate electrode is etched away to form a first insulating layer on both ends of the gate electrode and keep the height consistent with the gate electrode; forming a gate dielectric layer on the first insulating layer and the gate electrode; forming a source electrode and a drain electrode on the gate dielectric layer; A second insulating layer is formed on the gate dielectric layer and between the source, drain and gate electrodes, and after forming, a portion higher than the source and drain electrodes is etched away to make the height of the second insulating layer consistent with the source and drain regions, and a plurality of nanometer-scale grooves are etched on the second insulating layer; The graphene film is grown by chemical vapor deposition and then transferred onto the source and drain electrodes and the second insulating layer. Boron nitride is covered on top of the graphene, and the film is patterned by laser direct writing and etching to form a graphene channel layer.

8. The preparation method according to claim 7, characterized in that: The gate electrode metal is one of Pb / Au, Ni / Au, Sn / Au, and Ti / Au, and the gate electrode metal is realized by electron beam evaporation; the gate dielectric layer is realized by atomic layer deposition ALD or chemical vapor deposition PECVD, and the gate dielectric layer is TiO 2、 One of Al2O3, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, ZrO2, and LaAlO, and the thickness of the gate dielectric layer is 100nm-300nm.

9. The preparation method according to claim 7, characterized in that: The formation of the source-drain electrode includes: spin coating a high-precision photoresist layer on the gate dielectric layer, then performing precision patterning on the photoresist layer to expose the area where the electrode needs to be evaporated, and performing electron beam evaporation on the area.

10. The preparation method according to claim 7, characterized in that: The first insulating layer and the second insulating layer are formed by preparing a precursor solution and then using surface treatment, spin coating, low-temperature baking and high-temperature annealing processes, and nanometer-scale grooves are formed on the second insulating layer by focused ion beam or etching.

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