Chip testability design program code generation device and method

Abstract

The present invention provides a device and method for generating program code for chip design for testability, the device comprising a chip design file processing module for receiving chip design files; a design for testability circuit generation and marking module for adding test points and observation points in the circuit of the chip according to the design for testability rules of the chip; a resource dynamic calculation module for dynamically generating a pseudo netlist according to flattening rules; a virtual device modeling module for modeling virtual devices and recording the FPGA model generated when generating the pseudo netlist; a simulation and design for testability collaborative optimization module for generating simulation code of a verification platform according to the completion degree of the program code of the chip design file and performing simulation; and a design data sharing module for storing shared chip design files. The present invention also provides a method for implementing the above-mentioned device. The present invention can improve the efficiency of designing chip test circuits and improve the flexibility and ease of use of collaborative design of tools at different chip design stages.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional integrated circuits, and in particular to a chip testability design program code generation device and a method for implementing the device. Background Art

[0002] With the development of chip technology, three-dimensional stacked chips have been widely used. In the design and production process of three-dimensional stacked chips, the chips need to be tested and adjusted repeatedly. Usually, in the initial stage of three-dimensional stacked chip design, designers will build the overall architecture of the chip based on multiple factors such as actual application requirements, performance requirements, power consumption constraints, and cost budgets, and clarify each functional module, and then select suitable chiplets and IP components. In order to facilitate subsequent testing work, the concept of Design For Testability (DFT) is usually incorporated into the chip design stage. Once problems are found in the overall design process of the chip, it may be necessary to adjust or even replace the applied IP components or key modules such as chiplets.

[0003] In the chip design process, Verilog files are widely used. Verilog files are a language used for electronic system-level design and hardware description, which allows designers to describe complex digital logic circuits and systems in text form. For this reason, chip testing is often based on chip design files such as Verilog files.

[0004] Current Verilog coding tools play a vital role in the current hardware design and verification field. Common Verilog development tools include Vivado, Quartus, ModelSim, etc. Although these Verilog development tools provide powerful Verilog code writing, simulation, synthesis and implementation functions. However, with the development of testability design technology in the chip design process, more and more Verilog coding tools begin to support testability design-related functions. However, the current testability design technology has the following six deficiencies and defects:

[0005] First, the functional integration of testability design is low. There are limitations in the integration of testability design functions, and a comprehensive and easy-to-use testability design function set is not provided. This requires designers to manually perform tedious configuration and coding work when adding testability design circuits, increasing the design complexity and error risk of the chip.

[0006] Second, in the hardware design process, the modules and codes that have been written should be able to be easily reused to improve design efficiency and reduce duplication of work. However, since the Verilog coding tools currently used often do not support fast module traversal and reuse, designers need to repeatedly write similar codes, which reduces the design efficiency of the chip.

[0007] Third, some design tools only support basic testability design functions, such as simple boundary scan testing, but fail to provide more complex and advanced testing strategies or methods. This limits the flexibility of designers in meeting specific design testing requirements and fails to fully detect potential faults.

[0008] Fourth, the process of inserting test logic in some design tools lacks sufficient automation and flexibility, and designers need to manually make a lot of modifications and adjustments to ensure the correctness and completeness of the test logic. This not only increases the design time of the chip, but may also introduce additional errors.

[0009] Fifth, the integration and ease of use of testability design circuits are crucial for designers. However, some current design tools are insufficient in this regard, which requires designers to spend more time and energy to learn and use related functions, reducing chip design efficiency.

[0010] Sixth, in terms of simulation tests related to testability design, some tools cannot provide comprehensive support, and designers cannot quickly integrate and couple functional circuits and test circuits, and thus cannot dynamically consider issues such as test circuit resources and power consumption. This leads to problems with the chip in actual testing, increasing the design risk and cost of the chip. Summary of the invention

[0011] The first object of the present invention is to provide a chip testability design program code generation device with high testability design functional integration and high testing efficiency.

[0012] A second object of the present invention is to provide a chip design for testability program code generation method based on the above-mentioned chip design for testability program code generation device.

[0013] To achieve the first purpose of the present invention, the chip testability design program code generation device provided by the present invention includes a chip design file processing module, which is used to receive the chip design file, parse the chip design file, and extract the circuit structure and logic information of the chip; a testability design circuit generation and marking module, which is used to add test points and observation points in the circuit of the chip according to the chip testability design rules, and mark the test points and observation points; a resource dynamic calculation module, which is used to dynamically generate a pseudo netlist according to the flattening rules, and the generated pseudo netlist includes an FPGA model generated by applying keyword template mapping after flattening the circuit extracted from the chip design file without optimization; a virtual device modeling module, which is used to model the virtual device and record the FPGA model generated when generating the pseudo netlist; a simulation and testability design collaborative optimization module, which is used to generate the simulation code of the verification platform according to the completion degree of the program code of the chip design file and simulate, and feedback the problems existing in the chip design file according to the simulation results; a design data sharing module, which is used to store shared chip design files and data.

[0014] As can be seen from the above scheme, the chip testability design program code generation device automatically analyzes the structure and logical function of the chip circuit through an intelligent coding method, quickly generates a test circuit designed for testability of a specific circuit, and significantly improves the efficiency of test circuit coding. Compared with the traditional method of manually writing test circuits, the present invention can greatly shorten the chip design cycle and reduce labor costs. At the same time, the testability design circuit generation and marking module can generate test circuit models for specific circuits, and these models can be reused, thereby further improving the efficiency of testing.

[0015] In addition, the present invention can accurately identify each module and signal path in the circuit, ensuring that the generated test circuit fully matches the original design circuit. The highly automated process reduces the possibility of human error and improves the accuracy and reliability of the test circuit.

[0016] Moreover, during the chip testing process, the test circuit of the generated testability design is highly compatible with the mainstream Verilog coding tools and can be seamlessly integrated into the existing design process. At the same time, the present invention provides flexible test configuration options, so that designers can easily adjust the parameters and strategies of the test circuit according to specific needs, thereby improving the flexibility and convenience of test verification.

[0017] A preferred solution is that the testability design circuit generation and marking module is also used to comprehensively optimize the chip circuit according to the scanning information of the chip design file and generate an updated chip design file.

[0018] It can be seen that after the comprehensive optimization of the chip circuit, an updated chip design file is generated according to the optimized circuit, so that the chip design file can be updated in a timely and automatic manner, thereby improving the chip testing and design efficiency.

[0019] A further solution is that the virtual device modeling module is also used to model the device according to pre-specified pins and generate a branch circuit model.

[0020] It can be seen that the virtual device modeling module can automatically generate device models, such as implementing adders, subtractors and other devices, and can improve the degree of automation of chip testing.

[0021] A further solution is that the FPGA model recorded by the virtual device modeling module can be reused.

[0022] It can be seen that since the virtual device modeling module can record the FPGA model and the FPGA model can be reused, when the FPGA model is needed in other scenarios, the FPGA model can be directly obtained without recalculation, thus reducing the time required for modeling.

[0023] A further solution is that the design data sharing module is also used to display the design progress in a visual manner and to share and manage IP core packaging files.

[0024] It can be seen that the design data sharing module can share and manage various files such as IP core packaging files, which can facilitate the calling of various files in the subsequent design and testing process and improve the testing efficiency.

[0025] A further solution is that the chip design file processing module includes at least one of the following: a Verilog file processing module, a netlist file processing module, a GDSII file processing module and a LEF file processing module.

[0026] To achieve the above-mentioned second purpose, the chip testability design program code generation method provided by the present invention includes: a chip design file processing module loads the chip design file, and parses the chip design file to extract the circuit structure and logic information of the chip; the testability design circuit generation and marking module adds test points and observation points in the chip circuit according to the chip testability design rules, and marks the test points and observation points; the simulation and testability design collaborative optimization module generates simulation code according to the extracted information, and generates and simulates the simulation code of the verification platform according to the program code completion degree of the chip design file, and dynamically optimizes the parameters of the chip design file; the simulation and testability design collaborative optimization module also simulates the chip design file with the testability design circuit, performs logic synthesis on the chip design file when the simulation result does not meet the requirements, and converts the result of the logic synthesis into a gate-level netlist; the generated gate-level netlist and chip design file are stored in the design data sharing module.

[0027] As can be seen from the above scheme, the present invention automatically analyzes the structure and logical function of the chip circuit through the intelligent coding method, quickly generates a test circuit designed for testability of a specific circuit, and can improve the efficiency of test circuit coding. In addition, the present invention can generate a test circuit model for a specific circuit, and since these models can be reused, the efficiency of testing can be improved.

[0028] A preferred solution is to analyze the codes of each module in the chip design file when parsing the chip design file, parse the connection relationship and functional logic between each module through the top-level module, and update the N-ary tree structure of the chip in real time.

[0029] It can be seen that since the N-ary tree structure of the chip can be updated in real time, the internal structure of the chip can be automatically analyzed during the chip testing and verification process, and corresponding tests can be performed based on the chip structure.

[0030] A further solution is to update the N-ary tree structure of the chip in real time while mapping the N-ary tree structure of the chip into a linear table, design the tree node hierarchy according to the chip module hierarchy, and sort and store them in a predetermined order.

[0031] It can be seen that the internal structure of the chip can be stored in real time according to a pre-set order, which is conducive to reading the N-ary tree structure related data of the chip during subsequent testing, thereby improving the testing and verification efficiency.

[0032] A further solution is that the simulation and testability design collaborative optimization module also synthesizes the N-ary tree from the bottom to the top until the topmost module of the N-ary tree is synthesized.

[0033] It can be seen that synthesizing the N-ary tree from the bottom to the top can ensure the accuracy of the internal structure analysis of the chip and avoid inaccurate testing caused by missing some information during the synthesis process. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural block diagram of an embodiment of a chip testability design program code generation device of the present invention.

[0035] Figure 2 It is a flow chart of an embodiment of a method for generating program code for chip testability design according to the present invention.

[0036] The present invention is further described below in conjunction with the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0037] The chip testability design program code generation device of the present invention can be run on a computer and implemented through a computer program. It is mainly used to improve the design efficiency of the chip test circuit, and through intelligent generation of the program code of the test circuit, it takes into account the hierarchical design of the functional circuit and the test circuit module, so as to achieve the purpose of modular design and modular packaging reuse. In addition, the present invention establishes a reusable testability design circuit model, and realizes collaborative reuse through a private cloud or cloud storage method, so as to take into account the coupling of different stages of chip design at the same time, and better apply the testability design collaboration to each stage of chip design.

[0038] Chip testability design program code generation device embodiment:

[0039] See also Figure 1 The chip testability design program code generation device of this embodiment has a chip design file processing module 10, a testability design circuit generation and marking module 21, a resource dynamic calculation module 22, a virtual device modeling module 23, a simulation and testability design collaborative optimization module 24, and a design data sharing module 25.

[0040] Among them, the chip design file processing module 10 has a Verilog file processing module 11, a netlist file processing module 12, a GDSII file processing 13 and a LEF file processing 14. The Verilog file processing module 11 is used to read and parse the Verilog source code, and extract the circuit structure and logic information of the chip. The netlist file processing module 12 is used to process the netlist file generated after synthesis, and parse the logical elements and their connection relationships in the circuit. The GDSII file processing module 13 is used to implement the import and parsing of the GDSII file, and to obtain the geometric information of the circuit. The LEF file processing module 14 is used to process the LEF file and extract key information such as the physical size and pin position of the unit in the library.

[0041] The netlist file is a file generated after the chip is synthesized. In the electronic design automation process, synthesis is a key step, which converts the source code written in a high-level hardware description language (such as Verilog or VHDL) into a lower-level gate-level or transistor-level description. This conversion process generates a netlist file, which lists in detail all the logic elements in the circuit (such as AND gates, OR gates, triggers, etc.) and the connection relationship between various logic elements. In addition, the synthesis process will also optimize the layout of the gate-level circuit.

[0042] In the semiconductor manufacturing process, GDSII files are typically the output of circuit layout tools, which generate circuit geometry based on netlist files and other design rules.

[0043] LEF files are process and unit description files used for automatic layout and routing during chip design. The input of LEF files usually comes from data provided by the process library supplier, which describes the physical size, pin location, metal layer information, etc. of various units in the library.

[0044] The design for testability circuit generation and marking module 21 adds test points and observation points to the circuit according to the design for testability rules, and marks the added test points and observation points. In addition, the design for testability circuit generation and marking module 21 can also perform comprehensive optimization of the circuit according to the Verilog scanning information of each module in the chip design file, and generate chip design files such as updated Verilog files.

[0045] For different testability design models, the testability design circuit generation and marking module 21 adopts different test point adding rules. For example, for the Testbench verification platform, by generating test vectors and applying them to the circuit, the output response of the circuit is observed. The Testbench verification platform also records the input and output data during the test process, and uses these data to quickly add test points and observation points, and improve test coverage. For another example, for the tree structure diagram, the location where the test points and observation points need to be added can be quickly located. Since the tree structure diagram can also help understand the function of the circuit and the signal flow, test points and observation points can be added more accurately.

[0046] The virtual device modeling module 23 is used to simulate and model unimplemented IP circuits, core circuits or unauthorized IP circuits, such as IP circuits generated by templates and learning algorithms, and then mapped to actual processes, process libraries, device libraries, and similar device libraries in subsequent processes. Preferably, the device library can be generated in advance according to the actual design mapping formed by the design requirements and the divided module circuits, or a third-party device library can be collected to selectively generate a virtual device library. In addition, the virtual device modeling module 23 can also support automatic device modeling of specified pins according to the output, and generate branch circuit models in formats such as XML or Verilog for interconnection verification and test circuit verification between cores.

[0047] In the chip design process, flattening is usually closely related to the chip synthesis process, but when the Verilog hardware language is written, the netlist and resource evaluation after the overall logic synthesis cannot be obtained. For this reason, the resource dynamic calculation module 22 needs to dynamically generate a pseudo netlist of Verilog according to the flattening rules to help designers better understand the resource requirements and optimization potential of the design, so that when adding the testability design circuit, the resource evaluation process can be better carried out, the additional resources required for the testability design logic can be considered, and the design can be ensured to meet the testability design requirements. Among them, the pseudo netlist includes an FPGA model generated by applying keyword template mapping after flattening the circuit extracted from the chip design file without optimization. These FPGA models can be collected in the virtual device modeling module 23 and can be collected and reused.

[0048] When the virtual device modeling module 23 constructs a virtual device, it can also be obtained according to the mapping technology of the resource dynamic calculation module 22. Specifically, the mapping technology can be implemented in the following multiple ways: first, obtain the variables of the circuit, and directly map the reg type keyword of the circuit at the RTL level into the memory resource; second, analyze the circuit path according to the input and output analysis logic of the circuit, and map it into the wiring resource, wherein the wiring resource is the physical channel used to connect various logic units and memory resources in the FPGA; third, directly convert the logical operator into the corresponding basic logic gate, such as AND, NOR, XOR gate, etc.; fourth, for the modules in the circuit that implement functions such as addition, subtraction, multiplication, and division, they are mapped into devices such as adders, subtractors, multipliers, and dividers; fifth, directly map the conditional statement into a MUX data multiplexer; sixth, for complex logic statements, directly map them into FPGA models or logic units of FPGA models.

[0049] When the designer stops writing program code, the simulation and testability design collaborative optimization module 24 can automatically generate simulation code for verification platforms such as Testbench and perform simulation according to the completion of the written Verilog and other chip design files. In addition, the simulation and testability design collaborative optimization module 24 will also prompt the problems existing in the Verilog program code according to the simulation results. Therefore, the simulation and testability design collaborative optimization module 24 can not only verify the design of the functional circuit, but also verify the coupling of the testability design circuit and the functional circuit.

[0050] The design data sharing module 25 can provide design data sharing functions in private cloud and public cloud modes, and preferably supports data sharing within a local area network. In addition, the design data sharing module 25 can realize the sharing and management of resources such as design progress visualization, chip design files, and IP core packaging files. The design data sharing module 25 also stores the model data of the mapping between Verilog code and logic netlist, the static template data of Verilog, and generates an interface for dynamic Verilog code configured according to semantic parameters.

[0051] Chip testability design program code generation method embodiment:

[0052] Combine the following Figure 2 The specific process of the chip testability design program code generation method is introduced. First, the chip testability design program code generation device is initialized. Specifically, the chip design file processing module 10 executes step S11 to load the chip design file, such as loading the Verilog syntax library to ensure the accuracy of syntax parsing, and loading the testability design code template library to provide a basic template for subsequent testability design.

[0053] Then, the chip design file is parsed and the circuit structure and logic information are extracted. For example, the chip design file processing module 10 captures the handle of the chip design file, for example, by calling the system API to obtain the window handle of the Verilog writing program, and through the window handle, further obtains the process handle of the Verilog writing program.

[0054] Next, prepare the testability design coding, for example, check whether the environment and resources required for the testability design coding are ready, and initialize the internal data structures and variables related to the testability design coding.

[0055] Then, the chip testability design program code generation device performs normalized monitoring and analysis. Specifically, when in idle state, the chip testability design program code generation device waits to be activated or automatically triggered. If the testability design circuit generation step is triggered, the test operation is entered. If it is not necessarily activated, the input information is continuously monitored, including monitoring code editing, saving and other operations, and the code of each module in each chip design file is analyzed, and the connection relationship and functional logic between each module are parsed through the top-level module.

[0056] Usually, the structure of the chip is stored in the form of multiple N-ary trees. Therefore, the chip testability design program code generation device needs to update the chip's N-ary tree structure in real time to ensure that each module and its internal elements in each chip design file, such as registers, interface signals, etc., are correctly represented. In addition, the chip's N-ary tree structure is mapped into a linear table, and the tree node hierarchy is designed according to the chip module hierarchy, sorted by depth and sequence number from left to right, for easy subsequent processing.

[0057] If the designer has input the chip design file and needs to perform testability design layout, step S12 needs to be executed, and the testability design circuit generation and marking module 21 adds test points and observation points to the chip circuit according to the testability design rules, and the added test points and observation points need to be marked.

[0058] Then, generate the code of the Testbench verification platform, and perform simulation based on the generated code, that is, execute step S13. Specifically, for each top-level module of the N-ary tree structure of the chip, extract the information of its connection module in sequence, and generate the simulation code of the corresponding Testbench verification platform according to the extracted information. Then, run the generated simulation code to verify whether the functions and connection relationships of each module meet the design requirements. If the simulation result meets the design, record the input and output information, and update the status of the corresponding subtree node in the N-ary tree to "Testbench simulation passed". If the simulation result reports an error, a prompt message is issued to prompt the designer that the code needs to be modified, and the status of the N-ary tree node of the corresponding module is annotated as "Testbench simulation failed".

[0059] For each module of the N-ary tree structure, the above steps need to be repeated until all modules have gone through the steps of generating code and performing simulation tests on the code. Then, based on the above test results, the connection relationship N-ary tree structure of the entire Verilog chip design file is generated, including individual and overall module inputs and outputs. Next, the design data sharing module 25 is used to realize silent parallel simulation and the generation of the N-ary tree structure, thereby improving test efficiency and accuracy.

[0060] Then, the simulation and testability design collaborative optimization module 24 performs comprehensive optimization and testability design. Specifically, if in step S13, all module designs of the chip meet the design requirements, the comprehensive optimization stage is entered. In the comprehensive optimization stage, it is necessary to integrate the comprehensive optimization function of the resource dynamic calculation module 22, parameterize and synthesize the chip design file, and perform dynamic optimization. For the N-ary tree structure of the chip, it can be processed from the bottom to the top according to the N-ary tree node module until the top-level module is synthesized.

[0061] If the designer chooses to generate a test circuit for the testability design, it is necessary to traverse the N-ary tree structure and generate boundary scan, scan test and other circuits based on the template technology. In addition, the chip testability design program code generation device also provides an interface so that the designer can easily insert the generated test circuit into the chip design file such as Verilog.

[0062] Then, execute step S14 to simulate and optimize the chip design file. Specifically, the Verilog chip design file with the test circuit designed for testability is simulated on the Testbench verification platform. If the simulation result meets the design requirements, the comprehensive optimization function of the resource dynamic calculation module 22 is used for logic synthesis. Since the chip testability design program code generation device has the ability to synthesize the chip circuit, it can display the resources, power consumption and other data of each module of the chip in a structured manner, so as to better enable designers to optimize the test circuit and perform collaborative modification and optimization. In addition, the logic synthesis result is converted into a gate-level netlist to provide a basis for subsequent physical implementation.

[0063] Finally, step S15 is executed to share the design data. Specifically, the gate-level netlist, N-ary tree structure file, Verilog chip design file, etc. generated in step S14 are uploaded to the designated directory of the design data sharing module 25. When uploading files, it is necessary to ensure that the uploaded files are complete and accurate so that the uploaded files can be accessed and used by other members or tools of the design team.

[0064] The present invention applies testability design to improve the test efficiency and test coverage of the chip. There are three ways to perform testability design, namely scan test (Scan Test), built-in self-test (BIST) and boundary scan (Boundary Scan).

[0065] Scan testing is to convert the storage units (such as registers) in the circuit into controllable and observable storage units, and connect these units into one or more shift registers to form a scan chain. When performing scan testing, the test vector is input through the scan chain and the output response is captured. The principle of scan testing is to convert the sequential circuit test into a combinational circuit test, thereby simplifying the test process. Through the scan chain, the state of the register can be easily controlled and its output can be observed.

[0066] The code generation method for scan test is to switch the scan enable by relying on the flag. The difference from traditional coding is that the designer needs to select the parameterized input of the module register that needs to be scanned or define the register name with certain characteristics when encoding. The characteristic can be configured during parameterization, such as adding regscanX to the module name and register characteristic suffix that needs to be scanned, where X is the incrementing serial number of the register for testability design scanning. When the designer calls the interface, all registers that need to add scan chains are automatically formed into a global serial scan chain output. In order to take into account the scanning efficiency, the designer can parameterize the input and output of the compressed scan chain to generate the Verilog code module for scan testing.

[0067] Built-in self-test is to add a test circuit structure inside the circuit, which can generate stimulus and compare the response by itself. According to the type of circuit under test, built-in self-test can be divided into memory built-in self-test (MBIST) and logic circuit built-in self-test (LBIST). The principle of built-in self-test is to test the circuit through the stimulus signal generated internally and automatically compare the response signal with the expected result. This method does not require external test equipment, reducing the test cost.

[0068] The code generation method of built-in self-test includes generating the code required by the Testbench verification platform for each complete module code first, verifying the generated code, and saving the verification results. Similarly, because Verilog chip design files are often divided into layers and modules, each division is first generated Testbench code for verification, and the verification results are saved. The verification tool can be open source, analyze the results of the Testbench verification, identify the input, output and key test points of the module, determine which test vectors can fully cover the function and fault model of the module, and then generate multiple test tools, such as test controllers, test point selectors and output comparators. Among them, the test controller is used to generate test vectors and control the generation of test processes, and complete code generation according to the global operating logic of each module and the input and output of each module. The test point selector is used to select the circuit point to be tested and generate code. The output comparator is used to compare the actual output with the expected output, establish a test fault model based on the output and input, and generate the logic of the test fault model comparison code.

[0069] The built-in self-test code contains the module results and system results of parallel testing of each module of the chip, and the result query is formed by the module name. When the module or system changes, the built-in self-test logic code is updated to ensure that it remains valid.

[0070] Boundary scan is to insert boundary scan cells on the input and output ports of the circuit. These cells can control and observe the status of the port. Through the boundary scan register chain, the input and output ports can be accessed and controlled. Since boundary scan technology allows test equipment to test the input and output ports of the circuit through the scan chain, it can detect the connection problems between the circuit and the external circuit.

[0071] The code generation method of boundary scan includes generating code templates through the JTAG interface and scan chain with configuration parameters. In the process of boundary scan code generation, it is necessary to parameterize the boundary scan register design quantity and generate the boundary scan register. When resetting, the internal register and the boundary scan register code need to be cleared. When the boundary scan is enabled, the boundary scan register code needs to be updated; in normal operation, the internal register is updated and the code is output.

[0072] Application of the method of the present invention can achieve efficient coding and adding test codes, and also allow designers to check the program code. Therefore, the chip testability design program code generation device can check the correctness and consistency of the code in real time or near real time, thereby reducing the workload of later debugging and modification.

[0073] In addition, since the present invention silently structures the entire chip design as an N-ary tree, the connection relationship between different modules of the chip design circuit can be clearly displayed. This structured representation method helps designers to better perform logic design and to make more systematic evaluations when checking or analyzing problems. Since the generation of the N-ary tree structure is also performed in parallel during the silent coding stage, the parallel processing efficiency of large-scale circuit design and module verification can be significantly improved, which not only saves the time of regenerating the N-ary tree structure during subsequent problem analysis and test code, but also enables designers to discover problems earlier and correct them.

[0074] In addition, when testing the code on the Testbench verification platform, if a module of the chip has a problem, the node that failed the test can be clearly displayed through the N-tree structure. The intelligent capture and modification mechanism helps designers quickly locate the problem and fix it, thereby improving the test efficiency and design quality of the chip.

[0075] Since there are redundant circuits and branch circuits in the chip, the N-ary tree structure can quickly identify redundant circuits and logic circuits, thereby providing an evaluation and testing basis for adding testability design circuits to subsequent designs. Furthermore, due to the tree-structured circuit module connection design, it is more convenient to generate testability design test circuit code, improve the efficiency of automatic test code generation, and also improve the accuracy of inserting test points and observation points of testability design, thereby improving the coverage of testability design circuits and the completeness of fault models.

[0076] Finally, the N-tree structure generated by the present invention can generate an N-tree model, which provides an important reference for subsequent layout and routing. Through the N-tree model and netlist data, designers can more accurately understand the connection relationship and spatial distribution between the various modules of the chip, so as to formulate a more reasonable layout and routing scheme. The gate-level netlist, N-tree file, and Verilog file sharing data mode better solve the problems of large calculation amount, difficult modification, and low automation of the gate-level netlist obtained after synthesis in the traditional chip design process.

[0077] It should be emphasized that the above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip testability design program code generation device, characterized in that: include: A chip design file processing module, used to receive a chip design file, parse the chip design file, and extract the circuit structure and logic information of the chip; A testability design circuit generation and marking module, used to add test points and observation points in the circuit of the chip according to the testability design rules of the chip, and mark the test points and the observation points; A resource dynamic calculation module, used for dynamically generating a pseudo netlist according to a flattening rule, wherein the generated pseudo netlist includes an FPGA model generated by applying keyword template mapping after flattening the circuit extracted from the chip design file without optimization; A virtual device modeling module, used for performing simulation modeling on an unimplemented IP circuit, a core circuit or an unauthorized IP circuit, and recording an FPGA model generated when generating the pseudo netlist; The simulation and testability design collaborative optimization module is used to generate the simulation code of the verification platform according to the completion degree of the program code of the chip design file and perform simulation, and feedback the problems existing in the chip design file according to the simulation results; A design data sharing module, used for storing the shared chip design files and data; Among them, the structure of the chip is stored in the structure of multiple N-ary trees; The chip testability design program code generation device updates the N-ary tree structure of the chip in real time to ensure that each module and its internal elements in each chip design file are correctly represented.

2. The chip testability design program code generation device according to claim 1, characterized in that: The testability design circuit generation and marking module is also used to comprehensively optimize the chip circuit according to the scanning information of the chip design file and generate an updated chip design file.

3. The chip testability design program code generation device according to claim 1, characterized in that: The virtual device modeling module is also used to model the device according to the pre-specified pins and generate a branch circuit model.

4. The chip testability design program code generation device according to claim 2, characterized in that: The FPGA model recorded by the virtual device modeling module can be reused.

5. The chip testability design program code generation device according to any one of claims 1 to 4, characterized in that: The design data sharing module is also used to display the design progress in a visual manner, and to share and manage IP core packaging files.

6. The chip testability design program code generation device according to any one of claims 1 to 4, characterized in that: The chip design file processing module includes at least one of the following: a Verilog file processing module, a netlist file processing module, a GDSII file processing module and a LEF file processing module.

7. A chip testability design program code generation method, characterized in that: include: The chip design file processing module loads the chip design file, parses the chip design file, and extracts the circuit structure and logic information of the chip; The testability design circuit generation and marking module adds test points and observation points in the circuit of the chip according to the testability design rules of the chip, and marks the test points and the observation points; The resource dynamic calculation module dynamically generates a pseudo netlist according to the flattening rule, wherein the generated pseudo netlist includes an FPGA model generated by applying keyword template mapping after flattening the circuit extracted from the chip design file without optimization; The simulation and testability design collaborative optimization module generates simulation code based on the extracted information, generates simulation code for the verification platform based on the completion degree of the program code of the chip design file, performs simulation, and dynamically optimizes the parameters of the chip design file; The simulation and testability design collaborative optimization module also simulates the chip design file with the testability design circuit, performs logic synthesis on the chip design file when the simulation result does not meet the requirements, and converts the result of the logic synthesis into a gate-level netlist; The generated gate-level netlist and chip design file are stored in a design data sharing module; Among them, the structure of the chip is stored in the structure of multiple N-ary trees; When parsing the chip design file, the code of each module in the chip design file is analyzed, the connection relationship and functional logic between the modules are parsed through the top-level module, and the N-ary tree structure of the chip is updated in real time; The information on which the simulation and testability design collaborative optimization module generates the simulation code is information on the connection modules of each top-level module of the N-ary tree structure.

8. The chip testability design program code generation method according to claim 7, characterized in that: While updating the N-ary tree structure of the chip in real time, the N-ary tree structure of the chip is mapped into a linear table, and the tree node hierarchy is designed according to the chip module hierarchy, and is sorted and stored in a predetermined order.

9. The chip testability design program code generation method according to claim 8, characterized in that: The simulation and testability design collaborative optimization module also synthesizes the N-ary tree from the bottom to the top until the topmost module of the N-ary tree is synthesized.

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